WO2020063918A1 - 半导体功率器件 - Google Patents

半导体功率器件 Download PDF

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Publication number
WO2020063918A1
WO2020063918A1 PCT/CN2019/108739 CN2019108739W WO2020063918A1 WO 2020063918 A1 WO2020063918 A1 WO 2020063918A1 CN 2019108739 W CN2019108739 W CN 2019108739W WO 2020063918 A1 WO2020063918 A1 WO 2020063918A1
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gate
type
control gate
power device
region
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PCT/CN2019/108739
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English (en)
French (fr)
Inventor
刘磊
刘伟
毛振东
袁愿林
王睿
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苏州东微半导体有限公司
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Priority claimed from CN201811147319.1A external-priority patent/CN110970501A/zh
Priority claimed from CN201811147326.1A external-priority patent/CN110970496A/zh
Application filed by 苏州东微半导体有限公司 filed Critical 苏州东微半导体有限公司
Publication of WO2020063918A1 publication Critical patent/WO2020063918A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application belongs to the technical field of semiconductor power devices, for example, relates to a semiconductor power device.
  • FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor power device of the related art.
  • a semiconductor power device of the related art includes: an n-type semiconductor substrate 100, and n located at the bottom of the n-type semiconductor substrate 100.
  • a drain region 10 is located in the n-type semiconductor substrate 100 and an n-type drift region 11 above the n-type drain region 10.
  • a plurality of gate trenches in the n-type semiconductor substrate 100 are located adjacent to each other.
  • the control gate 13 is generally located at the upper sidewall position of the gate trench and controls the opening and closing of the current channel between the n-type source region 17 and the n-type drift region 11 by an external gate voltage.
  • the shielding gate 15 is located in the gate trench and is isolated from the n-type semiconductor substrate 100 and the control gate 13 through an isolation dielectric layer 14.
  • the shielding gate 15 is connected to the n-type source region 17 through the source metal layer 19, so that the shielding gate 15 can pass through
  • the external source voltage forms a lateral electric field in the n-type drift region 11 and plays a role in improving the withstand voltage.
  • the interlayer insulating layer 18 is used to isolate the source metal layer 19 from the gate metal layer. Based on the positional relationship of the cross section, the gate metal layer is not shown in FIG. 1.
  • the source metal layer 19 is in contact with the n-type source region 17 and the p-type body region 16 at a middle position of the p-type body region 16.
  • the source metal layer 19 is embedded in p In the p-type body region 16, n-type source regions 17 are provided on both sides of the source metal layer 19 in the p-type body region 16. Due to the limitation of the lithography process conditions, the distance between adjacent gate trenches is difficult to narrow. .
  • the present application provides a semiconductor power device to avoid a situation in which a pitch between adjacent gate trenches in a semiconductor power device in the related art is difficult to narrow.
  • the present application provides a semiconductor power device including: an n-type semiconductor substrate; p-type body regions and gate trenches which are located in the n-type semiconductor substrate and are alternately and alternately arranged in sequence; A first control gate and a second control gate at the sides of the upper side, and the first control gate and the second control gate are respectively separated from the semiconductor substrate by a gate dielectric layer; A shielding gate at the bottom of the trench, the shielding gate being isolated from the semiconductor substrate, the first control gate, and the second control gate by an isolation dielectric layer; located in the p-type body region and close to the first An n-type source region on one side of the two control gates; one source contact hole located above the p-type body region, the source contact hole extending to the first control gate side and above the gate trench, The n-type source region, the p-type body region, the first control gate, and the shield gate are all connected to a source voltage through a source metal layer in the source contact hole, and the second control gate External gate voltage.
  • FIG. 1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor power device according to the related art
  • FIG. 2 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor power device provided by the present application.
  • FIG. 3 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor power device provided by the present application.
  • FIG. 2 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor power device provided by the present application.
  • a semiconductor power device provided in the embodiment of the present application includes an n-type semiconductor substrate 200.
  • the material of the n-type semiconductor substrate 200 is usually silicon.
  • the gate trenches 201 and the p-type body regions 26 which are located in the n-type semiconductor substrate 200 and are alternately arranged in sequence are shown in the example of the present application.
  • Six gate trenches 201 are exemplarily shown.
  • the first control gate 33 and the second control gate 23 are respectively located at the side walls of the upper side of the gate trench 201, and the first control gate 33 and the second control gate 23 pass through the gate dielectric layer 22 and the n-type semiconductor substrate, respectively. 200 isolation.
  • Shielding gate 25 The shielding gate 25 is located at the lower part of the gate trench 201, and the shielding gate 25 is isolated from the n-type semiconductor substrate 200, the first control gate 33, and the second control gate 23 through an isolation dielectric layer 24.
  • the shielding gate 25 and the isolation dielectric layer 24 cover the gate trench 201 and extend upward to the upper part of the gate trench 201 and separate the first control gate 33 and the second control gate 23 from the upper part of the gate trench 201, as shown in FIG. 2 Show.
  • a width of an upper portion of the gate trench 201 is larger than a width of a lower portion of the gate trench 201, as shown in FIG. 2.
  • the thickness of the isolation dielectric layer 24 between the shielding gate 25 and the n-type semiconductor substrate 200 may be the same as or greater than the thickness of the isolation dielectric layer 24 between the shielding gate 25 and the first control gate 33 and the second control gate 23.
  • the isolation between the shield gate 25 and the n-type semiconductor substrate 200 is only exemplarily shown.
  • the thickness of the dielectric layer 24, the thickness of the isolation dielectric layer 24 between the shield grid 25 and the first control grid 33, and the thickness of the isolation dielectric layer 24 between the shield grid 25 and the second control grid 23 are the same.
  • the material of the gate dielectric layer 22 and the isolation dielectric layer 24 is silicon oxide, and the materials of the first control gate 33, the second control gate 23, and the shield gate 25 are doped polysilicon, respectively.
  • the n-type source region 27 is located in the p-type body region 26 and near the second control gate 23.
  • the n-type semiconductor substrate portion between the p-type body region 26 and the n-type drain region 20 is an n-type drift region 21 of a semiconductor power device.
  • the source contact hole 203 extends to one side of the first control gate 33 to above the gate trench 201 so that the p-type The body region 26, the n-type source region 27, the first control gate 33, and the shield gate 25 are connected to the source voltage through a source metal layer 29 in the source contact hole 203.
  • the source metal layer 29 is embedded in the p-type body region 26. Therefore, the n-type source region 27 is located in the p-type body region 26 and is interposed between the source metal layer 29 and the first control gate 33.
  • the source metal layer 29 may not be embedded in the p-type body region 26, but a contact region with a high doping concentration may be formed in the p-type body region. The contact region is in contact with the p-type body region.
  • This structure is a structure often used in related technologies, and will not be specifically shown in the implementation column of this application.
  • the second control gate 23 is connected to the gate voltage through the gate metal layer.
  • the second control gate 23 controls the opening and closing of the current channel between the n-type source region 27 and the n-type drift region 21 by the gate voltage. .
  • the interlayer insulating layer 28 is used to isolate the source metal layer 29 from the gate metal layer.
  • the material of the interlayer insulating layer 28 is usually silicon glass, borophosphosilicate glass, or phosphosilicate glass.
  • a source contact hole 203 located above the p-type body region 26 extends to one side of the first control gate 33 to above the gate trench 201.
  • the body region 26, the n-type source region 27, the first control gate 33, and the shield gate 25 can be connected to the source voltage through the source metal layer 29 in the source contact hole 203 at the same time, so that formation in the p-type body region 26 can be avoided.
  • An n-type source region between the source metal layer 29 and the first control gate 33, and an n-type source between the second control gate 23 and the source metal layer 29 is formed only in the p-type body region 26 Region 27, which can reduce the limitation of the lithography process conditions, can further reduce the distance between adjacent gate trenches 201, and further increase the doping concentration of the n-type semiconductor substrate 200 under the same operating voltage condition. Reduce the on-resistance of semiconductor power devices.
  • the drain region located at the bottom of the n-type semiconductor substrate 200 may also be p-type doped. Therefore, the semiconductor power device of the present application is an insulated gate bipolar transistor (IGBT) power device.
  • the n-type source region is the n-type emitter region of the IGBT power device
  • the p-type drain region is the p-type collector region of the IGBT power device.
  • an n-type collector region can also be formed on the bottom of the n-type semiconductor substrate 200 ( That is, the n-type drain region), the n-type collector region and the p-type collector region are arranged alternately at intervals.
  • an n-type field cut-off region 60 can also be formed on the p-type collector region.
  • IGBT power devices are commonly used structures in related technologies and will not be shown in detail in the implementation column of this application.
  • a semiconductor power device provided in the present application: a source contact hole located above a body region extends to a side of a first control gate to above a gate trench, so that the first control gate in the body region, the source region, and the gate trench,
  • the shielding gate can simultaneously connect the source voltage through the source metal layer in the source contact hole, thereby avoiding the formation of a source region between the source metal layer and the first control gate in the body region, and only in the body.
  • a source region between the source metal layer and the second control gate is formed in the region, which can reduce the limitation of the lithographic process conditions, can further reduce the spacing between adjacent gate trenches, and can improve the semiconductor substrate.
  • the bottom doping concentration reduces the on-resistance of the semiconductor power device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种半导体功率器件，包括：半导体衬底（200）；位于所述半导体衬底（200）中且依次间隔交替排列的栅沟槽（201）和体区（26）；位于所述栅沟槽（201）中的栅介质层（22）、第一控制栅（33）、第二控制栅（23）、隔离介质层（24）和屏蔽栅（25）；位于所述体区（26）中且靠近所述第二控制栅（23）一侧的源区（27）；位于所述体区（26）上方的一个源极接触孔（203），所述源极接触孔（203）向所述第一控制栅（33）一侧延伸至所述栅沟槽（201）上方；所述源区（27）、所述体区（26）、所述第一控制栅（33）和所述屏蔽栅（25）均通过所述源极接触孔（203）中的源极金属层（29）外接源极电压。

Description

半导体功率器件
本申请要求在2018年09月29日提交中国专利局、申请号为201811147326.1的中国专利申请，2018年09月29日提交中国专利局、申请号为201811147319.1的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于半导体功率器件技术领域，例如涉及一种半导体功率器件。
背景技术
图1是相关技术的一种半导体功率器件的剖面结构示意图，如图1所示，相关技术的一种半导体功率器件包括：n型半导体衬底100，位于n型半导体衬底100的底部的n型漏区10，位于n型半导体衬底100中且位于n型漏区10之上的n型漂移区11，位于n型半导体衬底100中的多个栅沟槽，位于相邻的所述栅沟槽之间的p型体区16，位于p型体区16中的n型源区17，位于所述栅沟槽中的栅介质层12、控制栅13、隔离介质层14和屏蔽栅15，控制栅13通常位于栅沟槽的上部的侧壁位置处并通过外部栅极电压来控制n型源区17与n型漂移区11之间的电流沟道的开启和关断。屏蔽栅15位于栅沟槽中并通过隔离介质层14与n型半导体衬底100和控制栅13隔离，屏蔽栅15通过源极金属层19与n型源区17连接，从而屏蔽栅15可以通过外部源极电压在n型漂移区11内形成横向电场，起到提高耐压的作用。层间绝缘层18用于将源极金属层19与栅极金属层隔离，基于剖面的位置关系，栅极金属层在图1中未示出。
相关技术的如图1所示的半导体功率器件，源极金属层19在p型体区16的中部位置与n型源区17和p型体区16接触，通常源极金属层19嵌入至p型体区16中，p型体区16中在源极金属层19的两侧都设有n型源区17，受光刻工艺条件的限制，相邻的栅沟槽之间的间距难以缩小。
发明内容
本申请提供一种半导体功率器件，以避免相关技术中的半导体功率器件中相邻的栅沟槽之间的间距难以缩小的情况。
本申请提供了一种半导体功率器件，包括：n型半导体衬底；位于所述n型半导体衬底中且依次间隔交替排列的p型体区和栅沟槽；分别位于所述栅沟槽的上部的两侧侧壁位置处的第一控制栅和第二控制栅，所述第一控制栅和所述第二控制栅分别通过栅介质层与所述半导体衬底隔离；位于所述栅沟槽的下部的屏蔽栅，所述屏蔽栅通过隔离介质层与所述半导体衬底、所述第一控制栅、所述第二控制栅隔离；位于所述p型体区中且靠近所述第二控制栅一侧的n型源区；位于所述p型体区上方的一个源极接触孔，所述源极接触孔向所述第一控制栅一侧延伸至所述栅沟槽上方，所述n型源区、所述p型体区、所述第一控制栅和所述屏蔽栅均通过所述源极接触孔中的源极金属层外接源极电压，所述第二控制栅外接栅极电压。
附图说明
为了更加清楚地说明本申请示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。显然，所介绍的附图只是本申请所要描述的一部分实施例的附图，而不是全部的附图。
图1是相关技术的一种半导体功率器件的一个实施例的剖面结构示意图；
图2是本申请提供的一种半导体功率器件的一个实施例的剖面结构示意图；
图3是本申请提供的一种半导体功率器件的一个实施例的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，通过具体方式，完整地描述本申请的技术方案。
应当理解，本申请所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的厚度，且所列图形大小并不代表实际尺寸；说明书附图是示意性的，不应限定本申请的范围。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制备引起的偏差等。
图2是本申请提供的一种半导体功率器件的一个实施例的剖面结构示意图。如图2所示，本申请实施列提供的一种半导体功率器件包括一个n型半导体衬 底200，n型半导体衬底200的材料通常为硅。位于n型半导体衬底200底部的n型漏区20。
位于n型半导体衬底200中且依次间隔交替排列的栅沟槽201和p型体区26，在本申请实施列中示例性的示出了6个栅沟槽201。位于每一个栅沟槽201中的栅介质层22、第一控制栅33、第二控制栅23、隔离介质层24和屏蔽栅25。第一控制栅33和第二控制栅23分别位于栅沟槽201的上部的两侧侧壁位置处，第一控制栅33和第二控制栅23分别通过栅介质层22与n型半导体衬底200隔离。屏蔽栅25屏蔽栅25位于栅沟槽201的下部，且屏蔽栅25通过隔离介质层24与n型半导体衬底200、第一控制栅33、第二控制栅23隔离，在一实施例中，屏蔽栅25和隔离介质层24覆盖栅沟槽201向上延伸至栅沟槽201的上部并且在栅沟槽201的上部将第一控制栅33和第二控制栅23分隔开，如图2所示。在一实施例中，栅沟槽201的上部的宽度大于栅沟槽201的下部的宽度，如图2所示。
屏蔽栅25与n型半导体衬底200之间的隔离介质层24的厚度可以和屏蔽栅25与第一控制栅33、第二控制栅23之间的隔离介质层24的厚度相同，也可以大于屏蔽栅25与第一控制栅33、第二控制栅23之间的隔离介质层24的厚度，图2中，仅示例性的示出了屏蔽栅25与n型半导体衬底200之间的隔离介质层24的厚度、屏蔽栅25与第一控制栅33之间的隔离介质层24的厚度、屏蔽栅25与第二控制栅23之间的隔离介质层24的厚度相同的结构。
通常，栅介质层22和隔离介质层24的材质分别为氧化硅，第一控制栅33、第二控制栅23和屏蔽栅25的材质分别为掺杂的多晶硅。
位于p型体区26中且靠近第二控制栅23一侧的n型源区27。位于p型体区26和n型漏区20之间的n型半导体衬底部分为半导体功率器件的n型漂移区21。
形成在层间绝缘层28中且位于p型体区26上方的一个源极接触孔203，源极接触孔203向第一控制栅33的一侧延伸至栅沟槽201的上方，使得p型体区26、n型源区27、第一控制栅33和屏蔽栅25通过源极接触孔203中的源极金属层29外接源极电压。
图2中，源极金属层29嵌入至p型体区26内，由此，n型源区27位于p型体区26中且介于源极金属层29与第一控制栅33之间。在一实施例中，源极金属层29可以不嵌入至p型体区26中，而是在p型体区内形成高掺杂浓度的 接触区，源极金属层通过该高掺杂浓度的接触区与p型体区接触连接，该结构为相关技术中经常使用的结构，本申请实施列中不再具体展示。
第二控制栅23通过栅极金属层外接栅极电压，第二控制栅23通过栅极电压来控制介于n型源区27和n型漂移区21之间的电流沟道的开启和关断。基于剖面的位置关系，图2中没有展示栅极金属层的具体结构。层间绝缘层28用于将源极金属层29与栅极金属层隔离，层间绝缘层28的材质通常为硅玻璃、硼磷硅玻璃或磷硅玻璃。
如图2所示的本申请提供的一种半导体功率器件，位于p型体区26上方的一个源极接触孔203向第一控制栅33的一侧延伸至栅沟槽201上方，这样p型体区26、n型源区27、第一控制栅33和屏蔽栅25可以同时通过源极接触孔203中的源极金属层29外接源极电压，从而可以避免在p型体区26内形成介于源极金属层29与第一控制栅33之间的n型源区，而只在p型体区26内形成介于第二控制栅23和源极金属层29之间的n型源区27，这能够减少光刻工艺条件的限制，可以进一步减小相邻的栅沟槽201之间的间距，进而在相同的工作电压条件下可以提高n型半导体衬底200的掺杂浓度，降低半导体功率器件的导通电阻。
本申请的半导体功率器件，位于n型半导体衬底200底部的漏区也可以为p型掺杂，由此，本申请的半导体功率器件为绝缘栅双极型晶体管(IGBT)功率器件，此时n型源区为IGBT功率器件的n型发射极区，p型漏区为IGBT功率器件的p型集电极区，此时，还可以在n型半导体衬底200底部形成n型集电极区(即n型漏区)，n型集电极区和p型集电极区依次间隔交替排布。同时参见图3，还可以在p型集电极区之上形成n型场截止区60，IGBT功率器件是相关技术中的常用结构，本申请实施列中不再详细展示。
本申请提供的一种半导体功率器件：位于体区上方的源极接触孔向第一控制栅一侧延伸至栅沟槽上方，这样体区、源区和栅沟槽中的第一控制栅、屏蔽栅可以同时通过该源极接触孔中的源极金属层外接源极电压，从而可以避免在体区内形成介于源极金属层与第一控制栅之间的源区，而只在体区内形成介于源极金属层和第二控制栅之间的源区，这能够减少光刻工艺条件的限制，可以进一步减小相邻的栅沟槽之间的间距，进而可以提高半导体衬底的掺杂浓度，降低半导体功率器件的导通电阻。
以上具体实施方式及实施例是对本申请提出的一种半导体功率器件的技术思想的具体支持，不能以此限定本申请的保护范围，凡是按照本申请提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本申请技术方案保护的范围。

Claims (9)

  1. 一种半导体功率器件，包括：
    n型半导体衬底；
    位于所述n型半导体衬底中且依次间隔交替排列的p型体区和栅沟槽；
    分别位于所述栅沟槽的上部的两侧侧壁位置处的第一控制栅和第二控制栅，所述第一控制栅和所述第二控制栅分别通过栅介质层与所述半导体衬底隔离；
    位于所述栅沟槽的下部的屏蔽栅，所述屏蔽栅通过隔离介质层与所述半导体衬底、所述第一控制栅、所述第二控制栅隔离；
    位于所述p型体区中且靠近所述第二控制栅一侧的n型源区；
    位于所述p型体区上方的一个源极接触孔，所述源极接触孔向所述第一控制栅一侧延伸至所述栅沟槽上方，所述n型源区、所述p型体区、所述第一控制栅和所述屏蔽栅通过所述源极接触孔中的源极金属层外接源极电压，所述第二控制栅外接栅极电压。
  2. 如权利要求1所述的半导体功率器件，其中，所述源极金属层嵌入至所述p型体区内，所述n型源区位于所述源极金属层与所述第二控制栅之间。
  3. 如权利要求1所述的半导体功率器件，其中，所述屏蔽栅与所述n型半导体衬底之间的隔离介质层的厚度大于或者等于所述屏蔽栅与所述第一控制栅之间的隔离介质层的厚度，所述屏蔽栅与所述n型半导体衬底之间的隔离介质层的厚度大于或者等于所述屏蔽栅与所述第二控制栅之间的隔离介质层的厚度。
  4. 如权利要求1所述的半导体功率器件，其中，所述屏蔽栅和所述绝缘介质层向上延伸至所述栅沟槽的上部并且在所述栅沟槽的上部将所述第一控制栅和所述第二控制栅分隔开。
  5. 如权利要求1所述的半导体功率器件，其中，所述栅沟槽的上部的宽度大于所述栅沟槽的下部的宽度。
  6. 如权利要求1所述的半导体功率器件，还包括位于所述n型半导体衬底底部的n型漏区。
  7. 如权利要求1所述的半导体功率器件，还包括位于所述n型半导体衬底底部的p型漏区。
  8. 如权利要求7所述的半导体功率器件，还包括位于所述n型半导体衬底底部的n型漏区，所述n型漏区和所述p型漏区依次间隔交替排布。
  9. 如权利要求7所述的半导体功率器件，还包括位于所述n型半导体衬底内且位于所述p型漏区上方的n型场截止区。
PCT/CN2019/108739 2018-09-29 2019-09-27 半导体功率器件 WO2020063918A1 (zh)

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Publication number Priority date Publication date Assignee Title
US20090096019A1 (en) * 2007-02-08 2009-04-16 Dev Alok Girdhar Mosgated power semiconductor device with source field electrode
CN103681853A (zh) * 2012-09-18 2014-03-26 株式会社东芝 半导体装置及其制造方法
CN107134489A (zh) * 2017-06-07 2017-09-05 无锡罗姆半导体科技有限公司 新型的场截止阳极短路型绝缘栅双极型晶体管
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CN107799601A (zh) * 2017-09-29 2018-03-13 上海华虹宏力半导体制造有限公司 屏蔽栅沟槽功率mostet器件及其制造方法

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Publication number Priority date Publication date Assignee Title
US20090096019A1 (en) * 2007-02-08 2009-04-16 Dev Alok Girdhar Mosgated power semiconductor device with source field electrode
CN103681853A (zh) * 2012-09-18 2014-03-26 株式会社东芝 半导体装置及其制造方法
CN107134489A (zh) * 2017-06-07 2017-09-05 无锡罗姆半导体科技有限公司 新型的场截止阳极短路型绝缘栅双极型晶体管
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