WO2020063735A1 - Technologie d'accès mémoire et système informatique - Google Patents

Technologie d'accès mémoire et système informatique Download PDF

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Publication number
WO2020063735A1
WO2020063735A1 PCT/CN2019/108122 CN2019108122W WO2020063735A1 WO 2020063735 A1 WO2020063735 A1 WO 2020063735A1 CN 2019108122 W CN2019108122 W CN 2019108122W WO 2020063735 A1 WO2020063735 A1 WO 2020063735A1
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Prior art keywords
data
value
dram
memory
stored
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PCT/CN2019/108122
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English (en)
Chinese (zh)
Inventor
基拉·卡夫
迪帕克·马修
奇拉格·苏尔达山
马赛厄斯·荣格
克里斯蒂安·韦斯
诺伯特·韦恩
朗诺斯·弗洛里安
李鸽子
杨伟
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华为技术有限公司
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Priority claimed from CN201811369316.2A external-priority patent/CN110968451B/zh
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2020063735A1 publication Critical patent/WO2020063735A1/fr
Priority to US17/217,570 priority Critical patent/US11521674B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Definitions

  • the present application relates to the field of computer technology, and in particular, to a memory access technology and a computer system.
  • DRAM Dynamic random access memory
  • Cell leakage cell leakage
  • Crosstalk Crosstalk
  • the memory controller design has a fixed refresh interval for each row, for example, the refresh interval can be 64ms.
  • the refresh interval needs to be reduced, which will cause frequent refresh of DRAM, increase system power consumption and occupy system bandwidth.
  • a memory access technology and a computer system provided in the present application can reduce the error probability of data stored in a DRAM memory.
  • the present application provides a memory access method. According to the method, after receiving the first data to be written into the dynamic random access memory DRAM, it is determined that the number of the first value in the first data is greater than the number of the second value, and it is determined that the DRAM is used to be high on the bit line. The first value is stored when voltage is applied and the second value is stored when the bit line is low voltage. In response to the above determination, the first data is inverted to obtain second data, and the second data is stored in the DRAM.
  • the above-mentioned memory access method provided in this application may determine whether the first data to be stored is inverted and stored according to the number of first and second values in the first data to be written into the DRAM memory and the storage mode of the DRAM. In order to reduce the number of high-charge memory cells in the dynamic random access memory DRAM, the error probability of the first data is reduced.
  • the first value in the first data is flipped to the second value, and the second value in the first data is flipped. Is the first value to obtain the second data.
  • the method described in this application can reuse the data bus flip DBI signal on the existing memory bus, making the method easier to implement.
  • the first or second possible implementation manner of the first aspect in a third possible implementation manner of the first aspect, is “1", and the second value Is "0"; or the first value is "0" and the second value is "1".
  • the method further includes, after receiving the read request, according to the first carried in the read request.
  • An address reads the second data from the DRAM. After determining that the second data is data stored after being inverted, the second data is inverted to obtain the first data.
  • the determining that the second data is data stored after being flipped includes: according to the second data, The flip flag in the ECC encoding determines that the second data is data stored after the flip.
  • the present application provides a computer device.
  • the computer device includes a dynamic random access memory DRAM, and a memory controller connected to the DRAM.
  • the memory controller is configured to execute the first aspect and any of the first aspects.
  • the present application provides a memory.
  • the memory includes a dynamic random access memory DRAM, a communication interface, and a flip module.
  • the DRAM is used to store data
  • the communication interface is connected to the DRAM, and is used to determine that the number of first values in the first data is greater than the number of second values, and to determine that the DRAM is used for high voltage on the bit line
  • the first value is stored at times and the second value is stored when the bit line is low voltage, and in response to the above determination, the first data is inverted to obtain the second data, and the second data is stored In the DRAM.
  • the inversion module is configured to invert the first value in the first data to the second value, and invert the The second value is inverted to the first value to obtain the second data.
  • the inversion module is configured to invert the first of the received data according to the indication of the DBI signal on the first data bus. A value is converted to a second value to obtain the second data.
  • the communication interface is further configured to receive a read request, and the read request carries a first address.
  • the flip module is further configured to determine that the second data read from the DRAM according to the first address is data stored after the flip, and in response to the above determination, flip the second data to obtain Said first data.
  • the first value is “1" and the second value is “0" ; Or the first value is "0" and the second value is "1".
  • the present application provides a memory access method.
  • the method includes, after receiving first data to be written into a dynamic random access memory DRAM, determining that the number of “1” in the first data is greater than the number of “0”.
  • the storage mode of the DRAM is a storage mode in which the stored data is logic "1" when the bit line is at a high voltage.
  • the first data is inverted to obtain second data, and the second data is stored in the DRAM.
  • the present application provides another memory access method.
  • the method includes, after receiving third data to be written into the dynamic random access memory DRAM, determining that the number of "1" in the third data is less than "0".
  • the storage mode of the DRAM is a storage mode in which data is stored at logic "0" when the bit line is at a high voltage.
  • the third data is inverted to obtain fourth data, and the fourth data is stored in the DRAM.
  • the memory access method may determine whether the data to be stored is inverted and stored according to the number of "1" and "0" in the data to be written into the DRAM memory, and the storage mode of the DRAM. In order to reduce the number of high-charge memory cells in the dynamic random access memory DRAM, the probability of data errors is reduced.
  • the present application further provides a computer program product including program code, and the instructions included in the program code are executed by a computer to implement the method described in the first aspect or the second aspect.
  • the present application further provides a computer-readable storage medium for storing program code, and the instructions included in the program code are executed by a computer to implement the foregoing first aspect, the first The method described in the fourth aspect, or the fifth aspect.
  • FIG. 1 is a schematic diagram of a computer system architecture according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a memory controller according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a data flipping method according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of still another memory controller according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of still another computer system according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of a method for reading data according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of writing data according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of reading data according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of a memory access method according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a computer system architecture according to an embodiment of the present invention.
  • the computer system 100 may include at least a processor 102, a memory controller 106, and a memory 108.
  • the memory controller 106 may be integrated in the processor 102.
  • the computer system 100 may further include a communication interface and other devices such as an externally stored magnetic disk, which is not limited herein.
  • the processor 102 is a computing core and a control core of the computer system 100.
  • the processor 102 may include a plurality of processor cores 104.
  • the processor 102 may be a very large-scale integrated circuit.
  • An operating system and other software programs are installed in the processor 102, so that the processor 102 can implement access to the memory 108, cache, and disk.
  • the Core 104 in the processor 102 may be, for example, a central processing unit (CPU), or other specific integrated circuit (Application Specific Integrated Circuit, ASIC).
  • the memory controller 106 is a bus circuit controller that controls the memory 108 internally of the computer system 100 and is used to manage and plan data transmission from the memory 108 to the Core 104. Through the memory controller 106, data can be exchanged between the memory 108 and the Core 104.
  • the memory controller 106 may be a separate chip and connected to the Core 104 through a system bus. Those skilled in the art may know that the memory controller 106 may also be integrated into the processor 102 (as shown in FIG. 1) or may be built into the Northbridge. The embodiment of the present invention does not limit the specific position of the memory controller 20. In practical applications, the memory controller 106 may control necessary logic to write data to or read data from the memory 108.
  • the memory 108 is the main memory of the computer system 100.
  • the memory 108 is connected to the memory 108 through a double data rate (DDR) bus.
  • the memory 108 is generally used to store various running software in the operating system, input and output data, and information exchanged with external storage. In order to improve the access speed of the processor 102, the memory 108 needs to have the advantage of fast access speed.
  • dynamic random access memory DRAM
  • the processor 102 can access the memory 108 at a high speed through the memory controller 106, and perform a read operation and a write operation on any storage unit in the memory 1080.
  • the memory 108 is described as an example of DRAM. Therefore, the memory 108 may also be referred to as a DRAM 108.
  • the data is stored in a storage unit (also called a DRAM cell) of the DRAM 108.
  • the storage unit refers to the smallest storage cell (cell) for storing data.
  • a memory cell can store 1 bit of data.
  • some storage units can also implement multi-value storage.
  • DRAM uses the amount of storage capacity of the capacitor to represent data 0 and 1. Due to the leakage phenomenon of the capacitor, if the charge in the capacitor is insufficient, the stored data will be wrong.
  • the memory controller 106 refreshes the data in the DRAM 108 to prevent the DRAM 108 from losing data.
  • DRAM 108 is volatile. When the computer system 100 is powered off, the information in DRAM 108 will no longer be saved.
  • the DRAM cells in the DRAM 108 are arranged into a matrix. This matrix is called DRAM bank.
  • the memory controller 106 can locate any bit in the DRAM bank through the corresponding row and column decoder.
  • Multiple DRAM banks can form a DRAM chip (also known as a memory chip), and multiple DRAM chips can form a DRAM rank.
  • Multiple DRAM ranks can be integrated into a dual-inline-memory-modules (DIMM).
  • the DRAM 108 may include a plurality of channels 110. Each channel 110 may include at least one rank, and each rank may include at least one bank.
  • Each bank includes multiple storage units for storing data.
  • rank refers to a memory chip connected to the same chip select signal.
  • the memory controller 106 can write to chips in the same rank, and chips in the same rank also share the same control signals.
  • the memory controller 106 can respectively access the data in the memory cells in the various channels in the DRAM 108 through the memory bus.
  • the memory cells in a DRAM bank are connected to a word line and a bit line, respectively.
  • the word line connects multiple memory cells in the horizontal direction
  • the bit line is used to connect multiple memory cells in the vertical direction. unit.
  • the word line is used to enable the memory cell
  • the bit line is used to charge the capacitor in each memory cell, so that the amount of storage capacity of the capacitor can be used to represent the data 0 and 1. It can be understood that when the bit line is at a high level, there is more electric energy stored in the capacitor, or in other words, there is more electric charge in the capacitor. When the bit line is low, there is less power stored in the capacitor, or less charge in the capacitor.
  • a DRAM memory cell can be considered as a noise channel.
  • the inventor found in the process of implementing the present invention that data error conditions in DRAM can be divided into two types, one is that the data changes from logic 0 to logic 1 and the other is that the data changes from logic 1 to logic 0.
  • Studies have shown that assuming that the amount of charge in a DRAM memory cell is high in logic 1, the probability of the data changing from logic 0 to logic 1 is much smaller than the probability of changing logic 1 to logic 0. Therefore, reducing the number of memory cells storing high charges in the DRAM array can greatly reduce the error probability of the DRAM array.
  • FIG. 2 is a schematic structural diagram of a memory controller according to an embodiment of the present invention.
  • the memory controller 106 may include a communication interface 1061, an ECC module 1062, and a flip module 1063.
  • the communication interface 1061 may be implemented based on an existing DDR bus interface protocol.
  • the communication interface 1061 is configured to receive data to be written and sent to the memory DRAM 108 by the Core 104.
  • the ECC module 1062 is configured to check and correct the data to be written received by the communication interface 1061 to obtain the ECC code of the data to be written.
  • the flip module 1063 may be used to execute the data flip method shown in FIG. 3.
  • FIG. 3 is a flowchart of a data reversing method according to an embodiment of the present invention. Specifically, as shown in FIG. 3, the method may include the following steps. It can be understood that the data inversion method shown in FIG. 3 may also be referred to as a memory access method provided by an embodiment of the present invention.
  • step 302 first data to be written into a memory is received.
  • the memory controller 106 can receive the first data sent by the core 104 through the communication interface 1061 between the memory controller 106 and the core 104.
  • the size of the first data may be determined according to a bandwidth of the DDR bus.
  • the first data may be 64 bits or 32 bits. The size of the first data is not limited herein.
  • step 304 it is determined whether the number of "1" in the first data is greater than the number of "0". When the number of “1” in the first data is greater than the number of “0”, the method proceeds to step 306. When the number of “1” in the first data is less than the number of “0”, the method proceeds to step 308.
  • step 306 it is determined whether the storage mode of the DRAM is a first mode, where the first mode is used to indicate that the corresponding data when the amount of charge in the capacitor in the storage unit is high is a storage form of logic "1" .
  • the method proceeds to step 310.
  • the storage mode of the DRAM is not the first mode, the method proceeds to step 314.
  • the memory module of the DRAM may include a first mode and a second mode, wherein the first mode may also be referred to as a true cell bit storage mode, and the true cell bit storage mode refers to a DRAM array
  • the second mode may also be referred to as an anti-cell bit storage mode.
  • the anti-cell bit storage mode refers to a storage form in which the data corresponding to a higher amount of charge in the capacitance of a memory cell is a logic "0".
  • the true cell bit storage mode refers to a storage mode that stores a logic “1” when the bit line is high voltage and a logic “0" when the bit line is low voltage.
  • the anti-cell bit storage mode refers to a storage mode that stores a logic "1” when the bit line is at a low voltage and a logic “0” when the bit line is at a high voltage.
  • the first mode is a storage mode in which data is stored at a logic “1” when the bit line is at a high voltage
  • the second mode is a storage mode in which data is stored at a logic “0” when the bit line is at a high voltage. Storage mode. It should be noted that the storage mode of the DRAM can be obtained according to the factory information provided by the manufacturer of the DRAM chip, or it can be detected by itself.
  • step 304 If it is determined in step 304 that the number of "1" in the first data is greater than the number of "0”, and in this step, it is determined that the storage data is a logical "1" storage when the bit line is a high voltage Mode, the method proceeds to step 310. If it is determined in this step that the storage mode is a storage mode in which the stored data is a logic “0” when the bit line is at a high voltage, the method proceeds to step 314.
  • step 308 it is determined whether the storage mode of the DRAM is a first mode, where the first mode is used to indicate that when the amount of charge in the capacitance of the storage unit is high, the corresponding data is a logical "1" storage .
  • the method proceeds to step 314.
  • the storage mode of the DRAM is not the first mode, the method proceeds to step 310. Specifically, if it is determined in step 304 that the number of "1" in the first data is less than the number of "0”, and if it is further determined in this step that the storage mode is that the bit line is high voltage, the stored data is If the storage mode is logic “1”, the method proceeds to step 314.
  • the method proceeds to step 310.
  • step 310 the data of each bit in the first data is flipped to obtain the second data, and the process proceeds to step 312.
  • the logical "1" in the first data may be inverted to a logical "0”
  • the logical "0" in the first data may be inverted to a logical "1"
  • the data obtained by inverting the first data is referred to as the second data.
  • this can be achieved using a flip circuit.
  • the flip circuit can be implemented by negating the value of each bit through an NOT gate array.
  • the second data is written into a memory cell of the DRAM.
  • the memory controller may send the flipped second data to the memory 108, and carry the flipped identifier in the ECC code obtained by the ECC module to the memory 108, and the memory 108 may store the obtained second data and the ECC code.
  • the flip flag is used to indicate whether the received first data is flipped.
  • the flip flag is used to indicate whether the second data stored in the DRAM is the flipped data.
  • the flip flag may be carried in the ECC code, and whether the second data is the flipped data is indicated by a preset bit in the preset ECC code.
  • the identification of the flip flag is not specifically limited. For example, a logic “1” may be used to indicate that the first data is flipped, and a logic “0” may be used to indicate that the first data is not flipped.
  • step 314 the first data is written into the DRAM. Specifically, the memory controller writes the first data and the ECC code obtained by the ECC coding module according to the first data into a storage unit of the DRAM.
  • the following four situations may occur.
  • step 304 it can be known in combination with steps 304, 308, and 310 that if it is determined in step 304 that the number of "1" in the first data is less than the number of "0", and in step 308, If the storage mode of the DRAM is a storage mode where the data stored when the bit line is at a high voltage is a logic "0", it means that after the first data is written into the DRAM, a high charge is stored in a memory cell for storing the first data There are also more storage units, which may increase the probability of data errors in the storage units. Therefore, in this case, data of each bit in the first data needs to be stored after being inverted.
  • step 304 it is further determined that the storage mode of the DRAM is not a storage mode where the data stored when the bit line is high voltage is a logic "1", but a storage mode where the data stored when the bit line is high voltage is a logic "0" , It means that after the first data is written into the DRAM, there are not many high-charge memory cells in the memory cells used to store the first data. In this case, the probability of error is not high, so there is no need to The first data is stored after being inverted.
  • step 304 if it is determined in step 304 that the number of "1" in the first data is less than the number of "0", and in step 308, it is further determined that the storage mode of the DRAM is a storage mode in which the data stored when the bit line is at a high voltage is a logic "1", then the first data is written into the DRAM to store the first data.
  • the probability of error is not high, so there is no need to store the first data after it is inverted.
  • whether to treat the data may be determined according to the number of logical "1" and logical "0" in the data to be written and the storage mode of the DRAM.
  • the stored data is stored after being inverted, so that after the data is stored in the DRAM, the number of high-charge memory cells in the DRAM array can be reduced, and the probability of data errors is reduced.
  • the embodiment of the present invention uses the first data as an example to describe different situations that may occur when writing one data to a DRAM having different storage modes.
  • the first data is written to In the first DRAM, the first situation described in steps 304, 306, and 310 may occur.
  • the second situation described in steps 304, 308, and 310 may occur.
  • the third data may be inverted to obtain the fourth data And writing the obtained fourth data into the second DRAM to reduce the number of high-charge memory cells in the second DRAM and reduce the error probability.
  • the third and fourth situations described above may also occur.
  • the flip flag may be carried in the ECC code, and a preset bit in the preset ECC code is used to indicate whether the first data to be written to the DRAM is flipped and stored. .
  • 8-bit ECC encoding is required for 64-bit data.
  • a part of 8 bits can be used as a flip flag.
  • the last 1 bit in the ECC code may be used as the flip flag, and the last 2 or 3 bits in the ECC code may be used as the flip flag.
  • the number of bits occupied by the flip flag can be determined according to specific conditions.
  • how many bits of the flip flag are needed can be determined according to the size of the data to be flipped. For example, assuming that the size of the first data is 64 bits, and the 64 bits are also inverted when performing the inversion, one bit in the ECC encoding may be used as the inversion identifier. If the inversion is performed to determine whether the inversion is performed on the upper 32 bits and the lower 32 bits in the first data respectively, 2 bits in the ECC encoding may be used as the inversion flag.
  • the first data is data of 64 bits.
  • the first data may be sent to the ECC module 1062 and the flip module 1063, respectively.
  • the ECC module 1062 performs ECC processing on the first data to obtain a 6-bit ECC code.
  • the flip module 1063 may process the high 32-bit and low 32-bit of the first data respectively according to the method shown in FIG. 3 described above, to determine whether to flip and store the high 32-bit and low 32-bit data, and generate a 2-bits flip flag.
  • 1 bit in the flip flag is used to indicate whether the data of higher 32 bits in the first data is flipped, and the other 1 bit is used to indicate whether the data in the lower 32 bits of the first data is flipped. It can be understood that no matter whether the first data is inverted, the data generated by the memory controller to the memory 108 is 64 bits.
  • the memory controller 106 may send the 64-bits data, the 6-bit ECC code, and the 2-bit flip flag to the memory 108 for storage in the storage unit of the DRAM. Specifically, during the transmission, the memory controller 106 can transmit the 64-bit data to be stored and the DRAM through DQ [63: 0] on the DQ line, and transmit the 6-bit ECC code through DQ [69:64], and pass DQ [71:70] transmits the flip flag.
  • the flip flag and the ECC code can be stored together in the ECC memory chip area. It can be seen from the above embodiments that since the data inversion and ECC encoding are performed in parallel in this embodiment, no additional inversion delay is introduced.
  • FIG. 4 is a schematic structural diagram of another memory controller 106 according to an embodiment of the present invention.
  • the memory controller shown in FIG. 4 includes a data queue 1064 in addition to the communication interface 1061, the ECC module 1062, and the flip module 1063 shown in FIG. Still taking the above-mentioned first data of 64bits as an example, in the memory controller shown in FIG. 4, after the communication interface 1061 receives the first data, the first data can be used by the flip module 1063 according to the above FIG.
  • the method shown determines whether to perform a flip process and obtains a flip flag.
  • the data processed by the inversion module 1063 and the inversion flag may be sent to the data queue 1064 and the ECC module 1062, respectively.
  • the data processed by the inversion module includes the second data obtained by inverting the first data, and may also refer to the first data that is not inverted.
  • the ECC module 1062 can perform ECC encoding on the data processed by the flip module 1063 and the flip flag.
  • the data processed by the flip module 1063, the flip flag, and the ECC code in the data queue 1064 can be sent to the memory together. 108 for storage. It can be understood that the embodiment shown in FIG.
  • the ECC module 1062 only encodes the input first data
  • the ECC module may perform ECC processing on the data processed by the inversion module 1063 and the obtained inversion identifier to obtain an ECC code.
  • the above embodiment is described by using the data inversion method shown in FIG. 3 in a memory controller as an example.
  • the memory access method provided by the embodiment of the present invention may also be implemented in a DRAM memory module.
  • the following describes still another implementation method provided by an embodiment of the present invention with reference to FIGS. 3 and 5.
  • the existing DDR4 has DBI technology, which is mainly used to invert data on the bus to reduce power consumption when data is transmitted on the bus. If the embodiment shown in FIG. 5 is designed based on a DBI scheme in an existing computer system.
  • FIG. 5 is a schematic structural diagram of a computer system according to an embodiment of the present invention.
  • the memory controller 106 in the computer system shown in FIG. 5 includes a communication interface 1061, an ECC module 1062, and a main DDR physical layer interface (PHY) 1065.
  • the communication interface 1061 is configured to communicate with the core 104 and receive first data to be written into the memory 108 sent by the core 104.
  • the ECC module 1062 is configured to perform an ECC check on the first data to obtain an ECC code.
  • the main DDR physical layer interface (also known as the main DDR PHY) 1065 is a physical layer interface connected to the memory 108 on the host side.
  • the main DDR PHY1065 has a Data Bus Inversion (DBI) function.
  • DBI Data Bus Inversion
  • the existing DBI technology less power consumption is required when transmitting logic "1" on the bus. Therefore, the existing DBI technology will determine whether to be transmitted according to the number of "1" in the data to be transmitted. The data is transferred in reverse.
  • the master DDR 1065 on the memory controller 106 side and the slave DDR physical layer interface on the memory 108 side have DBI functions.
  • the main DDR PHY 1065 on the side of the memory controller 106 is mainly used to detect the number of “1” in the data sent by the memory controller 106 to the memory 108 to determine whether it is necessary to perform a post-flip transmission.
  • the dbi_n signal is used to notify whether the data received from the DDR physical layer interface (from the DDR PHY) 1081 in the memory 108 is the data that is transmitted by being inverted. It should be noted that, in the computer system shown in FIG. 5, the structure of the memory controller 106 is not changed.
  • the memory 108 in the computer system shown in FIG. 5 includes a slave DDR physical layer interface (PHY) 1081 and a DRAM array 1084 connected to the slave DDR 1081.
  • the DDR PHY 1081 may include a flip module 1082 and a second DBI module 1083.
  • the DRAM array 1084 includes a plurality of DRAM ranks, and each rank includes a plurality of DRAM storage cells (also referred to as: DRAM cells) for storing data.
  • the second DBI module 1082 is a DBI module corresponding to the first DBI module 1066 on the memory controller 106 side, and is used to reverse the received data according to the dbi_n signal after the first DBI module 1066 implements the reverse transmission of the first data.
  • the first DBI module 1066 does not perform the flip transmission on the first data
  • the second DBI module also does not perform flip processing on the data it receives according to the received dbi_n signal.
  • the data output by the second DBI module is the data to be stored that the core 104 sends to the memory controller.
  • a flip module 1083 is added to the existing DDR PHY 1081.
  • the inversion module 1083 is configured to receive the data processed by the second DBI module 1082 and process the data input to the inversion module 1083 according to the data inversion method shown in FIG. 3.
  • the flip module 1083 may reuse the dbi_n signal indication sent by the main DDR 1065 to determine whether the data output by the second DBI module 1082 needs to be flipped and stored.
  • the first data is still used as an example for description. Because DBI technology is to ensure that there are as many logic "1" s transmitted on the bus as possible to reduce the power consumption of the bus transmission. Therefore, when the received dbi_n signal from the second DBI module 1083 in the secondary PHY 1081 indicates that the primary DDR PHY 1065 has not reversed the transmission of the first data, it means that the number of logic "1" in the first data is greater than The number of "0". When the received dbi_n signal from the second DBI module 1083 in the slave PHY 1081 indicates that the master DDR 1065 has reversed the transmission of the first data, it means that the number of logic "1" in the first data is less than logic "0 "quantity.
  • the flip module 1083 After obtaining the ratio of the number of logic “1” in the data to be stored, the flip module 1083 further determines whether the data output by the second DBI module needs to be flipped and stored in the DRAM according to the storage mode of the DRAM array.
  • the dbi_n signal may also be referred to as a data bus inversion DBI signal.
  • the inversion module 1083 only reuses the dbi_n signal in the existing DBI function to judge the logic "1" and logic "0" in the data to be stored The number of sizes without the need to detect it by yourself.
  • FIG. 5 is described with the flip module 1083 located in the slave PHY 1081. In practical applications, the flip module 1083 may also exist independently of the slave PHY 1081. It is not limited here.
  • the above embodiment describes the data flip processing method from the process of writing data.
  • the following will briefly introduce the process of reading data.
  • the data reading method described in FIG. 6 may be used for processing.
  • the method for reading data may include the following steps.
  • step 602 a read request sent by a host is received, and the read request carries an address of data to be read.
  • the second data and the corresponding ECC code are read from the memory according to the address.
  • the embodiment of the present invention is described by using the second data stored in the foregoing data writing process as an example.
  • step 606 it is determined that the second data is the data stored after the inversion according to the inversion identifier in the ECC encoding.
  • step 608 the second data is decoded to obtain the first data. Specifically, the second data is flipped according to the flip flag to obtain the first data.
  • the above-mentioned method for reading data may be implemented by the memory controller 106, and specifically may be implemented by the flip module 1063 in the memory controller 106 shown in FIG. 2 and FIG. 4, or may be implemented by the memory 108 It is realized by turning over the module 1083. It is not limited here. In practical applications, the flip module 1083 in the memory controller 106 shown in FIG. 5 may also exist independently of the memory controller.
  • the flip module 1083 in FIG. 5 is not necessary, and the second DBI module 1082 in the DDR PHY 1081 can be directly multiplexed to implement the method shown in FIG. 3.
  • the memory controller can generate two flags to separately control the DBI function of the host and the DBI function of the memory module.
  • the memory controller generates a flip flag from the number of 1 in the data to notify the DBI function of the host whether to perform a data flip operation.
  • the memory controller also generates a dbi_n signal from the mapping relationship between the address and the Anti Cell / True cell in parallel and sends it directly to the memory module to control whether the module performs a flip operation.
  • the final data, flip flag (flip flag) and ECC code are all stored in the DRAM particles.
  • the first data is 0000 and 1111 are taken as examples to describe how to write data into DRAMs of different storage modes in combination with the DBI function.
  • the memory controller In the first case, assuming that the first data is “0000” and the storage mode of the DRAM corresponding to the address where the first data is to be stored is true, the memory controller generates a flip.
  • the identification bit (such as the flip identification bit in FIG. 7) and the dbi_n signal, wherein the flip identification bit (flip) is 1, and the dbi_n signal is 1.
  • the flip flag is used to instruct the first DBI module 1066 (the host-side DBI module) in the memory controller 106 shown in FIG. 5 to perform a flip operation. As mentioned before, the flip flag can be carried in the ECC encoding of the first data.
  • the first DBI module 1066 When the first DBI module 1066 receives the first data and the ECC encoding of the first data, the first data "0000” is inverted according to the flip flag to obtain data "Data”: “1111”, and The inverted data “1111” is transmitted to the second DBI module 1082 in the DDR HPY through the memory bus. And, the memory controller sends the dbi_n signal to the second DBI module 1082 in the DDR HPY through the memory bus. When the second DBI module 1082 receives the dbi_n signal, it will invert the data Data ': “1111” received from the memory bus to obtain the data "Data”: 0000, and the inverted data "Data”: 0000 Stored in a memory cell of a DRAM array. Among them, the data “” after the data is turned over: 0000 is the same as the first data. According to this method, when the first data is 0000 and the storage mode is true, the data may not be stored when the data is stored. Perform flip storage
  • the memory controller when the first data Data is "1111" and the storage mode corresponding to the address of the first data is true, the memory controller generates a flip flag of 0, and the generated The dbi_n signal is 1. According to the flip identification, the first DBI module 1066 on the host side will not flip the first data, but directly transmits the first data “1111” through the memory bus.
  • the second DBI module 1082 receives the first data "1111” and the dbi_n: 1 signal, the second DBI module 1082 will flip the received first data according to the dbi_n signal, and after the flip is obtained, The second data (Data): 0000 is stored in the DRAM array. According to this method, when the first data is "1111" and the storage mode is true, the existing memory can be reused.
  • the DBI module (such as the second DBI module 1082 in FIG. 5) inverts the first data to be stored and stores the first data.
  • the memory controller when the first data Data is 0000 and the storage mode corresponding to the memory address to store the first data is an anti-cell storage mode, the memory controller generates a flip flag of 1 and generates The dbi_n signal is 0.
  • the host-side DBI module (such as the first DBI module 1066 in FIG. 5) flips the first data "0000" according to the flip identifier to obtain Data ': 1111, and passes the flipped data Data': 1111 through The memory bus is sent to the second DBI module 1082 in the memory.
  • the second DBI module 1082 After the second DBI module 1082 receives the data Data ': 1111, since the dbi_n signal is 0, the second DBI module 1082 does not flip the received data Data': 1111, and directly turns the memory controller side
  • the data of the first DBI module 1066 after the inversion Data ': 1111 is stored in a storage unit of the DRAM array. In this case, when the first data is "0000" and the storage mode is anticell, the data can be reused by multiplexing the first DBI module 1066 in the existing memory controller shown in FIG. 5 to the data. Storing data as a result of the flip can also achieve the effect of reducing the error rate of the data.
  • the memory controller when the first data Data is 1111 and the storage mode corresponding to the memory address to store the first data is an anti-cell storage mode, the memory controller generates a flip identifier. Is 0, and the generated dbi_n signal is 0.
  • the host-side DBI module (such as the first DBI module 1066 in FIG. 5) does not transmit the first data "1111" according to the flip identifier.
  • the second DBI module 1082 on the memory side receives data from the memory bus, After 1111 (see Data ': 1111 in Figure 7) and the dbi_n signal, since the dbi_n signal is 0, it is used to indicate that the received data is not inverted.
  • the second DBI module 1082 will not perform the first data received.
  • the 1111 is reversed, and the first data 1111 (see Data ": 1111 in Fig. 7) can be directly stored in the DRAM array.
  • the first data is" 1111 "and the storage mode is In the case of an anti-cell, neither the first DBI module nor the second DBI module need to flip the first data.
  • the above description takes the first data as "0000” and "1111” as examples.
  • the first data is stored in the DRAM and anti of the true cell respectively.
  • a case where flip memory is required in a cell's DRAM is described in detail. It can be understood that the data "1111” is only an example of the first data whose number of "1” is greater than the number of "0”, and "0000" is also only the first data whose number of "0” is greater than the number of "1” An example.
  • true cell refers to a storage mode where the bit line is at a high voltage when the data is "1”
  • anti cell refers to a storage mode where the bit line is at a high voltage when the data is "0”.
  • the flip flag bit is “1” to indicate that data needs to be flipped
  • the flip flag bit is “0” to indicate that data needs not to be flipped.
  • the dbi_n signal is “1” to indicate that data needs to be inverted
  • the dbi_n signal is “0” to indicate that data is not to be inverted.
  • the flip flag bit can be “0” to indicate that data needs to be flipped
  • the dbi_n signal is “0” to indicate that data needs to be flipped. It is not limited here.
  • FIG. 7 uses a DBI module in an existing computer system as an example to describe how to write data to reduce the probability of error in storing data.
  • Figure 8 will briefly introduce how to read data from the multiplexed DBI module.
  • the memory controller sends a read request and a dbi_n signal to the memory module.
  • the memory module receives the dbi_n signal, it configures whether the DBI module of the DDR PHY (such as the second DBI module 1082 in FIG. 5) turns the read data.
  • the DBI module through the memory module is flipped, and then the corresponding data, flip flag (flip flag bit) and ECC code are returned to the host-side DRR PHY.
  • the host uses the DQ line corresponding to the flip flag bit to determine whether to perform data flipping on the received data.
  • the data and ECC are returned to the memory controller.
  • the first data is read, and the first data is 0000 and 1111, respectively. How to read data from DRAMs of different storage modes in combination with the DBI function is described as an example.
  • the dbi_n signal can be configured to “1” to indicate the DBI module in the memory (as shown in FIG. 5).
  • the second DBI module 1082) inverts the data.
  • the first data is "0000” and the storage mode is True cell storage mode
  • the data stored in the DRAM array is Data ": 0000, and the flip flag in the ECC encoding is 1 Therefore, in the process of reading data, as shown in FIG.
  • the read process shown in FIG. 8 is an opposite process to the corresponding write process in FIG. 7.
  • the process of reading data 1111 from the True Cell DRAM can be seen in the diagram of the second case in Figure 8.
  • the process of reading the data 0000 from Anti Cell's DRAM can be seen in the diagram of the third case in Figure 8.
  • For the process of reading data 1111 in the cell's DRAM refer to the illustration of the fourth scenario in FIG. 8.
  • the second to fourth situations in FIG. 8 reference may be made to the specific description of the first situation, and details are not described herein again.
  • the dbi_n signal when the storage mode is True cell mode, the dbi_n signal is configured to be “1”, which is used to instruct the second DBI module in the memory to perform the received data. Flip. When the storage mode is the Anti cell mode, the dbi_n signal is configured to be "0", which is used to instruct the second DBI module in the memory not to flip the received data.
  • the data received by the second DBI module includes data sent from the memory controller received from the memory bus, and also includes data read from the DRAM array. In practical applications, the dbi_n signal can also be "0" to instruct the second DBI module in the memory to flip the received data.
  • the embodiment of the present invention does not limit the specific identification of the dbi_n signal.
  • FIG. 9 is a flowchart of a memory access method according to an embodiment of the present invention. As shown in FIG. 9, the method may be executed by a memory controller, or may be a flip module (also referred to as a flip circuit) in a memory module. carried out. For convenience of description, the method shown in FIG. 9 is described below by taking a memory controller as an example.
  • the memory controller receives first data to be written into the dynamic random access memory DRAM.
  • the storage mode of the DRAM is a storage mode in which the stored data is the first value when the bit line is at a high voltage.
  • the first value or the second value is used to indicate a bit value in the first data. For example, in one case, the first value is “1" and the second value is "0". In another case, the first value is "0" and the second value is "1".
  • the memory controller inverts the first data to obtain the second data in response to the judgment. Specifically, the memory controller needs to invert the first value "1" in the first data to the second value "0", and invert the second value "0" in the first data to the first value. "1” to get the second data. Then in step 908, the second data is stored in the DRAM.
  • the storage mode of the DRAM is a storage mode in which the data is "1" when the bit line is at a high voltage (that is, a true cell storage mode)
  • the second data is stored in the DRAM, the The number of high charges in the memory cell storing the second data in the DRAM is relatively small, and the probability of the second data being wrong will be less than the error probability of the first data.
  • the memory controller when the first value is “0" and the second value is “1”, if the storage mode in the DRAM is a high voltage on the bit line, the stored data is the first value (that is, “0” ”) Storage mode (that is, the aforementioned Anti-cell storage mode), in step 906, the memory controller also responds to the above determination, and inverts the first data to obtain the second data. Specifically, the memory controller needs to invert the first value "0" in the first data to the second value "1”, and invert the second value "1” in the first data to the first value. "0” to get the second data. Then in step 908, the second data is stored in the DRAM.
  • the storage mode of the DRAM is a storage mode in which data is stored as "0" when the bit line is at a high voltage (that is, an anti-cell storage mode)
  • the second data is stored in the DRAM, the The number of high charges in the memory cell storing the second data in the DRAM is relatively small, and the probability of the second data being wrong will be less than the error probability of the first data.
  • the number of the first numerical values in the first data may be greater than the number of the second numerical values according to the data bus inverting the DBI signal (that is, the dbi_n signal in the foregoing embodiment).
  • the DBI signal is used to indicate whether data needs to be transmitted in reverse. When the number of "1" in the data is greater than the number of "0", the power consumption of the bus transmission is small.
  • the first value when the first value is “1” and the second value is “0”, it can be determined that the number of the first value in the first data is greater than A second value, wherein the first DBI signal is used to indicate that the first data is data that does not need to be transmitted on a data bus after being inverted.
  • the first value when the first value is "1” and the second value is “0”, it can be learned from the first DBI signal that the number of "1" in the first data is greater than "0”, The first data does not need to be flipped and transmitted, and bus transmission power consumption can be saved.
  • the first value When the first value is “0" and the second value is “1”, it can be judged according to the second data bus that the DBI signal is inverted. The number of the first value in the data is greater than the second value. Quantity, wherein the second DBI signal is used to indicate that the first data is data to be transmitted on the data bus after being inverted. Put another way, when the first value is "0" and the second value is “1", it can be learned from the second DBI signal that the number of "0" in the first data is greater than "1", The first data needs to be inverted and transmitted to save bus transmission power consumption.
  • the storage mode of the DRAM chip in the DRAM array of data determines whether the data to be stored is inverted and stored to reduce the number of high-charge storage cells in the DRAM array and reduce the data error rate.
  • the device embodiments described above are only schematic.
  • the division of the modules is only a logical function division, and there may be another division manner in actual implementation.
  • multiple modules or components can be combined or integrated into another system, or some features can be ignored or not implemented.
  • the connections between the modules discussed in the above embodiments may be electrical, mechanical, or other forms.
  • the modules described as separate components may or may not be physically separated.
  • the component displayed as a module may or may not be a physical module.
  • each functional module in each of the applied embodiments may exist independently or be integrated into a processing module.
  • An embodiment of the present invention further provides a computer program product for data processing, including a computer-readable storage medium storing program code, where the program code includes instructions for executing the method flow described in any one of the foregoing method embodiments.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a magnetic disk, an optical disk, a random access memory (RAM), a solid state hard disk (Solid State Disk, SSD), or a nonvolatile Various non-transitory machine-readable media such as memory (non-volatile memory) that can store program code.

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Abstract

La présente invention porte sur un procédé d'accès mémoire et sur un système informatique. Le procédé d'accès mémoire peut déterminer, sur la base du nombre de « 1 » et de « 0 » dans des données à écrire dans une mémoire DRAM et un mode de stockage de mémoire DRAM, si des données à stocker doivent être mises en rotation et stockées, ce qui permet de réduire le nombre d'unités de stockage dans la mémoire DRAM transportant une charge élevée, et de réduire ainsi la probabilité d'erreur de données.
PCT/CN2019/108122 2018-09-30 2019-09-26 Technologie d'accès mémoire et système informatique WO2020063735A1 (fr)

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CN1518742A (zh) * 2001-06-11 2004-08-04 ģ��װ�ù�˾ 带位线预先充电、反转数据写入、保存数据输出的低功耗动态随机存取存储器
CN106406767A (zh) * 2016-09-26 2017-02-15 上海新储集成电路有限公司 一种非易失性双列直插式存储器及存储方法
CN108369819A (zh) * 2015-12-09 2018-08-03 英特尔公司 在自刷新模式期间附加刷新操作的执行

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Publication number Priority date Publication date Assignee Title
CN1518742A (zh) * 2001-06-11 2004-08-04 ģ��װ�ù�˾ 带位线预先充电、反转数据写入、保存数据输出的低功耗动态随机存取存储器
CN108369819A (zh) * 2015-12-09 2018-08-03 英特尔公司 在自刷新模式期间附加刷新操作的执行
CN106406767A (zh) * 2016-09-26 2017-02-15 上海新储集成电路有限公司 一种非易失性双列直插式存储器及存储方法

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