WO2020062423A1 - 一种曲面阵列基板及其制备方法 - Google Patents

一种曲面阵列基板及其制备方法 Download PDF

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Publication number
WO2020062423A1
WO2020062423A1 PCT/CN2018/113350 CN2018113350W WO2020062423A1 WO 2020062423 A1 WO2020062423 A1 WO 2020062423A1 CN 2018113350 W CN2018113350 W CN 2018113350W WO 2020062423 A1 WO2020062423 A1 WO 2020062423A1
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metal layer
array substrate
layer
curved array
channel
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French (fr)
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尹炳坤
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US16/326,204 priority Critical patent/US10930678B2/en
Publication of WO2020062423A1 publication Critical patent/WO2020062423A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
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    • H10W20/071—Manufacture or treatment of dielectric parts thereof
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
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    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
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    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

Definitions

  • the present invention relates to the field of display technology, and in particular, to a flexible array substrate and a preparation method thereof.
  • the curved display Compared with the flat display, the curved display has a wider viewing angle, which can reduce the distortion of close viewing, and can achieve product differentiation.
  • the stress of the film layer is large when the display screen is bent, which causes the film layer to be easily broken when the display screen is bent, which affects the display effect.
  • the film layer When the curved display screen is bent, the film layer has a large stress, which may cause the film layer to be broken when the curved display screen is bent, which affects the display effect.
  • a curved array substrate includes:
  • a first metal layer disposed on the substrate
  • An insulating layer disposed on the substrate and covering the first metal layer, and a material of the insulating layer includes one or more of silicon nitride and silicon oxide;
  • a semiconductor layer provided on the insulating layer
  • a second metal layer disposed on the insulating layer and connected to the semiconductor layer;
  • a through hole is provided near the bending center on the insulating layer, and the second metal layer is connected to the first metal layer through the through hole.
  • a channel is opened on the second metal layer, and both ends of the channel extend to the edge of the second metal layer to penetrate the second metal layer.
  • At least one of said channels is located at a bending center.
  • the channel penetrates the upper and lower sides of the second metal layer.
  • the semiconductor layer is located on the side of the channel.
  • a curved array substrate includes:
  • a first metal layer disposed on the substrate
  • An insulating layer disposed on the substrate and covering the first metal layer
  • a semiconductor layer provided on the insulating layer
  • a second metal layer disposed on the insulating layer and connected to the semiconductor layer;
  • a through hole is provided near the bending center on the insulating layer, and the second metal layer is connected to the first metal layer through the through hole.
  • a channel is opened on the second metal layer, and both ends of the channel extend to the edge of the second metal layer to penetrate the second metal layer.
  • At least one of said channels is located at a bending center.
  • the channel penetrates the upper and lower sides of the second metal layer.
  • the semiconductor layer is located on the side of the channel.
  • the invention also provides a method for preparing a curved array substrate, including:
  • An insulating layer covering the first metal layer is formed on the substrate;
  • a second metal layer filling the through hole is formed on the insulating layer, and the second metal layer is connected to the first metal layer;
  • S60 Perform a patterning process on the second metal layer to form a source and a drain connected to the semiconductor layer.
  • the method for preparing the curved array substrate further includes:
  • a channel is opened on the second metal layer, and two ends of the channel extend toward an edge of the second metal layer to penetrate the second metal layer.
  • At least one of said channels is located at a bending center.
  • the channel penetrates the upper and lower sides of the second metal layer.
  • the semiconductor layer is located on the side of the channel.
  • a channel is opened on the portion of the second metal layer located at the center of the bend to reduce the distance between the vertex of the second metal layer along the centerline of the bend and the neutral plane, and reduce the stress on the vertex of the second metal layer.
  • the through-hole is used to realize the connection between the second metal layer and the first metal layer, thereby enhancing the connection strength between the second metal layer and the insulating layer, thereby reducing the risk of stress fracture of the second metal layer.
  • FIG. 1 is a schematic structural diagram of a curved array substrate in a specific embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a manufacturing process of a curved array substrate in a specific embodiment of the present invention
  • FIG. 3 to FIG. 6 are detailed schematic diagrams of a detailed manufacturing process of a curved array substrate in a specific embodiment of the present invention.
  • the present invention is directed to the existing curved display screen.
  • the film layer stress is large, which causes the film layer to be easily broken when the curved display screen is bent, which affects the display effect.
  • the present invention can solve the above problems.
  • a curved array substrate as shown in FIG. 1, the curved array substrate includes a substrate 10, a first metal layer 20 disposed on the substrate 10, and a first metal layer disposed on the substrate 10 and covering the first metal layer.
  • the insulating layer 30 is provided with a through hole 31 near the bending center, and the second metal layer 50 is connected to the first metal layer 20 through the through hole 31.
  • Connecting the second metal layer 50 to the first metal layer 20 through the through hole 31 improves the connection strength of the second metal layer 50 and the insulating layer 30, thereby increasing the stress resistance of the second metal layer 50, thereby reducing the second metal layer 50 risk of stress fracture.
  • a channel 51 is opened on the second metal layer 50, and both ends of the channel 51 extend to the edge of the second metal layer 50 to penetrate the second metal layer 50, and the semiconductor layer 40 is located at The side of the channel 51 is described.
  • one or more channels 51 may be provided.
  • the number of channels 51 may be selected according to actual needs. Generally speaking, the greater the thickness of the curved array substrate, the more channels need to be opened. The greater the number of 51.
  • At least one of the channels 51 is located at a bending center.
  • the stress at any point is related to the bending radius and the distance from the point to the neutral plane 60. The greater the distance, the greater the stress at this point.
  • the neutral plane 60 is an area where no stress is applied when the curved array substrate is bent.
  • the neutral plane 60 is the substrate 10. An interface with the first metal layer 20.
  • the channel 51 penetrates the upper and lower sides of the second metal layer 50.
  • At least one channel 51 is disposed at the center of the bend, and the distance between the vertex of the second metal layer 50 and the neutral plane 60 along the direction of the bend center line 70 is reduced, thereby reducing the second metal layer 50
  • the vertices of the substrate are stressed, thereby reducing the risk of the second metal layer 50 breaking due to stress.
  • the present invention also provides a method for preparing a curved array substrate. As shown in FIG. 2, the method for preparing a curved array substrate includes:
  • An insulating layer 30 covering the first metal layer 20 is formed on the substrate 10;
  • a patterned semiconductor layer 40 is formed on the insulating layer 30.
  • a second metal layer 50 filling the through hole 31 is formed on the insulating layer 30, and the second metal layer 50 is connected to the first metal layer 20;
  • the second metal layer 50 is connected to the first metal layer 20 through the through hole 31, thereby increasing the stress resistance of the second metal layer 50, thereby reducing the risk of the second metal layer 50 breaking due to stress.
  • FIGS. 3 to 6 For a detailed manufacturing process of the curved array substrate, refer to FIGS. 3 to 6.
  • a first metal layer 20 is deposited by a physical vapor deposition method, and a first metal layer pattern is formed by exposure, development, and etching.
  • the first metal layer 20 may also be formed by other methods, such as a chemical vapor deposition method.
  • an insulating layer 30 is formed by a chemical vapor deposition method, and a material of the insulating layer 30 includes one or more of silicon nitride and silicon oxide.
  • a through hole 31 is formed on the insulating layer 30 near the bending center by an etching process.
  • a semiconductor layer 40 is formed on the insulating layer 30 by a chemical vapor deposition method, and a patterning process is performed on the semiconductor layer 40 to form a patterned semiconductor layer 40.
  • a second metal layer 50 is formed on the insulating layer 30 by a physical vapor deposition method, and the second metal layer 50 is connected to the first metal layer 20 through the through hole 31.
  • the second metal layer 50 is patterned to form a source 52 and a drain 53 connected to the semiconductor layer 40.
  • the method for preparing the curved array substrate further includes: opening a channel 51 on the second metal layer 50, and both ends of the channel 51 extend to the edge of the second metal layer 50 to penetrate the second metal layer 50.
  • the metal layer 50 and the semiconductor layer 40 are located on the side of the channel 51.
  • At least one of the channels 51 is located at a bending center.
  • the channel 51 penetrates the upper and lower sides of the second metal layer 50.
  • the at least one channel 51 is arranged at the bending center, and the distance between the vertex of the second metal layer 50 and the neutral plane 60 along the direction of the bending center line 70 is reduced, so that the vertex of the second metal layer 50 is reduced. Stress, thereby reducing the risk of the second metal layer 50 breaking due to stress.
  • a beneficial effect of the present invention is that a channel 51 is provided on a portion of the second metal layer 50 located at the bending center, and the distance between the vertex of the second metal layer 50 along the bending center line 70 and the neutral plane 60 is reduced.
  • the stress on the apex of the second metal layer 50 is reduced, and the connection between the second metal layer 50 and the first metal layer 20 is achieved by using the through hole 31, and the connection strength between the second metal layer 50 and the insulating layer 20 is enhanced, thereby reducing Risk of the second metal layer 50 breaking due to stress.

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  • Thin Film Transistor (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种曲面阵列基板，包括基板、设置于所述基板上的第一金属层、设置于所述基板上且覆盖所述第一金属层的绝缘层、设置于所述绝缘层上的半导体层和设置于所述绝缘层上且与所述半导体层连接的第二金属层；其中，所述绝缘层上靠近弯曲中心处设置有通孔，所述第二金属层通过所述通孔与所述第一金属层连接。

Description

一种曲面阵列基板及其制备方法 技术领域
本发明涉及显示技术领域，尤其涉及一种柔性阵列基板及其制备方法。
 背景技术
相对于平面显示而言，曲面显示具有更广的视角，可以减少近距离观看的失真度，并且可以实现产品的差异化。然而显示屏弯曲时膜层应力较大，从而导致显示屏弯曲时易造成膜层断裂，影响显示效果。
 技术问题
曲面显示屏弯曲时膜层应力较大，从而导致曲面显示屏弯曲时易造成膜层断裂，影响显示效果。
 技术解决方案
一种曲面阵列基板，包括：
基板；
设置于所述基板上的第一金属层；
设置于所述基板上且覆盖所述第一金属层的绝缘层，所述绝缘层的制成材料包括氮化硅和氧化硅中的一种或多种；
设置于所述绝缘层上的半导体层；以及
设置于所述绝缘层上且与所述半导体层连接的第二金属层；
其中，所述绝缘层上靠近弯曲中心处设置有通孔，所述第二金属层通过所述通孔与所述第一金属层连接。
优选的，所述第二金属层上开设有沟道，所述沟道两端向所述第二金属层边缘延伸以贯穿所述第二金属层。
优选的，至少一条所述沟道位于弯曲中心处。
优选的，所述沟道贯穿所述第二金属层的上下两侧。
优选的，所述半导体层位于所述沟道侧部。
一种曲面阵列基板，包括：
基板；
设置于所述基板上的第一金属层；
设置于所述基板上且覆盖所述第一金属层的绝缘层；
设置于所述绝缘层上的半导体层；以及
设置于所述绝缘层上且与所述半导体层连接的第二金属层；
其中，所述绝缘层上靠近弯曲中心处设置有通孔，所述第二金属层通过所述通孔与所述第一金属层连接。
优选的，所述第二金属层上开设有沟道，所述沟道两端向所述第二金属层边缘延伸以贯穿所述第二金属层。
优选的，至少一条所述沟道位于弯曲中心处。
优选的，所述沟道贯穿所述第二金属层的上下两侧。
优选的，所述半导体层位于所述沟道侧部。
本发明还提供一种曲面阵列基板的制备方法，包括：
S10、在基板上形成第一金属层；
S20、在所述基板上形成覆盖所述第一金属层的绝缘层；
S30、在所述绝缘层上形成图案化的半导体层；
S40、通过蚀刻工艺在所述绝缘层上靠近弯曲中心处形成通孔；
S50、在所述绝缘层上形成填充所述通孔的第二金属层，所述第二金属层与所述第一金属层连接；
S60、对所述第二金属层进行图案化处理，以形成与所述半导体层连接的源极和漏极。
优选的，所述曲面阵列基板的制备方法还包括：
S70、在所述第二金属层上开设沟道，所述沟道两端向所述第二金属层边缘延伸以贯穿所述第二金属层。
优选的，至少一条所述沟道位于弯曲中心处。
优选的，所述沟道贯穿所述第二金属层的上下两侧。
优选的，所述半导体层位于所述沟道侧部。
 有益效果
在第二金属层位于弯曲中心处的部分上开设沟道，减少第二金属层沿弯曲中心线方向上的顶点与中性平面之间的间距，减小第二金属层的顶点所受得应力，同时利用通孔实现第二金属层与第一金属层的连接，增强第二金属层与绝缘层的连接强度，从而降低第二金属层因应力断裂的风险。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明具体实施方式中曲面阵列基板的结构示意图；
图2为本发明具体实施方式中曲面阵列基板的制备流程示意图；
图3至图6为本发明具体实施方式中曲面阵列基板的详细制备流程示意图。
附图标记：
10、基板；20、第一金属层；30、绝缘层；31、通孔；40、半导体层；50、第二金属层；51、沟道；52、源极；53、漏极；60、中性平面；70、弯曲中心线。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的曲面显示屏，曲面显示屏弯曲时膜层应力较大，从而导致曲面显示屏弯曲时易造成膜层断裂，影响显示效果，本发明可以解决上述问题。
一种曲面阵列基板，如图1所示，所述曲面阵列基板包括基板10、设置于所述基板10上的第一金属层20、设置于所述基板10上且覆盖所述第一金属层20的绝缘层30、设置于所述绝缘层30上的半导体层40以及设置于所述绝缘层30上且与所述半导体层40连接的第二金属层50。
其中，所述绝缘层30上靠近弯曲中心处设置有通孔31，所述第二金属层50通过所述通孔31与所述第一金属层20连接。
将第二金属层50通过通孔31与第一金属层20连接，提高第二金属层50与绝缘层30的连接强度，从而增加第二金属层50的抗应力能力，从而降低第二金属层50因应力断裂的风险。
其中，所述第二金属层50上开设有沟道51，所述沟道51两端向所述第二金属层50边缘延伸以贯穿所述第二金属层50，所述半导体层40位于所述沟道51侧部。
需要说明的是，所述沟道51可以设置一条或多条，在具体实施中，可根据实际需要选择沟道51的数量，一般而言，曲面阵列基板的厚度越大，需要开设的沟道51的数量越多。
具体的，至少一条所述沟道51位于弯曲中心处。
可以理解的是，如图1所示，由于弯曲时，任意点的应力大小与弯曲半径及该点到中性平面60的距离相关，距离越大，该点应力越大，可知弯曲时沿弯曲中心线70方向，曲面顶点应力最大；其中，所述中性平面60是在曲面阵列基板被弯曲时没有应力被施加的区域，在本实施例中，所述中性平面60为所述基板10与所述第一金属层20的交界面。
具体的，所述沟道51贯穿所述第二金属层50的上下两侧。
在一实施例中，将至少一条沟道51设置在弯曲中心处，减小沿弯曲中心线70方向的第二金属层50的顶点与中性平面60的距离，从而减小第二金属层50的顶点所受应力，从而降低第二金属层50因应力断裂的风险。
基于上述曲面阵列基板，本发明还提供一种曲面阵列基板的制备方法，如图2所示，所述曲面阵列基板的制备方法包括：
S10、在基板10上形成第一金属层20；
S20、在所述基板10上形成覆盖所述第一金属层20的绝缘层30；
S30、在所述绝缘层30上形成图案化的半导体层40；
S40、通过蚀刻工艺在所述绝缘层30上靠近弯曲中心处形成通孔31；
S50、在所述绝缘层30上形成填充所述通孔31的第二金属层50，所述第二金属层50与所述第一金属层20连接；
S60、对所述第二金属层50进行图案化处理，以形成与所述半导体层40连接的源极52和漏极53。
将第二金属层50通过通孔31与第一金属层20连接，从而增加第二金属层50的抗应力能力，从而降低第二金属层50因应力断裂的风险。
具体的，所述曲面阵列基板的详细制备过程参见图3至图6。
如图3所示，采用物理气相沉积法沉积第一金属层20，通过曝光、显影以及蚀刻形成第一金属层图形。
需要说明的是，在具体实施中，也可采用其他方法形成第一金属层20，如化学气相沉积法。
如图4所示，通过化学气相沉积法形成绝缘层30，所述绝缘层30的制成材料包括氮化硅和氧化硅中的一种或多种。
如图5所示，通过蚀刻工艺在所述绝缘层30上靠近弯曲中心处形成通孔31。
如图6所示，通过化学气相沉积法在所述绝缘层30上形成半导体层40，并对半导体层40进行图案化处理，以形成图案化的半导体层40。
通过物理气相沉积法在所述绝缘层30上形成第二金属层50，所述第二金属层50通过所述通孔31与第一金属层20连接。
对所述第二金属层50进行图案化处理，形成与所述半导体层40连接的源极52和漏极53。
其中，所述曲面阵列基板的制备方法还包括：在所述第二金属层50上开设沟道51，所述沟道51两端向所述第二金属层50边缘延伸以贯穿所述第二金属层50，所述半导体层40位于所述沟道51侧部。
具体的，至少一条所述沟道51位于弯曲中心处。
具体的，所述沟道51贯穿所述第二金属层50的上下两侧。
将至少一条所述沟道51设置在弯曲中心处，减小沿弯曲中心线70方向的第二金属层50的顶点与中性平面60的距离，从而减小第二金属层50的顶点所受应力，从而降低第二金属层50因应力断裂的风险。
本发明的有益效果为：在第二金属层50位于弯曲中心处的部分上开设沟道51，减少第二金属层50沿弯曲中心线70方向上的顶点与中性平面60之间的间距，减小第二金属层50的顶点所受得应力，同时利用通孔31实现第二金属层50与第一金属层20的连接，增强第二金属层50与绝缘层20的连接强度，从而降低第二金属层50因应力断裂的风险。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种曲面阵列基板，其中，所述曲面阵列基板包括：
    基板；
    设置于所述基板上的第一金属层；
    设置于所述基板上且覆盖所述第一金属层的绝缘层，所述绝缘层的制成材料包括氮化硅和氧化硅中的一种或多种；
    设置于所述绝缘层上的半导体层；以及
    设置于所述绝缘层上且与所述半导体层连接的第二金属层；
    其中，所述绝缘层上靠近弯曲中心处设置有通孔，所述第二金属层通过所述通孔与所述第一金属层连接。
  2. 根据权利要求1所述的曲面阵列基板，其中，所述第二金属层上开设有沟道，所述沟道两端向所述第二金属层边缘延伸以贯穿所述第二金属层。
  3. 根据权利要求2所述的曲面阵列基板，其中，至少一条所述沟道位于弯曲中心处。
  4. 根据权利要求3所述的曲面阵列基板，其中，所述沟道贯穿所述第二金属层的上下两侧。
  5. 根据权利要求4所述的曲面阵列基板，其中，所述半导体层位于所述沟道侧部。
  6. 一种曲面阵列基板，其中，所述曲面阵列基板包括：
    基板；
    设置于所述基板上的第一金属层；
    设置于所述基板上且覆盖所述第一金属层的绝缘层；
    设置于所述绝缘层上的半导体层；以及
    设置于所述绝缘层上且与所述半导体层连接的第二金属层；
    其中，所述绝缘层上靠近弯曲中心处设置有通孔，所述第二金属层通过所述通孔与所述第一金属层连接。
  7. 根据权利要求6所述的曲面阵列基板，其中，所述第二金属层上开设有沟道，所述沟道两端向所述第二金属层边缘延伸以贯穿所述第二金属层。
  8. 根据权利要求7所述的曲面阵列基板，其中，至少一条所述沟道位于弯曲中心处。
  9. 根据权利要求8所述的曲面阵列基板，其中，所述沟道贯穿所述第二金属层的上下两侧。
  10. 根据权利要求9所述的曲面阵列基板，其中，所述半导体层位于所述沟道侧部。
  11. 一种曲面阵列基板的制备方法，其中，所述曲面阵列基板的制备方法包括：
    S10、在基板上形成第一金属层；
    S20、在所述基板上形成覆盖所述第一金属层的绝缘层；
    S30、在所述绝缘层上形成图案化的半导体层；
    S40、通过蚀刻工艺在所述绝缘层上靠近弯曲中心处形成通孔；
    S50、在所述绝缘层上形成填充所述通孔的第二金属层，所述第二金属层与所述第一金属层连接；
    S60、对所述第二金属层进行图案化处理，以形成与所述半导体层连接的源极和漏极。
  12. 根据权利要求11所述的曲面阵列基板的制备方法，其中，所述曲面阵列基板的制备方法还包括：
    S70、在所述第二金属层上开设沟道，所述沟道两端向所述第二金属层边缘延伸以贯穿所述第二金属层。
  13. 根据权利要求12所述的曲面阵列基板的制备方法，其中，至少一条所述沟道位于弯曲中心处。
  14. 根据权利要求13所述的曲面阵列基板的制备方法，其中，所述沟道贯穿所述第二金属层的上下两侧。
  15. 根据权利要求14所述的曲面阵列基板的制备方法，其中，所述半导体层位于所述沟道侧部。
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