WO2020062275A1 - 栅控二极管及芯片 - Google Patents

栅控二极管及芯片 Download PDF

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Publication number
WO2020062275A1
WO2020062275A1 PCT/CN2018/109179 CN2018109179W WO2020062275A1 WO 2020062275 A1 WO2020062275 A1 WO 2020062275A1 CN 2018109179 W CN2018109179 W CN 2018109179W WO 2020062275 A1 WO2020062275 A1 WO 2020062275A1
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Prior art keywords
gate
dimensional semiconductor
semiconductor layer
layer
drain
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PCT/CN2018/109179
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English (en)
French (fr)
Inventor
李伟
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华为技术有限公司
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Priority to PCT/CN2018/109179 priority Critical patent/WO2020062275A1/zh
Priority to CN201880098167.2A priority patent/CN112805837B/zh
Publication of WO2020062275A1 publication Critical patent/WO2020062275A1/zh
Priority to US17/208,492 priority patent/US11894422B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode

Definitions

  • the invention relates to the technical field of electronic communication, in particular to semiconductor devices, and further relates to a gate-controlled diode and a chip having the gate-controlled diode.
  • Common semiconductor devices such as diodes are widely used in circuits such as rectification, detection, limiting, and voltage stabilization, and belong to a device with two electrodes.
  • the traditional crystal diode is a pn junction formed by a p-type semiconductor and an n-type semiconductor.
  • a space charge layer is formed on both sides of the interface and a self-built electric field is established.
  • the pn junction is loaded on both sides.
  • the diffusion current caused by the difference in carrier concentration is equal to the drift current caused by the self-built electric field, and is in an electrical equilibrium state.
  • a forward voltage bias is generated, the mutual suppression effect of the external electric field and the self-built electric field of the diode causes the carrier's diffusion current to increase, causing a forward current.
  • the embodiments of the present application provide a semiconductor device that can regulate the conduction direction, so as to improve the application flexibility performance of the semiconductor device.
  • the present application provides a gate control diode, which includes a substrate, a gate layer laminated on the substrate, a gate insulating layer, a first two-dimensional semiconductor layer, a second two-dimensional semiconductor layer, and a source. An electrode and a drain spaced from the source;
  • the gate is embedded on the surface of the substrate, and the gate insulating layer covers the surface of the substrate on which the gate is provided;
  • the first two-dimensional semiconductor layer is formed of a bipolar conductive material, the first two-dimensional semiconductor layer is laminated on the gate insulation layer, and the second two-dimensional semiconductor layer is partially laminated on the gate insulation. Layer, another part is stacked on the first two-dimensional semiconductor layer, and the second two-dimensional semiconductor layer and the first two-dimensional semiconductor layer are stacked to form a heterojunction, and the heterojunction is in the positive side of the substrate.
  • the projection is located in the orthographic projection of the grid in the base layer;
  • the source is electrically connected to the second two-dimensional semiconductor layer and is insulated from the first two-dimensional semiconductor layer
  • the drain is electrically connected to the first two-dimensional semiconductor layer and the second two-dimensional semiconductor.
  • Layer insulation, and the conductive path of the gate-controlled diode is from the source through the heterojunction to the drain, or from the drain through the heterojunction to the source.
  • the gate control diode of the present application uses a two-dimensional semiconductor to form a heterojunction.
  • the source and drain are located on both sides of the heterojunction and the gate is recessed in the substrate.
  • the parasitic capacitance between the gate and the source and drain is reduced.
  • Small, two-dimensional semiconductor layer with drain connection at the same time has bipolar conductivity, and the gate insulating layer is one of HfO 2 , Al2O 3 , ZrO 2 , HfxZr 1 -xO 2 , HfLaO, Y 2 O 3 , and thickness It is thin.
  • the gate has sufficient gate capacitance, and the bidirectionality of the conductive path of the gate-controlled diode can be controlled by the gate voltage, so that the diode includes a forward conduction and Compared with the prior art single-directional diode, the reverse conduction tunability has higher application flexibility performance.
  • a side of the gate far from the oxide protective layer protrudes from the surface of the oxide protective layer or is flush with the surface of the oxide protective layer.
  • a surface of a side of the gate far from the oxide protective layer is flush with a surface of the oxide protective layer, so as to ensure that the gate insulating layer has a flatness.
  • the material of the first two-dimensional semiconductor layer is tungsten diselenide
  • the material of the second two-dimensional semiconductor layer is tin diselenide, but it is not limited to the two types of two-dimensional semiconductor materials listed.
  • the first two-dimensional semiconductor layer includes a first portion and a second portion connected to the first portion.
  • the second two-dimensional semiconductor layer includes a third portion and a fourth portion connected to the third portion.
  • the third portion is stacked on the first portion.
  • a heterojunction is formed on the first portion, the source is located on a surface of the fourth portion, and the drain is located on a surface of the second portion.
  • the gate-control diode further includes an isolation layer located between the drain and an end of the second two-dimensional semiconductor layer constituting the heterojunction portion.
  • the material of the isolation layer is an insulating oxide, and the isolation layer realizes isolation of the drain from the second two-dimensional semiconductor layer.
  • the source electrode in a vertical direction, is located directly above the heterojunction. At this time, the intervention resistance is relatively small, and a larger current will be obtained.
  • the gate includes a bottom surface connected to the oxide protection layer, a first end surface adjacent to the drain electrode, and a second end surface adjacent to the source electrode, and the first end surface and the second end surface The end surfaces are connected to opposite ends of the bottom surface;
  • the drain includes a first side
  • the source includes a second side spaced apart from the first side
  • the first side is coplanar with the first end surface
  • the second side is coplanar with the second end surface.
  • the present application provides a chip including a circuit and the gate control diode applied to the circuit.
  • the chip is an RF energy harvesting chip
  • the present application provides a method for manufacturing a gated diode, the method includes:
  • step 1 a recess is formed on the surface of the oxide protective layer of the base, and a gate is formed in the recess.
  • a photoresist is used to define a gate region on the oxide protective layer by using a photolithography process, and a portion of the surface of the oxide protective layer other than the gate region is formed by using the photoresist as a mask. Occlusion.
  • An oxide protective layer located in the gate region is etched by a reactive ion etching method to form a recess in the substrate.
  • a gate is formed in the recess by a vapor deposition method, wherein the gate fills the recess.
  • Step 2 forming a gate insulating layer on the surface of the oxide protective layer, so that the gate insulating layer covers the gate, and is used to protect the gate and isolate the heterojunction and the oxide protective layer.
  • the material of the gate insulating layer is one of HfO 2 , Al2O 3 , ZrO 2 , HfxZr 1 -xO 2 , HfLaO, Y 2 O 3 .
  • Step 3 forming a channel layer and a drain on the gate insulating layer, the channel layer including a first two-dimensional semiconductor layer, a second two-dimensional semiconductor layer, and a first two-dimensional semiconductor layer and a second two-dimensional semiconductor layer The formed heterojunction, the drain is located on the first two-dimensional semiconductor layer and is insulated from the second two-dimensional semiconductor layer; wherein the material of the first two-dimensional semiconductor layer is tungsten diselenide, and The material of the second two-dimensional semiconductor layer is tin diselenide.
  • the step of forming a channel layer on the gate insulating layer includes:
  • a photolithography process is used to define an isolation layer region on the layer structure composed of the first two-dimensional semiconductor layer and the drain, and a photoresist is used as a mask.
  • the photoresist covered with an insulating oxide layer Removing the photoresist covered with an insulating oxide layer to form an isolation layer in the isolation layer region, and the isolation layer covers a part of the drain and the connection position of the drain and the first two-dimensional semiconductor layer; wherein the material of the spacer layer is an SiO2 or Al 2 O 3.
  • the second two-dimensional semiconductor layer is connected to a side of the isolation layer far from the drain.
  • an isolation layer is formed before the second two-dimensional semiconductor layer is formed. Due to the existence of the isolation layer, it is possible to prevent The portion where the first two-dimensional semiconductor layer is connected to the drain causes accidental damage and destroys its performance; at the same time, the isolation layer can isolate the drain and the second two-dimensional semiconductor layer to prevent conduction between the two. .
  • Step 4 forming a source electrode opposite to the drain interval on the trench layer, wherein the source electrode achieves a first conduction direction through the heterojunction to the drain electrode, and the drain electrode passes through The heterojunction to the source achieves a second conduction direction.
  • the source electrode is formed by a patterning process.
  • the step of forming a recessed portion on the surface of the oxide protective layer of the base and forming a gate in the recessed portion further includes planarizing the gate to expose the gate.
  • the surface of the recessed portion is flush with the surface of the oxide protection layer to ensure quality in the subsequent fabrication process of the channel layer.
  • the source and drain are located on both sides of the heterojunction and the gate is recessed in the substrate.
  • the parasitic capacitance between the gate and the source-drain is reduced.
  • the gate insulating layer of the silicon dioxide material and the two-dimensional oxide layer containing bidirectional conductivity can control the conduction polarity of the first two-dimensional material by the gate voltage, and further the bidirectional conductance of the conductive path of the gated diode It can realize the regulation of the conduction direction and the turn-on voltage, so as to improve the flexible performance of the application of the diode, and can realize the small signal rectification to reduce the complexity of the small signal rectification circuit.
  • FIG. 1a is a schematic cross-sectional view of a gate-controlled diode according to an embodiment of the present application
  • Figure 1b is a top view of the gate control diode shown in Figure 1a;
  • FIG. 2a and 2b are a schematic cross-sectional view and a top view of the gate control diode shown in FIG. 1a after the first two-dimensional semiconductor layer is formed;
  • FIG. 3 is a schematic cross-sectional view of the gate-control diode shown in FIG. 1a after the drain is formed;
  • 4a and 4b are a cross-sectional view and a top view of the gate-control diode shown in FIG. 1a after forming an isolation layer, respectively;
  • 5a and 5b are respectively a cross-sectional view and a top view of the gate-control diode shown in FIG. 1a after forming a second two-dimensional semiconductor layer;
  • FIG. 6 is a schematic cross-sectional view of another embodiment of a gate-controlled diode, which is different from FIG. 1a in that there is an overlap between a gate, a source, and a drain;
  • FIG. 7a and 7b are schematic diagrams of forward operation of the gated diode shown in FIG. 1a and FIG. 6;
  • FIG. 8a and 8b are schematic diagrams of the reverse working principle of the gated diode shown in FIG. 1a and FIG. 6;
  • FIG. 9a and FIG. 9b are line voltage diagrams of the gate control diode shown in FIG. 1a and FIG. 6 to control the forward and reverse diode working voltages through the gate voltage;
  • FIG. 10 is a flowchart of a gate control diode manufacturing method provided by the present application.
  • FIGS. 11-12, 13a, 13b, 14a, and 14b are schematic structural diagrams corresponding to a plurality of steps in the manufacturing process of the gate control diode manufacturing method of the present application.
  • the present application protects a gate-controlled diode, which is applied to circuits such as rectification and voltage stabilization, and controls the magnitude of the turn-on voltage through the gate voltage.
  • the left-right direction is the X-axis direction
  • the direction perpendicular to the thickness of the gate control diode (substrate surface) is the Y-axis direction.
  • the X-axis direction which is the length direction of the gate 13, the first two-dimensional semiconductor layer 15, and the second two-dimensional semiconductor layer 16, the gate 13, the first two-dimensional semiconductor layer 15, and the first
  • the width direction of the two-dimensional semiconductor layer 16 is the Z-axis direction.
  • the gate control diode includes a substrate 10, an oxide protective layer 12, a gate 13, a gate insulating layer 14, a first two-dimensional semiconductor layer 15, and a second two-dimensional semiconductor layer laminated on a surface of the substrate 10. 16 and a source electrode 18 and a drain electrode 19, and the source electrode 18 and the drain electrode 19 are disposed at intervals.
  • the gate 13 is embedded on the surface of the substrate 10, and the gate insulating layer 14 covers a surface of the substrate 10 on which the gate 13 is provided.
  • the gate insulating layer 14 is formed of a material having a high dielectric constant.
  • the first two-dimensional semiconductor layer 15 is formed of a bipolar conductive material.
  • the first two-dimensional semiconductor layer 15 is stacked on the gate insulating layer 14.
  • the second two-dimensional semiconductor layer 16 is partially stacked on the gate insulating layer 14.
  • On the gate insulating layer 14, another part is stacked on part of the first two-dimensional semiconductor layer 15, and the second two-dimensional semiconductor layer 16 and the first two-dimensional semiconductor layer 15 are stacked to form a heterojunction 17.
  • the orthographic projection of the heterojunction 17 on the substrate 11 is located within the orthographic projection of the grid 13 on the substrate 11 layer.
  • the heterojunction is an interface region in which two or more different semiconductor materials are stacked in contact.
  • the source electrode 18 is electrically connected to the second two-dimensional semiconductor layer 16 and is insulated from the first two-dimensional semiconductor layer 15, and the drain electrode 19 is electrically connected to the first two-dimensional semiconductor layer 15 and is electrically connected to the first two-dimensional semiconductor layer 15.
  • the two-dimensional and two-dimensional semiconductor layer 16 is insulated, and the conductive path of the gate control diode is from the source electrode 18 through the heterojunction 17 to the drain electrode 19, or from the drain electrode 19 through the heterojunction 17 to ⁇ ⁇ ⁇ 18 ⁇
  • each functional layer of the gate control diode has a regular structure, the thickness of the functional layers is uniformly set, and high working efficiency can be ensured. This design is consistent with existing chips and electronic equipment. Such as miniaturization, thin and light development trends. Because the source 18 and the drain 19 are spaced apart and there is no possibility of connection, as long as the heterojunction, source, and drain are intercepted when acquiring the cross-section, each functional layer of the gate-control diode to achieve gate voltage control can be intercepted. Structure, and when these various functional layers are non-uniform, the electrical connection relationship of each functional layer will not change, as long as it conforms to the layer structure and matching relationship of the cross section taken in this embodiment, it can be solved.
  • Each functional layer includes a substrate, a gate, a gate insulating layer, a heterojunction, a source and a drain, and an isolation layer according to the second embodiment of the present application.
  • the source 18 and the drain 19 are cylindrical or other irregular shapes, but their functions are to cooperate with the heterojunction to flow electrons.
  • the source 18 is electrically connected to the second two-dimensional semiconductor layer 16 and the first two
  • the two-dimensional semiconductor layer 15 is insulated
  • the drain electrode 19 is electrically connected to the first two-dimensional semiconductor layer 15 and is insulated from the second two-dimensional semiconductor layer 16.
  • the first two-dimensional semiconductor layer 15 and the second two-dimensional semiconductor layer 16 can never be It is in contact with the gate 13. Therefore, in this embodiment, a cross-sectional view and a plan view are used as reference schematic illustrations.
  • the gate control diode uses a two-dimensional semiconductor to form a heterojunction.
  • the material of the first two-dimensional semiconductor layer 15 is tungsten diselenide, which is a bipolar conductive material, and the second two-dimensional
  • the material of the semiconductor layer 16 is a two-dimensional semiconductor material heavily doped with P-type or N-type ions such as tin diselenide.
  • the first two-dimensional semiconductor layer 15 connected to the drain 19 has bipolar conductivity, and there is only a gate insulating layer 14 between the heterojunction 17 and the gate 13.
  • the gate insulating layer 14 has a high dielectric constant.
  • the material is formed so that the gate has sufficient gate capacitance to control the conduction polarity of the first two-dimensional semiconductor layer 15, thereby realizing the bidirectionality of the conductive path of the gated diode, that is, the source 18 Conduction through the heterojunction 17 to the drain 19 (reverse direction), or conduction from the drain 19 through the heterojunction 17 to the source 18 (forward) so that all
  • the diode has the characteristics of forward conduction and reverse conduction, and has higher flexibility than the single-directional diode of the prior art.
  • the gate voltage can be used to control the diode's forward or reverse conduction turn-on voltage. When the turn-on voltage is small, the loss of signal voltage during rectification can be reduced, thereby reducing the loss of operating voltage.
  • the gate 13 controls the first two-dimensional semiconductor layer 15 to be p-type doped
  • the second two-dimensional semiconductor layer 16 is heavily doped p-type or n-type
  • the heterojunction between the two is It is pn + type, or n + p type, and has a large hole concentration to conduct electricity. It is a forward diode.
  • the gate controls the first two-dimensional semiconductor layer 15 to make it n-type doped, its own electron concentration is lower. High and conductive, the heterojunction of the two is an nn + junction, which is a reverse diode, so as long as the doped ion type of the first two-dimensional semiconductor layer 15 is controlled, forward conduction or reverse conduction can be achieved.
  • the substrate 10 is formed of an insulating material such as quartz or sapphire, or the substrate 10 includes a substrate 11 and an oxide protective layer 12 laminated on a surface of the substrate 11, and the substrate 11 is made of a silicon material. Therefore, the oxide protective layer 12 is made of a silicon dioxide material.
  • the substrate 10 includes a substrate 11 and an oxide protective layer 12. The oxide protective layer 12 covers the entire surface of the substrate 11 for forming a gate-control diode to form a substrate with the substrate. An oxide substrate structure to ensure carrier transport.
  • the gate insulating layer 14 is one of HfO 2 , Al 2 O 3 , ZrO 2 , HfxZr 1 -xO 2 , HfLaO, and Y 2 O 3 with a high dielectric constant; the gate 13 and the source 18 and the drain electrode 19 are each made of a conductive metal material.
  • the oxide protective layer 12 includes a first surface (not shown) connected to the substrate 11 and a second surface 120 opposite to the first surface. The first surface faces the substrate. 11 is connected to the substrate 11.
  • the gate 13 is embedded in the second surface 120 of the oxide protection layer 12. Specifically, a concave portion is recessed on the second surface 120 of the oxide protective layer 12, and the gate electrode 13 is formed in the concave portion and fills the concave portion.
  • the oxide protective layer 12 has a layer structure.
  • the concave portion is a rectangular groove for receiving the gate electrode 13.
  • the concave portion may be a groove of other shapes.
  • the gate electrode 13 is a regular rectangular layer, and the surface of the gate electrode 13 protrudes from the surface 120 of the oxide protective layer 12 or the surface 120 of the oxide protective layer 12. Level. In this embodiment, the surface of the gate 13 is flush with the surface 120 of the oxide protective layer 12, which can ensure the flatness of the oxide semiconductor layer 11 and the gate 13 to ensure the gate insulating layer 14. With high flatness, cracks and wrinkles are unlikely to occur during the manufacturing process of the first two-dimensional semiconductor layer 15 and the second two-dimensional semiconductor layer 16 and affect the performance of the gated diode.
  • the gate insulating layer 14 covers a surface of the substrate 10 on which the gate 13 is provided. Specifically, the gate insulating layer 14 covers the second surface 120 of the oxide protective layer 12, and is used to insulate the gate 13 from other layer structures laminated on the gate 13. In this embodiment, the gate insulating layer 14 covers the entire second surface 120 of the oxide protective layer 12, (see FIG. 2b) can be directly formed by putting the substrate 11 into the ALD chamber and growing using atomic layer deposition technology. Therefore, a photolithography process is not required, and the processing steps are simplified.
  • the gate insulating layer 14 is made of a high dielectric constant material instead of silicon dioxide, and the thickness can be made thinner using atomic layer deposition technology, which improves the gate capacitance and enables the gate to effectively control bipolar conductivity
  • the conductive polarity of the first two-dimensional semiconductor layer 15 controls the bidirectionality of the conductive path of the diode.
  • the thickness of the gate insulating layer 14 is between 2 nm and 50 nm, as long as the gate 13 can control the first two-dimensional semiconductor layer 15 well, because the dielectric constants of different oxides are different, The thickness required by different oxides for the gate insulating layer 14 is not the same, and it is also related to the operating voltage of the application scenario.
  • this thickness needs to be increased to withstand a higher operating voltage. Similarly, if the working voltage is small, and this thickness can also be reduced, so that the gate control diode can be effectively regulated and controlled even at a small working voltage.
  • the first two-dimensional semiconductor layer 15 includes a first portion 151 and a second portion 152 connected to the first portion 151.
  • the first portion 151 and the second portion 152 is the same layer structure formed by the same process step.
  • the first two-dimensional semiconductor layer 15 is a regular rectangular layer, and the first portion 151 and the second portion 152 are uniform in thickness, and is formed on the surface 140 of the gate insulating layer 14; the first portion The orthographic projection of 151 and the second portion 152 is completely located in the gate 13 and partially overlaps with the gate 13.
  • the width of the first two-dimensional semiconductor layer 15 is less than or equal to the width of the gate 13.
  • the length of the first portion 151 is shorter than the length of the gate 13.
  • the length and width refer to the maximum dimensions of the two dimensions.
  • the heterojunction 17 is not formed until the drain 19 is formed after the first two-dimensional semiconductor layer 15 is formed. Therefore, in this embodiment, an embodiment in which the drain 19 and the isolation layer 20 are provided with the second two-dimensional semiconductor layer 16 and a heterojunction will be described first.
  • the drain electrode 19 covers the surfaces of the first two-dimensional semiconductor layer 15 and the gate insulating layer 14 through a metal layer, and is then formed on the surface through a coating and a photolithography process.
  • the surface of the second portion 152 of the first two-dimensional semiconductor layer 15 is on a side remote from the first portion 151.
  • the drain electrode 19 of this embodiment is an elongated bar having a uniform thickness and includes a first side surface 191 facing the source electrode 18.
  • the length direction of the drain electrode 19 is the width direction of the gate electrode 13, that is, the Z-axis direction. In this embodiment, the length of the drain electrode 19 is greater than the width of the first two-dimensional semiconductor 15.
  • the shape of the drain is not limited to a long shape, but it is necessary to cover the first two-dimensional semiconductor layer 15 and not exceed the edge of the gate insulating layer 14 to ensure the conduction efficiency.
  • the thickness of the drain electrode 19 may be a step distribution, and may cover the end of the second portion 152 and be connected to the surface of the gate insulating layer 14, but it must be insulated from the gate 13. In fact, in order to reduce the volume of the diode device, the drain 19 may be formed on the surface of the second portion 152. It should be noted that a partial region Q having the second portion 152 between the first portion 151 and the drain electrode 19 of the first two-dimensional semiconductor layer 15 is provided to the first two-dimensional semiconductor layer 15 for the gate 13.
  • the maximum effective control is achieved, and the orthographic projection of the partial region Q is located in the grid 13.
  • the drain 19 is spaced from the end of the third portion 161 away from the fourth portion 162 and is insulated. In this embodiment, it is implemented by an isolation layer. For details, see the description below.
  • the gate control diode further includes an isolation layer 20 provided on the first two-dimensional semiconductor layer 15, and the isolation layer 20 is located between the drain 19 and the drain 19. Between the second two-dimensional semiconductor layers 16.
  • the width of the isolation layer 20 in the Z-axis direction is less than or equal to the length of the drain electrode 19 and greater than or equal to the width of the third portion 161 to ensure that the drain electrode 19 can be effectively isolated from the second Two-dimensional semiconductor layer 16.
  • the width of the isolation layer 20 is smaller than the length of the drain electrode 19, which can save processing materials.
  • the isolation layer 20 is formed on the second portion 152 of the first two-dimensional semiconductor layer 15 through a photomask and a coating process. Then, the base material layer of the second two-dimensional semiconductor layer 16 is formed by a photolithography process, and the base material layer of the excess two-dimensional semiconductor layer connected to the drain electrode 19 is removed by an etching process to form the and the drain. The pole is insulated from the second two-dimensional semiconductor layer 16.
  • a material of the isolation layer 20 is SiO 2 or Al 2 O 3 .
  • the two-dimensional semiconductor material layer is then patterned to obtain a first two-dimensional semiconductor layer 15 having a predetermined pattern.
  • the drain electrode 19 is then formed on the first two-dimensional semiconductor layer 15 by coating or depositing a metal layer and a patterning process. Due to the flatness of the gate, the first two-dimensional material layer is tiled on the gate insulating layer 14, and the material is not prone to cracks and wrinkles during the formation of the first two-dimensional semiconductor material layer and is affected. Device performance.
  • the second two-dimensional semiconductor layer 16 includes a third portion 161, a fourth portion 162, and an extension portion 163 connected in order along the X-axis direction.
  • the third portion 161 and the fourth portion 162 and the extension portion 163 have the same layer structure formed by the same process step.
  • the second two-dimensional semiconductor layer 16 is a regular rectangular layer when viewed in a Y-axis direction.
  • the third portion 161 is formed on the surface of the first portion 151 and covers the first portion 151.
  • the first part 151 forms the heterojunction 17, and the orthographic projection of the heterojunction 17 is completely located in the gate 13.
  • the orthographic projection of the third portion 161 and the first portion 151 on the grid 13 is completely coincident.
  • the length of the third portion 161 is equal to the length of the first portion 151 in the X-axis direction, and the width of the third portion 161 is equal to the width of the first portion 151 in the Y-axis direction.
  • the third portion 161 may be larger than the width dimension of the first portion 151.
  • the orthographic projection of the third portion 161 is completely located in the gate 13 and partially overlaps the gate 13, that is, the width of the second two-dimensional semiconductor layer 16 is less than or equal to the width of the gate 13,
  • the length of the third portion 161 is shorter than the length of the gate 13.
  • the third portion 161 is stacked on the surface 140 of the gate insulating layer 14 and covers an end portion of the first portion 151.
  • the thicknesses of the third portion 161 and the fourth portion 162 are uniform and the same.
  • the fourth portion 162 has a larger thickness only at a position where a step difference is generated when the end portion of the first portion 151 covers the gate insulating layer 14.
  • the extension portion 163 is located on a partial region Q of the second portion 162, the isolation layer 20 is located between the drain 19 and the extension portion 163, and two opposite surfaces of the isolation layer 20 are connected to the drain, respectively.
  • the electrode 19 and the extension portion 163 insulate the drain electrode 19 from the second two-dimensional semiconductor layer 16 and prevent the drain electrode 19 and the second two-dimensional semiconductor layer 16 from being electrically conducted.
  • one end of the isolation layer 20 protrudes from the extension portion 163 of the second two-dimensional semiconductor layer 16 and covers a portion of the drain electrode 19, and the other end is located between the extension portion 163 and the first portion 151.
  • the isolation layer 20 can protect the drain electrode 19 and the first two-dimensional semiconductor layer 15 from being etched when the base material layer of the second two-dimensional semiconductor layer 16 is etched, thereby achieving the effect of protection; at the same time, the isolation layer 20 realizes Insulation effect.
  • first two-dimensional semiconductor layer 15 and the second two-dimensional semiconductor layer 16 are irregular or non-rectangular, as long as it is ensured that the orthographic projection of the heterojunction 17 is definitely located on the gate 13 It is sufficient to control the voltage of the gate 13 to the first two-dimensional semiconductor layer 15 effectively.
  • the heterojunction formed based on tin diselenide and bipolar tungsten diselenide can control the forward and reverse conduction of the gated diode by regulating the gate voltage, and tin diselenide
  • the heterojunction without lattice mismatch formed with tungsten diselenide will not cause interface defects, and the process of preparing a heterojunction diode is relatively simple, and the heterojunction 17 can better suppress the reaction of the gated diode. To the current to obtain a greater rectification ratio.
  • the source electrode 18 and the drain electrode 19 are spaced apart.
  • the source electrode 18 is located on a side of the fourth portion 162 of the second two-dimensional semiconductor layer 16 away from the third portion 161.
  • the source electrode 18 and the drain electrode 19 are formed in the same process.
  • the source electrode 18 in this embodiment is an elongated bar having a uniform thickness.
  • the length direction of the source electrode 18 is the width direction of the gate electrode 13.
  • the length of the source electrode 18 is greater than the width of the second two-dimensional semiconductor 16.
  • the shape of the source electrode 18 is not limited to a long shape, but it should cover the second two-dimensional semiconductor 16 and not exceed the edge of the gate insulating layer 14 to ensure the conduction efficiency.
  • the thickness of the source electrode 18 may be a step distribution, and may cover the end of the fourth portion 162 and be connected to the surface of the gate insulating layer 14, but it must be insulated from the gate 13.
  • the source electrode 18 may be formed on the surface of the fourth portion 162.
  • a groove is formed on a surface of the fourth portion 162 away from the third portion 161, and the source electrode 18 is formed in the groove.
  • a front projection portion of the source electrode 18 and a small portion of the gate electrode 13 overlap.
  • the source electrode 18 may be stacked on the third portion 161 constituting the heterojunction 17 and spaced a certain distance from the drain electrode 19, and the distance does not affect the conductivity of the diode.
  • the access resistance is relatively small, a larger current can be obtained.
  • the source electrode 18 and the drain electrode 19 are located on opposite sides of the heterojunction 17, and the gate electrode 13 is embedded in the oxide protection layer 12 and not between the source electrode and the drain electrode.
  • the source and the drain are opposite, and the opposite sides of the gate 13 (viewed along the X-axis direction) are completely staggered from the source 18 and the drain 19 to avoid the gate 13 and the source 18 and the drain 19 in the X-axis direction.
  • the purpose of reducing the parasitic capacitance between the opposite sides of the gate 13 and the source 18 and the drain 19 and improving the conductivity is achieved.
  • the signal loss is small in high-frequency applications, which is conducive to improving the high-frequency characteristics of the device.
  • the gate electrode 13 includes a bottom surface 130, a first end surface 131, and a second end surface 132 connected to the oxide protection layer 12.
  • the two end surfaces 132 are connected to opposite ends of the bottom surface 130 in the X-axis direction.
  • the drain electrode 19 includes a first side surface 191 facing the source electrode 18, and the source electrode 18 includes a second side surface 181 spaced apart from the first side surface 191.
  • the first side surface 191 is coplanar with the first end surface 131 or has an effective distance (the distance between the gate and source-drain control), and the second side 181 is coplanar with the second end 132 or has an effective distance.
  • the first side surface 191 is coplanar with the first end surface 131
  • the second side surface 181 is coplanar with the second end 132 surface, so that the drain electrode 19, the source electrode 18, and the The overlapping area between the gate electrodes 13 in the Y-axis direction can better reduce the parasitic capacitance between the source electrode 18, the drain electrode 19, and the gate electrode 13, thereby ensuring a sufficient control voltage.
  • the conductive path of the gate control diode includes a forward conducting path and a reverse conducting path.
  • the forward conducting path refers to the drain 19 through the heterojunction 17 to the source 18,
  • the on-current flows from the drain electrode 19 through the second two-dimensional semiconductor layer 16 of the heterojunction 17 to the first two-dimensional semiconductor layer 15 to the source electrode 18.
  • the reverse conduction path refers to the conduction from the source 18 through the heterojunction 17 to the drain 19, and the conduction current from the source 18 through the first two-dimensional semiconductor layer of the heterojunction 17 to the second two-dimensional To the drain 19 after the semiconductor layer.
  • FIG. 7a and FIG. 7b are schematic diagrams of forward operation of a diode.
  • Vg-V T ⁇ 0 the gate voltage performs p-type electrostatic doping on the first two-dimensional semiconductor layer 15, and forms a pn junction diode with the n-type conductive second two-dimensional semiconductor layer 16.
  • Vd When it is> 0, the carriers are diffusion transport, and electrons are injected into the second two-dimensional semiconductor layer 16 from the source electrode 18, and then cross the barrier (heterojunction) into the first two-dimensional semiconductor layer 15 and are collected by the drain electrode 19.
  • Vd is the gate voltage
  • V T is the threshold voltage
  • Vd is the bias voltage applied to the drain.
  • the barrier width between the drain 19 and the first two-dimensional semiconductor layer 15 decreases, and holes are more easily injected into the first two-dimensional semiconductor layer 15 and therefore turn on The voltage decreases, as shown in the IV characteristic curve of the forward diode of Fig. 9a.
  • the turn-on voltage of the forward diode is adjustable with the gate voltage and decreases with the decrease of the gate voltage. When the gate voltage decreases from -4V to -5V , The turn-on voltage is reduced from about 0.8V to 0.3V.
  • FIG. 8a and Figure 8b are schematic diagrams of diode reverse operation.
  • Vg-V T > 0 and Vd ⁇ 0 the corresponding energy band corresponding relationship is shown in Figure 8b.
  • the layer 15 is n-type doped. Most of the carrier electrons are injected into the first two-dimensional semiconductor layer 15 from the drain 19, and then enter the source 18 after the second two-dimensional semiconductor layer 16.
  • the diode is in a conducting state, that is, reverse conducting. .
  • the diode 8a after the majority of carriers are injected from the source 18, they encounter the second two-dimensional semiconductor layer 16-the first two-dimensional semiconductor layer 15 interface (different (Mass junction) has a higher potential barrier, and it is difficult for carriers to cross the barrier. The current generated is very small. The minority can be injected through the drain 19, but the number of minority is small and the current generated is very small.
  • the diode is high resistance ( (Non-conducting) state. Diodes have smaller junction capacitance and lower point voltage, so they can be used for rectification of high-frequency signals.
  • FIG. 9b is the IV characteristic curve of the reverse diode.
  • the turn-on voltage of the reverse diode can be adjusted by the gate voltage. It can be seen from Figure 9b that as the gate voltage increases, the turn-on voltage of the reverse diode decreases. When increasing to 3V, the turn-on voltage drops from about -1V to about -0.2V.
  • the turn-on voltage is controllable with the gate voltage, and a turn-on voltage as low as 0.2V can be obtained to achieve small signal rectification to reduce the The complexity of the signal rectification circuit.
  • This application also protects a chip, which may be an integrated chip, which includes a circuit and the gate control diode applied to the circuit.
  • the chip is an RF chip or a chip for a memory.
  • the gate control diode is used as a small-signal rectifier diode in the energy harvesting circuit of the chip to rectify the RF signal.
  • the gate control diode can also be used in a memory chip, and is mainly used in a gating circuit of a non-volatile magnetic random access memory, a resistance change memory, and a phase change memory.
  • the chip adopts the gate control diode, which can change the conduction direction of the current and improve the working performance of the chip.
  • the implementation of the present application also protects a method for manufacturing a gate-controlled diode, which can be used for manufacturing the above-mentioned gate-controlled diode.
  • the method includes:
  • step S1 a concave portion is formed on the surface 120 of the oxide protective layer 12 of the substrate 11, and a gate electrode 13 is formed in the concave portion.
  • FIG. 11 The specific diagram is shown in FIG. 11, which includes, in a first step, a photoresist is used to define a gate region on the oxide protective layer 12 by using a photoresist, and the photoresist is used as a mask to remove the surface of the oxide protective layer. Partial occlusion outside the gate area;
  • a reactive ion etching method is used to etch an oxide protective layer located in the gate region to form a recess in the oxide protective layer 12;
  • a gate electrode 13 is formed in the recessed portion by evaporation, wherein the gate electrode 13 fills the recessed portion;
  • the fourth step is to remove the photoresist.
  • the material of the oxide protection layer 12 is silicon dioxide
  • the material of the substrate is silicon
  • the gate is made of Ti or Au material.
  • the substrate and the oxide protective layer may be replaced with an insulating material such as quartz or sapphire.
  • This step further includes planarizing the gate electrode 13 so that a surface of the gate electrode 13 exposed on the recessed portion is flush with a surface 120 of the oxide protective layer 12.
  • step S2 as shown in FIG. 12, an atomic layer deposition process is used to form a gate insulating layer 14 on the surface of the oxide protective layer 12, so that the gate insulating layer 14 covers the gate 13.
  • the substrate shown in FIG. 11 is put into an ALD chamber to grow a gate insulating layer using atomic layer deposition technology.
  • the gate insulating layer uses HfO 2 , Al 2 O 3 , ZrO 2 , HfxZr with high dielectric constants.
  • One of 1- xO 2 , HfLaO, Y 2 O 3 instead of silicon dioxide, and the thickness can be made thinner using atomic layer deposition technology, which increases the gate capacitance and enables the gate to effectively control the first two dimensions
  • the conduction polarity of the material is 10 nm.
  • a channel layer and a drain electrode 19 are formed on the gate insulating layer 14.
  • the channel layer includes a first two-dimensional semiconductor layer 15, a second two-dimensional semiconductor layer 16, and a first The heterojunction 17 formed by the two-dimensional semiconductor layer 15 and the second two-dimensional semiconductor layer 16; the drain electrode 19 is located on the first two-dimensional semiconductor layer 15 and is insulated from the second two-dimensional semiconductor layer 16.
  • the material of the first two-dimensional semiconductor layer is tungsten diselenide having bipolar conductivity, and the material of the second two-dimensional semiconductor layer is tin diselenide.
  • the drain electrode 19 is completed after the first two-dimensional semiconductor layer 15 is formed and before the second two-dimensional semiconductor layer 16 is formed, as described below.
  • This step specifically includes: forming a first two-dimensional semiconductor layer 15 and a drain electrode 19 on the surface side of the first two-dimensional semiconductor layer 15 on the surface of the gate insulating layer 14 as shown in FIG. 3.
  • a film layer transfer process (growing on another substrate (such as a silicon substrate, a sapphire substrate, etc.), and then transferring to a substrate with a gate insulating layer prepared) or directly growing the first layer on the gate insulating layer
  • a first two-dimensional semiconductor layer 15 having a predetermined pattern is obtained after a two-dimensional semiconductor material layer through a patterning process.
  • the drain electrode 19 is then formed on the first two-dimensional semiconductor layer 15 by coating or depositing a metal layer and a patterning process. Due to the flatness of the gate, the first two-dimensional material layer is tiled on the gate insulation layer 14, and the material is not prone to cracks and wrinkles during the formation of the first and second material layers and is affected. Device performance.
  • a photoresist B is used to define an isolation layer region A on the layer structure composed of the first two-dimensional semiconductor layer 15 and the drain electrode 19 by using a photolithography process, and the photoresist B is used as a mask. Shielding part of the first two-dimensional semiconductor layer 15 and part of the drain electrode 19 outside the isolation layer region A;
  • An insulating oxide layer C is formed on the photoresist B and the isolation layer region A in a deposition manner.
  • the photoresist B covered with the insulating oxide layer C is removed to form an isolation layer 20 in the isolation layer area A, and the isolation layer covers part of the drain electrode 19 and the drain electrode.
  • the isolation layer 20 can insulate the drain from the second two-dimensional semiconductor layer 16 formed later. At the same time, this step is more suitable for protecting the drain and the first two-dimensional semiconductor layer 15 when manufacturing a diode in a large area.
  • a second two-dimensional semiconductor layer 16 and a heterojunction 17 are formed on the surface of the gate insulating layer 14 and the first two-dimensional semiconductor layer 15, the first two-dimensional A portion where the semiconductor layer 15 and the second two-dimensional semiconductor layer 16 overlap is a heterojunction 17, and the second two-dimensional semiconductor layer 16 is connected to a side of the isolation layer away from the drain electrode 19.
  • the method includes: forming a second two-dimensional semiconductor material layer D on the drain electrode 19, the isolation layer 20, the first two-dimensional semiconductor layer 15, and the unshielded gate insulating layer; Film transfer process (growth on other substrates (such as silicon substrate, sapphire substrate, etc.), and then transfer to the substrate on which the first two-dimensional semiconductor layer 15 has been prepared) or directly grow on the first two-dimensional semiconductor layer 15 .
  • the photoresist E is used as a mask to etch the second two-dimensional semiconductor material layer D to form a second two-dimensional semiconductor layer 16 having a predetermined pattern through a patterning process, and the first two-dimensional semiconductor layer 15 and the first A portion where the two-dimensional semiconductor layer 16 overlaps is a heterojunction 17.
  • the first two-dimensional semiconductor layer 15 and the second two-dimensional semiconductor layer 16 form a channel layer.
  • the drain 19 and the first between the drain 19 and the end of the second two-dimensional semiconductor material layer D may be protected by the isolation layer 20.
  • the two-dimensional semiconductor layer 15 avoids that the gap between the drain 19 and the end of the second two-dimensional semiconductor material layer D is too large (affects the conduction performance) or is too small (damages the drain), thereby avoiding the The semiconductor layer 15 causes accidental damage and destroys its performance; at the same time, the second two-dimensional semiconductor layer 16 covers the first two-dimensional semiconductor layer 15 to completely isolate the source from the first two-dimensional semiconductor layer 15.
  • a source electrode 18 is formed on the channel layer opposite to the drain electrode 19, wherein the source electrode 18 is connected to the drain electrode 19 through the heterojunction 17 to achieve the first In the conduction direction, a second conduction direction is achieved by the drain 19 through the heterojunction 17 to the source 18.
  • the source electrode 18 may be located on an end of the second two-dimensional semiconductor layer 16 away from the drain electrode 19, or may be located above a heterojunction.
  • a groove is provided on the opposite side of the second two-dimensional semiconductor layer 16 from the drain, and the source electrode 18 is located in the groove to reduce the step difference of the layer structure of the entire diode.
  • the source and drain are located on both sides of the heterojunction, reducing parasitic capacitance with the gate. 7a to 9b, the first conduction direction is a forward conduction, the diode is a forward diode, the second conduction direction is a reverse conduction, and the diode is a reverse diode.
  • the method for manufacturing a gate-controlled diode can manufacture diodes in large quantities at the same time.
  • the substrate includes several gate-controlled diode regions; each gate-controlled diode region is used to form a gate-controlled diode.
  • Each of the plurality of gate-controlled diodes having the same function is formed at the same time by using the same process step. For example, when forming an isolation layer, the isolation layers of several gate-controlled diodes are formed by forming a large-area isolation material layer and then patterning them uniformly. This can reduce processing steps and save costs.

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Abstract

本申请实施例提供一种栅控二极管，其包括衬底、层叠于衬底上的栅极、栅极绝缘层、第一二维半导体层、第二二维半导体层、源极和与源极间隔设置的漏极；栅极嵌设于衬底的表面，栅极绝缘层覆盖衬底设有栅极的表面；第一二维半导体层层叠于栅极绝缘层上，第二二维半导体层部分层叠于栅极绝缘层上，另一部分层叠第一二维半导体层上，第二二维半导体层与第一二维半导体层层叠的部分形成异质结，异质结在基底的正投影位于栅极在基底层的正投影内；源极与第二二维半导体层电导通且与第一二维半导体层绝缘，漏极与第一二维半导体层电导通与第二二维半导体层绝缘，栅控二极管的导电通路为由源极经异质结至漏极，或者由漏极经异质结至源极。

Description

栅控二极管及芯片 技术领域
本发明涉及电子通信技术领域，尤其涉及半导体器件，进一步的涉及栅控二极管以及具有所述栅控二极管的芯片。
背景技术
常见的半导体器件如二极管被广泛应用于整流、检波、限幅、稳压等电路中，属于一种具有两个电极的器件。传统的晶体二极管是一个由p型半导体和n型半导体形成的p-n结，在其界面处两侧形成了空间电荷层，并且建有自建电场，当不存在外加电压时，因为p-n结两边载流子浓度差引起的扩散电流和自建电场引起的漂移电流相等而处于电平衡状态。当产生正向电压偏置时，外界电场与二极管自建电场的互相抑消作用使载流子的扩散电流增加引起了正向电流。当产生反向电压偏置时，外界电场与自建电场进一步加强，形成在一定反向电压范围中与反向偏置电压值无关的反向饱和电流(不导通)。如此就使一个独立的二极管只允许电流由单一方向(正向或者反向)流过，所以，二极管在电路中应用的灵活度比较低。
发明内容
本申请实施例提供一种可以调控导通方向的半导体器件，以提高半导体器件的应用灵活性能。
第一方面，本申请提供了一种栅控二极管，其包括衬底、层叠于所述衬底上的栅极、栅极绝缘层、第一二维半导体层、第二二维半导体层、源极和与所述源极间隔设置的漏极；
所述栅极嵌设于所述衬底的表面，所述栅极绝缘层覆盖所述衬底设有栅极的表面；
所述第一二维半导体层为双极性导电材料形成，所述第一二维半导体层层叠于所述栅极绝缘层上，所述第二二维半导体层部分层叠于所述栅极绝缘层上，另一部分层叠所述第一二维半导体层上，所述第二二维半导体层与第一二维半导体层层叠的部分形成异质结，所述异质结在所述基底的正投影位于所述栅极在所述基底层的正投影内；
所述源极与所述第二二维半导体层电导通且与所述第一二维半导体层绝缘，所述漏极与所述第一二维半导体层电导通与所述第二二维半导体层绝缘，所述栅控二极管的导电通路为由所述源极经异质结至所述漏极，或者由所述漏极经所述异质结至所述源极。
本申请的栅控二极管采用二维半导体形成异质结，源极和漏极位于所述异质结两侧且栅极凹设于基底内，栅极与源极漏极之间的寄生电容减小，同时漏极连接的二维半导体层具有双极性导电，并且栅极绝缘层采用HfO 2、Al2O 3、ZrO 2、HfxZr 1-xO 2、HfLaO、Y 2O 3中的一种，厚度较薄，本实施例中，只有10nm，以使栅极有足够的栅电容，可以通过栅极电压来控制所述栅控二极管的导电通路的双向性，以使所述二极管包括正向导通与反向导通可调性，相较于现有技术的单一方向性的二极管具有较高的应用灵活性能。
一种实施方式中，所述栅极远离所述氧化物保护层的一侧凸出所述氧化物保护层的表面或者与所述氧化物保护层的该表面平齐。本实施例中，所述栅极远离所述氧化物保护层 的一侧的表面与所述氧化物保护层的表面平齐，以保证所述栅极绝缘层具有较平整度，在第一二维半导体层和第二二维半导体层制作过程中不容易出现破裂和褶皱而影响器件性能。
其中，所述第一二维半导体层的材料为二硒化钨，所述第二二维半导体层的材料为二硒化锡，但是不限于列举出的这两种二维半导体材料。
所述第一二维半导体层包括第一部分和连接第一部分的第二部分，所述第二二维半导体层包括第三部分和连接第三部分的第四部分，所述第三部分层叠于所述第一部分上形成异质结，所述源极位于所述第四部分的表面，所述漏极位于所述第二部分的表面。
一种实施方式中，所述栅控二极管还包括隔离层，所述隔离层位于所述漏极与所述第二二维半导体层构成所述异质结部分的端部之间。所述隔离层的材料为绝缘氧化物，所述隔离层实现漏极与第二二维半导体层的隔离。
一种实施方式中，在竖直方向上，所述源极位于所述异质结正上方，此时介入电阻相对较小，会获得更大的电流。
一种实施方式中，所述栅极包括与所述氧化物保护层连接的底面、邻近所述漏极的第一端面和邻近所述源极的第二端面，所述第一端面和第二端面连接所述底面的相对两端；
所述漏极包括第一侧面，所述源极包括与所述第一侧面间隔相对的第二侧面，所述第一侧面与第一端面共面，所述第二侧面与第二端面共面或者具有有效距离；即漏极、源极位于异质结相对两侧，可以避免所述漏极、源极与所述栅极之间的重叠部分，减小所述漏极与栅极之间的寄生电容，进而保证导通性能。
第二方面，本申请提供一种芯片，包括电路及应用于所述电路的所述的栅控二极管。所述芯片为RF能量采集芯片
第三方面，本申请提供一种栅控二极管的制作方法，所述方法包括：
步骤1，在基底的氧化物保护层的表面形成凹部，并在所述凹部内形成栅极。本步骤中，具体包括，采用光刻工艺使用光刻胶在所述氧化物保护层上定义栅极区域，并以光刻胶做掩膜将氧化物保护层表面上除栅极区域以外的部分遮挡。
采用反应离子刻蚀方式蚀刻位于所述栅极区域的氧化物保护层，以在所述衬底形成凹部。
采用蒸镀方式在所述凹部内形成栅极，其中，所述栅极将所述凹部填满。
去掉光刻胶。以实现将栅极嵌设在氧化物保护层上，减小与源漏极支架内的寄生电容。
步骤2，在所述氧化物保护层的表面形成栅极绝缘层，以使所述栅极绝缘层覆盖所述栅极，用于保护栅极和隔离异质结与氧化物保护层。所述栅极绝缘层材料为HfO 2、Al2O 3、ZrO 2、HfxZr 1-xO 2、HfLaO、Y 2O 3中的一种。
步骤3，在栅极绝缘层上形成沟道层和漏极，所述沟道层包括第一二维半导体层、第二二维半导体层及第一二维半导体层和第二二维半导体层形成的异质结，所述漏极位于所述第一二维半导体层上并与第二二维半导体层绝缘；其中，所述第一二维半导体层的材料为二硒化钨，所述第二二维半导体层的材料为二硒化锡。
本实施例中，在所述栅极绝缘层上形成沟道层的步骤，包括：
在所述栅极绝缘层的表面形成第一二维半导体层和位于第一二维半导体层表面一侧的漏极；
采用光刻工艺使用光刻胶在所述第一二维半导体层及漏极构成的层结构上定义隔离层区域，并以光刻胶做掩膜将位于所述隔离层区域以外的部分所述第一二维半导体层及部分漏极遮挡；
采用沉积的方式在所述光刻胶及所述隔离层区域上形成绝缘氧化物层，
去掉覆盖有绝缘氧化物层的所述光刻胶以在所述隔离层区域形成隔离层，所述隔离层覆盖部分所述漏极及所述漏极与第一二维半导体层的连接位置；其中，所述隔离层的材料为SiO2或Al 2O 3。
在所述栅极绝缘层的表面和所述第一二维半导体层上形成第二二维半导体层，所述第一二维半导体层和第二二维半导体层重叠的部分为异质结，且第二二维半导体层连接所述隔离层远离所述漏极的一侧。
本申请的栅控二极管的制作方法中，在制作第二二维半导体层之前先形成隔离层，由于隔离层的存在，可以避免在第二二维半导体材料层采用刻蚀方式制作图案过程中对所述第一二维半导体层与漏极连接的部分造成误伤而破坏其性能；同时，所述隔离层可以隔离所述漏极与所述第二二维半导体层，防止两者之间导通。
步骤4，在所述沟槽层上形成与所述漏极间隔相对的源极，其中，所述源极经异质结至所述漏极实现第一导通方向，由所述漏极经所述异质结至所述源极实现第二导通方向。所述源极为金属材料通过图案化工艺形成。
一种实施方式中，在基底的氧化物保护层的表面形成凹部，并在所述凹部内形成栅极的步骤中，还包括，对所述栅极进行平整化，使所述栅极露出所述凹部的表面与所述氧化物保护层的表面平齐，保证后续沟道层制作过程中的质量。
本申请所述的栅控二极管中，源极和漏极位于所述异质结两侧且栅极凹设于基底内，栅极与源极漏极之间的寄生电容减小，同时采用非二氧化硅材料的栅极绝缘层以及包含双向导电性的二维氧化物层，可以通过栅极电压来控制第一二维材料的导通极性，进而所述栅控二极管的导电通路的双向性，实现导通方向和开启电压的调控，以提高二极管的应用灵活性能，且可以实现小信号整流，以降低小信号整流电路的复杂度。
附图说明
图1a是本申请实施例提供的栅控二极管的截面示意图；
图1b是图1a所示栅控二极管的俯视图；
图2a和图2b分别是图1a所示的栅控二极管在形成所述第一二维半导体层后的截面示意图和俯视图；
图3是图1a所示的栅控二极管在形成所述漏极后的截面示意图；
图4a和图4b分别是图1a所示的栅控二极管形成隔离层后的截面图和俯视图；
图5a和图5b分别是图1a所示的栅控二极管形成第二二维半导体层后的截面图和俯视图；
图6为栅控二极管的另一实施例的截面示意图，与图1a不同在于栅极与源极和漏极是否有重叠部分；
图7a、图7b是图1a、图6所示的栅控二极管正向工作原理图；
图8a、图8b是图1a、图6所示的栅控二极管反向工作原理图；
图9a、图9b是图1a、图6所示的栅控二极管通过栅压控制正向二极管和反向二极管工作开启电压线图；
图10是本申请提供的栅控二极管制作方法流程图；
图11-图12、图13a、图13b、图14a、图14b是本申请的栅控二极管制作方法在制作过程中对应多个步骤的结构示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
本申请保护一种栅控二极管，其应用于整流、稳压等电路中，并通过栅压控制开启电压的大小。以下请参阅图1a和图1b，本实施例中，以左右方向为X轴方向，垂直于所述栅控二极管厚度(衬底表面)的方向为Y轴方向。沿着X轴方向，即是栅极13、第一二维半导体层15和所述第二二维半导体层16的长度方向，所述栅极13、第一二维半导体层15和所述第二二维半导体层16的宽度方向为Z轴方向。
所述栅控二极管包括衬底10、层叠于所述衬底10的表面的氧化物保护层12、栅极13、栅极绝缘层14、第一二维半导体层15、第二二维半导体层16以及源极18和漏极19，所述源极18与所述漏极19间隔设置。所述栅极13嵌设于所述衬底10的表面上，所述栅极绝缘层14覆盖所述衬底10设有所述栅极13的表面。本实施例中，所述栅极绝缘层14由具有高介电常数材料形成。
所述第一二维半导体层15由双极性导电材料形成，所述第一二维半导体层15层叠于所述栅极绝缘层14上，所述第二二维半导体层16部分层叠于所述栅极绝缘层14上，另一部分层叠于部分所述第一二维半导体层15上，所述第二二维半导体层16与第一二维半导体层15层叠部分形成异质结17，所述异质结17在所述基底11的正投影位于所述栅极13在所述基底11层的正投影内。所述异质结是由两层以上不同的半导体材料层叠相接触的界面区域。
所述源极18与第二二维半导体层16电导通并与所述第一二维半导体层15绝缘，所述漏极19与所述第一二维半导体层15电导通并与所述第二二维半导体层16绝缘，所述栅控二极管的导电通路为由所述源极18经异质结17至所述漏极19，或者由所述漏极19经所述异质结17至所述源极18。
需要说明的是，本实施例中，所述栅控二极管各个功能层为规则结构，功能层的厚度是均匀设置的，并且可以保证高的工作效率，这种设计符合现有的芯片、电子设备等小型化、轻薄化发展趋势。由于源极18和漏极19间隔设置且无连接的可能，获取截面时只要截取到异质结、源极和漏极，既可以截取到所述栅控二极管的实现栅压控制的各个功能层结构，而当所述这些各个功能层为非均匀的情况下，但各个功能层的电性连接关系是不会改变的，只要符合本实施例截取的截面的层结构和配合关系，均可以解决本申请解决的技术问题及实现本申请的技术效果。各个功能层包括衬底、栅极、栅极绝缘层、异质结、源极和漏极，以及本申请第二实施例的隔离层。比如，源极18和漏极19为圆柱形或者其它 非规则形状，但其功能均是与异质结配合供电子流动，源极18与第二二维半导体层16电连接且与第一二维半导体层15绝缘，而漏极19与第一二维半导体层15电连接而与第二二维半导体层16绝缘，所述第一二维半导体层15和第二二维半导体层16永远不能与栅极13接触。所以本实施例中以截面和俯视图作为参照示意图进行说明。
本申请实施例，所述的栅控二极管采用二维半导体形成异质结，所述第一二维半导体层15的材料为二硒化钨，为双极性导电材料，所述第二二维半导体层16的材料为二硒化锡等重掺杂P型或N型离子的二维半导体材料。其中与漏极19连接的第一二维半导体层15具有双极性导电，并且异质结17与栅极13之间只有栅极绝缘层14间隔，栅极绝缘层14采用具有高介电常数的材料形成，以使栅极有足够的栅电容可以去控制第一二维半导体层15的导通极性，进而实现所述栅控二极管的导电通路的双向性，即由所述源极18经异质结17至所述漏极19(反向)的导通，或者由所述漏极19经所述异质结17至所述源极18(正向)的导通，以使所述二极管具有正向导通与反向导通的特性，相较于现有技术的单一方向性的二极管具有较高的灵活性。同时，可以通过控制栅极电压来控制二极管正向导通或反向导通的开启电压，当开启电压小时可减小整流时信号电压的损耗，进而减小工作电压的耗损。其中，当栅极13控制第一二维半导体层15让其变成p型掺杂的时候，由于第二二维半导体层16为重掺杂的p型或者n型，两者的异质结为pn+型，或者n+p型，空穴浓度较大实现导电，为正向二极管；当栅极控制第一二维半导体层15让其变成n型掺杂的时候，自有电子浓度较高而导电，两者的异质结为nn+结，就为反向二极管，所以只要控制第一二维半导体层15的掺杂离子类型即可实现正向导通或者反向导通。
具体的，所述衬底10由石英、蓝宝石等绝缘的材料形成，或者所述衬底10包括基底11和层叠于所述基底11表面的氧化物保护层12，所述基底11为硅材料制成，所述氧化物保护层12由二氧化硅材料制成。而本实施例中，所述衬底10包括基底11和氧化物保护层12，所述氧化物保护层12覆盖所述基底11用于形成栅控二极管的的整个表面，以与所述基底构成具有氧化物的衬底结构，以保证载流子的传输。所述栅极绝缘层14采用具有高介电常数的HfO 2、Al 2O 3、ZrO 2、HfxZr 1-xO 2、HfLaO、Y 2O 3中的一种；所述栅极13、源极18和漏极19均由导电金属材料制成。
本实施例中，所述氧化物保护层12包括与所述基底11连接的第一表面(图未标)和与所述第一表面相对设置的第二表面120，第一表面朝向所述基底11并与基底11连接。所述栅极13嵌设于所述氧化物保护层12的第二表面120。具体的，在所述氧化物保护层12的第二表面120上凹设凹部，所述栅极13形成于所述凹部内并填满所述凹部。所述氧化物保护层12为层结构，本实施例中，所述凹部为矩形凹槽，用于容纳所述栅极13，当然，所述凹部也可以是其它形状的凹槽。
本实施例中，所述栅极13为规则的矩形层状，所述栅极13的表面凸出所述氧化物保护层12的表面120或者与所述氧化物保护层12的所述表面120平齐。本实施例中，所述栅极13的表面与所述氧化物保护层12的表面120平齐，可以保证氧化物半导体层11与栅极13的平整性，以保证所述栅极绝缘层14具有较高的平整度，在第一二维半导体层15和第二二维半导体层16的制作过程中不容易出现破裂和褶皱而影响所述栅控二极管的性能。
所述栅极绝缘层14覆盖所述衬底10设有所述栅极13的表面。具体的，所述栅极绝缘 层14覆盖氧化物保护层12的第二表面120，用于栅极13与层叠于栅极13上的其他层结构绝缘。本实施例中，所述栅极绝缘层14覆盖氧化物保护层12的整个第二表面120，(参见图2b)可以直接通过将基底11放进ALD腔室利用原子层沉积技术进行生长而形成，从而不需要光刻工艺，简化了加工步骤。栅极绝缘层14采用高介电常数的材料制成而非二氧化硅，且厚度可以用原子层沉积技术做到较薄，提高了栅电容，使得栅极能有效控制具有双极性导电性能的第一二维半导体层15的导通极性，从而控制二极管的导电通路的双向性。进一步的，所述栅极绝缘层14的厚度位于2nm-50nm之间，只要实现栅极13能很好的控制第一二维半导体层15即可，因为不同氧化物的介电常数不同，用不同的氧化物做栅极绝缘层14所需的厚度也不一样，也和应用场景的工作电压有关，如果工作电压高，则需要加大这个厚度以承受较高的工作电压，类似地，如果工作电压小，也可以减小这个厚度，这样在小的工作电压下也能有效调控所述栅控二极管。
请参阅图2a、图2b，在X轴方向上，所述第一二维半导体层15包括第一部分151和与第一部分151连接的第二部分152，所述第一部分151与所述第二部分152为同一工艺步骤形成的同一层结构。
本实施例中，所述第一二维半导体层15为规则矩形层状且第一部分151和第二部分152厚度均匀，其形成于所述栅极绝缘层14的表面140上；所述第一部分151和所述第二部分152的正投影完全位于所述栅极13内并与所述栅极13部分重叠，所述第一二维半导体层15的宽度小于等于所述栅极13的宽度，所述第一部分151的长度小于所述栅极13的长度。所述第一二维半导体层15为不规则的情况下，所述长度和宽度是指该两个维度的最大尺寸。在所述第一二维半导体层15形成后即形成漏极19后才去做异质结17。故本实施例中，先介绍漏极19和隔离层20在提供所述第二二维半导体层16与异质结的实施例。
参阅图3，本实施例中，所述漏极19是通过金属层覆盖所述第一二维半导体层15和栅极绝源层14的表面，然后通过涂层及光刻工艺形成于所述第一二维半导体层15的第二部分152的表面上远离第一部分151的一侧。本实施例的漏极19为厚度均匀的长条形并包括朝向所述源极18的第一侧面191。所述漏极19的长度方向为所述栅极13的宽度方向也就是Z轴方向，本实施例中漏极19的长度大于第一二维半导体15的宽度。在其他实施方式中，所述漏极的形状不限于长条形，但要覆盖所述第一二维半导体层15且不超过所述栅极绝缘层14的边缘，以保证导电效率。漏极19厚度可以为阶梯分布，可以覆盖所述第二部分152的端部并与栅极绝缘层14的表面连接，但必须与栅极13绝缘。实际上，为了减少二极管器件的体积，所述漏极19形成于所述第二部分152的表面即可。需要说明的是，所述第一二维半导体层15的第一部分151和漏极19之间具有所述第二部分152的部分区域Q，为了栅极13对所述第一二维半导体层15达到最大有效控制，所述部分区域Q的正投影位于所述栅极13内。所述漏极19与所述第三部分161远离第四部分162的端部间隔且绝缘设置，本实施例中，是通过隔离层实现，具体参见下文描述。
进一步的，请参阅图1a、图4a和图4b，所述栅控二极管还包括设于所述第一二维半导体层15上的隔离层20，所述隔离层20位于所述漏极19与所述第二二维半导体层16之间。在Z轴方向上所述隔离层20的宽度小于或等于所述漏极19的长度并大于或等于所述第三部分161的宽度，以保证可以有效隔离所述漏极19与所述第二二维半导体层16。在Z 轴方向上，所述隔离层20的宽度小于所述漏极19的长度，可以节省加工材料。所述隔离层20通过光掩膜和涂布工艺在所述第一二维半导体层15的第二部分152上形成。然后再通过光刻工艺形成所述第二二维半导体层16的基础材料层，通过蚀刻工艺去除与所述漏极19连接的多余的二维半导体层的基础材料层才形成所述的与漏极绝缘的第二二维半导体层16。所述隔离层20的材料为SiO 2或Al 2O 3。具体的，通过膜层转移工艺(生长在其它基底(比如硅基底、蓝宝石基底等)上)，然后转移至已制备好有栅极绝缘层的基底上或者在栅极绝缘层上直接生长第一二维半导体材料层之后通过图案化工艺得到具有预设图案的第一二维半导体层15。然后通过涂布或者沉积金属层以及图案化工艺在所述第一二维半导体层15上形成所述漏极19。由于栅极的平整性，所述第一二维材料层平铺在所述栅极绝缘层14上，在形成所述第一二维半导体材料层的过程中材料不容易出现破裂和褶皱而影响器件性能。
请参阅图5a、图5b，所述第二二维半导体层16包括沿着X轴方向依次连接第三部分161、第四部分162及延伸部分163。所述第三部分161与所述第四部分162及延伸部分163为同一工艺步骤形成的同一层结构。所述第二二维半导体层16在Y轴方向视角看，为规则矩形层状，所述第三部分161形成于所述第一部分151的表面上并覆盖所述第一部分151，并且与所述第一部分151形成所述异质结17，所述异质结17的正投影完全位于所述栅极13内。其中，所述第三部分161和所述第一部分151在栅极13的正投影完全重合。可以理解为在X轴方向上，所述第三部分161的长度等于所述第一部分151的长度，Y轴方向上所述第三部分161的宽度等于所述第一部分151的宽度。当然，所述第三部分161可以大于所述第一部分151的宽度尺寸。所述第三部分161的正投影完全位于所述栅极13内并与所述栅极13部分重叠，即所述第二二维半导体层16的宽度小于或等于所述栅极13的宽度，所述第三部分161的长度小于所述栅极13的长度。所述第三部分161层叠于所述栅极绝缘层14的表面140上并覆盖所述第一部分151的端部。第三部分161和第四部分162的厚度是均匀的且相同，第四部分162只是在覆盖第一部分151的端部至栅极绝缘层14时产生台阶落差的位置厚度较大。
所述延伸部分163位于所述第二部分162的部分区域Q上，所述隔离层20位于所述漏极19与延伸部分163之间，且所述隔离层20相对两表面分别连接所述漏极19与所述延伸部分163，将漏极19与第二二维半导体层16绝缘，防止漏极19与第二二维半导体层16电导通。具体的，所述隔离层20的一端伸出第二二维半导体层16的延伸部分163并覆盖部分所述漏极19，另一端位于所述延伸部分163与所述第一部分151之间。所述隔离层20可以在蚀刻所述第二二维半导体层16的基础材料层时保护漏极19和第一二维半导体层15不被蚀刻到，达到保护的效果；同时，隔离层20实现绝缘效果。
在其它实施方式中，所述第一二维半导体层15和第二二维半导体层16非规则情况下或者非矩形情况下，只要保证异质结17的正投影是一定位于所述栅极13内即可，进而保证栅极13电压对第一二维半导体层15的有效控制。基于二硒化锡和双极性导电性能的二硒化钨形成的异质结可以通过调控栅极电压来实现所述栅控二极管的正向导通和反向导通的控制，并且二硒化锡和二硒化钨形成的异质结无晶格失配不会导致界面缺陷，在制备异质结二极管的工艺上比较简单，且异质结17能更好的抑制所述栅控二极管的反向电流，获 得更大的整流比。
请参图1a和图1b，所述源极18与所述漏极19间隔设置。所述源极18位于所述第二二维半导体层16的第四部分162的表面远离第三部分161的一侧，所述源极18与所述漏极19的形成工艺相同。本实施例的源极18为厚度均匀的长条形，源极18的长度方向为所述栅极13的宽度方向，并且源极18的长度大于第二二维半导体16的宽度。在其他实施方式中，所述源极18的形状不限于长条形，但要覆盖所述第二二维半导体16且不超过所述栅极绝缘层14的边缘，以保证导电效率。源极18厚度可以为阶梯分布，可以覆盖所述第四部分162的端部并与栅极绝缘层14的表面连接，但必须与栅极13绝缘。实际上，为了减少二极管器件的体积及厚度，所述源极18形成于所述第四部分162的表面即可。进一步的，所述第四部分162的表面上远离第三部分161的一侧设有凹槽，所述源极18形成于所述凹槽内。本实施例中，所述源极18的正投影部分与所述栅极13一小部分重叠。在其他实施方式中，所述源极18可以层叠于构成所述异质结17的所述第三部分161上并与所述漏极19间隔一定距离且该距离不影响二极管的导电率，此时接入电阻相对较小，可以获得更大的电流。
本实施例中，如图1a所示，所述源极18和漏极19位于异质结17的相对两侧，而栅极13嵌入氧化物保护层12内并非源极和漏极之间与源极和漏极相对，栅极13的相对两侧(沿着X轴方向方向看)与源极18、漏极19完全错开，避免栅极13与源极18和漏极19在X轴方向方向上存在更大的交叠区域(平行板电容器原理)，而产生更大交叠寄生电容，减小本申请的栅极13与源极18、漏极19交叠面积，因而寄生电容会小很多以实现减小栅极13相对两侧与源极18、漏极19间的寄生电容，提升导电率的目的，进而在高频应用时信号损失较小，有利于提高器件的高频特性。
请参阅图6，在另一种实施例中，所述栅极13包括与所述氧化物保护层12连接的底面130、第一端面131和第二端面132，所述第一端面131和第二端面132连接所述底面130的位于X轴方向上的相对两端。所述漏极19包括朝向所述源极18的第一侧面191，所述源极18包括与所述第一侧面191间隔相对的第二侧面181，沿着Y轴方向，所述第一侧面191与第一端面131共面或者具有有效距离(实现栅极对源漏极控制的距离)，所述第二侧面181与第二端132面共面或者具有有效距离。本实施例中，所述第一侧面191与第一端面131共面，所述第二侧面181与第二端132面共面，从而可以减小所述漏极19、源极18与所述栅极13之间的在Y轴方向上的交叠区域，更好的减小所述源极18、漏极19与栅极13之间的寄生电容，进而保证有足够的控制电压。
本实施例中，所述栅控二极管的导电通路包括正向导通通路和反向导通通路，所述正向导通通路是指由所述漏极19经异质结17至所述源极18，导通电流由漏极19经异质结17的第二二维半导体层16到第一二维半导体层15后至所述源极18。反向导通通路是指由所述源极18经所述异质结17至所述漏极19，导通电流由源极18经异质结17的第一二维半导体层到第二二维半导体层后至所述漏极19。
具体的，参见图7a、图7b，为二极管正向工作原理图。当Vg-V T＜0时，如图所示，栅压对第一二维半导体层15进行p型静电掺杂，与n型导电的第二二维半导体层16构成pn结二极管，当Vd＞0时，载流子为扩散输运，电子由源极18注入第二二维半导体层16， 然后跨越势垒(异质结)进入第一二维半导体层15并被漏极19搜集，空穴从漏极19注入第一二维半导体层15，然后跨越结区势垒并被源极18搜集，即完成正向导通。当Vd＜0，pn结处于反偏状态，结区势垒宽度较大，阻止了载流子的运动，表现为高阻(不导通)的状态。其中，Vg为栅压，V T为阈值电压，Vd为漏极所加偏压。
当正向导通时，随着Vg-V T的减小，漏极19与第一二维半导体层15之间的势垒宽度减小，空穴更易注入第一二维半导体层15，因此开启电压降低，如图9a正向二极管的I-V特性曲线所示，正向二极管的开启电压随栅压可调节，且随栅压的减小而减小，当栅压从-4V降至-5V时，开启电压从约0.8V降至0.3V。
参见图8a、图8b，为二极管反向工作原理图，当Vg-V T＞0，且Vd＜0时，其对应的能带对应关系原理图8b所示，栅压对第一二维半导体层15进行n型掺杂，多数载流子电子由漏极19注入第一二维半导体层15，经第二二维半导体层16后进入源极18，二极管为导通状态，即反向导通。当Vg-V T＞0，且Vd＞0时，图8a所示，多数载流子由源极18注入后遇到第二二维半导体层16-第一二维半导体层15界面处(异质结)的势垒较高，载流子难以越过势垒，产生的电流很小，少子可以经漏极19注入，但少子的数量较少，产生的电流也很小，二极管为高阻(不导通)状态。二极管具有更小的结电容，降低点压，因此可应用于高频信号的整流。
当Vg-V T＞0，且Vd＜0时，二极管反向导通时，随着Vg-V T的增大，漏极与第二二维半导体层16之间的势垒宽度变窄，电子更易经隧穿由漏极注入第一二维半导体层15，开启电压降低。图9b为反向二极管的I-V特性曲线，反向二极管的开启电压可由栅压进行调节，从图9b中可看出，随栅压增加，反向二极管的开启电压降低，当栅压从-3V增加至3V时，开启电压从约-1V降至约-0.2V。本申请所述栅控二极管的导电通路的以正向二极管和反向二极管工作时，其开启电压随栅极电压可控，可以获得低至0.2V的开启电压，实现小信号整流，以降低小信号整流电路的复杂度。
本申请还保护一种芯片，所述芯片可以是集成芯片，其包括电路及应用于所述电路的所述栅控二极管。所述芯片为RF芯片或者用于存储器的芯片。所述芯片为RF芯片时，所述栅控二极管应用于所述芯片的能量采集电路中作为小信号的整流性二极管对RF信号进行整流。所述栅控二极管还可以用于存储器的芯片，主要是用于非易失性的磁性随机存储器、阻变式存储器及相变存储器的选通电路中。所述芯片采用了所述栅控二极管，可以实现电流的导通方向的更换，提高了芯片的工作性能。
请参阅图10，本申请实施还保护一种栅控二极管的制作方法，可以用于制作上述栅控二极管。所述方法包括：
步骤S1，在基底11的氧化物保护层12的表面120形成凹部，并在所述凹部内形成栅极13。
具体的如图11，包括，第一步，采用光刻工艺使用光刻胶在所述氧化物保护层12上定义栅极区域，并以光刻胶做掩膜将氧化物保护层表面上除栅极区域以外的部分遮挡；
第二步，采用反应离子刻蚀方式蚀刻位于所述栅极区域的氧化物保护层，以在所述氧化物保护层12形成凹部；
第三步，采用蒸镀方式在所述凹部内形成栅极13，其中，所述栅极13将所述凹部填 满；
第四步，去掉光刻胶。
本实施例中，所述氧化物保护层12的材料为二氧化硅，所述基底的材料为硅，所述栅极为Ti或Au材料制成。当然，所述基底和氧化物保护层可以用石英或者蓝宝石等绝缘材料替代。
本步骤中，还包括，对所述栅极13进行平整化，使所述栅极13露出所述凹部的表面与所述氧化物保护层12的表面120平齐。
步骤S2，如图12，采用原子层沉积工艺在所述氧化物保护层12的表面形成栅极绝缘层14，以使所述栅极绝缘层14覆盖所述栅极13。
具体的是将图11所示的基底放进ALD腔室利用原子层沉积技术进行栅极绝缘层生长，栅极绝缘层采用具有高介电常数的HfO 2、Al 2O 3、ZrO 2、HfxZr 1-xO 2、HfLaO、Y 2O 3中的一种，而非二氧化硅，且厚度可以用原子层沉积技术做到较薄，提高了栅电容，使得栅极能有效控制第一二维材料的导通极性。本实施例中，所述栅极绝缘层的厚度为10nm，
如图3、图1a，步骤S3，在栅极绝缘层14上形成沟道层和漏极19，所述沟道层包括第一二维半导体层15、第二二维半导体层16及第一二维半导体层15和第二二维半导体层16形成的异质结17；所述漏极19位于所述第一二维半导体层15上并与第二二维半导体层16绝缘。
本实施例中，所述第一二维半导体层的材料为具有双极性导电的二硒化钨，所述第二二维半导体层的材料为二硒化锡。本实施例中，漏极19是在第一二维半导体层15形成后，第二二维半导体层16形成之前完成的，具体如下所述。
本步骤具体包括：如图3，在所述栅极绝缘层14的表面形成第一二维半导体层15和位于第一二维半导体层15表面一侧的漏极19。本步骤中，通过膜层转移工艺(生长在其它基底上(比如硅基底、蓝宝石基底等)，然后转移至已制备好有栅极绝缘层的基底上)或者在栅极绝缘层上直接生长第一二维半导体材料层之后通过图案化工艺得到具有预设图案的第一二维半导体层15。然后通过涂布或者沉积金属层以及图案化工艺在所述第一二维半导体层15上形成所述漏极19。由于栅极的平整性，所述第一二维材料层则平铺在所述栅极绝缘层14上，在形成所述第一第二材料层的过程中材料不容易出现破裂和褶皱而影响器件性能。
参阅图13a和图13b，采用光刻工艺使用光刻胶B在所述第一二维半导体层15及漏极19构成的层结构上定义隔离层区域A，并以光刻胶B做掩膜将位于所述隔离层区域A以外的部分所述第一二维半导体层15及部分漏极19遮挡；
采用沉积的方式在所述光刻胶B及所述隔离层区A域上形成绝缘氧化物层C。
如图4a和图4b，去掉覆盖有绝缘氧化物层C的所述光刻胶B以在所述隔离层区域A形成隔离层20，所述隔离层覆盖部分所述漏极19及所述漏极19与第一二维半导体层15的连接位置。所述隔离层20可以将漏极与后续形成的第二二维半导体层16绝缘，同时，本步骤更适合在大面积制作二极管时，对漏极和第一二维半导体层15的保护。
图14a和图14b以及图6，在所述栅极绝缘层14的表面和所述第一二维半导体层15上形成第二二维半导体层16及异质结17，所述第一二维半导体层15和第二二维半导体层 16重叠的部分为异质结17，且第二二维半导体层16连接所述隔离层远离所述漏极19的一侧。具体包括：先在所述漏极19、隔离层20、第一二维半导体层15以及未被遮挡的栅极绝缘层上形成第二二维半导体材料层D；第二二维半导体材料层通过膜层转移工艺(生长在其它基底上(比如硅基底、蓝宝石基底等)，然后转移至已制备好有第一二维半导体层15的基底上)或者在第一二维半导体层15上直接生长。然后通过图案化工艺使采用光刻胶E为掩膜板蚀刻第二二维半导体材料层D形成具有预设图案的第二二维半导体层16，并且所述第一二维半导体层15和第二二维半导体层16重叠的部分为异质结17。所述第一二维半导体层15和第二二维半导体层16形成沟道层。
在此步骤中，在第二二维半导体材料层D刻蚀过程中，可以通过隔离层20保护漏极19和漏极19与第二二维半导体材料层D端部之间的所述第一二维半导体层15，避免漏极19与第二二维半导体材料层D的端部之间的空隙过大(影响导通性能)或者过小(损坏漏极)，进而避免对第一二维半导体层15造成误伤而破坏其性能；同时第二二维半导体层16将第一二维半导体层15覆盖以实现完全隔离源极与第一二维半导体层15。
再次参阅图1a，步骤S4，在所述沟道层上形成与所述漏极19间隔相对的源极18，其中，所述源极18经异质结17至所述漏极19实现第一导通方向，由所述漏极19经所述异质结17至所述源极18实现第二导通方向。
所述源极18可以位于所述第二二维半导体层16的表面上远离漏极19的端部，也可以位于异质结上方。本实施例中，所述第二二维半导体层16与所述漏极相对的一侧设有凹槽，所述源极18位于凹槽内，以减小整个二极管的层结构的段差，所述源极和漏极位于异质结两侧，减小与栅极之间的寄生电容。结合图7a至图9b，所述第一导通方向即为正向导通，二极管为正向二极管，所述第二导通方向为反向导通，二极管为反向二极管。
本申请实施例所述的栅控二极管的制作方法，可以大批量同时制作二极管，实际上，所述衬底上包括数个栅控二极管区域；每一个栅控二极管区域用于形成一个栅控二极管，所述数个栅控二极管的每一相同功能的层在形成时，都是采用同一工艺步骤同时形成。比如，在形成隔离层时，数个栅控二极管的隔离层是通过大面积的形成隔离材料层再统一图案化形成，如此可以减少加工工艺步骤，节省成本。
以上是本发明实施例的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明实施例原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明实施例的保护范围。

Claims (12)

  1. 一种栅控二极管，其特征在于，包括衬底、层叠于所述衬底上的栅极、栅极绝缘层、第一二维半导体层、第二二维半导体层、源极和与所述源极间隔设置的漏极；
    所述栅极嵌设于所述衬底的表面，所述栅极绝缘层覆盖所述衬底设有栅极的表面；
    所述第一二维半导体层为双极性导电材料形成，所述第一二维半导体层层叠于所述栅极绝缘层上，所述第二二维半导体层部分层叠于所述栅极绝缘层上，另一部分层叠所述第一二维半导体层上，所述第二二维半导体层与第一二维半导体层层叠的部分形成异质结，所述异质结在所述基底的正投影位于所述栅极在所述基底层的正投影内；
    所述源极与所述第二二维半导体层电导通且与所述第一二维半导体层绝缘，所述漏极与所述第一二维半导体层电导通与所述第二二维半导体层绝缘，所述栅控二极管的导电通路为由所述源极经异质结至所述漏极，或者由所述漏极经所述异质结至所述源极。
  2. 如权利要求1所述的栅控二极管，其特征在于，所述栅极绝缘层的材料为HfO 2、Al2O 3、ZrO 2、HfxZr 1-xO 2、HfLaO、Y 2O 3中的一种。
  3. 如权利要求1或2所述的栅控二极管，其特征在于，所述栅极绝缘层的厚度为2nm-50nm。
  4. 如权利要求1-3任一项所述的栅控二极管，其特征在于，所述第二二维半导体层为中掺杂p型或n二维半导体材料制成。
  5. 如权利要求1-4任一项所述的栅控二极管，其特征在于，所述第一二维半导体层的材料为二硒化钨，所述第二二维半导体层的材料为二硒化锡。
  6. 如权利要求1-5任一项所述的栅控二极管，其特征在于，所述第一二维半导体层包括第一部分和连接第一部分的第二部分，所述第二二维半导体层包括第三部分和连接第三部分的第四部分，所述第三部分层叠于所述第一部分上形成异质结，所述源极位于所述第四部分的表面，所述漏极位于所述第二部分的表面。
  7. 如权利要求6所述的栅控二极管，其特征在于，所述栅控二极管还包括隔离层，所述隔离层位于所述漏极与所述第二二维半导体层构成所述异质结部分的端部之间。
  8. 如权利要求6所述的栅控二极管，其特征在于，所述隔离层的材料为绝缘氧化物。
  9. 如权利要求1-8任一项所述的栅控二极管，其特征在于，所述栅极朝向所述栅极绝缘层的一侧凸出所述氧化物保护层的表面或者与所述氧化物保护层的表面平齐。
  10. 如权利要求1-9任一项所述的栅控二极管，其特征在于，所述栅极包括与所述氧化物保护层连接的底面、邻近所述漏极的第一端面和邻近所述源极的第二端面，所述第一端面和第二端面连接所述底面的相对两端；
    所述漏极包括第一侧面，所述源极包括与所述第一侧面间隔相对的第二侧面，所述第一侧面与第一端面共面，所述第二侧面与第二端面共面或者具有有效距离。
  11. 如权利要求1-10任一项所述的栅控二极管，其特征在于，所述基底的材料为硅，所述氧化物保护层的材料为二氧化硅。
  12. 一种芯片，其特征在于，包括电路及应用于所述电路的如权利要求1-11任一项所述的栅控二极管。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102592997A (zh) * 2012-03-11 2012-07-18 复旦大学 一种栅控二极管半导体器件的制造方法
US20150171202A1 (en) * 2013-12-17 2015-06-18 Fujitsu Limited Field effect semiconductor device
CN107104140A (zh) * 2017-06-15 2017-08-29 北京大学 一种二维材料/半导体异质结隧穿晶体管及制备方法
CN107248530A (zh) * 2017-06-15 2017-10-13 北京大学 一种二维材料/半导体异质结垂直隧穿晶体管及制备方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101336482B (zh) * 2005-11-29 2010-12-01 香港科技大学 低密度漏极hemt
US7385251B2 (en) 2006-01-18 2008-06-10 International Business Machines Corporation Area-efficient gated diode structure and method of forming same
US7888775B2 (en) * 2007-09-27 2011-02-15 Infineon Technologies Ag Vertical diode using silicon formed by selective epitaxial growth
US9761443B2 (en) * 2014-01-31 2017-09-12 The Regents Of The University Of California Method for passivating surfaces, functionalizing inert surfaces, layers and devices including same
US20170098716A1 (en) * 2015-02-20 2017-04-06 University Of Notre Dame Du Lac Two-dimensional heterojunction interlayer tunneling field effect transistors
US10504721B2 (en) * 2015-04-30 2019-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Staggered-type tunneling field effect transistor
CN107735864B (zh) * 2015-06-08 2021-08-31 美商新思科技有限公司 衬底和具有3d几何图形上的2d材料沟道的晶体管
CN106685247B (zh) 2017-01-12 2018-03-09 中国科学院地质与地球物理研究所 一种微弱小信号精密整流系统
US10236386B2 (en) * 2017-01-17 2019-03-19 The Board Of Trustees Of The University Of Illinois Vertical hetero- and homo-junction tunnel field-effect transistors
US11605730B2 (en) * 2018-01-19 2023-03-14 Northwestern University Self-aligned short-channel electronic devices and fabrication methods of same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102592997A (zh) * 2012-03-11 2012-07-18 复旦大学 一种栅控二极管半导体器件的制造方法
US20150171202A1 (en) * 2013-12-17 2015-06-18 Fujitsu Limited Field effect semiconductor device
CN107104140A (zh) * 2017-06-15 2017-08-29 北京大学 一种二维材料/半导体异质结隧穿晶体管及制备方法
CN107248530A (zh) * 2017-06-15 2017-10-13 北京大学 一种二维材料/半导体异质结垂直隧穿晶体管及制备方法

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