WO2020056843A1 - 阵列基板、显示面板及显示设备 - Google Patents

阵列基板、显示面板及显示设备 Download PDF

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Publication number
WO2020056843A1
WO2020056843A1 PCT/CN2018/111534 CN2018111534W WO2020056843A1 WO 2020056843 A1 WO2020056843 A1 WO 2020056843A1 CN 2018111534 W CN2018111534 W CN 2018111534W WO 2020056843 A1 WO2020056843 A1 WO 2020056843A1
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Prior art keywords
electrode
pixel
array substrate
pole
gate
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Ceased
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PCT/CN2018/111534
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English (en)
French (fr)
Inventor
李泽尧
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US16/253,219 priority Critical patent/US20200089033A1/en
Publication of WO2020056843A1 publication Critical patent/WO2020056843A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel and a display device using the array substrate.
  • a thin film transistor liquid crystal display occupies a dominant position in the current display market due to its advantages such as high response speed, high brightness, and high contrast.
  • a thin film transistor liquid crystal display includes an array substrate, a color substrate, and a liquid crystal layer filled between the two substrates.
  • an array substrate with a bottom-gate structure is generally used.
  • FIG. 1 is a schematic diagram of a pixel unit of a general liquid crystal display panel.
  • the structure includes a data line 3a, a gate line 4a, and a thin film transistor 1a (Thin film transistor (TFT) and pixel electrode 2a.
  • the channel length is generally equal to the distance between the source and the drain.
  • the channel width is the perimeter of the channel. In the existing structure, the width and length are relatively small, which causes the charge rate of the array substrate to be too small, thereby affecting the display panel display effect.
  • the main purpose of this application is to provide an array substrate, which aims to improve the light transmittance of a display panel and improve the display effect.
  • the array substrate provided in this application includes:
  • a plurality of pixel structures each of which includes a thin film transistor covering a gate line and a pixel electrode located in a pixel region;
  • the thin film transistor includes a gate electrically connected to a gate line, a semiconductor layer covering the gate, a first electrode and a second electrode covering the semiconductor layer and spaced apart, and the second electrode surrounds The first electrode, the second electrode is electrically connected to the data line, and the pixel electrode is electrically connected to the first electrode.
  • the second pole is arranged in a ring shape, and the first pole is located at a center position of the second pole.
  • a channel is formed between the first and second poles, and a distance between an outer periphery of the first pole and an inner periphery of the second pole is a channel length, and a center of the channel
  • the perimeter of the line is the channel width, and the width-to-length ratio of the channel ranges from 8 ⁇ to 24 ⁇ .
  • An embodiment of the present application further includes a first isolation layer and a second isolation layer.
  • the first isolation layer is disposed between the gate and the semiconductor layer, and the second isolation layer covers the first isolation layer.
  • a second electrode, the pixel electrode covers the second isolation layer and is electrically connected to the first electrode.
  • the second isolation layer is provided with a connection port
  • the pixel electrode is provided with a connection branch.
  • the connection branch extends from the edge of the pixel electrode to the connection port and passes through the connection port.
  • the connection port is in contact with the first pole.
  • connection branch covers a peripheral edge of the connection port, and extends around the peripheral edge of the connection port.
  • the pixel electrode has a common electrode intersecting and a plurality of domains formed by dividing the common electrode.
  • Each of the domains is provided with a plurality of pixel branches, and the plurality of pixel branches are spaced in parallel. Arranged and arranged at an angle with the gate line or the data line.
  • the common electrode cross is cross-shaped, a plurality of pixel branches are radially distributed with the intersection point of the common electrode as a circle center, and a cut is formed between two adjacent pixel branches.
  • the present application also proposes a display panel including the array substrate, a color substrate, and a liquid crystal layer as described above, the color substrate and the array substrate form a sealed space, and the liquid crystal layer is disposed in the sealed space.
  • the present application also proposes a display device including the display panel as described above and a backlight module connected to the display panel.
  • the array substrate includes data lines and gate lines provided on the base substrate.
  • the array substrate is divided into a plurality of pixel regions, and each pixel region is provided with a thin film transistor, thereby realizing Independent control;
  • the thin film transistor includes a second electrode electrically connected to the data line and a first electrode connected to the pixel electrode, so that the signal of the data line is transmitted to the pixel electrode.
  • the second pole surrounds the first pole, so that the shape of the channel formed by the second pole and the first pole is closed without increasing the size of the thin film transistor.
  • the channel width is more open. It can reach the maximum, thereby significantly improving the aspect ratio, increasing the channel of electron circulation when charging the pixel electrode, thereby increasing the charging rate and effectively improving the display effect of the array substrate.
  • FIG. 1 is a schematic structural diagram of a pixel unit in an embodiment of an array substrate
  • FIG. 2 is a schematic structural diagram of a pixel unit in an embodiment of an array substrate of the present application
  • FIG. 3 is a cross-sectional view taken along line A-A in FIG. 2;
  • FIG. 4 is a partial structural diagram of a pixel unit in another embodiment of an array substrate of the present application.
  • fixed may be a fixed connection, a detachable connection, or a whole; It is a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements, unless it is clearly defined otherwise.
  • fixed may be a fixed connection, a detachable connection, or a whole; It is a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements, unless it is clearly defined otherwise.
  • the present application proposes an array substrate 100.
  • the array substrate 100 includes:
  • the thin film transistor 41 includes a gate electrode 411 electrically connected to the gate line 2, a semiconductor layer 412 covering the gate electrode 411, a first electrode 413 and a second electrode 414 covering the semiconductor layer 412 and spaced apart from each other.
  • the second electrode 414 surrounds the first electrode 413, the second electrode 414 is electrically connected to the data line 3, and the pixel electrode 42 is electrically connected to the first electrode 413.
  • the array substrate 100 is a thin film transistor substrate, that is, a TFT substrate.
  • the material of the substrate 1 includes a transparent glass plate, which does not affect the penetration of the backlight and provides a basic carrier.
  • the substrate 1 is not conductive, and electrons are required for movement and arrangement of liquid crystal molecules during the display process. Drive, so there is a conductive part on the carrier glass of the liquid crystal to control the movement of the liquid crystal, so the data line 3, the gate line 2, the thin film transistor 41, and the pixel electrode 42 are sequentially added to the base substrate 1, and the above elements all pass
  • the coating, exposure, development, and etching processes are superimposed on the substrate 1 to ensure the stability of the structure.
  • the data line 3 and the gate line 2 are made of an opaque non-ferrous metal material.
  • the data line 3 receives the data signal from the data driving circuit and transmits the content to be displayed.
  • the gate line 2 writes the data signal to the pixel electrode. 42, and provides a voltage for turning on and off the thin film transistor 41.
  • the pixel electrode 42 drives the liquid crystal molecules when the circuit is turned on, so that light passes through the content required for display.
  • Each pixel unit is provided with a thin film transistor 41 and a pixel electrode 42, and the thin film transistor 41 is provided on the gate line 2.
  • the pixel electrode 42 is located in each pixel region.
  • the thin film transistor 41 includes a gate electrode 411, a semiconductor layer 412, a first electrode 413, and a second electrode 414.
  • the first electrode 413 is a drain and the second electrode 414 is a source. Alternatively, the first electrode 413 may be a source.
  • the second electrode 414 is a drain, which is specifically related to the direction of current flow.
  • the first electrode 413 is connected to the pixel electrode 42 and the second electrode 414 is connected to the data line 3
  • the current flows from the second electrode 414 to the first electrode 413
  • the second electrode 414 is the source electrode
  • the first electrode 413 is the source and the second electrode 414 is the drain.
  • the thin film transistor 41 is charged, and a second electrode 414 is provided to be electrically connected to the data line 3, and a first electrode 413 is connected to the pixel electrode 42.
  • the gate 411 and the gate line 2 are electrically connected, and cooperate with the semiconductor layer 412 to control the opening and closing of each pixel structure 4.
  • a channel is formed between the first pole 413 and the second pole 414, and a distance between an outer periphery of the first pole 413 and an inner periphery of the second pole 414 is a channel length L, and a center of the channel
  • the perimeter of the line is the channel width W.
  • the semiconductor layer 412 is made conductive, and then the first pole 413 and the second pole 414 are communicated, so that the data of the data line 3 is transmitted to the pixels.
  • Electrode 42 during the charging of the thin film transistor 41, the electron flux is inversely proportional to the distance between the first pole 413 and the second pole 414, and proportional to the perimeter of the channel surrounded by the second pole 414 and the first pole 413. That is, it is proportional to the ratio W / L of the width and length of the channel.
  • the array substrate 100 includes a data line 3 and a gate line 2 provided on the base substrate 1.
  • the array substrate 100 is divided into a plurality of pixel regions, and each pixel region is provided with a thin film transistor 41, thereby realizing Independent control of each pixel structure 4; at the same time, the thin film transistor 41 includes a second pole 414 electrically connected to the data line 3 and a first pole 413 connected to the pixel electrode 42 so as to transmit the signal of the data line 3 to the pixel Electrode 42.
  • the second pole 414 surrounds the first pole 413, so that the shape of the channel formed by the second pole 414 and the first pole 413 is closed without increasing the size of the thin film transistor 41.
  • the channel width The shape of the channel with more openings can be maximized, thereby significantly increasing the aspect ratio.
  • the channel for electron circulation is increased, thereby increasing the charging rate and effectively improving the display effect of the array substrate 100.
  • the second pole 414 is arranged in a ring shape, and the first pole 413 is located at the center of the second pole 414.
  • the shapes of the first pole 413 and the second pole 414 may be circular, square, or other polygons.
  • the second pole 414 is arranged in a ring shape, and the shape of the first pole 413 is also circular.
  • the shape of the channel formed by the first pole 413 and the second pole 414 is annular.
  • the width of the channel can be increased, so that Increase the electron flow and increase the charging rate; on the other hand, the electron flow can be made more uniform at each location of the channel, thereby ensuring the stability of charging.
  • the shapes of the second electrode and the first electrode are both square, and the channel width in this structure can be maximized without increasing the area of the semiconductor layer 412, so that Further increase the charging rate.
  • a width-to-length ratio of the channel ranges from 8 ⁇ to 24 ⁇ .
  • the length of the channel can only be controlled to a size ranging from 3 to 6 micrometers. Therefore, without increasing the size of the thin film transistor 41, the range of the aspect ratio of the channel is set. Between 8 ⁇ and 24 ⁇ , the charging rate is significantly increased, the insufficient driving force caused by the power failure is avoided, the stability of the display panel display is ensured, and the display effect of the array substrate 100 is further improved.
  • the array substrate 100 further includes a first isolation layer 43 and a second isolation layer 44.
  • the first isolation layer 43 is disposed between the gate 411 and the semiconductor layer 412.
  • the second isolation layer 44 covers the first and second electrodes 413 and 414, and the pixel electrode 42 covers the second isolation layer 44 and is electrically connected to the first electrode 413.
  • the first isolation layer 43 and the second isolation layer 44 may be made of a non-conductive resin material, which prevents interference between adjacent conductive elements, thereby improving the display effect of the array substrate 100. Without affecting light transmission.
  • the array substrate 100 includes a light-transmitting area through which light can pass, and a light-opaque light-shielding area.
  • the data lines 3 and the gate lines 2 are made of a light-opaque non-ferrous metal, so they are located in the light-shielding area.
  • the thin film transistor 41 is also in a light-shielding area, and the pixel electrode 42 is a transparent conductive metal ITO (Indium Tin Oxide), which does not block the backlight, so the pixel electrode 42 is in a light-transmitting area, and a second isolation layer 44 is provided between the pixel electrode 42 and the first electrode 413. Therefore, a window is required for the connection between the two. Through, it may be disposed on the pixel electrode 42 or may be disposed above the gate line 2.
  • ITO Indium Tin Oxide
  • the second isolation layer 44 is provided with a connection port 441
  • the pixel electrode 42 is provided with a connection branch 421.
  • the connection branch 421 extends from the edge of the pixel electrode 42 to the connection port 441, and passes through Abutting with the first pole 413 through the connection port 441.
  • connection between the pixel electrode 42 and the first electrode 413 is achieved through the connection port 441, and the connection port 441 is located above the gate line 2, so that the connection position of the pixel electrode 42 and the first electrode 413 is set in the light-shielding area.
  • the light transmission area is increased, that is, the aperture ratio of the pixel structure 4 is increased, which can effectively increase the light transmittance, increase the number of liquid crystal molecules that are imaged, and increase the light transmittance, which can improve display quality and Brightness further improves the display effect.
  • connection branch 421 covers a periphery of the connection port 441, and extends around the periphery of the connection port 441.
  • connection branch 421 covers the periphery of the connection port 441, that is, the portion of the connection branch 421 located at the connection port 441 matches the shape of the connection port 441, so that the contact area between the connection branch 421 and the first pole 413 can be increased. Large, improve contact performance and stability of electrification.
  • connection branch 421 extends a certain distance from the periphery of the connection port 441 to the periphery, so that the cooperation between the connection branch 421 and the connection port 441 can be stabilized, and a gap between the connection branch 421 and the connection port 441 can be avoided due to assembly, thereby ensuring that The connection structure with the first pole 413 is stable.
  • connection branch 421 may be recessed into the connection port 441 to form a connection portion, which is consistent with the connection port 441, thereby improving the continuity of the internal current between the connection branch 421 and the pixel electrode 42, thereby Indirectly increase the charging rate.
  • the pixel electrode 42 has a common electrode 422 that is disposed in an intersecting manner and a plurality of domains formed by dividing the common electrode 422, and a plurality of pixels are disposed in each of the domains.
  • Branches 423, a plurality of pixel branches 423 are arranged in parallel at intervals, and are arranged at an angle with the gate line 2 or the data line 3.
  • the common electrode 422 of the pixel electrode 42 constitutes a main component thereof, and is consistent with the material of the pixel branch 423.
  • a plurality of pixel branches 423 are arranged in parallel and spaced apart, and are formed by the peripheral edge of the common electrode 422, that is,
  • the pixel electrode 42 is an integrated structure, and has a substantially fish-bone shape, which improves the conduction stability of the pixel electrode 42.
  • the common electrode 422 crosses in a cross shape, a plurality of pixel branches 423 are radially distributed with the intersection of the common electrode 422 as a circle center, and a notch 424 is formed between two adjacent pixel branches 423.
  • the two common electrodes 422 are cross-shaped, and one of the common electrodes 422 is parallel to the data line 3 and the other is parallel to the gate line 2.
  • the cross-shaped common electrode 422 can be divided into four areas: Four domains, and a plurality of pixel branches 423 in each domain are distributed radially with the intersection of the common electrode 422 as the center.
  • the plurality of pixel branches 423 are arranged in a 45-degree direction with the peripheral edge of the common electrode 422 in four domains, thereby increasing the direction in which the liquid crystal molecules are dumped, so that a higher light transmittance is obtained.
  • Cutouts 424 are formed between two adjacent pixel branches 423, so the cutouts 424 are also distributed in parallel and spaced apart. They are arranged at an angle to the gate line 2 or data line 3, specifically 45 degrees.
  • the slits 424 are densely arranged. Under the action of an electric field, the slits 424 can drive the liquid crystal molecules to rotate in the direction in which they are tilted, so that the liquid crystal molecules can be tilted at 45 degrees. At this time, the maximum light transmittance can be achieved. Aperture ratio to achieve high-quality display.
  • the present application also proposes a display panel (not shown), which includes the array substrate 100, a color substrate (not shown), and a liquid crystal layer (not shown) as described above.
  • the color substrate is formed with the array substrate 100.
  • the liquid crystal layer is disposed in the sealed space.
  • the display panel adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the functions brought by the technical solutions of the above-mentioned embodiments, and will not be repeated here.
  • the display panel may be a liquid crystal display panel. It can be understood that the display panel includes an array substrate 100 and a color substrate (CF, Colour, which are oppositely disposed). filter), and a liquid crystal layer sandwiched between the array substrate 100 and the color substrate.
  • the array substrate 100 and the color substrate form a sealed space through a sealing frame, and the liquid crystal layer is located in the sealed space.
  • the liquid crystal layer of the present application may include only liquid crystal molecules, or may include liquid crystal molecules and phototactic monomers.
  • the color substrate is composed of a glass substrate, a light-shielding layer, a color layer, a protective film, and a conductive film.
  • a TFT liquid crystal display an alkali-free glass is used for a glass substrate.
  • the light-shielding layer is a black matrix made of anti-reflection on a glass substrate to prevent light leakage between pixels and increase color contrast.
  • the material of the current light-shielding layer is a metal film, which is easy to make.
  • the black matrix corresponds to a light-shielding area of the array substrate 100.
  • the color layer mainly uses a color photoresist as a filter film layer, and the components include a polymer resin binder with high transparency and high heat resistance and a dye or pigment colorant, so that the transparent polymer resin has a color. Generally It must have the characteristics of light resistance, good heat resistance, high color saturation and good penetration.
  • the protective film is for protecting the color filter layer and increasing the smoothness of the surface.
  • the conductive film is a common electrode, and is configured to form a potential difference with the pixel electrode 42 of the array substrate 100 to drive liquid crystal molecules.
  • the display panel is further provided with a lower polarizer and an upper polarizer on the lower surface of the array substrate 100 and the upper surface of the color substrate.
  • the polarization directions of the two are perpendicular.
  • the light first passes through the lower polarizer and becomes linearly polarized light.
  • the directions of the polarizers are the same.
  • the light twists the 90-degree polarization direction by the tilt angle of the liquid crystal molecules, and then passes through the upper polarizer perpendicular to the lower polarizer to achieve the display screen.
  • the array substrate 100 may further be provided with an alignment film, and the alignment film covers the pixel electrode 42.
  • the material of the alignment film is polymer plastic.
  • When making the alignment film apply a solution-like material on the surface of the array substrate 100, and then solidify it. Roll it on the surface with a roller of flannel material to make the surface show a certain friction.
  • the surface of the alignment layer which can cause friction between the liquid crystal molecules, so that the liquid crystal molecules present a certain pretilt angle. Under the action of the electric field, the liquid crystal molecules can be dumped more quickly, and the light can pass quickly to ensure the image. Changes are precise and fast.
  • an alignment film is also provided on the color substrate.
  • the alignment film can also form a certain pretilt angle of the liquid crystal molecules close to the color substrate, thereby further accelerating the rate of liquid crystal molecules falling down under the action of an electric field, so that each pixel quickly displays a corresponding s color.
  • the liquid crystal molecules located between the array substrate 100 and the color substrate are arranged freely.
  • the liquid crystal molecules closer to the alignment film have a certain pretilt angle.
  • the liquid crystal The molecules are driven to fall at the same angle by the plurality of cutouts 424 of the pixel electrode 42, so that the liquid crystal molecules are poured more quickly, which ensures the smooth passage of light and achieves rapid development.
  • the voltage is removed, most of the liquid crystal molecules will return to the upright state, and at this time, light will not be passed through.
  • the present application also proposes a display device (not shown).
  • the display device includes the display panel as described above and a backlight module (not shown) connected to the display panel.
  • the display panel includes the above embodiments. Since the array substrate 100 adopts all the technical solutions of all the embodiments described above, it has at least all the effects brought by the technical solutions of the above embodiments, and will not be described in detail here.
  • the backlight module is disposed near the lower polarizer, and the backlight module is mainly provided to provide a uniform and good light source for the display device.
  • the backlight module generally includes a light source, a light guide sheet, a reflective sheet, and an optical film.
  • the reflective sheet may be a reflective coating applied on the surface of the light guide plate.
  • the light guide sheet can convert the light source from a point light source to a uniform surface light source.
  • the setting of the reflection sheet can prevent the light entering the light guide plate from exiting from the side facing away from the exit surface, and reflected it back to the light guide plate, which can prevent light.
  • the waste of energy can effectively improve the utilization of light.
  • a backlight source is provided by the above-mentioned backlight module, so that a display device can obtain a better display effect.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

一种阵列基板（100）、显示面板及显示设备，其中，所述阵列基板（100）包括衬底基板（1）和像素结构（4），像素结构（4）包括像素电极（42）、栅极（411）、半导体层（412）、第一极（413）及包围所述第一极（413）设置的第二极（414）。

Description

阵列基板、显示面板及显示设备
技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板、应用该阵列基板的显示面板及显示设备。
背景技术
薄膜晶体管液晶显示器因具有高反应速度、高亮度及高对比度等优点，在当前的显示器市场占据主导地位。薄膜晶体管液晶显示器包括阵列基板、彩色基板以及充满在两基板之间的液晶层，现有的液晶显示技术中，一般采用底栅结构的阵列基板，此类阵列基板的开态电流（即充电率）与沟道宽度成正比，与沟道长度成反比，即开态电流的大小取决于沟道的宽长比。请参阅图1，图1是一般液晶显示面板的像素单元示意图，结构中包括数据线3a、栅极线4a、薄膜晶体管1a（Thin film transistor，TFT）和像素电极2a。沟道长度一般等同于源极和漏极之间的距离，沟道宽度为沟道的周长，现有的结构中宽长比较小，导致阵列基板的充电率过小，从而影响显示面板的显示效果。
发明内容
本申请的主要目的是提供一种阵列基板 ，旨在提高显示面板的透光率，改善显示效果。
为实现上述目的，本申请提出的阵列基板，包括：
衬底基板，
若干条栅极线和数据线，覆盖于所述衬底基板上，所述栅极线和数据线彼此交叉形成有多个像素区域；
多个像素结构，每一像素结构包括覆盖于栅极线上的薄膜晶体管和位于一所述像素区域内的像素电极；
所述薄膜晶体管包括与栅极线电连接的栅极、覆盖于所述栅极的半导体层、覆盖于所述半导体层并间隔设置的第一极和第二极，所述第二极包围所述第一极，所述第二极与所述数据线电连接，所述像素电极与所述第一极电连接。
本申请的一实施例中，所述第二极呈环状设置，所述第一极位于所述第二极的中心位置。
本申请的一实施例中，所述第一极与第二极之间形成沟道，所述第一极外周缘与第二极的内周缘的间距为沟道长度，所述沟道的中心线的周长为沟道宽度，所述沟道的宽长比的范围为8π~24π。
本申请的一实施例中，还包括第一隔离层和第二隔离层，所述第一隔离层设于所述栅极和半导体层之间，所述第二隔离层覆盖于所述第一极和第二极，所述像素电极覆盖于所述第二隔离层并与所述第一极电连接。
本申请的一实施例中，所述第二隔离层开设有连接口，所述像素电极设有一连接分支，所述连接分支由所述像素电极的边缘延伸至所述连接口，并穿过所述连接口与所述第一极抵接。
本申请的一实施例中，所述连接分支覆盖于所述连接口的周缘，并于所述连接口的周缘向四周延伸。
本申请的一实施例中，所述像素电极具有交叉设置的公共电极和由所述公共电极分割形成的多个畴，每一所述畴内设有多个像素分支，多个像素分支平行间隔排布，且与所述栅极线或数据线呈夹角设置。
本申请的一实施例中，所述公共电极交叉呈十字型，多个像素分支以所述公共电极的交叉点为圆心呈放射状分布，两相邻所述像素分支之间形成有切口。
本申请还提出一种显示面板，包括如上所述的阵列基板、彩色基板和液晶层，所述彩色基板与所述阵列基板形成密封空间，所述液晶层设于所述密封空间。
本申请还提出一种显示设备，包括如上所述的显示面板及与所述显示面板连接的背光模组。
本申请技术方案中，阵列基板包括设于衬底基板上的数据线和栅极线，将阵列基板分割成多个像素区域，每一像素区域设有薄膜晶体管，从而实现对每一像素结构的独立控制；同时，薄膜晶体管包括与数据线电连接的第二极和与像素电极连接的第一极，从而实现将数据线的信号传输至像素电极。且，第二极包围第一极，从而在不增大薄膜晶体管的尺寸的情况下，使得第二极与第一极形成的沟道形状为封闭状态，此时沟道宽度较有开口的形状可以达到最大，从而显著提高宽长比，在对像素电极充电时增大了电子流通的通道，进而提高了充电率，有效提高阵列基板的显示效果。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为阵列基板一实施例中一像素单元的结构示意图；
图2为本申请阵列基板一实施例中一像素单元的部分结构示意图；
图3为图2中沿A-A线的剖视图；
图4为本申请阵列基板另一实施例中一像素单元的部分结构示意图。
附图标号说明：
标号 名称 标号 名称 标号 名称
1a 薄膜晶体管 4 像素结构 422 公共电极
2a 像素电极 41 薄膜晶体管 423 像素分支
3a 扫描线 411 栅极 424 切口
4a 栅极线 412 半导体层 43 第一隔离层
100 阵列基板 413 第一极 44 第二隔离层
1 衬底基板 414 第二极 441 连接口
2 栅极线 42 像素电极
3 数据线 421 连接分支
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，本申请实施例中所有方向性指示（诸如上、下、左、右、前、后……）仅设置为解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
在本申请中，除非另有明确的规定和限定，术语“连接”、“固定”等应做广义理解，例如，“固定”可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
另外，在本申请中如涉及“第一”、“第二”等的描述仅设置为描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种阵列基板100。
请参照图2和图3，在本申请实施例中，该阵列基板100包括：
衬底基板1，
若干条栅极线2和数据线3，覆盖于所述衬底基板1上，所述栅极线2和数据线3彼此交叉形成有多个像素区域；
多个像素结构4，每一像素结构4包括覆盖于栅极线2上的薄膜晶体管41和位于一所述像素区域内的像素电极42；
所述薄膜晶体管41包括与栅极线2电连接的栅极411、覆盖于所述栅极411的半导体层412、覆盖于所述半导体层412并间隔设置的第一极413和第二极414，所述第二极414包围所述第一极413，所述第二极414与所述数据线3电连接，所述像素电极42与所述第一极413电连接。
本实施例中，阵列基板100为薄膜晶体管基板，即，TFT基板。其包括的衬底基板1的材质为透明玻璃板，不影响背光源的穿过，提供基础的载体，但衬底基板1不导电，因显示过程中的液晶分子的运动和排列均需要电子来驱动，故而液晶的载体玻璃上有能够导电的部分来控制液晶的运动，因此在衬底基板1上依次加入数据线3、栅极线2、薄膜晶体管41及像素电极42，且上述元件均通过镀膜、曝光、显影与蚀刻工艺层层叠加到衬底基板1上，保证结构的稳定性。数据线3和栅极线2均是由不透光有色金属材料制得，数据线3接收来自数据驱动电路的数据信号，输送要显示的内容，栅极线2将该数据信号写入像素电极42，并为薄膜晶体管41提供开启关闭的电压，像素电极42在导通电路时对液晶分子进行驱动，从而使得光线通过显示所需要的内容。
俯视阵列基板100时，数据线3和栅极线2通过垂直交叉形成多个像素区域，每个像素单元内设有薄膜晶体管41和像素电极42，且薄膜晶体管41设于栅极线2上，像素电极42位于每一像素区域内。该薄膜晶体管41包括栅极411、半导体层412、第一极413和第二极414，其中第一极413是漏极，第二极414是源极，或者也可以是第一极413是源极，第二极414是漏极，具体与电流的流向有关。例如，当第一极413与像素电极42连接，第二极414与数据线3连接，当薄膜晶体管41充电时，电流由第二极414流向第一极413，则第二极414为源极，第一极413为漏极；当薄膜晶体管41放电时，电流由第一极413流向第二极414，此时第一极413为源极，第二极414为漏极。本实施例中对薄膜晶体管41充电，设置第二极414与数据线3电连接，第一极413与像素电极42连接。栅极411和栅极线2电连接，与半导体层412配合控制每一像素结构4的开启与关闭。
具体地，所述第一极413与第二极414之间形成沟道，所述第一极413外周缘与第二极414的内周缘的间距为沟道长度L，所述沟道的中心线的周长为沟道宽度W，通过对栅极411进行供电，从而使得半导体层412导电，进而使得第一极413与第二极414之间连通，实现将数据线3的数据传输至像素电极42，故而对薄膜晶体管41的充电过程中，电子流通量与第一极413与第二极414的间距成反比，与第二极414和第一极413围成的沟道的周长成正比，即与沟道的宽度与长度的比值W/L成正比。
本申请技术方案中，阵列基板100包括设于衬底基板1上的数据线3和栅极线2，将阵列基板100分割成多个像素区域，每一像素区域设有薄膜晶体管41，从而实现对每一像素结构4的独立控制；同时，薄膜晶体管41包括与数据线3电连接的第二极414和与像素电极42连接的第一极413，从而实现将数据线3的信号传输至像素电极42。且，第二极414包围第一极413，从而在不增大薄膜晶体管41的尺寸的情况下，使得第二极414与第一极413形成的沟道形状为封闭状态，此时沟道宽度较有开口的沟道形状可以达到最大，从而显著提高宽长比，在对像素电极42充电时增大了电子流通的通道，进而提高了充电率，有效提高阵列基板100的显示效果。
请再次参照图2，本申请的一实施例中，所述第二极414呈环状设置，所述第一极413位于所述第二极414的中心位置。
本实施例中，可以理解的，第一极413与第二极414的形状可以是圆形、方形或其他多边形。设置第二极414呈环状，第一极413的形状也为圆形，第一极413与第二极414围设形成的沟道形状为环形，一方面可以增大沟道的宽度，从而提高电子流通量，提高充电率；另一方面可以使得沟道的每一处的电子流通较为均匀，从而保证充电的稳定性。
请参照图4，本申请的另一实施例中，第二电极和第一电极的形状均为方形，该结构中的沟道宽度可以在不增加半导体层412的面积的情况下达到最大，从而进一步提高充电率。
本申请的一实施例中，所述沟道的宽长比的范围为8π~24π。
本实施例中，根据现有工艺，沟道的长度只能控制在范围为3~6微米的尺寸，故而在不增大薄膜晶体管41的尺寸的情况下，沟道的宽长比的范围设置在8π~24π，显著提高了充电率，避免断电后导致驱动力不够，保证显示面板显示的稳定性，进而提高阵列基板100的显示效果。
请参照图3，本申请的一实施例中，阵列基板100还包括第一隔离层43和第二隔离层44，所述第一隔离层43设于所述栅极411和半导体层412之间，所述第二隔离层44覆盖于所述第一极413和第二极414，所述像素电极42覆盖于所述第二隔离层44并与所述第一极413电连接。
本实施例中，第一隔离层43和第二隔离层44可采用不导电的树脂材料制作，在相邻的导电元件之间起到免受干扰的作用，从而可以提高阵列基板100的显示效果，且不影响光的透过。阵列基板100中有可使光透过的透光区，也会有不透光的遮光区，数据线3和栅极线2均是由不透光的有色金属制成，故而其位于遮光区，薄膜晶体管41也处在遮光区，像素电极42为透明导电金属ITO（Indium Tin Oxide），不阻挡背光，故像素电极42处在透光区，像素电极42与第一极413之间设有第二隔离层44，故而两者的连接需要设置窗口，该窗口不会使光透过，其可以设置在像素电极42上，也可以设置在栅极线2的上方。
具体地，所述第二隔离层44开设有连接口441，所述像素电极42设有一连接分支421，所述连接分支421由所述像素电极42的边缘延伸至所述连接口441，并穿过所述连接口441与所述第一极413抵接。
本实施例中，像素电极42与第一极413的连接通过连接口441实现，且连接口441位于栅极线2的上方，从而使得像素电极42与第一极413的连接位置设在遮光区上，进而增大了透光区域，即提高了像素结构4的开口率，从而可以有效增大光的透过率，增加成像的液晶分子数量，提高光线的透过率，可改善显示品质和亮度进一步提高显示效果。
本申请的一实施例中，所述连接分支421覆盖于所述连接口441的周缘，并于所述连接口441的周缘向四周延伸。
本实施例中，连接分支421覆盖于连接口441的周缘，即连接分支421位于连接口441的部分与连接口441的形状相匹配，从而可以使连接分支421与第一极413的接触面积增大，提高接触性能和通电的稳定性。且连接分支421于连接口441的周缘向四周延伸一定距离，从而可以使得连接分支421与连接口441的配合较为稳定，避免因为装配原因导致连接分支421与连接口441之间存在空隙，从而保证与第一极413的连接结构的稳定。具体地，连接分支421的中部可以向连接口441内凹设形成连接部位，该连接部位与连接口441相一致，从而提高了连接分支421与像素电极42之间内部电流的导通性，从而间接提高充电率。
请参照图2，本申请的一实施例中，所述像素电极42具有交叉设置的公共电极422和由所述公共电极422分割形成的多个畴，每一所述畴内设有多个像素分支423，多个像素分支423平行间隔排布，且与所述栅极线2或数据线3呈夹角设置。
本实施例中，像素电极42的公共电极422构成了其主要的组成部分，与像素分支423的材质一致，多个像素分支423之间平行间隔设置，且由公共电极422的周缘延伸形成，即像素电极42为一体结构，大致呈鱼骨状，提高像素电极42的导通稳定性。
具体地，所述公共电极422交叉呈十字型，多个像素分支423以所述公共电极422的交叉点为圆心呈放射状分布，两相邻所述像素分支423之间形成有切口424。
本实施例中，两公共电极422呈十字型，且公共电极422的一个与数据线3平行，另一与栅极线2平行，十字型的公共电极422可以分割出上下左右四个区域，即四个畴，每个畴内的多个像素分支423以公共电极422的交叉点为圆心呈放射状分布。且多个像素分支423分别在四个畴内与公共电极422的周缘呈45度方向排列，从而增加了液晶分子倾倒的方向，使得获得较高的透光率。
两相邻像素分支423之间形成有切口424（又称Slit），故切口424也有多个且平行间隔分布，其与栅极线2或数据线3呈夹角设置，具体为45度，多个切口424电极密集排列，在电场作用下该切口424可驱动液晶分子沿着其倾斜的方向转动，从而可以使液晶分子呈45度倾斜，此时可以达到最大的透光率，再配合较高的开口率，从而实现优质的显示效果。
本申请还提出一种显示面板（未图示），包括如上所述的阵列基板100、彩色基板（未图示）和液晶层（未图示），所述彩色基板与所述阵列基板100形成密封空间，所述液晶层设于所述密封空间。阵列基板100的具体结构参照上述实施例，由于显示面板采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有作用，在此不再一一赘述。
本实施例中，该显示面板可以为液晶显示面板，可以理解的，显示面板包括相对设置的阵列基板100和彩色基板（CF，Colour filter），及夹设于阵列基板100和彩色基板之间的液晶层，阵列基板100和彩色基板通过密封框形成密封空间，液晶层位于该密封空间内。本申请的液晶层可以仅有液晶分子，也可以是包括液晶分子和趋光性单体。
彩色基板由玻璃基板、遮光层、彩色层、保护膜及导电膜组成。在TFT液晶显示器中，玻璃基板需使用无碱玻璃。遮光层是在玻璃基板上制作防反射的黑色矩阵，防止画素间的漏光，以及增加色彩对比度，现通常使用的遮光层材质是金属膜，便于制作。该黑色矩阵与阵列基板100的遮光区相对应。彩色层主要以彩色光阻作为滤光膜层，成分包括高透明性及高耐热性的高分子型树脂类结合剂与染料或颜料类的着色剂，使透明的高分子树脂具有颜色，一般需具备耐光、耐热性佳、色彩饱和度高与穿透性好等特点。保护膜是为了保护彩色滤光层以及增加表面的平滑性。导电膜即为公共电极，配置为与阵列基板100的像素电极42形成电位差，从而对液晶分子进行驱动。
显示面板在阵列基板100下表面和彩色基板的上表面还设有下偏振片和上偏振片，两者的偏振方向垂直，光线先通过下偏振片，从而变成线性偏振光，偏振方向与下偏振片的方向一致，在穿过液晶层时，由于受液晶分子的折射，光线借助液晶分子的倾倒角度扭转90度偏振方向，从而穿过与下偏振片垂直的上偏振片，实现显示画面。
为了进一步提高液晶分子倾倒的速率，所述阵列基板100还可以设置配向膜，所述配向膜覆盖像素电极42。
配向膜的材质为高分子塑胶，在制作配向膜时，将溶液状的材料涂抹在阵列基板100的表面，然后固化，用绒布类材料的滚轮在其表面滚动，以使其表面呈现一定的摩擦取向层表面，该表面可与液晶分子之间产生摩擦，从而使液晶分子呈现一定的预倾角，在电场作用下，从而使得液晶分子倾倒的更加快速，保证光线可以快速通过，才能够保证图像的变化精确快速。
当然，彩色基板上也设置有配向膜，该配向膜可以使靠近彩色基板的液晶分子也形成一定的预倾角，从而在电场作用下，进一步加快液晶分子倾倒的速度，使每个像素快速显示相应的颜色。
当显示面板没有施加电压时，位于阵列基板100和彩色基板之间的液晶分子是自由分散排布的，较靠近配向膜的液晶分子会有一定的预倾角；当对显示面板施加电压时，液晶分子会由像素电极42的多个切口424驱动以相同的角度倾倒，从而使得液晶分子倾倒的更加迅速，保证光线的顺利通过，实现快速显像。当撤掉电压时，液晶分子大部分会回转至竖立状态，此时，不会使光线通过。
本申请还提出一种显示设备（未图示），该显示设备包括如上所述的显示面板及与所述显示面板连接的背光模组（未图示），该显示面板为包括上述实施例的阵列基板100，由于显示设备采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有作用，在此不再一一赘述。
本实施例中，背光模组靠近下偏光片设置，背光模组主要设置为显示设备提供均匀且亮度较好的光源。背光模组一般包括有光源、导光片、反射片以及光学膜片，反射片可以是涂覆在导光板表面的反射涂层。导光片可将光源由点光源转换为均匀的面光源，反射片的设置可以防止射入导光板的光线从背离出射面的一侧射出，并将其被反射回导光板中，可以防止光能的浪费，有效提高光线的利用率。由上述背光模组提供背光源，可以使显示设备得到更好的显示效果。
以上所述仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，包括：
    衬底基板，
    若干条栅极线和数据线，覆盖于所述衬底基板上，所述栅极线和数据线彼此交叉形成有多个像素区域；
    多个像素结构，每一像素结构包括覆盖于栅极线上的薄膜晶体管和位于一所述像素区域内的像素电极；以及
    所述薄膜晶体管包括与栅极线电连接的栅极、覆盖于所述栅极的半导体层、覆盖于所述半导体层并间隔设置的第一极和第二极，所述第二极包围所述第一极，所述第二极与所述数据线电连接，所述像素电极与所述第一极电连接。
  2. 如权利要求1所述的阵列基板，其中，所述第二极呈环状设置，所述第一极位于所述第二极的中心位置。
  3. 如权利要求2所述的阵列基板，其中，所述第一极与第二极之间形成沟道，所述第一极外周缘与第二极的内周缘的间距为沟道长度，所述沟道的中心线的周长为沟道宽度，所述沟道的宽长比的范围为8π~24π。
  4. 如权利要求2所述的阵列基板，其中，第二电极和第一电极的形状均为方形。
  5. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括第一隔离层和第二隔离层，所述第一隔离层设于所述栅极和半导体层之间，所述第二隔离层覆盖于所述第一极和第二极，所述像素电极覆盖于所述第二隔离层并与所述第一极电连接；所述第二极呈环状设置，所述第一极位于所述第二极的中心位置。
  6. 如权利要求1所述的阵列基板，其中，还包括第一隔离层和第二隔离层，所述第一隔离层设于所述栅极和半导体层之间，所述第二隔离层覆盖于所述第一极和第二极，所述像素电极覆盖于所述第二隔离层并与所述第一极电连接。
  7. 如权利要求6所述的阵列基板，其中，所述第二隔离层开设有连接口，所述像素电极设有一连接分支，所述连接分支由所述像素电极的边缘延伸至所述连接口，并穿过所述连接口与所述第一极抵接。
  8. 如权利要求7所述的阵列基板，其中，所述连接分支覆盖于所述连接口的周缘，并于所述连接口的周缘向四周延伸。
  9. 如权利要求8所述的阵列基板，其中，所述连接分支的中部向所述连接口内凹设形成连接部位，该连接部位与所述连接口相匹配。
  10. 如权利要求1所述的阵列基板，其中，所述像素电极具有交叉设置的公共电极和由所述公共电极分割形成的多个畴，每一所述畴内设有多个像素分支，多个像素分支平行间隔排布，且与所述栅极线或数据线呈夹角设置；所述第二极呈环状设置，所述第一极位于所述第二极的中心位置。
  11. 如权利要求10所述的阵列基板，其中，第二电极和第一电极的形状均为方形。
  12. 如权利要求1所述的阵列基板，其中，所述像素电极具有交叉设置的公共电极和由所述公共电极分割形成的多个畴，每一所述畴内设有多个像素分支，多个像素分支平行间隔排布，且与所述栅极线或数据线呈夹角设置。
  13. 如权利要求12所述的阵列基板，其中，所述像素电极为一体结构。
  14. 如权利要求1所述的阵列基板，其中，所述像素电极具有交叉设置的公共电极和由所述公共电极分割形成的多个畴，每一所述畴内设有多个像素分支，多个像素分支平行间隔排布，且与所述栅极线或数据线呈45度夹角设置。
  15. 如权利要求14所述的阵列基板，其中，所述公共电极交叉呈十字型，多个像素分支以所述公共电极的交叉点为圆心呈放射状分布，两相邻所述像素分支之间形成有切口。
  16. 一种显示面板，其中，包括阵列基板、彩色基板和液晶层，所述彩色基板与所述阵列基板形成密封空间，所述液晶层设于所述密封空间；
    所述阵列基板包括：衬底基板，
    若干条栅极线和数据线，覆盖于所述衬底基板上，所述栅极线和数据线彼此交叉形成有多个像素区域；
    多个像素结构，每一像素结构包括覆盖于栅极线上的薄膜晶体管和位于一所述像素区域内的像素电极；
    所述薄膜晶体管包括与栅极线电连接的栅极、覆盖于所述栅极的半导体层、覆盖于所述半导体层并间隔设置的第一极和第二极，所述第二极包围所述第一极，所述第二极与所述数据线电连接，所述像素电极与所述第一极电连接。
  17. 如权利要求16所述的显示面板，其中，所述第二极呈环状设置，所述第一极位于所述第二极的中心位置。
  18. 如权利要求16所述的显示面板，其中，所述阵列基板还设有配向膜，所述配向膜覆盖像素电极。
  19. 如权利要求16所述的显示面板，其中，还包括下偏振片和上偏振片，所述下偏振片设于所述阵列基板的下表面，所述上偏振片设于所述彩色基板的上表面。
  20. 一种显示设备，其中，包括显示面板及与所述显示面板连接的背光模组，所述显示面板包括阵列基板、彩色基板和液晶层，所述彩色基板与所述阵列基板形成密封空间，所述液晶层设于所述密封空间，所述阵列基板包括：衬底基板，
    若干条栅极线和数据线，覆盖于所述衬底基板上，所述栅极线和数据线彼此交叉形成有多个像素区域；
    多个像素结构，每一像素结构包括覆盖于栅极线上的薄膜晶体管和位于一所述像素区域内的像素电极；
    所述薄膜晶体管包括与栅极线电连接的栅极、覆盖于所述栅极的半导体层、覆盖于所述半导体层并间隔设置的第一极和第二极，所述第二极包围所述第一极，所述第二极与所述数据线电连接，所述像素电极与所述第一极电连接。
PCT/CN2018/111534 2018-09-17 2018-10-24 阵列基板、显示面板及显示设备 Ceased WO2020056843A1 (zh)

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