WO2020052584A1 - 一种硅片级封装划片槽的设计方法 - Google Patents

一种硅片级封装划片槽的设计方法 Download PDF

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Publication number
WO2020052584A1
WO2020052584A1 PCT/CN2019/105337 CN2019105337W WO2020052584A1 WO 2020052584 A1 WO2020052584 A1 WO 2020052584A1 CN 2019105337 W CN2019105337 W CN 2019105337W WO 2020052584 A1 WO2020052584 A1 WO 2020052584A1
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Prior art keywords
silicon wafer
level package
dicing groove
dicing
process monitoring
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PCT/CN2019/105337
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English (en)
French (fr)
Inventor
童红亮
王璐
王楠
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普冉半导体（上海）有限公司
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Publication of WO2020052584A1 publication Critical patent/WO2020052584A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting

Definitions

  • the invention relates to the field of semiconductor ICs, and in particular, to a method for designing a dicing groove of a silicon wafer level package.
  • a scribe groove is vacated between the two chips, and the scribe groove width ranges from 25-80um.
  • the fab will place process monitoring pattern 1 in the dicing groove. This part of the process monitoring pattern has metal wiring layers and metal vias, which can easily cause chip cracks during final package dicing.
  • WLCSP products are diced after testing. Because there is no final measurement after dicing, the current dicing groove structure often has shards during dicing due to the presence of graphics for process monitoring. The shards are difficult to find. There will be a certain probability of failure when used.
  • the invention provides a method for designing a dicing groove of a silicon wafer level package.
  • the process monitoring pattern of the dicing groove is placed inside the chip, thereby ensuring the dicing groove is clean and reducing the risk of chipping.
  • a method for designing a dicing groove of a silicon wafer level package which includes:
  • a process monitoring graphic is collectively placed in the selected area.
  • a scribe groove is formed between two adjacent chips.
  • the design method further includes:
  • the process monitoring pattern placed in the dicing groove is removed, so that no data with a metal wiring layer and a metal via is placed in the dicing groove.
  • the width of the dicing groove is between 45 microns and 80 microns.
  • the wafer is 8 inches or 12 inches.
  • the present invention has the following beneficial effects:
  • the process monitoring pattern of the dicing groove is placed inside the chip, so as to ensure the dicing groove is clean and the risk of possible chipping in the dicing is greatly reduced.
  • FIG. 1 is a dicing groove and a process monitoring graphic placement method in the prior art
  • FIG. 2 is a flowchart of a method for designing a dicing groove of a silicon wafer level package according to the present invention
  • FIG. 3 is a structural diagram of a dicing groove and a process monitoring graph according to the present invention.
  • a method for designing a dicing groove for a silicon wafer level package includes:
  • a process monitoring pattern 1 is collectively placed in the selected area.
  • selecting several regions refers to pre-selecting several regions in the main chip of the wafer.
  • the regions can be determined according to the distribution of the chip or the structure of the wafer. Specifically, a region can be selected as the subsequent process monitoring pattern. Drop area.
  • FIG. 3 shows a dicing groove and a process monitoring pattern placement structure diagram of the present invention.
  • WLCSP wafer level package
  • one of two adjacent chips is processed.
  • a scribe groove is formed in between.
  • the width between two adjacent scribe grooves is SX and SY, and the width of SX and SY is 45 ⁇ m-80 ⁇ m. It is used for dicing by laser, etching or blade.
  • the design method further includes: removing a process monitoring pattern placed in the dicing groove, so that no data with a metal wiring layer and a metal via is placed in the dicing groove.
  • the step of placing the process monitoring pattern in the selected area in a concentrated manner is as follows: placing the process pattern originally placed in the dicing groove in a pre-vacant region of the chip.
  • the wafer is packaged and diced to obtain corresponding chip products and chip areas with process monitoring graphics, and the chip areas are discarded.
  • the 8-inch wafer according to the embodiment of the present invention is described above with reference to the accompanying drawings. Further, the present invention can also be applied to a 12-inch wafer.
  • the method for designing a dicing groove of a silicon wafer-level package places the process monitoring pattern of the dicing groove inside the chip, thereby ensuring the cleanness of the dicing groove and complete process monitoring parameters, and reducing the risk of chipping.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种硅片级封装划片槽的设计方法，包括：在晶圆的芯片的阵列中选择若干区域；在选择的所述区域中集中放入工艺监控图形（1），所述的晶圆在进行硅片级封装产品加工过程中，相邻的两颗芯片之间形成一划片槽。能够将划片槽的工艺监控图形（1）放置到芯片内部，从而保证划片槽的干净，降低裂片风险。

Description

一种硅片级封装划片槽的设计方法 技术领域
本发明涉及半导体IC领域，具体涉及一种硅片级封装划片槽的设计方法。
背景技术
传统的8寸晶圆的硅片级封装(WLCSP)产品加工过程中，两颗芯片之间会空开一个划片槽，划片槽宽度从25-80um不等。晶圆厂会在划片槽内放置工艺监控图形1，这部分工艺监控的图形带有金属布线层和金属过孔，在最终封装划片的时候容易造成芯片裂片。
WLCSP产品是测试后再划片，由于划片后没有终测，目前的划片槽结构中由于存在工艺监控用的图形，往往会造成划片过程中的裂片，裂片很难被发现，在终端使用时候会有一定概率的失效。
发明的公开
本发明提供一种硅片级封装划片槽的设计方法，将划片槽的工艺监控图形放置到芯片内部，从而保证划片槽的干净，降低裂片风险。
为达到上述目的，本发明提出的技术方案为：
一种硅片级封装划片槽的设计方法，其特点是，包括：
在晶圆的芯片的阵列中选择若干区域；
在选择的所述区域中集中放入工艺监控图形。
所述的晶圆在进行硅片级封装产品加工过程中，相邻的两颗芯片之间形成一划片槽。
所述的设计方法进一步包括：
移除放置于划片槽内的工艺监控图形，使得所述划片槽内不放置任何带金属布线层及金属过孔的数据。
作为优选，所述的划片槽的宽度介于45微米至80微米之间。
作为优选，所述的晶圆为8英寸或12英寸。
相对于现有技术，本发明具有以下有益效果：
1.把划片槽的工艺监控图形放置到芯片内部，从而保证划片槽的干净，保证划片中可能的裂片风险大大降低。
2.保证监控参数图形的完整性。
3.应用范围广，可以同时用于8英寸或12英寸的晶圆。
附图的简要说明
图1为现有技术中划片槽及工艺监控图形放置方法；
图2为本发明一种硅片级封装划片槽的设计方法的流程图；
图3为本发明划片槽及工艺监控图形放置结构图。
实现本发明的最佳方式
以下结合附图通过具体实施例对本发明作进一步的描述，这些实施例仅用于说明本发明，并不是对本发明保护范围的限制。
如图1、2所示，一种硅片级封装划片槽的设计方法，包括：
在晶圆的芯片的阵列中选择若干区域；
在选择的所述区域中集中放入工艺监控图形1。
需要说明的是，选择若干区域是指在晶圆的主芯片中预先选择若干区域，区域可以根据芯片的分布或晶圆的结构来确定，具体地，可以选择一块区域作为后续的工艺监控图形的放置区域。
图3示出了本发明划片槽及工艺监控图形放置结构图，如图3所示，所述的晶圆在进行硅片级封装(WLCSP)产品加工过程中，相邻的两颗芯片之间形成一划片槽。相邻两个划片槽之间的宽度为SX和SY，SX和SY的宽度为45μm-80μm，用于激光、蚀刻或者刀片的划片。
在具体实施例中，该设计方法还包括：移除放置于划片槽内的工艺监控图形，使得所述划片槽内不放置任何带金属布线层及金属过孔的数据。
所述的在选择的所述区域中集中放入工艺监控图形具体为：将原先放置于划片槽中的工艺图形放置于芯片中预先空置的区域。
最后对晶圆进行封装划片，得到对应的各个芯片产品和带有工艺监控图形的芯片区域，将该芯片区域丢弃。
以上结合附图描述了根据本发明实施例的应用于8英寸的晶圆。进一步地，本发明还可以应用于12英寸晶圆。
综上所述，本发明一种硅片级封装划片槽的设计方法，将划片槽的工艺监控图形放置到芯片内部，从而保证划片槽的干净及工艺监控参数完整，降低裂片风险。

Claims (5)

  1. 一种硅片级封装划片槽的设计方法，其特征在于，包括：
    在晶圆的芯片的阵列中选择若干区域；
    在选择的所述区域中集中放入工艺监控图形。
  2. 如权利要求1所述的硅片级封装划片槽的设计方法，其特征在于，所述的晶圆在进行硅片级封装产品加工过程中，相邻的两颗芯片之间形成一划片槽。
  3. 如权利要求1所述的硅片级封装划片槽的设计方法，其特征在于，所述的设计方法进一步包括：
    移除放置于划片槽内的工艺监控图形，使得所述划片槽内不放置任何带金属布线层及金属过孔的数据。
  4. 如权利要求1所述的硅片级封装划片槽的设计方法，其特征在于，所述的划片槽的宽度介于45微米至80微米之间。
  5. 如权利要求1所述的硅片级封装划片槽的设计方法，其特征在于，所述的晶圆为8英寸或12英寸。
PCT/CN2019/105337 2018-09-13 2019-09-11 一种硅片级封装划片槽的设计方法 WO2020052584A1 (zh)

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CN109216178A (zh) * 2018-09-13 2019-01-15 普冉半导体（上海）有限公司 一种硅片级封装划片槽的设计方法
WO2022077502A1 (zh) * 2020-10-16 2022-04-21 华为技术有限公司 一种晶圆

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US20070293020A1 (en) * 2006-06-20 2007-12-20 Infineon Technologies Ag Singulating semiconductor wafers to form semiconductor chips
CN102810517A (zh) * 2011-06-03 2012-12-05 Nxp股份有限公司 半导体晶片及制造半导体晶片的方法
US20140264767A1 (en) * 2013-03-14 2014-09-18 Infineon Technologies Ag Wafer, Integrated Circuit Chip and Method for Manufacturing an Integrated Circuit Chip
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