WO2023019819A1 - 晶圆切割方法 - Google Patents

晶圆切割方法 Download PDF

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WO2023019819A1
WO2023019819A1 PCT/CN2021/136539 CN2021136539W WO2023019819A1 WO 2023019819 A1 WO2023019819 A1 WO 2023019819A1 CN 2021136539 W CN2021136539 W CN 2021136539W WO 2023019819 A1 WO2023019819 A1 WO 2023019819A1
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device wafer
wafer
groove
cutting process
cutting
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PCT/CN2021/136539
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English (en)
French (fr)
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李琳瑜
张景慧
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湖北三维半导体集成创新中心有限责任公司
湖北江城实验室
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Publication of WO2023019819A1 publication Critical patent/WO2023019819A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/38—Removing material by boring or cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K10/00—Welding or cutting by means of a plasma
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/40—Removing material taking account of the properties of the material involved
    • B23K26/402—Removing material taking account of the properties of the material involved involving non-metallic material, e.g. isolators
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K37/00—Auxiliary devices or processes, not specially adapted to a procedure covered by only one of the preceding main groups
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
    • B23K2103/56—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26 semiconducting

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a wafer cutting method.
  • wafer cutting methods mainly include: wheel cutting, laser cutting and plasma cutting.
  • the cutting method of the cutter wheel is very destructive, and it is easy to cause the dielectric layer in the wafer to break and cause popping or delamination, which affects the performance of the chip, and the lateral width of the cutting line formed by the cutter wheel is large, which is not conducive to chip miniaturization, and cannot Applied to the hybrid bonding interface with high surface requirements; the lateral width of the cutting line formed by laser cutting is small, but it will cause thermal remelting of the material.
  • Even if the surface of the wafer is covered with protective glue, the slag will be used as particles It will also accumulate around the notch; the application of plasma cutting is narrow, but the choice of etchant is more difficult.
  • UV film or blue film is used, such as UV film.
  • Film after the laser irradiates the UV film, the viscosity of the UV film decreases rapidly, and the crystal grains are easy to remove.
  • the use of this UV film during cutting requires a stretch film ring to undertake, and the process equipment is not compatible with the traditional semiconductor front-end wafer carrier equipment; and the UV film has low temperature resistance, and the temperature generally cannot exceed 100 degrees Celsius.
  • the cleaning condition is poor under special solvents such as alkali.
  • UV film Excessively high temperature or the influence of special solvents will cause the UV film to dissolve and affect the cutting of device wafers; and in traditional plasma cutting, it is necessary to use UV film in the etching environment.
  • the film may prematurely solidify under the light effect in the plasma, lose its stickiness, and cause the cut die to be impossible to clean.
  • the purpose of the present invention is to provide a wafer cutting method, improve the wafer cutting process, improve equipment applicability and reduce the wafer cutting lane.
  • the present invention provides a wafer cutting method, comprising:
  • the first groove communicates with the second groove to form a dicing line .
  • the device wafer includes a substrate and a hybrid bonding layer formed on the substrate, the surface of the hybrid bonding layer is the front side of the device wafer, and the first laser cutting The process grooves down the front side of the device wafer to form the first groove penetrating in the hybrid bonding layer.
  • the lateral width of the first groove is 0.1um-120um, and the vertical depth of the first groove is 1um-20um.
  • a wet etching process, a grinding process or a dry etching process is used to remove residues formed when the first groove is formed.
  • the step of temporarily bonding the front side of the device wafer to the carrier includes:
  • the plasma cutting process before adopting the plasma cutting process to groove downwards along the back side of the device wafer, it also includes:
  • the thickness of the device wafer after thinning is 1um-200um.
  • the step of using the plasma cutting process to groove downwards along the back surface of the device wafer includes:
  • patterned photoresist layer on the backside of the device wafer, the patterned photoresist layer having a first opening
  • a plasma cutting process is used to groove downwards along the first opening to form the second groove on the back surface of the device wafer.
  • a back connection structure is formed on the back of the device wafer, and the step of slotting downward along the back of the device wafer by the plasma cutting process includes:
  • grooves are cut down along the second openings by using the plasma cutting process to form the second grooves on the backside of the device wafer.
  • the lateral width of the second groove is 0.1um ⁇ 120um.
  • the first laser cutting process is used to make grooves downward along the front of the device wafer to form the first groove on the front of the device wafer;
  • the front-end device wafer carrier equipment can be used directly to process the cleanliness and flatness of the device wafer without conversion equipment, so that the device wafer The front side of the device wafer meets the requirements of the subsequent process; the front side of the device wafer is temporarily bonded to a carrier, and then the plasma cutting process is used to groove downward along the back side of the device wafer to form a second concave on the back side of the device wafer.
  • the first groove is connected with the second groove to form a cutting line
  • the plasma cutting process can also be directly processed by the front-end device wafer carrier equipment, without the need to upgrade the machine, and the plasma cutting process can make cutting Road reduction is beneficial to chip miniaturization; and the cutting film is not used in the cutting process, that is, the cutting film does not need to be dissipated during the cutting process and does not need to meet the requirements of the cutting film for plasma resistance; therefore, the present invention improves the device
  • the wafer cutting process combines the laser cutting process, temporary bonding and plasma cutting process, which makes the device applicability of the wafer cutting process higher, the process requirements of the plasma cutting are lower, and the device wafer cutting can be reduced. road.
  • FIG. 1 is a flowchart of a wafer cutting method provided in Embodiment 1 of the present invention.
  • FIGS. 2A to 2H are structural schematic diagrams corresponding to corresponding steps in the wafer cutting method provided by Embodiment 1 of the present invention.
  • 3A to 3C are structural schematic diagrams of forming second grooves in the wafer cutting method provided by Embodiment 2 of the present invention.
  • 10-device wafer 100-substrate; 200-interconnection structure layer; 300-hybrid bonding layer; 410-first groove; 420, 430-second groove; 500-carrier; 600-patterning 610-first opening; 700-carrier film; 800-back wiring structure; 810-second opening; 900-laser cutting protective layer.
  • FIG. 1 is a flow chart of the wafer cutting method provided in this embodiment. Please refer to FIG. 1, the present embodiment provides a wafer cutting method, including:
  • Step S1 providing a device wafer
  • Step S2 using a first laser cutting process to make grooves downward along the front surface of the device wafer to form a first groove on the front surface of the device wafer;
  • Step S3 removing residues from forming the first groove
  • Step S4 temporarily bonding the front side of the device wafer to a carrier.
  • Step S5 Grooving downwards along the backside of the device wafer by using a plasma cutting process to form a second groove on the backside of the device wafer, and the first groove communicates with the second groove to form a dicing line.
  • FIGS. 2A to 2H are structural diagrams corresponding to corresponding steps in the wafer cutting method provided in this embodiment.
  • the wafer cutting method provided in this embodiment will be described in detail below with reference to FIGS. 2A to 2H .
  • step S1 is performed: provide a device wafer 10, the device wafer 10 includes a substrate 100 and a hybrid bonding layer 300 formed on the front surface of the substrate 100, and the surface of the hybrid bonding layer 300 is a device wafer
  • the front side of the substrate 10 that is, the front side of the device wafer 10 is the hybrid bonding interface
  • the back side of the substrate 100 is the back side of the device wafer 10 .
  • an interconnection structure layer 200 is also formed between the substrate 100 and the hybrid bonding layer 300, the specific structure of the interconnection structure layer 200 is not limited here, and devices are formed in the device wafer 10 Structures, such as storage devices, MOS tubes, image sensors, etc.
  • step S2 is performed: the hybrid bonding layer 300 includes a metal layer and an insulating layer (not shown in the figure), and the hybrid bonding layer 300 is pre-grooved to open the metal layer and the insulating layer. Therefore, a first laser cutting process is used to cut grooves downward along the front surface of the device wafer 10 to form a first through groove 410 in the hybrid bonding layer 300 .
  • the interconnection structure layer 200 is formed between the substrate 100 and the hybrid bonding layer 300, the interconnection structure layer 200 is generally also cut by a laser cutting process, so the first laser cutting process is adopted along the device.
  • the interconnection structure layer 200 needs to be opened simultaneously so that the first groove 410 penetrates the hybrid bonding layer 300 and the interconnection structure layer 200 .
  • the lateral width of the first groove 410 may be 0.1 um-120 um
  • the vertical depth of the first groove 410 may be 1 um-20 um, but not limited to this range of lateral width and vertical depth.
  • the first laser cutting process can be performed under the carrier equipment of the front-end device wafer 10 without conversion equipment, which improves the applicability of the process equipment.
  • the front side of the device wafer 10 is a hybrid bonding interface.
  • the material of the insulating layer is generally a material with a low dielectric constant, and the insulating layer is generally a layer
  • the intermediate dielectric layer, that is, the first laser cutting process is used to cut the hybrid bonding layer 300; if the front side of the device wafer 10 is not a hybrid bonding interface, but the surface of a metal layer or an insulating layer, it is also necessary to use a laser cutting process to cut this metal layer or insulating layer.
  • step S3 is performed: after the first laser cutting process, a residue will be formed at the opening of the first groove 410, and this residue is at the opening of the first groove 410 after the first laser cutting process Formed slag, this residue affects the cleanliness and flatness of the hybrid bonding interface. Therefore, a wet etching process, a grinding process or a dry etching process is used to remove the residues when the first groove 410 is formed, so as to improve the flatness of the hybrid bonding interface, which is beneficial to subsequent hybrid bonding.
  • the etchant selected in the wet etching process has a high etching selectivity ratio, that is, the rate of etching residues is much greater than the rate of etching other materials on the surface of the device wafer 10, avoiding damage to other materials on the surface of the device wafer 10 cause a greater impact.
  • step S4 apply temporary bonding glue (not shown in the figure) on the front surface of the device wafer 10 and the surface of the carrier 500;
  • the slide 500 is temporarily bonded.
  • the slide 500 can be a glass slide or a silicon wafer, the slide 500 is not easily affected by high temperature, and the material of the temporary bonding glue is a polymer material dissolved after laser irradiation.
  • step S5 is performed: before using the plasma cutting process to groove downward along the back side of the device wafer 10, it also includes: flipping the device wafer 10, thinning the device wafer 10, and grinding backside of the device wafer 10 to reduce the thickness of the device wafer 10 .
  • the thinned device wafer 10 may have a thickness of 1 um ⁇ 200 um, but is not limited to this thickness range.
  • the plasma cutting process is used to groove downward along the back of the device wafer 10, that is, to groove downward along the back of the substrate 100, so as to form a second groove 420 on the back of the device wafer 10, the first groove 410 and The second groove 420 communicates.
  • the plasma cutting process stays on the surface of the carrier 500 or the surface of the temporary bonding glue.
  • a patterned photoresist layer 600 is formed on the back surface of the device wafer 10, the patterned photoresist layer 600 has a first opening 610, the position of the first opening 610 and the position of the first groove 410 The positions are vertically aligned; and, using a plasma cutting process to groove downwards along the first opening 610 to form a second groove 420 on the back side of the device wafer 10, the first groove 410 and the second groove 420 is connected to form a dicing line for dicing the device wafer 10 into a plurality of crystal grains.
  • the lateral width of the second groove 420 may be smaller than that of the first groove 410 , and the lateral width of the second groove 420 may be 0.1 um ⁇ 120 um, but is not limited to this lateral width range.
  • no dicing film such as UV film or blue film, does not need to dissipate heat from the dicing film and does not need to meet the requirements during the dicing process.
  • the cutting film s requirements for plasma resistance reduce the process requirements in the plasma cutting process; and the plasma cutting process can be directly processed by the front-end device wafer carrier equipment without upgrading the machine, which improves the wafer cutting process.
  • the applicability of equipment in the process and the plasma cutting process can reduce the cutting line, which is conducive to chip miniaturization.
  • the patterned photoresist layer 600 is removed, and the patterned photoresist layer 600 can be removed by an ashing process, because the patterned photoresist layer 600
  • the material is an organic material, and oxygen can react with the organic material in an ashing process to remove the patterned photoresist layer 600 .
  • FIG. 2G and FIG. 2H further, after removing the patterned photoresist layer, attach the back of the device wafer 10 to a carrier film 700, and then use laser irradiation to debond to remove the carrier film 500, revealing the device Hybrid bonding interface of wafer 10. Furthermore, cleaning and removing the temporary bonding glue on the surface of the crystal grains to obtain the crystal grains that have been cut and cleaned, under the action of the carrier film 700, it is convenient to clean the crystal grains; and then use a hybrid bonding method to connect the crystal grains to other device wafers , to achieve hybrid bonding of die and wafer.
  • FIG. 3A to 3C are schematic diagrams of the structure of the second groove formed in the wafer cutting method provided in this embodiment. Please refer to FIG. 3A-FIG. 3C.
  • the difference between this embodiment and Embodiment 1 is that, when performing step S5, after grinding the back surface of the device wafer 10 to reduce the thickness of the device wafer 10, the device wafer 10 is also included
  • the back connection structure 800 is formed on the back side of the substrate 100, that is, the back connection structure 800 is formed on the back side of the substrate 100.
  • etching, chemical vapor deposition, electroplating and other processes can be used to form the back connection structure 800.
  • the back connection structure 800 can be It is a combination of plugs, pads and metal lines, and the specific structure of the back wiring structure 800 is not shown in the figure. Since part of the back wiring structure 800 is formed on the vertical position of the first groove 410, for example, the test pad or metal line in the back wiring structure 800 may be formed on the vertical position of the first groove 410 for Electrical testing, so that the second groove cannot be directly formed by the plasma cutting process, that is, when the vertical position of the first groove 410 corresponding to the back surface of the device wafer 10 has metal, it cannot be directly formed by the plasma cutting process second groove.
  • the laser cutting protection layer 900 is first formed on the back side of the device wafer 10, and then the second laser cutting process is used to cut downwards along the back side of the device wafer 10, so as to form a through back connection structure in the back side of the device wafer 10.
  • the second opening 810 of 800 is used to open the partial area of the back wiring structure 800 in the vertical position of the first groove 410, and the second opening 810 and the first groove 410 are aligned in the vertical position; furthermore, using The plasma cutting process grooves downwards along the second opening 810 to form a second groove 430 on the back side of the device wafer 10, the first groove 410 communicates with the second groove 430, wherein the first groove 410, The second groove 430 and the second opening 810 form a dicing line for dicing the device wafer 10 into a plurality of crystal grains, and finally remove the laser dicing protective layer 900 .
  • the first laser cutting process is used to make grooves downward along the front surface of the device wafer to form the first groove on the front surface of the device wafer; Residues during the groove, after the first laser cutting process is pre-grooved to form the first groove, the front-end device wafer carrier equipment can be directly used to process the cleanliness and flatness of the device wafer, without the need for conversion equipment, so that The front side of the device wafer meets the requirements of subsequent processes; the front side of the device wafer is temporarily bonded to a carrier, and then the plasma cutting process is used to groove downward along the back side of the device wafer to form a
  • the second groove, the first groove and the second groove are connected to form a cutting line, in which the plasma cutting process can also be directly processed by the front-end device wafer carrier equipment, without the need to upgrade the machine, and the plasma cutting process
  • the dicing track can be reduced, which is beneficial to chip miniaturization; and the dicing film is not used in the

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Abstract

一种晶圆切割方法，包括：提供器件晶圆（10）；采用第一激光切割工艺沿器件晶圆（10）的正面向下开槽，以在器件晶圆（10）的正面形成第一凹槽（410）；去除形成第一凹槽（410）时的残留物；将器件晶圆（10）的正面和一载片（500）进行临时键合；以及，采用等离子体切割工艺沿器件晶圆（10）的背面向下开槽，以在器件晶圆（10）的背面形成第二凹槽（420、430），第一凹槽（410）与第二凹槽（420、430）连通构成切割道。

Description

晶圆切割方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种晶圆切割方法。
背景技术
目前对晶圆切割方式主要包括：刀轮切割方式、激光切割方式和等离子体切割方式。其中刀轮切割方式破坏性大，容易导致晶圆中的介质层碎裂产生蹦口或分层，影响芯片性能，且刀轮形成的切割道的横向宽度较大，不利于芯片微缩，且无法应用于表面要求很高的混合键合界面；激光切割方式形成的切割道的横向宽度较小，但是会导致材料的热重熔现象，即使在晶圆的表面盖上保护胶，熔渣作为颗粒物也会堆积在槽口周围；等离子体切割方式应用面较窄，不过刻蚀剂的选择难度较大。
在现有技术中需要在切割之前在晶圆的背面粘贴一层固定晶粒的膜，然后进行晶圆的切割，此膜也就是切割膜，一般会采用UV膜或蓝膜等，例如采用UV膜，在激光照射UV膜之后，UV膜的粘性迅速下降，晶粒容易取下。但是在切割时利用这种UV膜需要采用绷膜环去承接，而工艺设备和传统的半导体前段晶圆载体设备不兼容；并且UV膜耐温较低，温度一般不能超过100摄氏度，在强酸强碱等特殊溶剂下清洗状况较差，温度过高或特殊溶剂的影响会导致UV膜溶解，影响器件晶圆切割；并且在传统的等离子体切割时，需要在刻蚀环境中使用UV膜，UV膜在等离子体中的光效应下可能会提前固化，失去粘性，导致切割后的晶粒无法清洗。
发明内容
本发明的目的在于提供一种晶圆切割方法，改善晶圆切割工艺，提高设备适用性及缩小晶圆切割道。
为了达到上述目的，本发明提供了一种晶圆切割方法，包括：
提供器件晶圆；
采用第一激光切割工艺沿所述器件晶圆的正面向下开槽，以在所述器件 晶圆的正面形成第一凹槽；
去除形成所述第一凹槽时的残留物；
将所述器件晶圆的正面和一载片进行临时键合；以及，
采用等离子体切割工艺沿所述器件晶圆的背面向下开槽，以在所述器件晶圆的背面形成第二凹槽，所述第一凹槽与所述第二凹槽连通构成切割道。
可选的，所述器件晶圆包括衬底及形成于所述衬底上的混合键合层，所述混合键合层的表面为所述器件晶圆的正面，采用所述第一激光切割工艺沿所述器件晶圆的正面向下开槽，以在所述混合键合层中形成贯穿的所述第一凹槽。
可选的，所述第一凹槽的横向宽度为0.1um～120um，所述第一凹槽的垂向深度为1um～20um。
可选的，采用湿法刻蚀工艺、研磨工艺或干法刻蚀工艺去除形成所述第一凹槽时的残留物。
可选的，将所述器件晶圆的正面和所述载片进行临时键合的步骤包括：
在所述器件晶圆的正面及所述载片的表面涂布临时键合胶；通过所述临时键合胶将所述器件晶圆及所述载片进行临时键合。
可选的，在采用所述等离子体切割工艺沿所述器件晶圆的背面向下开槽之前，还包括：
研磨所述器件晶圆的背面以减薄所述器件晶圆的厚度。
可选的，减薄后的所述器件晶圆的厚度为1um～200um。
可选的，采用所述等离子体切割工艺沿所述器件晶圆的背面向下开槽的步骤包括：
在所述器件晶圆的背面形成图形化的光刻胶层，所述图形化的光刻胶层具有第一开口；以及，
采用等离子体切割工艺沿着所述第一开口向下开槽，以在器件晶圆的背面形成所述第二凹槽。
可选的，所述器件晶圆的背面形成有背连线结构，采用所述等离子体切割工艺沿所述器件晶圆的背面向下开槽的步骤包括：
在所述器件晶圆的背面涂布激光切割保护胶；
采用第二激光切割工艺沿着所述器件晶圆的背面向下切割，以在所述器件晶圆的背面中形成贯穿所述背连线结构的第二开口；以及，
采用所述等离子体切割工艺沿着所述第二开口向下开槽，以在器件晶圆的背面形成所述第二凹槽。
可选的，所述第二凹槽的横向宽度为0.1um～120um。
在本发明提供的晶圆切割方法中，先采用第一激光切割工艺沿器件晶圆的正面向下开槽，以在器件晶圆的正面形成第一凹槽；然后去除形成第一凹槽时的残留物，在第一激光切割工艺进行预开槽形成第一凹槽后可以直接采用前段器件晶圆载体设备进行器件晶圆洁净度和平整度处理，不需要转换设备，以使器件晶圆的正面满足后续工艺需求；将器件晶圆的正面和一载片进行临时键合，再采用等离子体切割工艺沿器件晶圆的背面向下开槽，以在器件晶圆的背面形成第二凹槽，第一凹槽与第二凹槽连通构成切割道，其中等离子体切割工艺也可以直接采用前段器件晶圆载体设备进行处理，无需对机台进行改造升级，并且等离子体切割工艺可以使切割道减小，有利于芯片微缩；以及切割过程中不利用切割膜，即在切割过程中不需要对切割膜进行散热和不需要满足切割膜对等离子体抗性的要求；因此本发明改善了器件晶圆切割工艺将激光切割工艺、临时键合及等离子体切割工艺进行结合，使器件晶圆切割工艺中设备适用性更高，等离子体切割时的工艺要求较低，并且能够缩小器件晶圆切割道。
附图说明
图1为本发明实施例一提供的晶圆切割方法的流程图；
图2A～图2H为本发明实施例一提供的晶圆切割方法中相应步骤对应的结构示意图；
图3A～图3C为本发明实施例二提供的晶圆切割方法中形成第二凹槽的结构示意图；
其中，附图标记为：
10-器件晶圆；100-衬底；200-互连结构层；300-混合键合层；410-第一凹槽；420、430-第二凹槽；500-载片；600-图形化的光刻胶层；610-第一开口； 700-承载膜；800-背连线结构；810-第二开口；900-激光切割保护层。
具体实施方式
下面将结合示意图对本发明的具体实施方式进行更详细的描述。根据下列描述，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
实施例一
图1为本实施例提供的晶圆切割方法的流程图。请参考图1，本实施例提供了一种晶圆切割方法，包括：
步骤S1：提供器件晶圆；
步骤S2：采用第一激光切割工艺沿器件晶圆的正面向下开槽，以在器件晶圆的正面形成第一凹槽；
步骤S3：去除形成第一凹槽时的残留物；
步骤S4：将器件晶圆的正面和一载片进行临时键合；以及，
步骤S5：采用等离子体切割工艺沿器件晶圆的背面向下开槽，以在器件晶圆的背面形成第二凹槽，第一凹槽与第二凹槽连通构成切割道。
图2A～图2H为本实施例提供的晶圆切割方法中相应步骤对应的结构示意图，下面结合图2A～图2H对本实施例提供的晶圆切割方法进行详细说明。
请参考图2A，执行步骤S1：提供器件晶圆10，器件晶圆10包括衬底100及形成于衬底100的正面上的混合键合层300，混合键合层300的表面为器件晶圆10的正面，即器件晶圆10的正面为混合键合界面，衬底100的背面为器件晶圆10的背面。在本实施例中，在衬底100和混合键合层300之间还形成有互连结构层200，在此不对互连结构层200的具体结构进行限定，在器件晶圆10中形成有器件结构，如存储器件、MOS管、图像传感器等。
请参考图2B，执行步骤S2：混合键合层300中包括金属层和绝缘层(图中未示出)，对混合键合层300进行预开槽打开金属层和绝缘层。因此采用第一激光切割工艺沿器件晶圆10的正面向下开槽，以在混合键合层300中形成 贯穿的第一凹槽410。在本实施例中，由于在衬底100和混合键合层300之间还形成有互连结构层200，一般也采用激光切割工艺切割互连结构层200，因此采用第一激光切割工艺沿器件晶圆10的正面向下开槽时，还需要同步将互连结构层200打开，使第一凹槽410贯穿混合键合层300和互连结构层200。在本实施例中，第一凹槽410的横向宽度可为0.1um～120um，第一凹槽410的垂向深度可为1um～20um，但不限于此横向宽度范围和垂向深度范围。在本实施例中，第一激光切割工艺可以在前段器件晶圆10载体设备下执行，不需要转换设备，提高工艺设备适用性。在本实施例中，器件晶圆10的正面为混合键合界面，由于混合键合层300中包括金属层和绝缘层，绝缘层的材料一般为低介电常数的材料，绝缘层一般为层间介质层，即采用第一激光切割工艺切割混合键合层300；若器件晶圆10的正面并非是混合键合界面，而是金属层或绝缘层的表面，也需要采用激光切割工艺切割此金属层或绝缘层。
请参考图2C，执行步骤S3：在第一激光切割工艺后，在第一凹槽410的开口处会形成残留物，此残留物为第一激光切割工艺后在第一凹槽410的开口处形成的熔渣，此残留物影响混合键合界面的洁净度和平整度。因此采用湿法刻蚀工艺、研磨工艺或是干法刻蚀工艺去除形成第一凹槽410时的残留物，以提升混合键合界面的平整度，有利于后续进行混合键合。在湿法刻蚀工艺中选用的刻蚀剂具有高刻蚀选择比，即刻蚀残留物的速率远大于刻蚀器件晶圆10的表面其它材质的速率，避免对器件晶圆10的表面其它材质造成较大的影响。
请继续参考图2C，执行步骤S4：在器件晶圆10的正面及载片500的表面均涂布临时键合胶(图中未示出)；然后通过临时键合胶将器件晶圆10及载片500进行临时键合。在本实施例中，载片500可为玻璃载片或硅片，载片500不易受高温影响，临时键合胶的材质为激光照射后溶解的聚合物材料。
请参考图2D及图2E，执行步骤S5：在采用等离子体切割工艺沿器件晶圆10的背面向下开槽之前，还包括：翻转器件晶圆10，对器件晶圆10进行减薄，研磨器件晶圆10的背面以减薄器件晶圆10的厚度。在本实施例中，减薄后的所述器件晶圆10的厚度可为1um～200um，但不限于此厚度范围。
采用等离子体切割工艺沿器件晶圆10的背面向下开槽，即沿衬底100的 背面向下开槽，以在器件晶圆10的背面形成第二凹槽420，第一凹槽410与第二凹槽420连通，在采用等离子体切割工艺沿器件晶圆10的背面向下开槽时，等离子体切割工艺停留在载片500的表面或者临时键合胶的表面。在本实施例中，在器件晶圆10的背面形成图形化的光刻胶层600，图形化的光刻胶层600具有第一开口610，第一开口610的位置和第一凹槽410的位置在垂向上对准；以及，采用等离子体切割工艺沿着第一开口610向下开槽，以在器件晶圆10的背面形成第二凹槽420，第一凹槽410与第二凹槽420连通构成切割道，以将器件晶圆10进行切割成多个晶粒。在本实施例中，第二凹槽420的横向宽度可小于第一凹槽410的横向宽度，第二凹槽420的横向宽度可为0.1um～120um，但不限于此横向宽度范围。在本实施例中，在将器件晶圆10进行切割成多个晶粒时，并未用到切割膜，如UV膜或蓝膜，在切割过程中不需要对切割膜进行散热和不需要满足切割膜对等离子体抗性的要求，降低等离子体切割工艺中的工艺要求；并且等离子体切割工艺可以直接采用前段器件晶圆载体设备进行处理，无需对机台进行改造升级，提高了晶圆切割工艺中设备适用性，以及等离子体切割工艺可以使切割道减小，有利于芯片微缩。
请参考图2F，在采用等离子体切割工艺切割完成之后，去除图形化的光刻胶层600，可采用灰化工艺去除图形化的光刻胶层600，由于图形化的光刻胶层600的材质为有机材料，采用灰化工艺中氧气可以与有机材料发生反应以去除图形化的光刻胶层600。
请参考图2G及图2H，进一步地，去除图形化的光刻胶层之后，将器件晶圆10的背面与一承载膜700贴合，然后采用激光照射解键合以取下载片500，显露出器件晶圆10的混合键合界面。进而，清洗去除晶粒表面的临时键合胶得到切割清洗好的晶粒，在承载膜700的作用下，便于对晶粒进行清洗；然后采用混合键合方式将晶粒和其它器件晶圆连接，以实现晶粒与晶圆的混合键合。
实施例二
图3A～图3C为本实施例提供的晶圆切割方法中形成第二凹槽的结构示意 图。请参考图3A～图3C，本实施例与实施例一的区别在于，执行步骤S5时，在研磨器件晶圆10的背面以减薄器件晶圆10的厚度之后，还包括在器件晶圆10的背面形成背连线结构800，即在衬底100的背面形成背连线结构800，一般可采用刻蚀、化学气相沉积及电镀等工艺去形成背连线结构800，背连线结构800可以是插塞、焊盘及金属线的组合，图中未具体示出背连线结构800中的具体结构。由于背连线结构800的部分形成在第一凹槽410垂向位置上，比如可能是背连线结构800中的测试焊盘或金属线形成在第一凹槽410的垂向位置上用于电性测试，从而不能直接采用等离子体切割工艺形成第二凹槽，即当器件晶圆10的背面对应的第一凹槽410的垂向位置上具有金属，则不能直接采用等离子体切割工艺形成第二凹槽。
因此先在器件晶圆10的背面形成激光切割保护层900，然后采用第二激光切割工艺沿着器件晶圆10的背面向下切割，以在器件晶圆10的背面中形成贯穿背连线结构800的第二开口810，以打开背连线结构800在第一凹槽410的垂向位置上的部分区域，第二开口810和第一凹槽410在垂向位置上对准；进而，采用等离子体切割工艺沿着第二开口810向下开槽，以在器件晶圆10的背面形成第二凹槽430，第一凹槽410与第二凹槽430连通，其中第一凹槽410、第二凹槽430及第二开口810构成切割道以将器件晶圆10进行切割成多个晶粒，最后去除激光切割保护层900。
综上，在本发明提供的晶圆切割方法中，先采用第一激光切割工艺沿器件晶圆的正面向下开槽，以在器件晶圆的正面形成第一凹槽；然后去除形成第一凹槽时的残留物，在第一激光切割工艺进行预开槽形成第一凹槽后可以直接采用前段器件晶圆载体设备进行器件晶圆洁净度和平整度处理，不需要转换设备，以使器件晶圆的正面满足后续工艺需求；将器件晶圆的正面和一载片进行临时键合，再采用等离子体切割工艺沿器件晶圆的背面向下开槽，以在器件晶圆的背面形成第二凹槽，第一凹槽与第二凹槽连通构成切割道，其中等离子体切割工艺也可以直接采用前段器件晶圆载体设备进行处理，无需对机台进行改造升级，并且等离子体切割工艺可以使切割道减小，有利于芯片微缩；以及切割过程中不利用切割膜，即在切割过程中不需要对切割膜进行散热和不需要满足切割膜对等离子体抗性的要求；因此本发明改善了器 件晶圆切割工艺将激光切割工艺、临时键合及等离子体切割工艺进行结合，使器件晶圆切割工艺中设备适用性更高，等离子体切割时的工艺要求较低，并且能够缩小器件晶圆切割道。
上述仅为本发明的优选实施例而已，并不对本发明起到任何限制作用。任何所属技术领域的技术人员，在不脱离本发明的技术方案的范围内，对本发明揭露的技术方案和技术内容做任何形式的等同替换或修改等变动，均属未脱离本发明的技术方案的内容，仍属于本发明的保护范围之内。

Claims (10)

  1. 一种晶圆切割方法，其特征在于，包括：
    提供器件晶圆；
    采用第一激光切割工艺沿所述器件晶圆的正面向下开槽，以在所述器件晶圆的正面形成第一凹槽；
    去除形成所述第一凹槽时的残留物；
    将所述器件晶圆的正面和一载片进行临时键合；以及，
    采用等离子体切割工艺沿所述器件晶圆的背面向下开槽，以在所述器件晶圆的背面形成第二凹槽，所述第一凹槽与所述第二凹槽连通构成切割道。
  2. 如权利要求1所述的晶圆切割方法，其特征在于，所述器件晶圆包括衬底及形成于所述衬底上的混合键合层，所述混合键合层的表面为所述器件晶圆的正面，采用所述第一激光切割工艺沿所述器件晶圆的正面向下开槽，以形成贯穿所述混合键合层的所述第一凹槽。
  3. 如权利要求2所述的晶圆切割方法，其特征在于，所述第一凹槽的横向宽度为0.1um～120um，所述第一凹槽的垂向深度为1um～20um。
  4. 如权利要求1所述的晶圆切割方法，其特征在于，采用湿法刻蚀工艺、研磨工艺或干法刻蚀工艺去除形成所述第一凹槽时的残留物。
  5. 如权利要求1所述的晶圆切割方法，其特征在于，将所述器件晶圆的正面和所述载片进行临时键合的步骤包括：
    在所述器件晶圆的正面及所述载片的表面涂布临时键合胶；
    通过所述临时键合胶将所述器件晶圆及所述载片进行临时键合。
  6. 如权利要求1所述的晶圆切割方法，其特征在于，在采用所述等离子体切割工艺沿所述器件晶圆的背面向下开槽之前，所述晶圆切割方法还包括：
    研磨所述器件晶圆的背面以减薄所述器件晶圆的厚度。
  7. 如权利要求6所述的晶圆切割方法，其特征在于，减薄后的所述器件晶圆的厚度为1um～200um。
  8. 如权利要求1所述的晶圆切割方法，其特征在于，采用所述等离子体切割工艺沿所述器件晶圆的背面向下开槽的步骤包括：
    在所述器件晶圆的背面形成图形化的光刻胶层，所述图形化的光刻胶层具有第一开口；以及，
    采用等离子体切割工艺沿着所述第一开口向下开槽，以在所述器件晶圆的背面形成所述第二凹槽。
  9. 如权利要求1所述的晶圆切割方法，其特征在于，所述器件晶圆的背面形成有背连线结构，采用所述等离子体切割工艺沿所述器件晶圆的背面向下开槽的步骤包括：
    在所述器件晶圆的背面涂布激光切割保护胶；
    采用第二激光切割工艺沿着所述器件晶圆的背面向下切割，以在所述器件晶圆的背面中形成贯穿所述背连线结构的第二开口；以及，
    采用所述等离子体切割工艺沿着所述第二开口向下开槽，以在所述器件晶圆的背面形成所述第二凹槽。
  10. 如权利要求8或9所述的晶圆切割方法，其特征在于，所述第二凹槽的横向宽度为0.1um～120um。
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