WO2020052558A1 - 发光二极管的半导体芯片及其量子阱层和制造方法 - Google Patents

发光二极管的半导体芯片及其量子阱层和制造方法 Download PDF

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WO2020052558A1
WO2020052558A1 PCT/CN2019/105166 CN2019105166W WO2020052558A1 WO 2020052558 A1 WO2020052558 A1 WO 2020052558A1 CN 2019105166 W CN2019105166 W CN 2019105166W WO 2020052558 A1 WO2020052558 A1 WO 2020052558A1
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layer
quantum well
quantum
semiconductor chip
gallium nitride
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French (fr)
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万志
卓祥景
尧刚
林志伟
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厦门乾照光电股份有限公司
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Definitions

  • the present invention relates to a light emitting diode, in particular to a semiconductor chip of a light emitting diode, a quantum well layer and a manufacturing method thereof.
  • III-V nitride As a direct band gap semiconductor, III-V nitride has excellent physical characteristics such as a large band gap width, a high breakdown electric field, and a high electron saturation mobility, and has attracted wide attention in the application in the field of LEDs.
  • semiconductor chips based on AlInGaN-based materials have received more and more attention due to their excellent device performance and broad application prospects.
  • the structure of the quantum well layer, the crystal quality between the well barriers, and the abrupt design between the well barriers are especially valued by the designers of semiconductor chips, that is, the design of the quantum well layer is the key to the design of the entire semiconductor chip.
  • the differences between the well barrier crystals will inevitably lead to the difference in the luminous efficiency and optical performance of the entire device.
  • the barrier of the quantum well layer of a semiconductor chip is grown under the same pressure, such as a blue-green semiconductor chip.
  • the quantum well of the quantum well layer is the main light-emitting layer, and its material is generally InGaN. If the growth pressure of the quantum well layer of the quantum well layer is too low, the incorporation efficiency of the In element will increase, but at the same time, the wavelength consistency and uniformity will be destroyed. If the growth pressure of the quantum well layer of the quantum well layer is too high, it will affect the atom migration rate, making the quantum well tend to grow in three dimensions, and then cause the surface of the quantum well to roughen and affect the quality of the crystal. Therefore, in the existing growth process In the quantum well layer, the growth of the quantum well is stabilized. However, because the material composition of the quantum well and the quantum barrier of the quantum well layer is different, the crystal quality of the well barrier interface of the quantum well and the quantum barrier grown under the same pressure is relatively low. difference.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode, a quantum well layer and a manufacturing method thereof, wherein the crystal quality of the well barrier interface of the quantum well and quantum barrier of the quantum well layer can be greatly improved to improve Light effect of the semiconductor chip.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode, a quantum well layer and a manufacturing method thereof, wherein the quantum well layer and the quantum barrier layer have different growth pressures to improve the quantum well layer.
  • the crystal mass of the well barrier interface of the quantum well and the quantum barrier.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode, a quantum well layer and a manufacturing method thereof, wherein a growth pressure of the quantum barrier of the quantum well layer is lower than a growth pressure of the quantum well, so as to improve the The crystal quality of the quantum well and the well barrier interface of the quantum barrier.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode, a quantum well layer and a manufacturing method thereof, wherein a growth pressure of the quantum barrier of the quantum well layer is lower than a growth pressure of the quantum well.
  • the atomic migration of the quantum barrier can be enhanced to promote two-dimensional growth of the surface of the quantum barrier, thereby facilitating the improvement of the crystal quality of the well barrier interface of the quantum barrier and the quantum well.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode, a quantum well layer and a manufacturing method thereof, wherein a growth pressure of the quantum barrier of the quantum well layer is lower than a growth pressure of the quantum well to promote group III
  • the incorporation of elements can promote the incorporation of In element into the quantum barrier by making the growth pressure of the quantum barrier lower than the growth pressure of the quantum well, so that when growing the semiconductor chip with blue-green light Can provide more light-emitting quantum dots to improve the light efficiency of the semiconductor chip.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode, a quantum well layer and a manufacturing method thereof, wherein the semiconductor chip provides a current spreading layer, and the current spreading layer is capable of uniformly spreading a current in the semiconductor chip. , Thereby improving the light efficiency of the semiconductor chip.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode, a quantum well layer and a manufacturing method thereof, wherein the current spreading layer can weaken a vertical current spreading capability of the semiconductor chip and improve a lateral current spreading capability of the semiconductor chip. So that the current spreads evenly on the semiconductor chip.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode, a quantum well layer and a manufacturing method thereof, wherein in a height direction of the semiconductor chip, a resistance state of the current spreading layer exhibits "low resistance-high resistance-low Resistance-high resistance ... "to weaken the longitudinal current expansion capability of the semiconductor chip and improve the lateral current expansion capability of the semiconductor chip.
  • the present invention provides a semiconductor chip of a light emitting diode, which includes:
  • N-type GaN layer wherein the N-type GaN layer is stacked on the substrate;
  • a quantum well layer wherein the quantum well layer is stacked on the N-type gallium nitride layer, wherein the quantum well layer includes at least one quantum barrier and at least one quantum well, which are stacked in sequence Well growth pressures are different;
  • a P-type GaN layer wherein the P-type GaN layer is stacked on the quantum well layer;
  • N-type electrode wherein the N-type electrode is electrically connected to the N-type gallium nitride layer;
  • a P-type electrode wherein the P-type electrode is electrically connected to the P-type gallium nitride layer.
  • a growth pressure of the quantum barrier of the quantum well layer is lower than a growth pressure of the quantum well.
  • a layer number parameter of the quantum barrier of the quantum well layer and a layer number parameter of the quantum well are both N, and a value range of the parameter N is: 3 ⁇ N ⁇ 20.
  • the quantum barrier of the quantum well layer is an Alx1Iny1Ga1-x1-y1N (0 ⁇ X1 ⁇ 1,0 ⁇ Y1 ⁇ 1) doped quantum barrier with a doping concentration of 1-5x10 18 cm -3 , wherein the quantum well of the quantum well layer is an Alx2Iny2Ga1-x2-y2N (0 ⁇ X2 ⁇ 1,0 ⁇ Y2 ⁇ 1) undoped quantum well.
  • a thickness dimension range of the quantum barrier of the quantum well is 5nm-15nm, and a thickness dimension range of the quantum well is 2nm-5nm.
  • the semiconductor chip further includes a buffer layer, wherein the buffer layer is stacked on the substrate, and the N-type gallium nitride layer is stacked on the buffer layer.
  • the buffer layer is a GaN buffer layer or an AlN buffer layer.
  • the semiconductor chip further includes a current spreading layer, wherein the current spreading layer is stacked on the N-type gallium nitride layer, and the quantum well layer is stacked on the current spreading layer.
  • the current spreading layer is an N-type current spreading layer; or the current spreading layer is an AlGaN type current spreading layer; or the current spreading layer is an InGaN current spreading layer.
  • the semiconductor chip further includes a protection layer, wherein the protection layer is stacked on the quantum well layer, and the P-type gallium nitride layer is stacked on the protection layer.
  • the semiconductor chip further includes an electron blocking layer, wherein the electron blocking layer is stacked on the protective layer, and the P-type gallium nitride layer is stacked on the electron blocking layer.
  • the N-type electrode is stacked on the current spreading layer, and the P-type electrode is stacked on the P-type gallium nitride layer.
  • the present invention further provides a quantum well layer, which is applied to a semiconductor chip, wherein the quantum well layer includes at least one quantum barrier and at least one quantum well, which are sequentially stacked.
  • the quantum wells have different growth pressures.
  • a growth pressure of the quantum barrier of the quantum well layer is lower than a growth pressure of the quantum well.
  • a layer number parameter of the quantum barrier of the quantum well layer and a layer number parameter of the quantum well are both N, and a value range of the parameter N is: 3 ⁇ N ⁇ 20.
  • the quantum barrier of the quantum well layer is an Alx1Iny1Ga1-x1-y1N (0 ⁇ X1 ⁇ 1,0 ⁇ Y1 ⁇ 1) doped quantum barrier with a doping concentration of 1-5x10 18 cm -3 , wherein the quantum well of the quantum well layer is an Alx2Iny2Ga1-x2-y2N (0 ⁇ X2 ⁇ 1,0 ⁇ Y2 ⁇ 1) undoped quantum well.
  • a thickness dimension range of the quantum barrier of the quantum well is 5nm-15nm, and a thickness dimension range of the quantum well is 2nm-5nm.
  • the present invention further provides a method for manufacturing a semiconductor chip of a light emitting diode, wherein the manufacturing method includes the following steps:
  • a cycle period for growing the quantum barrier and the quantum well is 3 cycles to 20 cycles.
  • the growth pressure of the quantum barrier is lower than the growth pressure of the quantum well.
  • the growth pressure of the quantum barrier is lower than the growth pressure of the quantum well.
  • the method further includes the following steps:
  • a doping concentration of the quantum barrier of the quantum well layer is 1-5 ⁇ 10 18 cm ⁇ 3 .
  • a thickness dimension range of the quantum barrier of the quantum well layer is 5nm-15nm, and a thickness dimension range of the quantum well is 2nm-5nm.
  • the manufacturing method before the step (a), further includes a step of growing a buffer layer from the substrate, so that in the step (a), the N-type nitrogen A gallium layer is grown on the buffer layer.
  • the manufacturing method before the step (b), further includes a step of: growing a current spreading layer from the N-type gallium nitride layer, so that in the step (b), The quantum well layer is grown on the current spreading layer.
  • step (c) before the step (c), further comprising the steps of: growing a protective layer from the quantum well layer and growing an electron blocking layer from the protective layer, so that in the step (c ), The P-type GaN layer is grown on the electron blocking layer.
  • FIG. 1 is a schematic cross-sectional view of one of the manufacturing steps of a semiconductor chip according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of a second manufacturing step of the semiconductor chip according to the above preferred embodiment of the present invention.
  • FIG. 3 is a schematic sectional view of the third manufacturing step of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view of the fourth manufacturing step of the semiconductor chip according to the above preferred embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view of the fifth manufacturing step of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional view of the sixth manufacturing step of the semiconductor chip according to the above preferred embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view of the seventh manufacturing step of the semiconductor chip according to the above preferred embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional view of the eighth step of manufacturing the semiconductor chip according to the above preferred embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view of a ninth step of manufacturing the semiconductor chip according to the above preferred embodiment of the present invention, which illustrates a cross-sectional state of the semiconductor chip.
  • a semiconductor chip of a light emitting diode according to a preferred embodiment of the present invention is disclosed and explained in the following description, wherein the semiconductor chip includes a Substrate 10, an N-type gallium nitride layer 20, a quantum well layer 30, a P-type gallium nitride layer 40, an N-type electrode 50, and a P-type electrode 60, wherein the N-type gallium nitride layer 20 Stacked on the substrate 10, the quantum well layer 30 is stacked on the N-type gallium nitride layer 20, the P-type gallium nitride layer 40 is stacked on the quantum well layer 30, and the N-type electrode 50 The N-type gallium nitride layer 20 is electrically connected, and the P-type electrode 60 is electrically connected to the P-type gallium nitride layer 40.
  • a current injected into the semiconductor chip from the N-type electrode 50 can pass through the N-type gallium nitride layer.
  • the current that enters the quantum well layer 30 and is injected into the semiconductor chip from the P-type electrode 60 can pass through the P-type gallium nitride layer 40 into the quantum well layer 30 to the quantum well layer. 30 composite glow.
  • the quantum well layer 30 includes at least one quantum well and at least one quantum barrier that are sequentially stacked, wherein the crystal quality at the interface between the quantum well and the well barrier of the quantum well layer 30 can be obtained. Great improvement to improve the light efficiency of the semiconductor chip.
  • the number of the quantum wells and the quantum barriers of the quantum well layer 30 are each N, that is, in the process of manufacturing the semiconductor chip, the quantum wells and The quantum barrier forms the quantum well layer 30, so that the first quantum barrier of the quantum well layer 30 is stacked on the N-type gallium nitride layer 20, and the first of the quantum well layer 30 is The quantum wells are stacked on the first quantum barrier, and the second quantum well of the quantum well layer 30 is stacked on the first quantum well, and the second quantum well layer 30 is stacked on the first quantum barrier.
  • the quantum well is stacked on the second quantum barrier ...
  • the Nth quantum barrier of the quantum well layer 30 is stacked on the N-1th quantum well, and the Nth of the quantum well layer 30
  • the quantum well is stacked on the Nth quantum barrier, and the crystal quality at the interface between the adjacent quantum well and the well barrier of the quantum barrier can be greatly improved, so as to improve the semiconductor chip.
  • Light effect For example, the consistency of the crystal quality of the well barrier interface of the quantum well layer and the quantum barrier of the quantum well layer 30 can be improved, thereby improving the crystal quality of the well barrier interface of the quantum well and the quantum barrier. .
  • the value of the parameter N ranges from 3 ⁇ N ⁇ 20, that is, the quantum well layer 30 of the semiconductor chip includes 3
  • the quantum barrier and the quantum well include cycles to 20 cycles (including 3 cycles and 20 cycles).
  • the number of layers of the quantum barrier and the number of layers of the quantum well of the quantum well layer 30 of the semiconductor chip are both 3 to 20 (including 3 and 20).
  • the growth pressure of the quantum barrier of the quantum well layer 30 and the quantum well is different, and it depends on the materials of the quantum barrier and the quantum well. A suitable pressure is selected. In this way, the crystal quality of the quantum barrier layer 30 and the quantum barrier well barrier interface can be greatly improved, so as to improve the light efficiency of the semiconductor chip.
  • the growth pressure of the quantum barrier of the quantum well layer 30 is lower than the growth pressure of the quantum well to improve the quantum barrier and The crystal quality of the well barrier interface of the quantum well.
  • the atomic migration of the quantum barrier can be enhanced to promote the quantum The surface of the barrier grows in two dimensions, which is beneficial to improving the crystal quality of the well barrier interface of the quantum barrier and the quantum well.
  • the N-type gallium nitride layer 20 of the semiconductor chip is a silicon (Si) -doped gallium nitride layer, wherein the silicon doping concentration of the N-type gallium nitride layer 20 is 1-10x10 18 cm -3 . More preferably, the thickness dimension of the N-type gallium nitride layer 20 of the semiconductor chip ranges from 3 ⁇ m to 6 ⁇ m (including 3 ⁇ m and 6 ⁇ m).
  • the P-type gallium nitride layer 40 of the semiconductor chip is a doped gallium nitride layer, wherein the doping concentration of the P-type gallium nitride layer 40 is 5-10 ⁇ 10 18 cm ⁇ 3 . More preferably, the thickness dimension of the P-type gallium nitride layer 40 of the semiconductor chip ranges from 100 nm to 200 nm (including 100 nm and 200 nm).
  • the material of the N-type electrode 50 is Ti (titanium) or Al (aluminum). Accordingly, the material of the P-type electrode 60 is Ni (nickel) or Au (gold).
  • the semiconductor chip further includes a buffer layer 70, wherein the buffer layer 70 is stacked on the substrate 10, and the N-type gallium nitride layer 20 is stacked on the buffer layer 70. Therefore, the N-type gallium nitride layer 20 is stacked on the substrate 10 such that the N-type gallium nitride layer 20 is stacked on the buffer layer 70 and the buffer layer 70 is stacked on the substrate 10. .
  • the buffer layer 70 can be kept between the N-type gallium nitride layer 20 and the substrate 10 to avoid the problem of lattice mismatch, which is beneficial to ensure the Stability and reliability of semiconductor chips.
  • the buffer layer 70 is a gallium nitride buffer layer.
  • the buffer layer 70 may be, but is not limited to, an undoped gallium nitride buffer layer.
  • the thickness dimension of the buffer layer 70 ranges from 20 nm to 50 nm (including 20 nm and 50 nm).
  • the buffer layer 70 is an AlN buffer layer.
  • the semiconductor chip further includes a current spreading layer 80, wherein the current spreading layer 80 is stacked on the N-type gallium nitride layer 20, and the quantum well layer 30 is stacked on the A current spreading layer 80 such that the quantum well layer 30 is stacked on the quantum well layer 30 such that the quantum well layer 30 is stacked on the current spreading layer 80 and the current spreading layer 80 is stacked on the N-type gallium nitride layer 20.
  • the N-type gallium nitride layer 20 is described.
  • the N-type electrode 50 is electrically connected to the N-type electrode 50 such that the N-type electrode 50 is electrically connected to the current spreading layer 80 and the current spreading layer 80 is electrically connected to the N-type gallium nitride layer 20.
  • the N-type gallium nitride layer 20 is such that the current injected through the N-type electrode 50 can enter the quantum well layer 30 through the N-type gallium nitride layer 20 after being expanded by the current spreading layer 80.
  • the current spreading layer 80 is an N-type current spreading layer.
  • the current spreading layer 80 is an AlGaN current spreading layer or an InGaN current spreading layer.
  • the current spreading layer 80 when the current spreading layer 80 is an N-type current spreading layer, the current spreading layer 80 includes at least one N-GaN layer and at least one U-GaN layer, wherein the N-GaN layer and the U-GaN layer -GaN layers are stacked on each other so that the current spreading layer 80 can exhibit a resistance state of "low resistance-high resistance-low resistance-high resistance " in the height direction.
  • the current The expansion layer 80 causes the vertical resistance of the semiconductor chip to be increased, thereby reducing the vertical current expansion capability of the semiconductor chip.
  • the current expansion layer 80 enables the horizontal current expansion capability of the semiconductor chip to be effectively improved. Therefore, it is beneficial for the current to be uniformly distributed and the luminous efficiency to be improved, which greatly improves the optical performance and the service life of the semiconductor chip.
  • the semiconductor chip further includes a protective layer 90, wherein the protective layer 90 is stacked on the quantum well layer 30 to maintain the crystal quality of the quantum well layer 30, thereby avoiding Damage to the composition and structure of the quantum well layer 30 in the subsequent growth process.
  • the protective layer 90 is a GaN cap layer.
  • the thickness dimension of the protective layer 90 ranges from 30 nm to 100 nm (including 30 nm and 100 nm).
  • the semiconductor chip further includes an electron blocking layer 100, wherein the electron blocking layer 100 is stacked on the protective layer 90, and the P-type gallium nitride layer 40 is stacked on the electrons.
  • the blocking layer 100 so that the P-type gallium nitride layer 40 is stacked on the electron blocking layer 100 with the P-type gallium nitride layer 40, and the electron blocking layer 100 is stacked on the protective layer 90 and the protection.
  • the layer 90 is stacked on the quantum well layer 30 in a manner that the layer 90 is stacked on the quantum well layer 30.
  • the electron blocking layer 100 has a higher band gap, which can reduce electron leakage, increase radiation recombination rate, and enhance light efficiency.
  • the electron blocking layer 100 is a P-type AlGaN electron blocking layer, wherein the doping concentration of the electron blocking layer 100 is 1-10 ⁇ 10 18 cm ⁇ 3 .
  • the thickness of the electron blocking layer 100 ranges from 0.1 ⁇ m to 0.5 ⁇ m (including 0.1 ⁇ m and 0.5 ⁇ m).
  • the substrate 10, the buffer layer 70, the N-type gallium nitride layer 20, and the semiconductor chip of the present invention will be further described in combination with the growth process of the semiconductor chip.
  • the protective layer 90, the electron blocking layer 100, the P-type gallium nitride layer 40, the N-type electrode 50, and the P-type electrode 60 And the characteristics of the semiconductor chip of the present invention.
  • the buffer layer 70, the N-type gallium nitride layer 20, and the current spreading are sequentially grown from the substrate 10 under a reaction growth pressure range of 100torr-500torr (including 100torr and 500torr).
  • the layer 80, the quantum well layer 30, the protective layer 90, the electron blocking layer 100, the P-type gallium nitride layer 40, the N-type electrode 50, and the P-type electrode 60 are sequentially grown from the substrate 10 under a reaction growth pressure range of 100torr-500torr (including 100torr and 500torr).
  • the step of growing the semiconductor chip includes: S1, growing the buffer layer 70 from the substrate 10; S2, growing the N-type gallium nitride layer 20 from the buffer layer 70; S3, Growing the current extension layer 80 from the N-type gallium nitride layer 20; S4, growing the quantum well layer 30 from the current extension layer 80; S5, growing the protective layer 90 from the quantum well layer 30 S6, growing the electron blocking layer 100 from the protective layer 90; S7, growing the P-type gallium nitride layer 40 from the electron blocking layer 100; S8, growing the N from the current spreading layer 80 A type electrode 50 and the P type electrode 60 are grown from the P type gallium nitride layer 40.
  • step S1 the buffer layer 70 is grown from the substrate 10, as shown in FIG. 2. Specifically, first, the substrate 10 is placed in a metal-organic chemical vapor deposition (MOCVD) apparatus. Secondly, high-purity hydrogen (H2) is introduced when the cavity temperature of the metal-organic compound vapor-phase epitaxial deposition equipment is about 1100 ° C, and the duration of the high-purity hydrogen (H2) is in the range of 10 minutes to 15 minutes (including 10 minutes and 15 minutes). Third, when the temperature range of the cavity of the metal organic compound vapor phase epitaxial deposition device is reduced to 900 ° C. to 1000 ° C. (including 900 ° C. and 1000 ° C.), the buffer layer 70 is grown by passing in a Ga source and an N source. The substrate 10 is described so that the buffer layer 70 is stacked on the substrate 10.
  • MOCVD metal-organic chemical vapor deposition
  • the buffer layer 70 is an undoped gallium nitride buffer layer.
  • the thickness dimension of the buffer layer 70 ranges from 20 nm to 50 nm (including 20 nm and 50 nm).
  • the type of the substrate 10 is not limited in the semiconductor chip of the present invention.
  • the substrate 10 may be a sapphire substrate, an AIN substrate, a SiC substrate, and a Si substrate. .
  • step S2 the N-type GaN layer 20 is grown from the buffer layer 70, as shown in FIG. 3.
  • a Ga source, a nitrogen source, and a silane (SiH4) are passed in to
  • a silicon (Si) doped N-type gallium nitride layer 20 is grown from the buffer layer 70, so that the N-type gallium nitride layer 20 is stacked on the buffer layer 70, wherein a Ga source / nitrogen source ( NH3) is an essential element for growth, N2 is a carrier gas, and silane (SiH4) is a doping source.
  • a Ga source / nitrogen source NH3
  • N2 is a carrier gas
  • silane (SiH4) is a doping source.
  • the buffer layer 70 is grown on the substrate 10 and the N-type gallium nitride layer 20 is grown on the buffer layer 20, the buffer layer 70 is maintained at Between the substrate 10 and the N-type gallium nitride layer 20, in this way, the problem of lattice mismatch between the substrate 10 and the N-type gallium nitride layer 20 can be avoided, Therefore, it is beneficial to ensure the stability and reliability of the semiconductor chip.
  • the thickness dimension of the N-type gallium nitride layer 20 ranges from 3 ⁇ m to 6 ⁇ m (including 3 ⁇ m and 6 ⁇ m).
  • the silicon doping concentration of the N-type gallium nitride layer 20 is 1-10 ⁇ 10 18 cm ⁇ 3 .
  • the current spreading layer 80 is grown from the N-type gallium nitride layer 20, as shown in FIG. 4.
  • the metal-organic compound vapor-phase epitaxial deposition device is continuously passed through.
  • the nitrogen source grows the non-doped U-GaN layer on the N-GaN layer, and in this manner cyclically grows the N-GaN for 5 cycles to 30 cycles (including 5 cycles and 30 cycles).
  • Layer and the U-GaN layer to form the current spreading layer 80 In this way, the current spreading layer 80 can allow a more uniform current distribution.
  • the N-GaN layer of the current spreading layer 80 is a silicon-doped layer and the U-GaN layer is an undoped layer, the N-GaN layer of the current spreading layer 80
  • the U-GaN layer 32 and the U-GaN layer 32 have different resistances, so that the current spreading layer 80 can exhibit a resistance state of "low resistance-high resistance-low resistance-high resistance " in the thickness direction of the semiconductor chip.
  • the current spreading layer 80 causes the vertical resistance of the semiconductor chip to be increased, thereby weakening the vertical current spreading capability of the semiconductor chip, and on the other hand, the current spreading layer 80 makes the The lateral current expansion capability of the semiconductor chip is effectively improved, which is beneficial to the current being evenly distributed and the luminous efficiency of the semiconductor chip is improved, which greatly improves the optical performance and the service life of the semiconductor chip.
  • the thickness size of the N-GaN layer and the thickness size of the U-GaN layer of the current spreading layer 80 can affect the resistance of the N-GaN layer and the resistance of the U-GaN layer. Therefore, By adjusting the thickness size of the N-GaN layer and the thickness size of the U-GaN layer of the current spreading layer 80, the current can be more uniformly distributed to improve the light efficiency of the semiconductor chip.
  • step S4 the quantum well layer 30 is grown from the current extension layer 80, as shown in FIG. 5.
  • the cavity temperature of the metal-organic compound vapor-phase epitaxial deposition device is reduced to 800 ° -900 ° C (including 800 ° C and 900 ° C), and an In source, a Ga source, a nitrogen source, and a silane (SiH4)
  • the quantum barrier has a thickness size ranging from 5nm to 15nm (including 5nm and 15nm) ) Alx1Iny1Ga1-x1-y1N (0 ⁇ X1 ⁇ 1,0 ⁇ Y1 ⁇ 1) quantum barrier.
  • the pressure of the cavity of the metal organic compound vapor phase epitaxial deposition device is increased to grow the undoped quantum well from the quantum barrier, wherein the quantum well has a thickness size ranging from 2nm to 5nm (including 2nm and 5nm) Al x2 In y2 Ga 1-x2-y2 N (0 ⁇ X2 ⁇ 1,0 ⁇ Y2 ⁇ 1) quantum wells.
  • the quantum barrier is grown from the quantum barrier. According to such a rule, 3 cycles to 20 cycles are grown to form the quantum well layer 30.
  • the growth pressure of the quantum barrier of the quantum well layer 30 is lower than the growth pressure of the quantum well, and in this way, the atoms of the quantum barrier migrate It can be enhanced to promote the two-dimensional growth of the surface of the quantum barrier, which is conducive to improving the crystal quality of the well barrier interface of the quantum barrier and the quantum well, and thereby improving the light efficiency of the semiconductor chip.
  • the growth pressure of the quantum barrier of the quantum well layer 30 is lower than the growth pressure of the quantum well, and the process of growing the quantum barrier can promote the incorporation of a group III element, such as the In element. Therefore, when the semiconductor chip with blue-green light is grown, more light-emitting quantum dots can be provided to improve the light efficiency of the semiconductor chip.
  • the growth pressure of the quantum well is 200torr-300torr (including 200torr and 300torr), and the growth pressure of the quantum barrier is lower than the growth pressure of the well region, such as The growth pressure of the quantum barrier is lower than the growth pressure of the quantum well by an interval of 5 torr-10 torr.
  • the growth pressure of the quantum barrier may be 190 torr-195 torr.
  • the growth pressure of the quantum barrier of the quantum well layer 30 is lower than the growth pressure of the quantum well by an interval of 5torr-10torr as an example.
  • the content and scope of the semiconductor chip used for exposing and explaining the present invention should not be considered as limiting the content and scope of the present invention.
  • a transmission electron microscope (TEM) / X-ray powder diffraction meter (XRD) may be used.
  • TEM transmission electron microscope
  • XRD X-ray powder diffraction meter
  • the structure and growth method of the quantum well layer 30 of the semiconductor chip of the present invention are applicable to the semiconductor chip of the full color system, for example, the structure and growth method of the quantum well layer 30 are suitable for InGaN-based blue-green light and AlGaN-based ultraviolet light.
  • the protective layer 90 is grown from the quantum well layer 30, as shown in FIG. 6. Specifically, after the internal temperature range of the metal organic compound vapor phase epitaxial deposition apparatus is reduced to 700 ° C. to 800 ° C. (including 700 ° C. and 800 ° C.), a Ga source is passed into the metal organic compound vapor phase epitaxial deposition apparatus. And a nitrogen source to grow the protective layer 90 on the quantum well layer 30, so that the protective layer 90 is stacked on the quantum well layer 30. That is, the protective layer 90 is the low-temperature GaN cap layer laminated on the quantum well layer 30.
  • the thickness of the protective layer 90 ranges from 30 nm to 100 nm (including 30 nm and 100 nm).
  • step S6 the electron blocking layer 100 is grown from the protective layer 90, as shown in FIG. 7. Specifically, after the internal temperature range of the metal organic compound vapor phase epitaxial deposition device is raised to 900 ° C-1000 ° C (including 900 ° C and 1000 ° C), an Al source, a Ga source, a nitrogen source, and a Mg source are passed in
  • the magnesium-doped AlGaN electron blocking layer 100 has a doping concentration of 1-10 ⁇ 10 18 cm ⁇ 3 , wherein an Al source, a Ga source, and a nitrogen source are growth sources, and a Mg source is a doping source.
  • the thickness of the electron blocking layer 100 ranges from 0.1 ⁇ m to 0.5 ⁇ m (including 0.1 ⁇ m and 0.5 ⁇ m).
  • step S7 the P-type GaN layer 40 is grown from the electron blocking layer 100, as shown in FIG. 8.
  • a Ga source, a nitrogen source, and a silane (SiH4) are passed into the metal organic compound vapor phase epitaxial deposition apparatus to grow a silicon-doped P-type gallium nitride layer 40 on the electron blocking layer 100.
  • the Ga source and nitrogen source are growth sources, and silane (SiH4) is a doping source.
  • the thickness of the P-type GaN layer 50 ranges from 100 nm to 200 nm (including 100 nm and 200 nm).
  • the doping concentration of the P-type GaN layer 50 is 5-10 ⁇ 10 18 cm ⁇ 3 .
  • the growing step further includes the step S8, growing the N-type electrode 50 from the current spreading layer 80 and growing the P from the P-type gallium nitride layer 40.
  • Type electrode 60 refer to FIG.
  • the present invention further provides a method for manufacturing a semiconductor chip, wherein the manufacturing method includes the following steps:
  • the N-type electrode 50 is electrically connected to the N-type gallium nitride layer 20 and the P-type electrode 60 is electrically connected to the P-type gallium nitride layer 40 to obtain the semiconductor chip.
  • the cycle period for growing the quantum barrier and the quantum well is 3 cycles to 20 cycles.
  • the growth pressure of the quantum barrier is lower than the growth pressure of the quantum well.
  • the method further includes the steps:
  • the "lamination" involved in the present invention may be a direct lamination or an indirect lamination.
  • stacking the N-type gallium nitride layer 20 on the substrate 10 may mean that the N-type gallium nitride layer 20 is indirectly stacked on the substrate 10, that is, on the N-type gallium nitride
  • Other layers may be provided between the layer 20 and the substrate 10.
  • the substrate 10 the buffer layer 70, the N-type gallium nitride layer 20, the current spreading layer 80, The thicknesses of the quantum well layer 30, the protective layer 90, the electron blocking layer 100, the N-type electrode 50, and the P-type electrode 60 are merely examples, and they do not represent the substrate 10, the The buffer layer 70, the N-type gallium nitride layer 20, the current spreading layer 80, the quantum well layer 30, the protective layer 90, the electron blocking layer 100, the N-type electrode 50, and The true thickness of the P-type electrode 60 will be described.
  • the substrate 10 the buffer layer 70, the N-type gallium nitride layer 20, the current spreading layer 80, the quantum well layer 30, the protective layer 90, and the electron blocking layer 100
  • the true ratio between the N-type electrode 50 and the P-type electrode 60 is not as shown in the drawings.

Abstract

一发光二极管的半导体芯片及其量子阱层和制造方法，其中所述半导体芯片包括一衬底（10）和依次层叠于所述衬底（10）的一N型氮化镓层（20）、一量子阱层（30）和一P型氮化镓层（40）以及被电连接于所述N型氮化镓层（20）的一N型电极（50）和被电连接于所述P型氮化镓层（40）的一P型电极（60），其中所述量子阱层（30）包括依次层叠的至少一量子垒和至少一量子阱，所述量子垒和所述量子阱的生长压力不同，通过这样的方式，能够改善所述量子阱和所述量子垒的阱垒界面的晶体质量，以提高所述发光二极管的光效。

Description

发光二极管的半导体芯片及其量子阱层和制造方法 技术领域
本发明涉及发光二极管，特别涉及一发光二极管的半导体芯片及其量子阱层和制造方法。
背景技术
近年来，随着LED(Light Emitting Diode)被大规模的推广和应用，LED相关技术也得到了突飞猛进式的发展。而III-V族氮化物作为直接带隙半导体，其具有禁带宽度大、击穿电场高、电子饱和迁移率高等优异的物理特征，在LED领域的应用受到了广泛的关注。尤其是以AlInGaN基为主要原料半导体芯片由于其卓越的器件性能和广泛的应用前景而受到越来越多的关注，由于半导体芯片的几乎全部光源均来自于半导体芯片的多量子阱层，因此，量子阱层的结构、阱垒之间的晶体质量、阱垒之间的突变设计尤其为半导体芯片的设计人员所重视，即，量子阱层的设计是整个半导体芯片的设计关键。因为半导体芯片的量子阱层的阱垒之间的不同的材料组成和生长条件的差异，必然会导致阱垒晶体之间的差异，进而影响整个器件的发光效率和光学性能。然而，在实际生产过程中，半导体芯片的量子阱层的阱垒采用同样的压力生长，例如蓝绿光的半导体芯片，量子阱层的量子阱是主要的发光层，其材料一般为InGaN，若量子阱层的量子阱的生长压力过低，则In元素的并入效率会增加，但同时波长一致性、均匀性均遭到破坏，表现为半宽增大、边带发光等，影响发光稳定性，若量子阱层的量子阱的生长压力太高，则影响原子迁移速率，使得量子阱趋向于三维生长，进而引起量子阱的表面粗糙化而影响晶体质量，因此，在现有的生长工艺中，量子阱层的量子阱的生长采用稳压生长，但是因为量子阱层的量子阱和量子垒的材料组成不同，导致相同压力下生长的量子阱和量子垒的阱垒界面的晶体质量较差。
发明内容
本发明的一个目的在于提供一发光二极管的半导体芯片及其量子阱层和制造方法，其中所述量子阱层的量子阱和量子垒的阱垒界面的晶体质量能够得到大幅度的改善，以提升所述半导体芯片的光效。
本发明的一个目的在于提供一发光二极管的半导体芯片及其量子阱层和制造方法，其中所述量子阱层的所述量子阱和所述量子垒的生长压力不同，以改善所述量子阱层的所述量子阱和所述量子垒的阱垒界面的晶体质量。
本发明的一个目的在于提供一发光二极管的半导体芯片及其量子阱层和制造方法，其中所述量子阱层的所述量子垒的生长压力低于所述量子阱的生长压力，以改善所述量子阱和所述量子垒的阱垒界面的晶体质量。
本发明的一个目的在于提供一发光二极管的半导体芯片及其量子阱层和制造方法，其中所述量子阱层的所述量子垒的生长压力低于所述量子阱的生长压力，通过这样的方式，所述 量子垒的原子迁移能够被增强，以促进所述量子垒的表面二维生长，从而有利于提升所述量子垒和所述量子阱的阱垒界面的晶体质量。
本发明的一个目的在于提供一发光二极管的半导体芯片及其量子阱层和制造方法，其中所述量子阱层的所述量子垒的生长压力低于所述量子阱的生长压力，以促进III族元素的并入，例如，通过使所述量子垒的生长压力低于所述量子阱的生长压力的方式能够促进In元素并入所述量子垒，这样在生长蓝绿光的所述半导体芯片时，能够提供更多的发光量子点，以提升所述半导体芯片的光效。
本发明的一个目的在于提供一发光二极管的半导体芯片及其量子阱层和制造方法，其中所述半导体芯片提供一电流扩展层，其中所述电流扩展层能够使电流在所述半导体芯片均匀地扩展，从而提高所述半导体芯片的光效。
本发明的一个目的在于提供一发光二极管的半导体芯片及其量子阱层和制造方法，其中所述电流扩展层能够削弱所述半导体芯片的纵向电流扩展能力和提高所述半导体芯片的横向电流扩展能力，从而使得电流在所述半导体芯片均匀地扩展。
本发明的一个目的在于提供一发光二极管的半导体芯片及其量子阱层和制造方法，其中在所述半导体芯片的高度方向，所述电流扩展层的电阻状态呈现出“低阻-高阻-低阻-高阻……”的电阻状态，以削弱所述半导体芯片的纵向电流扩展能力和提高所述半导体芯片的横向电流扩展能力。
依本发明的一个方面，本发明提供一发光二极管的半导体芯片，其包括：
一衬底；
一N型氮化镓层，其中所述N型氮化镓层层叠于所述衬底；
一量子阱层，其中所述量子阱层层叠于所述N型氮化镓层，其中所述量子阱层包括依次层叠的至少一量子垒和至少一量子阱，所述量子垒和所述量子阱的生长压力不同；
一P型氮化镓层，其中所述P型氮化镓层层叠于所述量子阱层；
一N型电极，其中所述N型电极被电连接于所述N型氮化镓层；以及
一P型电极，其中所述P型电极被电连接于所述P型氮化镓层。
根据本发明的一个实施例，所述量子阱层的所述量子垒的生长压力低于所述量子阱的生长压力。
根据本发明的一个实施例，所述量子阱层的所述量子垒的层数参数和所述量子阱的层数参数均为N，其中参数N的取值范围为：3≤N≤20。
根据本发明的一个实施例，所述量子阱层的所述量子垒是Alx1Iny1Ga1-x1-y1N(0<X1<1,0<Y1<1)掺杂量子垒，掺杂浓度为1-5x10 18cm -3，其中所述量子阱层的所述量子阱是Alx2Iny2Ga1-x2-y2N(0<X2<1,0<Y2<1)未掺杂量子阱。
根据本发明的一个实施例，所述量子阱的所述量子垒的厚度尺寸范围为5nm-15nm，所述量子阱的厚度尺寸范围为2nm-5nm。
根据本发明的一个实施例，所述半导体芯片进一步包括一缓冲层，其中所述缓冲层层叠于所述衬底，所述N型氮化镓层层叠于所述缓冲层。
根据本发明的一个实施例，所述缓冲层为GaN缓冲层或者AlN缓冲层。
根据本发明的一个实施例，所述半导体芯片进一步包括一电流扩展层，其中所述电流扩 展层层叠于所述N型氮化镓层，所述量子阱层层叠于所述电流扩展层。
根据本发明的一个实施例，所述电流扩展层是N型电流扩展层；或者所述电流扩展层是AlGaN型电流扩展层；或者所述电流扩展层是InGaN电流扩展层。
根据本发明的一个实施例，所述半导体芯片进一步包括一保护层，其中所述保护层层叠于所述量子阱层，所述P型氮化镓层层叠于所述保护层。
根据本发明的一个实施例，所述半导体芯片进一步包括一电子阻挡层，其中所述电子阻挡层层叠于所述保护层，所述P型氮化镓层层叠于所述电子阻挡层。
根据本发明的一个实施例，所述N型电极层叠于所述电流扩展层，所述P型电极层叠于所述P型氮化镓层。
依本发明的另一个方面，本发明进一步提供一量子阱层，其应用于一半导体芯片，其中所述量子阱层包括依次层叠的至少一量子垒和至少一量子阱，所述量子垒和所述量子阱的生长压力不同。
根据本发明的一个实施例，所述量子阱层的所述量子垒的生长压力低于所述量子阱的生长压力。
根据本发明的一个实施例，所述量子阱层的所述量子垒的层数参数和所述量子阱的层数参数均为N，其中参数N的取值范围为：3≤N≤20。
根据本发明的一个实施例，所述量子阱层的所述量子垒是Alx1Iny1Ga1-x1-y1N(0<X1<1,0<Y1<1)掺杂量子垒，掺杂浓度为1-5x10 18cm -3，其中所述量子阱层的所述量子阱是Alx2Iny2Ga1-x2-y2N(0<X2<1,0<Y2<1)未掺杂量子阱。
根据本发明的一个实施例，所述量子阱的所述量子垒的厚度尺寸范围为5nm-15nm，所述量子阱的厚度尺寸范围为2nm-5nm。
依本发明的另一个方面，本发明进一步提供一发光二极管的半导体芯片的制造方法，其中所述制造方法包括如下步骤：
(a)层叠一N型氮化镓层于一衬底；
(b)自所述N型氮化镓层循环生长一量子垒和一量子阱，以藉由多个所述量子垒和多个所述量子阱形成层叠于所述N型氮化镓层的一量子阱层，其中所述量子垒的生长压力和所述量子阱的生长压力不同；
(c)层叠一P型氮化镓层于所述量子阱层；以及
(d)电连接一N型电极于所述N型氮化镓层和电连接一P型电极于所述P型氮化镓层，以制得所述半导体芯片。
根据本发明的一个实施例，生长所述量子垒和所述量子阱的循环周期为3个周期至20个周期。
根据本发明的一个实施例，所述量子垒的生长压力低于所述量子阱的生长压力。
根据本发明的一个实施例，所述量子垒的生长压力低于所述量子阱的生长压力。
根据本发明的一个实施例，在所述步骤(b)中，进一步包括步骤：
(b.1)保持层叠有所述N型氮化镓层的所述衬底于一金属有机化合物气相外延沉积设备；
(b.2)通入In源、Ga源、氮源和硅烷于所述金属有机化合物气相外延沉积设备生长 掺杂的Alx1Iny1Ga1-x1-y1N(0<X1<1,0<Y1<1)量子垒，以形成层叠于所述N型氮化镓层的所述量子垒；
(b.3)降低所述金属有机化合物气相外延沉积设备的压力，通入In源、Ga源和氮源于所述金属有机化合物气相外延沉积设备生长未掺杂的Alx2Iny2Ga1-x2-y2N(0<X2<1,0<Y2<1)量子阱，以形成层叠于所述量子垒的所述量子阱；以及
(b.4)循环所述步骤(b.2)和所述步骤(b.3)，以层叠所述量子阱层于所述N型氮化镓层。
根据本发明的一个实施例，所述量子阱层的所述量子垒的掺杂浓度为1-5x10 18cm -3。
根据本发明的一个实施例，所述量子阱层的所述量子垒的厚度尺寸范围为5nm-15nm，所述量子阱的厚度尺寸范围为2nm-5nm。
根据本发明的一个实施例，在所述步骤(a)之前，所述制造方法进一步包括步骤：自所述衬底生长一缓冲层，从而在所述步骤(a)中，所述N型氮化镓层生长于所述缓冲层。
根据本发明的一个实施例，在所述步骤(b)之前，所述制造方法进一步包括步骤：自所述N型氮化镓层生长一电流扩展层，从而在所述步骤(b)中，所述量子阱层生长于所述电流扩展层。
根据本发明的一个实施例，在所述步骤(c)之前，进一步包括步骤：自所述量子阱层生长一保护层和自所述保护层生长一电子阻挡层，从而在所述步骤(c)中，所述P型氮化镓层生长于所述电子阻挡层。
附图说明
图1是依本发明的一较佳实施例的一半导体芯片的制造步骤之一的剖视示意图。
图2是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之二的剖视示意图。
图3是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之三的剖视示意图。
图4是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之四的剖视示意图。
图5是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之五的剖视示意图。
图6是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之六的剖视示意图。
图7是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之七的剖视示意图。
图8是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之八的剖视示意图。
图9是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之九的剖视示意图，其示意了所述半导体芯片的剖视状态。
具体实施方式
以下描述用于揭露本发明以使本领域技术人员能够实现本发明。以下描述中的优选实施例只作为举例，本领域技术人员可以想到其他显而易见的变型。在以下描述中界定的本发明的基本原理可以应用于其他实施方案、变形方案、改进方案、等同方案以及没有背离本发明的精神和范围的其他技术方案。
本领域技术人员应理解的是，在本发明的揭露中，术语“纵向”、“横向”、“上”、 “下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系是基于附图所示的方位或位置关系，其仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此上述术语不能理解为对本发明的限制。
可以理解的是，术语“一”应理解为“至少一”或“一个或多个”，即在一个实施例中，一个元件的数量可以为一个，而在另外的实施例中，该元件的数量可以为多个，术语“一”不能理解为对数量的限制。
参考本发明的说明书附图之附图1至图9，依本发明的一较佳实施例的一发光二极管的半导体芯片在接下来的描述中被揭露和被阐述，其中所述半导体芯片包括一衬底10、一N型氮化镓层20、一量子阱层30、一P型氮化镓层40、一N型电极50以及一P型电极60，其中所述N型氮化镓层20层叠于所述衬底10，所述量子阱层30层叠于所述N型氮化镓层20，所述P型氮化镓层40层叠于所述量子阱层30，所述N型电极50被电连接于所述N型氮化镓层20，所述P型电极60被电连接于所述P型氮化镓层40。当所述半导体芯片的所述N型电极50和所述P型电极60分别被加入电源时，自所述N型电极50被注入所述半导体芯片的电流能够经所述N型氮化镓层20进入所述量子阱层30和自所述P型电极60被注入所述半导体芯片的电流能过经所述P型氮化镓层40进入所述量子阱层30而在所述量子阱层30复合发光。
具体地说，所述量子阱层30包括依次层叠的至少一量子阱和至少一量子垒，其中所述量子阱层30的所述量子阱和所述量子垒的阱垒界面的晶体质量能够得到大幅度的改善，以提升所述半导体芯片的光效。更具体地说，所述量子阱层30的所述量子阱和所述量子垒的数量均是N个，即，在制造所述半导体芯片的过程中，生长N个周期的所述量子阱和所述量子垒以形成所述量子阱层30，从而使得所述量子阱层30的第一个所述量子垒层叠于所述N型氮化镓层20，所述量子阱层30的第一个所述量子阱层叠于第一个所述量子垒，所述量子阱层30的第二个所述量子垒层叠于第一个所述量子阱，所述量子阱层30的第二个所述量子阱层叠于第二个所述量子垒……所述量子阱层30的第N个所述量子垒层叠于第N-1个所述量子阱，所述量子阱层30的第N个所述量子阱层叠于第N个所述量子垒，其中相邻的所述量子阱和所述量子垒的阱垒界面的晶体质量能够被大幅度地改善，以此来提升所述半导体芯片的光效。例如，所述量子阱层30的所述量子阱和所述量子垒的阱垒界面的晶体质量的一致性能够被提升，从而改善所述量子阱和所述量子垒的阱垒界面的晶体质量。
在附图1至图9示出的所述半导体芯片的这个较佳示例中，参数N的取值范围为：3≤N≤20，即，所述半导体芯片的所述量子阱层30包括3个周期至20个周期(包括3个周期和20个周期)的所述量子垒和所述量子阱。换言之，所述半导体芯片的所述量子阱层30的所述量子垒的层数和所述量子阱的层数均为3层至20层(包括3层和20层)。
在本发明的所述半导体芯片的这个较佳示例中，所述量子阱层30的所述量子垒和所述量子阱的生长压力不同，其根据所述量子垒和所述量子阱的材料来选择适合的压力，通过这样的方式，所述量子阱层30的所述量子垒和所述量子阱的阱垒界面的晶体质量能够被大幅度地改善，以提升所述半导体芯片的光效。
具体地说，在本发明的所述半导体芯片的一个较佳示例中，所述量子阱层30的所述量 子垒的生长压力低于所述量子阱的生长压力，以改善所述量子垒和所述量子阱的阱垒界面的晶体质量。在生长所述量子阱层30的过程中，在压力较低的生长环境中生长所述量子阱层30的所述量子垒时，所述量子垒的原子迁移能够被增强，以促进所述量子垒的表面二维生长，从而有利于提升所述量子垒和所述量子阱的阱垒界面的晶体质量。
优选地，所述半导体芯片的所述N型氮化镓层20是硅(Si)掺杂氮化镓层，其中所述N型氮化镓层20的硅掺杂浓度为1-10x10 18cm -3。更优选地，所述半导体芯片的所述N型氮化镓层20的厚度尺寸范围为3μm-6μm(包括3μm和6μm)。
优选地，所述半导体芯片的所述P型氮化镓层40是掺杂氮化镓层，其中所述P型氮化镓层40的掺杂浓度为5-10x10 18cm -3。更优选地，所述半导体芯片的所述P型氮化镓层40的厚度尺寸范围为100nm-200nm(包括100nm和200nm)。
另外，所述N型电极50的材料为Ti(钛)或Al(铝)。相应地，所述P型电极60的材料为Ni(镍)或Au(金)。
继续参考附图1至图9，所述半导体芯片进一步包括一缓冲层70，其中所述缓冲层70层叠于所述衬底10，所述N型氮化镓层20层叠于所述缓冲层70，从而所述N型氮化镓层20以所述N型氮化镓层20层叠于所述缓冲层70和所述缓冲层70层叠于所述衬底10的方式层叠于所述衬底10。在所述半导体芯片中，所述缓冲层70能够以被保持在所述N型氮化镓层20和所述衬底10之间的方式避免晶格失配的问题，从而有利于保证所述半导体芯片的稳定性和可靠性。
在本发明的所述半导体芯片的一个较佳示例中，所述缓冲层70是氮化镓缓冲层，例如，所述缓冲层70可以是但不限于未掺杂氮化镓缓冲层。当所述缓冲层70为未掺杂氮化镓缓冲层时，所述缓冲层70的厚度尺寸范围为20nm-50nm(包括20nm和50nm)。可选地，在本发明的所述半导体芯片的其他较佳示例中，所述缓冲层70是AlN缓冲层。
继续参考附图1至图9，所述半导体芯片进一步包括一电流扩展层80，其中所述电流扩展层80层叠于所述N型氮化镓层20，所述量子阱层30层叠于所述电流扩展层80，从而所述量子阱层30以所述量子阱层30层叠于所述电流扩展层80和所述电流扩展层80层叠于所述N型氮化镓层20的方式层叠于所述N型氮化镓层20。所述N型电极50以所述N型电极50被电连接于所述电流扩展层80和所述电流扩展层80被电连接于所述N型氮化镓层20的方式被电连接于所述N型氮化镓层20，从而通过所述N型电极50被注入的电流能够在被所述电流扩展层80扩展后经所述N型氮化镓层20进入所述量子阱层30。
在本发明的所述半导体芯片的一个较佳示例中，所述电流扩展层80是N型电流扩展层。可选地，在本发明的所述半导体芯片的另一个较佳示例中，所述电流扩展层80是AlGaN电流扩展层或InGaN电流扩展层。
进一步地，当所述电流扩展层80是N型电流扩展层时，所述电流扩展层80包括至少一N-GaN层和至少一U-GaN层，其中所述N-GaN层和所述U-GaN层相互层叠，以使所述电流扩展层80在高度方向能够呈现出“低阻-高阻-低阻-高阻……”的电阻状态，通过这样的方式，一方面，所述电流扩展层80使得所述半导体芯片的纵向电阻被增加，从而削弱所述半导体芯片的纵向电流扩展能力，另一方面，所述电流扩展层80使得所述半导体芯片的横向电流扩展能力被有效地提升，从而有利于电流被均匀地分布和提高发光效率，这对于所 述半导体芯片的光学性能和使用寿命均有较大程度的改善。
继续参考附图1至图9，所述半导体芯片进一步包括一保护层90，其中所述保护层90层叠于所述量子阱层30，以维持所述量子阱层30的晶体质量，从而避免在后续的生长过程中对所述量子阱层30的组分、结构的破坏。优选地，所述保护层90是GaN帽层。优选地，所述保护层90的厚度尺寸范围为30nm至100nm(包括30nm和100nm)。
继续参考附图1至图9，所述半导体芯片进一步包括一电子阻挡层100，其中所述电子阻挡层100层叠于所述保护层90，所述P型氮化镓层40层叠于所述电子阻挡层100，从而所述P型氮化镓层40以所述P型氮化镓层40层叠于所述电子阻挡层100、所述电子阻挡层100层叠于所述保护层90和所述保护层90层叠于所述量子阱层30的方式层叠于所述量子阱层30。所述电子阻挡层100具有较高的带隙，能够减少电子泄漏，增加辐射复合速率，增强光效
优选地，所述电子阻挡层100是P型AlGaN电子阻挡层，其中所述电子阻挡层100的掺杂浓度为1-10x10 18cm -3。优选地，所述电子阻挡层100的厚度尺寸范围为0.1μm-0.5μm(包括0.1μm和0.5μm)。
在接下来的描述中，将结合所述半导体芯片的生长过程进一步描述本发明的所述半导体芯片的所述衬底10、所述缓冲层70、所述N型氮化镓层20、所述电流扩展层80、所述量子阱层30、所述保护层90、所述电子阻挡层100、所述P型氮化镓层40、所述N型电极50和所述P型电极60之间的相互关系和本发明的所述半导体芯片的特征。
具体地说，在反应生长压力范围为100torr-500torr(包括100torr和500torr)的条件下自所述衬底10依次生长所述缓冲层70、所述N型氮化镓层20、所述电流扩展层80、所述量子阱层30、所述保护层90、所述电子阻挡层100、所述P型氮化镓层40、所述N型电极50和所述P型电极60。更具体地说，所述半导体芯片的生长步骤包括：S1，自所述衬底10生长所述缓冲层70；S2，自所述缓冲层70生长所述N型氮化镓层20；S3，自所述N型氮化镓层20生长所述电流扩展层80；S4，自所述电流扩展层80生长所述量子阱层30；S5，自所述量子阱层30生长所述保护层90；S6，自所述保护层90生长所述电子阻挡层100；S7，自所述电子阻挡层100生长所述P型氮化镓层40；S8，自所述电流扩展层80生长所述N型电极50和自所述P型氮化镓层40生长所述P型电极60。
下面，将对根据本发明的所述半导体芯片的上述较佳实施例的各个生长步骤进行详细说明。
在步骤S1，自所述衬底10生长所述缓冲层70，参考附图2。具体地说，首先，将所述衬底10放入一金属有机化合物气相外延沉淀设备(Metal-organic Chemical Vapor Deposition，MOCVD)。其次，在所述金属有机化合物气相外延沉积设备的腔体温度为1100℃左右时通入高纯氢气(H2)，其中通入高纯氢气(H2)的时长范围为10分钟-15分钟(包括10分钟和15分钟)。第三，在所述金属有机化合物气相外延沉积设备的腔体温度范围被降低至900℃-1000℃(包括900℃和1000℃)时通入Ga源和N源生长所述缓冲层70于所述衬底10，以使所述缓冲层70层叠于所述衬底10。
优选地，所述缓冲层70是非掺杂氮化镓缓冲层。优选地，所述缓冲层70的厚度尺寸范围为20nm-50nm(包括20nm和50nm)。
值得一提的是，所述衬底10的类型在本发明的所述半导体芯片中不受限制，例如，所述衬底10可以是蓝宝石衬底、AIN衬底、SiC衬底和Si衬底。
接着，在步骤S2中，自所述缓冲层70生长所述N型氮化镓层20，参考附图3。具体地说，在所述金属有机化合物气相外延沉积设备的腔体温度被升高至1100℃-1200℃(包括1100℃和1200℃)时通入Ga源、氮源和硅烷(SiH4)，以自所述缓冲层70生长硅(Si)掺杂的所述N型氮化镓层20，从而使所述N型氮化镓层20层叠于所述缓冲层70，其中Ga源/氮源(NH3)为生长必要元素，N2为载气，硅烷(SiH4)为掺杂源。
本领域技术人员应当理解的是，因为所述缓冲层70生长于所述衬底10和所述N型氮化镓层20生长于所述缓冲层20，因此，所述缓冲层70被保持在所述衬底10和所述N型氮化镓层20之间，通过这样的方式，能够避免所述衬底10和所述N型氮化镓层20之间的晶格失配的问题，从而有利于保证所述半导体芯片的稳定性和可靠性。
优选地，所述N型氮化镓层20的厚度尺寸范围为3μm-6μm(包括3μm和6μm)。优选地，所述N型氮化镓层20的硅掺杂浓度为1-10x10 18cm -3。
接着，在所述步骤S3中，自所述N型氮化镓层20生长所述电流扩展层80，参考附图4。例如，在本发明的所述半导体芯片的一个较佳示例中，在所述N型氮化镓层20生长于所述缓冲层70中之后，继续向所述金属有机化合物气相外延沉积设备通入Ga源、氮源和硅烷(SiH4)，以自所述N型氮化镓层20生长硅掺杂的所述N-GaN层，然后向所述金属有机化合物气相外延沉积设备通入Ga源和氮源以生长非掺杂的所述U-GaN层于所述N-GaN层，以此方式循环生长5个周期-30个周期(包括5个周期和30个周期)的所述N-GaN层和所述U-GaN层以形成所述电流扩展层80，通过这样的方式，所述电流扩展层80能够允许电流更均匀地分布。
具体地说，因为所述电流扩展层80的N-GaN层为硅掺杂层，而所述U-GaN层为非掺杂层，因此，所述电流扩展层80的所述N-GaN层和所述U-GaN层32具有不同的电阻，从而使得所述电流扩展层80在所述半导体芯片的厚度方向能够呈现出“低阻-高阻-低阻-高阻……”的电阻状态，通过这样的方式，一方面，所述电流扩展层80使得所述半导体芯片的纵向电阻被增加，从而削弱所述半导体芯片的纵向电流扩展能力，另一方面，所述电流扩展层80使得所述半导体芯片的横向电流扩展能力被有效地提升，从而有利于电流被均匀地分布和提高所述半导体芯片的发光效率，这对于所述半导体芯片的光学性能和使用寿命均有较大程度的改善。另外，所述电流扩展层80的所述N-GaN层的厚度尺寸和所述U-GaN层的厚度尺寸能够影响所述N-GaN层的电阻和所述U-GaN层的电阻，因此，通过调整所述电流扩展层80的所述N-GaN层的厚度尺寸和所述U-GaN层的厚度尺寸能够使电流更均匀地分布，以提高所述半导体芯片的光效。
接着，在所述步骤S4，自所述电流扩展层80生长所述量子阱层30，参考附图5。具体地说，首先，将所述金属有机化合物气相外延沉积设备的腔体温降低至800℃-900℃(包括800℃和900℃)，通入In源、Ga源、氮源和硅烷(SiH4)，以自所述电流扩展层80生长所述量子垒，其中所述量子垒的掺杂浓度为1-5x10 18cm-3，所述量子垒是厚度尺寸范围为5nm-15nm(包括5nm和15nm)的Alx1Iny1Ga1-x1-y1N(0<X1<1,0<Y1<1)量子垒。其次，升高所述金属有机化合物气相外延沉积设备的腔体的压力，以自所述量子垒生长未掺杂的所述量 子阱，其中所述量子阱是厚度尺寸范围为2nm-5nm(包括2nm和5nm)的Al x2In y2Ga 1-x2-y2N(0<X2<1,0<Y2<1)量子阱。按照上述方式在降低所述金属有机化合物气相外延沉积设备的腔体的压力后自所述量子阱生长所述量子垒，和在升高所述金属有机化合物气相外延沉积设备的腔体的压力后自所述量子垒生长所述量子阱。按照如此规律生长3个周期至20个周期以形成所述量子阱层30。
也就是说，在本发明的所述半导体芯片中，所述量子阱层30的所述量子垒的生长压力低于所述量子阱的生长压力，通过这样的方式，所述量子垒的原子迁移能够被增强，以促进所述量子垒的表面二维生长，从而有利于提升所述量子垒和所述量子阱的阱垒界面的晶体质量，进而提高所述半导体芯片的光效。并且，所述量子阱层30的所述量子垒的生长压力低于所述量子阱的生长压力的生长方式，在生长所述量子垒的过程中能够促进III族元素的并入，例如In元素，从而在生长蓝绿光的所述半导体芯片时，能够提供更多的发光量子点，以提升所述半导体芯片的光效。
例如，在AlInGaN的所述量子阱层30中，所述量子阱的生长压力为200torr-300torr(包括200torr和300torr)，所述量子垒的生长压力低于所述阱区的生长压力，例如所述量子垒的生长压力比所述量子阱的生长压力低5torr-10torr的间隔量。例如，当所述量子阱的生长压力为200torr时，所述量子垒的生长压力可以是190torr-195torr。当然，本领域技术人员应当理解的是，本发明的说明书中以所述量子阱层30的所述量子垒的生长压力比所述量子阱的生长压力低5torr-10torr的间隔量为例，以用于揭露和阐述本发明的所述半导体芯片的内容和范围，其并不应当被视为是对本发明的内容和范围的限制。例如，在选择所述量子阱层30的所述量子阱和所述量子垒的生长压力时，可以采用透射电子显微镜(Transmission Electron Microscope，TEM)/X射线衍射仪(X-ray Powder diffractometer，XRD)判断所述量子阱和所述量子垒的阱垒界面的晶体质量或者同等条件下所述半导体芯片的发光效率的方式来确定所述量子阱和所述量子垒的合适的生长压力。
值得一提的是，本发明的所述半导体芯片的所述量子阱层30的结构和生长方式适用于全色系的所述半导体芯片，例如所述量子阱层30的结构和生长方式适用于以InGaN为主的蓝绿光和以AlGaN为主的紫外光。
接着，在所述步骤S5，自所述量子阱层30生长所述保护层90，参考附图6。具体地说，在所述金属有机化合物气相外延沉积设备的内部温度范围被降低至700℃-800℃(包括700℃和800℃)之后，向所述金属有机化合物气相外延沉积设备通入Ga源和氮源，以生长所述保护层90于所述量子阱层30，以使所述保护层90层叠于所述量子阱层30。也就是说，所述保护层90是层叠于所述量子阱层30的所述低温GaN帽层。优选地，所述保护层90的厚度尺寸范围为30nm-100nm(包括30nm和100nm)。通过生长所述保护层90于所述量子阱层30的方式，能够在后续的生长过程中维持所述量子阱层30的晶体质量，避免后续的高温生长对所述量子阱层30的组分和/或结构的破坏。
接着，在步骤S6，自所述保护层90生长所述电子阻挡层100，参考附图7。具体地说，在所述金属有机化合物气相外延沉积设备的内部温度范围被升高至900℃-1000℃(包括900℃和1000℃)后，通入Al源、Ga源、氮源和Mg源，生长镁掺杂的AlGaN的所述电子阻挡层100，其中掺杂浓度为1-10x10 18cm -3，其中Al源、Ga源和氮源为生长源，Mg源为 掺杂源。优选地，所述电子阻挡层100的厚度尺寸范围为0.1μm-0.5μm(包括0.1μm和0.5μm)。
接着，在步骤S7，自所述电子阻挡层100生长所述P型氮化镓层40，参考附图8。具体地说，向所述金属有机化合物气相外延沉积设备通入Ga源、氮源和硅烷(SiH4)，以生长硅掺杂的所述P型氮化镓层40于所述电子阻挡层100，其中Ga源和氮源为生长源，硅烷(SiH4)为掺杂源。
优选地，所述P型氮化镓层50的厚度尺寸范围为100nm-200nm(包括100nm和200nm)。优选地，所述P型氮化镓层50的掺杂浓度为5-10x10 18cm -3。
另外，在800℃-900℃(包括800℃和900℃)温度范围于氮气(N2)氛围下退火20分钟-30分钟(包括20分钟和30分钟)，以完成所述半导体芯片的生长。值得一提的是，在退火之前，所述生长步骤还包括所述步骤S8，自所述电流扩展层80生长所述N型电极50和自所述P型氮化镓层40生长所述P型电极60，参考附图9。
依本发明的另一个方面，本发明进一步提供一半导体芯片的制造方法，其中所述制造方法包括如下步骤：
(a)层叠所述N型氮化镓层20于所述衬底10；
(b)自所述N型氮化镓层20循环生长所述量子垒和所述量子阱，以藉由多个所述量子垒和多个所述量子阱形成层叠于所述N型氮化镓层20的所述量子阱层30，其中所述量子垒的生长压力和所述量子阱的生长压力不同；
(c)层叠所述P型氮化镓层40于所述量子阱层30；以及
(d)电连接所述N型电极50于所述N型氮化镓层20和电连接所述P型电极60于所述P型氮化镓层40，以制得所述半导体芯片。
优选地，生长所述量子垒和所述量子阱的循环周期为3个周期-20个周期。
优选地，所述量子垒的生长压力低于所述量子阱的生长压力。
在所述步骤(b)中，进一步包括步骤：
(b.1)保持层叠有所述N型氮化镓层20的所述衬底10于所述金属有机化合物气相外延沉积设备；
(b.2)通入In源、Ga源、氮源和硅烷于所述金属有机化合物气相外延沉积设备生长掺杂的Alx1Iny1Ga1-x1-y1N(0<X1<1,0<Y1<1)量子垒，以形成层叠于所述N型氮化镓层的所述量子垒；
(b.3)降低所述金属有机化合物气相外延沉积设备的压力，通入In源、Ga源和氮源于所述金属有机化合物气相外延沉积设备生长未掺杂的Alx2Iny2Ga1-x2-y2N(0<X2<1,0<Y2<1)量子阱，以形成层叠于所述量子垒的所述量子阱；以及
(b.4)循环所述步骤(b.2)和所述步骤(b.3)，以层叠所述量子阱层30于所述N型氮化镓层20。
值得注意的是，在本发明中所涉及的“层叠”可以是直接层叠，也可以是间接层叠。例如，所述N型氮化镓层20层叠于所述衬底10可以是指所述N型氮化镓层20间接地层叠于所述衬底10，即，在所述N型氮化镓层20和所述衬底10之间还可以设置有其他层，例如， 在所述N型氮化镓层20和所述衬底10之间还可以设置有所述缓冲层70。相应地，所述缓冲层70层叠于所述衬底10可以是指所述缓冲层70直接地层叠于所述衬底10，即，直接在所述衬底10上生长所述缓冲层70。
值得注意的是，在本发明的附图只用示出的所述半导体芯片的所述衬底10、所述缓冲层70、所述N型氮化镓层20、所述电流扩展层80、所述量子阱层30、所述保护层90、所述电子阻挡层100、所述N型电极50和所述P型电极60的厚度仅为示例，其并不表示所述衬底10、所述缓冲层70、所述N型氮化镓层20、所述电流扩展层80、所述量子阱层30、所述保护层90、所述电子阻挡层100、所述N型电极50和所述P型电极60的真实厚度。并且，所述衬底10、所述缓冲层70、所述N型氮化镓层20、所述电流扩展层80、所述量子阱层30、所述保护层90、所述电子阻挡层100、所述N型电极50和所述P型电极60之间的真实比例也不像附图中示出的那样。
本领域的技术人员可以理解的是，以上实施例仅为举例，其中不同实施例的特征可以相互组合，以得到根据本发明揭露的内容很容易想到但是在附图中没有明确指出的实施方式。
本领域的技术人员应理解，上述描述及附图中所示的本发明的实施例只作为举例而并不限制本发明。本发明的目的已经完整并有效地实现。本发明的功能及结构原理已在实施例中展示和说明，在没有背离所述原理下，本发明的实施方式可以有任何变形或修改。

Claims (33)

  1. 一发光二极管的半导体芯片，其特征在于，包括：
    一衬底；
    一N型氮化镓层，其中所述N型氮化镓层层叠于所述衬底；
    一量子阱层，其中所述量子阱层层叠于所述N型氮化镓层，其中所述量子阱层包括依次层叠的至少一量子垒和至少一量子阱，所述量子垒和所述量子阱的生长压力不同；
    一P型氮化镓层，其中所述P型氮化镓层层叠于所述量子阱层；
    一N型电极，其中所述N型电极被电连接于所述N型氮化镓层；以及
    一P型电极，其中所述P型电极被电连接于所述P型氮化镓层。
  2. 根据权利要求1所述的半导体芯片，其中所述量子阱层的所述量子垒的生长压力低于所述量子阱的生长压力。
  3. 根据权利要求2所述的半导体芯片，其中所述量子阱层的所述量子垒的层数参数和所述量子阱的层数参数均为N，其中参数N的取值范围为：3≤N≤20。
  4. 根据权利要求1所述的半导体芯片，其中所述量子阱层的所述量子垒是Alx1Iny1Ga1-x1-y1N(0<X1<1,0<Y1<1)掺杂量子垒，掺杂浓度为1-5x10 18cm -3，其中所述量子阱层的所述量子阱是Alx2Iny2Ga1-x2-y2N(0<X2<1,0<Y2<1)未掺杂量子阱。
  5. 根据权利要求2所述的半导体芯片，其中所述量子阱层的所述量子垒是Alx1Iny1Ga1-x1-y1N(0<X1<1,0<Y1<1)掺杂量子垒，掺杂浓度为1-5x10 18cm -3，其中所述量子阱层的所述量子阱是Alx2Iny2Ga1-x2-y2N(0<X2<1,0<Y2<1)未掺杂量子阱。
  6. 根据权利要求3所述的半导体芯片，其中所述量子阱层的所述量子垒是Alx1Iny1Ga1-x1-y1N(0<X1<1,0<Y1<1)掺杂量子垒，掺杂浓度为1-5x10 18cm -3，其中所述量子阱层的所述量子阱是Alx2Iny2Ga1-x2-y2N(0<X2<1,0<Y2<1)未掺杂量子阱。
  7. 根据权利要求4所述的半导体芯片，其中所述量子阱的所述量子垒的厚度尺寸范围为5nm-15nm，所述量子阱的厚度尺寸范围为2nm-5nm。
  8. 根据权利要求5所述的半导体芯片，其中所述量子阱的所述量子垒的厚度尺寸范围为5nm-15nm，所述量子阱的厚度尺寸范围为2nm-5nm。
  9. 根据权利要求6所述的半导体芯片，其中所述量子阱的所述量子垒的厚度尺寸范围为5nm-15nm，所述量子阱的厚度尺寸范围为2nm-5nm。
  10. 根据权利要求1至9中任一所述的半导体芯片，进一步包括一缓冲层，其中所述缓冲层层叠于所述衬底，所述N型氮化镓层层叠于所述缓冲层。
  11. 根据权利要求10所述的半导体芯片，其中所述缓冲层为GaN缓冲层或者AlN缓冲层。
  12. 根据权利要求1至9中任一所述的半导体芯片，进一步包括一电流扩展层，其中所述电流扩展层层叠于所述N型氮化镓层，所述量子阱层层叠于所述电流扩展层。
  13. 根据权利要求10所述的半导体芯片，进一步包括一电流扩展层，其中所述电流扩展层层叠于所述N型氮化镓层，所述量子阱层层叠于所述电流扩展层。
  14. 根据权利要求13所述的半导体芯片，其中所述电流扩展层是N型电流扩展层；或者所述电流扩展层是AlGaN型电流扩展层；或者所述电流扩展层是InGaN电流扩展层。
  15. 根据权利要求1至9中任一所述的半导体芯片，进一步包括一保护层，其中所述保护层层叠于所述量子阱层，所述P型氮化镓层层叠于所述保护层。
  16. 根据权利要求13所述的半导体芯片，进一步包括一保护层，其中所述保护层层叠于所述量子阱层，所述P型氮化镓层层叠于所述保护层。
  17. 根据权利要求16所述的半导体芯片，进一步包括一电子阻挡层，其中所述电子阻挡层层叠于所述保护层，所述P型氮化镓层层叠于所述电子阻挡层。
  18. 根据权利要求17所述的半导体芯片，其中所述N型电极层叠于所述电流扩展层，所述P型电极层叠于所述P型氮化镓层。
  19. 一量子阱层，其应用于一半导体芯片，其特征在于，所述量子阱层包括依次层叠的至少一量子垒和至少一量子阱，所述量子垒和所述量子阱的生长压力不同。
  20. 根据权利要求19所述的量子阱层，其中所述量子阱层的所述量子垒的生长压力低于所述量子阱的生长压力。
  21. 根据权利要求20所述的量子阱层，其中所述量子阱层的所述量子垒的层数参数和所述量子阱的层数参数均为N，其中参数N的取值范围为：3≤N≤20。
  22. 根据权利要求19至21中任一所述的量子阱层，其中所述量子阱层的所述量子垒是Alx1Iny1Ga1-x1-y1N(0<X1<1,0<Y1<1)掺杂量子垒，掺杂浓度为1-5x10 18cm -3，其中所述量子阱层的所述量子阱是Alx2Iny2Ga1-x2-y2N(0<X2<1,0<Y2<1)未掺杂量子阱。
  23. 根据权利要求22所述的量子阱层，其中所述量子阱的所述量子垒的厚度尺寸范围为5nm-15nm，所述量子阱的厚度尺寸范围为2nm-5nm。
  24. 一发光二极管的半导体芯片的制造方法，其特征在于，所述制造方法包括如下步骤：
    (a)层叠一N型氮化镓层于一衬底；
    (b)自所述N型氮化镓层循环生长一量子垒和一量子阱，以藉由多个所述量子垒和多个所述量子阱形成层叠于所述N型氮化镓层的一量子阱层，其中所述量子垒的生长压力和所述量子阱的生长压力不同；
    (c)层叠一P型氮化镓层于所述量子阱层；以及
    (d)电连接一N型电极于所述N型氮化镓层和电连接一P型电极于所述P型氮化镓层，以制得所述半导体芯片。
  25. 根据权利要求24所述的制造方法，其中生长所述量子垒和所述量子阱的循环周期为3个周期至20个周期。
  26. 根据权利要求24所述的制造方法，其中所述量子垒的生长压力低于所述量子阱的生长压力。
  27. 根据权利要求25所述的制造方法，其中所述量子垒的生长压力低于所述量子阱的生长压力。
  28. 根据权利要求27所述的制造方法，其中在所述步骤(b)中，进一步包括步骤：
    (b.1)保持层叠有所述N型氮化镓层的所述衬底于一金属有机化合物气相外延沉积设备；
    (b.2)通入In源、Ga源、氮源和硅烷于所述金属有机化合物气相外延沉积设备生长掺杂的Alx1Iny1Ga1-x1-y1N(0<X1<1,0<Y1<1)量子垒，以形成层叠于所述N型氮化镓层的所述量子垒；
    (b.3)降低所述金属有机化合物气相外延沉积设备的压力，通入In源、Ga源和氮源于所述金属有机化合物气相外延沉积设备生长未掺杂的Alx2Iny2Ga1-x2-y2N(0<X2<1,0<Y2<1)量子阱，以形成层叠于所述量子垒的所述量子阱；以及
    (b.4)循环所述步骤(b.2)和所述步骤(b.3)，以层叠所述量子阱层于所述N型氮化镓层。
  29. 根据权利要求28所述的制造方法，其中所述量子阱层的所述量子垒的掺杂浓度为1-5x10 18cm -3。
  30. 根据权利要求29所述的制造方法，其中所述量子阱层的所述量子垒的厚度尺寸范围为5nm-15nm，所述量子阱的厚度尺寸范围为2nm-5nm。
  31. 根据权利要求24至30中任一所述的制造方法，其中在所述步骤(a)之前，所述制造方法进一步包括步骤：自所述衬底生长一缓冲层，从而在所述步骤(a)中，所述N型氮化镓层生长于所述缓冲层。
  32. 根据权利要求24至30中任一所述的制造方法，其中在所述步骤(b)之前，所述制造方法进一步包括步骤：自所述N型氮化镓层生长一电流扩展层，从而在所述步骤(b)中，所述量子阱层生长于所述电流扩展层。
  33. 根据权利要求24至30中任一所述的制造方法，其中在所述步骤(c)之前，进一步包括步骤：自所述量子阱层生长一保护层和自所述保护层生长一电子阻挡层，从而在所述步骤(c)中，所述P型氮化镓层生长于所述电子阻挡层。
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