WO2020052019A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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Publication number
WO2020052019A1
WO2020052019A1 PCT/CN2018/112864 CN2018112864W WO2020052019A1 WO 2020052019 A1 WO2020052019 A1 WO 2020052019A1 CN 2018112864 W CN2018112864 W CN 2018112864W WO 2020052019 A1 WO2020052019 A1 WO 2020052019A1
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Prior art keywords
gate
metal layer
drain
source
region
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PCT/CN2018/112864
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English (en)
French (fr)
Inventor
黄北洲
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惠科股份有限公司
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Priority to US16/319,476 priority Critical patent/US11735639B2/en
Publication of WO2020052019A1 publication Critical patent/WO2020052019A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material

Definitions

  • This solution relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • TFT-LCDs thin film transistor liquid crystal displays
  • the thin film transistor display is mainly composed of an array substrate (Thin Film Transistor Array, TFT array), a color filter substrate (Color Filter), and a liquid crystal layer (Liquid Crystal Layer).
  • the array substrate is a thin film transistor (Thin Film Transistor (TFT) and a pixel electrode (Pixel Electrode) corresponding to each thin film transistor, and the thin film transistor is used as a switching element of a liquid crystal display.
  • the array substrate mainly uses a bottom gate structure (TFT).
  • TFT bottom gate structure
  • the parasitic capacitance of the thin film transistor (TFT) is relatively large, which is not conducive to the high resolution and aperture ratio of the display panel and affects the display quality of the display panel.
  • the purpose of this application is to provide an array substrate and a display panel to solve the problem of large parasitic capacitance.
  • the array substrate includes:
  • a first metal layer disposed on a surface of the substrate
  • An insulating layer disposed on a surface of the first metal layer
  • a semiconductor layer provided on the surface of the insulating layer
  • a second metal layer disposed on a surface of the semiconductor layer
  • the area of the overlapping area of the first metal layer and the second metal layer is smaller than the area of the non-overlapping area of the first metal layer and the second metal layer.
  • the first metal layer includes a gate electrode disposed on a substrate
  • the second metal layer includes a source electrode and a drain electrode, the source electrode is disposed on one side of the semiconductor layer, and the drain electrode is disposed On the other side of the semiconductor layer;
  • the area of the overlapping area of the source and the gate is smaller than the area of the non-overlapping area of the source and the gate, and the area of the overlapping area of the drain and the gate is smaller than the area of the non-overlapping area of the drain and the gate.
  • the length of the overlapping region of the source and gate is L1
  • the length of the non-overlapping region of the source and gate is L2
  • the length of the overlapping region of the drain and gate is L3, and the drain and
  • the length of the gate non-overlapping region is L4; the L1 is less than L2, and the L3 is less than L4.
  • the values of L1 and L3 are in a range of 0.5 ⁇ m to 3 ⁇ m.
  • the L1 is a quarter to two thirds of the L2; and the L3 is a quarter to two thirds of the L4.
  • the width of the overlapping area of the gate and source is W1
  • the width of the source is W2
  • the width of the overlapping area of the gate and drain is W3
  • the width of the drain is W4, and the W1 Less than W2, said W3 is less than W4.
  • the thickness of the overlapping area of the gate and source is D1
  • the thickness of the overlapping area of the gate and drain is D2
  • the thickness of the non-overlapping area of the gate, source, and drain is D3
  • the D1 and D2 are smaller than D3.
  • the thickness of the region where the source overlaps the gate is H1
  • the thickness of the region where the source overlaps the gate is H2
  • the thickness of the region where the drain overlaps the gate is H3
  • the thickness of the non-overlapping region on the drain and the gate is H4; the H2 is greater than H1, and the H4 is greater than H3.
  • D1 is one-third to two-thirds of D3, and D2 is one-third to two-thirds of D3.
  • H1 is one-third to two-thirds of H2
  • H3 is one-third to two-thirds of H4.
  • the display panel includes an array substrate.
  • the array substrate includes:
  • a first metal layer disposed on a surface of the substrate
  • An insulating layer disposed on a surface of the first metal layer
  • a semiconductor layer provided on the surface of the insulating layer
  • a second metal layer disposed on a surface of the semiconductor layer
  • the area of the overlapping area of the first metal layer and the second metal layer is smaller than the area of the non-overlapping area of the first metal layer and the second metal layer.
  • Another object of the present application is to provide a method for manufacturing an array substrate, including the steps of forming a first metal layer, an insulating layer, a semiconductor layer, a second metal layer, a passivation layer, and an ITO layer on a substrate;
  • the area of the area where the first metal layer and the second metal layer overlap is smaller than the area of the non-overlapping area of the first metal layer and the second metal layer.
  • the array substrate mainly uses a bottom gate structure (Bottom Gate TFT).
  • the area of the overlapping area of the first metal layer and the second metal layer is relatively large, and the parasitic capacitance of the thin film transistor (TFT) is relatively large. Larger is not conducive to the high resolution and aperture ratio of the display panel and affects the display quality of the display panel.
  • the first metal layer is located below the second metal layer, and the area of the overlapping area of the first metal layer and the second metal layer is smaller than the area of the non-overlapping area of the first metal layer and the second metal layer, and the area of the overlapping area is reduced.
  • the parasitic capacitance generated between the first metal layer and the second metal layer is reduced, which is conducive to the high resolution and aperture ratio of the display panel, and improves the display quality of the display panel.
  • 1 is a schematic cross-sectional view of an array substrate
  • FIG. 2 is a schematic cross-sectional view of another array substrate according to the present application.
  • FIG. 3 is a schematic top view of an array substrate according to the present application.
  • FIG. 4 is a schematic cross-sectional view of another array substrate according to the present application.
  • FIG. 5 is a schematic cross-sectional view of another array substrate of the present application.
  • an array substrate 10 is disclosed.
  • the array substrate 10 includes: a substrate 11, a first metal layer 12 provided on a surface of the substrate 11, and a first metal.
  • the area of the overlapping area of the first metal layer 12 and the second metal layer 15 is smaller than the area of the non-overlapping area of the first metal layer 12 and the second metal layer 15.
  • the array substrate 10 mainly uses a bottom gate structure (Bottom Gate TFT).
  • Bottom Gate TFT the area of the overlapping area of the first metal layer 12 and the second metal layer 15 is large, and the parasitic capacitance of the thin film transistor (TFT) is relatively large. Larger is not conducive to the high resolution and aperture ratio of the display panel and affects the display quality of the display panel.
  • the first metal layer 12 is located below the second metal layer 15, and the area of the area where the first metal layer 12 and the second metal layer 15 overlap is smaller than the area of the non-overlapping area of the first metal layer 12 and the second metal layer 15. The area of the overlapping area is reduced, and the parasitic capacitance generated between the first metal layer 12 and the second metal layer 15 is reduced, which is conducive to the high resolution and aperture ratio of the display panel and improves the display quality of the display panel.
  • the first metal layer 12 includes a gate electrode 121 disposed on the surface of the substrate 11, the second metal layer 15 includes a source electrode 151 and a drain electrode 152, and the source electrode 151 is disposed on the semiconductor layer 14. On one side, the drain electrode 152 is disposed on the other side of the semiconductor layer 14;
  • the area of the overlapping area of the source 151 and the gate 121 is smaller than the area of the non-overlapping area of the source 151 and the gate 121, and the area of the overlapping area of the drain 152 and the gate 121 is smaller than the non-overlapping area of the drain 152 and the gate 121. Area.
  • the area of the overlapping area of the source 151, the drain 152, and the gate 121 is large, and the parasitic capacitance of the thin film transistor (TFT) is relatively large, which is not conducive to the high resolution and aperture ratio of the display panel, and affects the display quality of the display panel.
  • the gate 121 is located below the source 151 and the drain 152.
  • the area of the overlapping area of the source 151 and the gate 121 is smaller than the area of the non-overlapping area of the source 151 and the gate 121, and the area of the overlapping area of the drain 152 and the gate 121 is less than
  • the area of the non-overlapping area of the drain electrode 152 and the gate electrode 121 is reduced, and the area of the overlapping area is reduced.
  • the parasitic capacitance generated between the gate electrode 121 and the source electrode 151 and the drain electrode 152 is reduced, which is beneficial to the high resolution and the aperture ratio of the display panel. Improve the display quality of the display panel.
  • the length of the overlapping region of the source 151 and the gate 121 is L1, and the length of the non-overlapping region of the source 151 and the gate 121 is L2; the length of the overlapping region of the drain 152 and the gate 121 Is L3, and the length of the non-overlapping region of the drain electrode 152 and the gate electrode 121 is L4; the L1 is less than L2, and the L3 is less than L4.
  • the length of the overlapping region of the source 151 and the gate 121 is shorter than the length of the non-overlapping region of the source 151 and the gate 121, and the length of the overlapping region of the drain 152 and the gate 121 is shorter than the length of the non-overlapping region of the drain 152 and the gate 121.
  • the area of the overlapping area between the gate 121 and the source 151 and the drain 152 is reduced, and the parasitic capacitance generated between the gate 121 and the source 151 and the drain 152 is reduced, which is conducive to the high resolution and the aperture ratio of the display panel and improves the display.
  • the display quality of the panel is provided.
  • the value of L1 and L3 ranges from 0.5 ⁇ m to 3 ⁇ m.
  • the value range of L1 and L3 is 0.5 ⁇ m to 3 ⁇ m.
  • the yellow light alignment accuracy can be guaranteed.
  • the gate 121 and the source 151, The length of the overlapping area of the drain 152 is neither too long, the parasitic capacitance is small, nor too short. The length of the overlapping area is sufficient.
  • the semiconductor layer 14 between the overlapping area of the gate 121 and the source 151 and the drain 152 is charged. 151 and drain 152 have good conduction effect.
  • the L1 is a quarter to two thirds of the L2; and the L3 is a quarter to two thirds of the L4.
  • L1 is a quarter to two-thirds of L2
  • L3 is a quarter to two-thirds of L4, such as one-quarter, one-third, one-half, three- At two-thirds, the length of the overlapping area of the gate 121 with the source 151 and the drain 152 is neither too long, the parasitic capacitance is small, nor too short, and the length of the overlapping area is sufficient.
  • the semiconductor layer 14 between the overlapping regions of 152 is sufficient, and the conduction effect of the source 151 and the drain 152 is good.
  • the width of the overlapping region of the gate 121 and the source 151 is W1, and the width of the source 151 is W2; the width of the overlapping region of the gate 121 and the drain 152 is W3, and the drain The width of 152 is W4; the W1 is smaller than W2, and the W3 is smaller than W4.
  • the width of the overlapping area of the gate 121 and the source 151 is smaller than the width of the non-overlapping area of the gate 121 and the source 151, and the width of the overlapping area of the gate 121 and the drain 152 is smaller than that of the non-overlapping area of the gate 121 and the drain 152. Width, the area of the overlapping area between the gate 121 and the source 151 and the drain 152 is reduced, and the parasitic capacitance generated between the gate 121 and the source 151 and the drain 152 is reduced, which is beneficial to the high resolution and the aperture ratio of the display panel. Improve the display quality of the display panel.
  • the thickness of the area where the gate 121 overlaps with the source 151 is D1
  • the thickness of the area where the gate 121 overlaps with the drain 152 is D2.
  • the thickness of the gate 121 with the source 151 and the drain is D3; the D1 and D2 are smaller than D3.
  • the thickness of the region where the gate 121 overlaps with the source 151 and the thickness of the region where the gate 121 overlaps with the drain 152 are smaller than the thickness of the non-overlapping region between the gate 121 and the source 151 and the drain 152. As the distance between the overlapping regions of the electrodes 152 increases, the parasitic capacitance can be further reduced, which is conducive to the high resolution and aperture ratio of the display panel and improves the display quality of the display panel.
  • the thickness of the region where the source electrode 151 overlaps with the gate electrode 121 is H1, and the thickness of the region where the source electrode 151 does not overlap with the gate electrode 121 is H2;
  • the thickness of the 121 overlapping area is H3, and the thickness of the non-overlapping area on the drain electrode 152 and the gate 121 is H4; the H2 is greater than H1, and the H4 is greater than H3.
  • the thickness of the region overlapped with the gate 121 on the source 151 is smaller than the thickness of the region not overlapped with the gate 121 on the source 151, and the thickness of the region overlapped with the gate 121 on the drain 152 is smaller than the thickness of the region not overlapped with the gate 121.
  • the distance between the overlapping regions of the source electrode 151 and the drain electrode 152 is increased, and the parasitic capacitance can be further reduced, which is conducive to the high resolution and aperture ratio of the display panel and improves the display quality of the display panel.
  • D1 is one-third to two-thirds of D3, and D2 is one-third to two-thirds of D3.
  • D1 is one-third to two-thirds of D3, such as one-third, one-half, two-thirds
  • D2 is one-third to two-thirds of D3, such as one-third
  • the thickness of the overlapping area of the gate 121 with the source 151 and the drain 152 is appropriate. It can increase the distance between the overlapping areas, and the parasitic capacitance can be further reduced, which is good for display.
  • the high resolution and aperture ratio of the panel improve the display quality of the display panel; it can also ensure that the overlapping area is not easily broken or damaged due to being too thin, and the semiconductor layer 14 is normally turned on.
  • H1 is one-third to two-thirds of H2
  • H3 is one-third to two-thirds of H4.
  • H1 is one-third to two-thirds of H2, such as one-third, one-half, and two-thirds;
  • H3 is one-third to two-thirds of H4,
  • the thickness of the overlapping area between the source 151 and the drain 152 and the gate 121 is appropriate.
  • the distance between the overlapping areas can be increased, and the parasitic capacitance can be further increased.
  • the reduction is beneficial to the high resolution and the aperture ratio of the display panel, and improves the display quality of the display panel. It can also ensure that the overlapping area is not easily broken or damaged due to being too thin, and the semiconductor layer 14 is normally turned on.
  • a display panel in another embodiment of the present application, referring to FIGS. 1 to 5, a display panel is disclosed.
  • the display panel includes an array substrate 10.
  • the array substrate 10 includes a substrate 11 and is disposed on a surface of the substrate 11.
  • the array substrate 10 of the display panel mainly uses a bottom gate structure (Bottom Gate TFT).
  • Bottom Gate TFT the area of the overlapping area of the first metal layer 12 and the second metal layer 15 is large, and the thin film transistor (TFT)
  • TFT thin film transistor
  • the parasitic capacitance is relatively large, which is not conducive to the high resolution and aperture ratio of the display panel, and affects the display quality of the display panel.
  • the first metal layer 12 is located below the second metal layer 15, and the area of the overlapping area of the first metal layer and the second metal layer 15 is smaller than the area of the non-overlapping area of the first metal layer 12 and the second metal layer 15, The area of the overlapping area is reduced, and the parasitic capacitance generated between the first metal layer 12 and the second metal layer 15 is reduced, which is conducive to the high resolution and aperture ratio of the display panel and improves the display quality of the display panel.
  • a method for manufacturing an array substrate 10 includes forming a first metal layer 12, an insulating layer 13, a semiconductor layer 14, a second metal layer 15, a passivation layer, Step of ITO layer;
  • the area of the area where the first metal layer 12 and the second metal layer 15 overlap is smaller than that of the first metal layer 12 and the second metal layer 15. The area of the overlapping area.
  • This method can make the area of the overlapping area of the first metal layer 12 and the second metal layer 15 smaller than the area of the non-overlapping area of the first metal layer 12 and the second metal layer 15, and the area of the overlapping area is reduced.
  • the reduction in parasitic capacitance generated between the two metal layers 15 is beneficial to the high resolution and aperture ratio of the display panel, and to improve the display quality of the display panel.
  • the panel of the present application may be a TN panel (full name is Twisted Nematic, that is, a twisted nematic panel), an IPS panel (In-PaneSwitcing, plane conversion), a VA panel (Multi-domain Vertica Aignment, multi-quadrant vertical alignment technology), of course , Or other types of panels, applicable.
  • TN panel full name is Twisted Nematic, that is, a twisted nematic panel
  • IPS panel In-PaneSwitcing, plane conversion
  • VA panel Multi-domain Vertica Aignment, multi-quadrant vertical alignment technology

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Abstract

一种阵列基板(10)及显示面板。阵列基板(10)包括第一金属层(12)和第二金属层(15)；第一金属层(12)与第二金属层(15)的重叠区域的面积小于第一金属层(12)与第二金属层(15)的非重叠区域的面积。

Description

一种阵列基板及显示面板
本申请要求于2018年9月13日提交中国专利局、申请号为CN201821501613.3、发明名称为“一种阵列基板及显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本方案涉及显示技术领域，尤其涉及一种阵列基板及显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
多媒体社会的急速进步，多半受惠于半导体元件或显示装置的飞跃性进步。就显示器而言，具有高画质、空间利用效率佳、低消耗功率、无辐射等优越特性的薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)已逐渐成为市场的主流。
薄膜晶体管显示器主要由阵列基板(Thin Film Transistor Array，TFT Array)、彩色滤光基板(Color Filter)和液晶层(Liquid Crystal Layer)所构成，其中阵列基板是由多个阵列排列的薄膜晶体管(Thin Film Transistor，TFT)以及与每一个薄膜晶体管对应配置的像素电极(Pixel Electrode)所组成，而薄膜晶体管用来作为液晶显示的开关元件。阵列基板主要采用的是底栅结构(Bottom Gate TFT)，薄膜晶体管(TFT)寄生电容相对较大，不利于显示面板的高分辨及开口率，影响显示面板的显示品质。
技术解决方案
本申请的目的在于提供一种阵列基板及显示面板，以解决寄生电容较大的问题。
为实现上述目的，本申请提供了一种阵列基板，所述阵列基板包 括：
基底；
第一金属层，设置在基底表面；
绝缘层，设置在第一金属层表面；
半导体层，设置在绝缘层表面；
第二金属层，设置在半导体层表面；
所述第一金属层与第二金属层之间存在重叠区域；
所述第一金属层与第二金属层重叠区域的面积小于第一金属层与第二金属层非重叠区域的面积。
可选的，所述第一金属层包括栅极，设置在基底上，所述第二金属层包括源极、漏极，所述源极设置在半导体层的一侧上，所述漏极设置在半导体层的另一侧上；
所述栅极与源极之间存在重叠区域，栅极与漏极之间存在重叠区域；
所述源极与栅极重叠区域的面积小于源极与栅极非重叠区域的面积，所述漏极与栅极重叠区域面积小于漏极与栅极非重叠区域的面积。
可选的，所述源极与栅极重叠区域长度为L1，所述源极与栅极非重叠区域的长度为L2；所述漏极与栅极重叠区域长度为L3，所述漏极与栅极非重叠区域长度为L4；所述L1小于L2，所述L3小于L4。
可选的，所述L1和L3的数值范围为0.5μm至3μm。
可选的，所述L1是L2的四分之一至三分之二；所述L3是L4的四分之一至三分之二。
可选的，所述栅极与源极重叠区域宽度为W1，所述源极的宽度为W2；所述栅极与漏极重叠区域宽度为W3，所述漏极宽度为W4；所述W1 小于W2，所述W3小于W4。
可选的，所述栅极与源极重叠区域的厚度为D1，所述栅极与漏极重叠区域的厚度为D2，所述栅极与源极、漏极非重叠区域的厚度为D3；所述D1和D2小于D3。
可选的，所述源极上与栅极重叠区域的厚度为H1，所述源极上与栅极非重叠区域的厚度为H2；所述漏极上与栅极重叠区域的厚度为H3，所述漏极上与栅极非重叠区域的厚度为H4；所述H2大于H1，所述H4大于H3。
可选的，所述D1是D3的三分之一至三分之二，所述D2是D3的三分之一至三分之二。
可选的，所述H1是H2的三分之一至三分之二，所述H3是H4的三分之一至三分之二。
本申请的另一目的在于提供一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
基底；
第一金属层，设置在基底表面；
绝缘层，设置在第一金属层表面；
半导体层，设置在绝缘层表面；
第二金属层，设置在半导体层表面；
所述第一金属层与第二金属层之间存在重叠区域；
所述第一金属层与第二金属层重叠区域的面积小于第一金属层与第二金属层非重叠区域的面积。
本申请的又一目的在于提供一种阵列基板的制作方法，包括基底上形成第一金属层、绝缘层、半导体层、第二金属层、钝化层和ITO层的步骤；
其中，在形成第一金属层以及形成第二金属层的步骤中，使得在第一金属层与第二金属层重叠区域的面积小于第一金属层与第二金属层非重叠区域的面积。
申请人研究发现，阵列基板主要采用的是底栅结构(Bottom GateTFT)，这种结构的阵列基板，第一金属层与第二金属层的重叠区域面积较大，薄膜晶体管(TFT)寄生电容相对较大，不利于显示面板的高分辨及开口率，影响显示面板的显示品质。本申请中，第一金属层位于第二金属层之下，第一金属层与第二金属层重叠区域的面积小于第一金属层与第二金属层非重叠区域的面积，重叠区域面积减小，第一金属层与第二金属层之间产生的寄生电容减小，有利于显示面板的高分辨及开口率，提升显示面板的显示品质。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是一种阵列基板剖面示意图；
图2是本申请另一种阵列基板剖面示意图；
图3是本申请一种阵列基板俯视示意图；
图4是本申请另一种阵列基板剖面示意图；
图5是本申请另一种阵列基板剖面示意图。
本申请的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实 现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
如图1所示，发明人了解到一种阵列基板结构。
下面结合附图和较佳的实施例对本申请作进一步说明。
如图2至图5所示，在一实施例中，公布了一种阵列基板10，所述阵列基板10包括：基底11、设置在基底11表面的第一金属层12、设 置在第一金属层12表面的绝缘层13、设置在绝缘层13表面的半导体层14、设置在半导体层14表面的第二金属层15；所述第一金属层12与第二金属层15之间存在重叠区域；所述第一金属层12与第二金属层15重叠区域的面积小于第一金属层12与第二金属层15非重叠区域的面积。
阵列基板10主要采用的是底栅结构(Bottom Gate TFT)，这种结构的阵列基板10，第一金属层12与第二金属层15的重叠区域面积较大，薄膜晶体管(TFT)寄生电容相对较大，不利于显示面板的高分辨及开口率，影响显示面板的显示品质。本申请中，第一金属层12位于第二金属层15之下，第一金属层12与第二金属层15重叠区域的面积小于第一金属层12与第二金属层15非重叠区域的面积，重叠区域面积减小，第一金属层12与第二金属层15之间产生的寄生电容减小，有利于显示面板的高分辨及开口率，提升显示面板的显示品质。
在一实施例中，所述第一金属层12包括栅极121，设置在基底11表面，所述第二金属层15包括源极151、漏极152，所述源极151设置在半导体层14的一侧上，所述漏极152设置在半导体层14的另一侧；
所述栅极121与源极151之间存在重叠区域，栅极121与漏极152之间存在重叠区域；
所述源极151与栅极121重叠区域的面积小于源极151与栅极121非重叠区域的面积，所述漏极152与栅极121重叠区域面积小于漏极152与栅极121非重叠区域的面积。
本方案中，源极151、漏极152与栅极121的重叠区域面积较大，薄膜晶体管(TFT)寄生电容相对较大，不利于显示面板的高分辨及开口率，影响显示面板的显示品质。栅极121位于源极151和漏极152之下，源极151与栅极121重叠区域的面积小于源极151与栅极121非重叠区域的面积，漏极152与栅极121重叠区域面积小于漏极152与栅极121非重叠区域的面积，重叠区域面积减小，栅极121与源极151、漏极152之间产生的寄生电容减小，有利于显示面板的高分辨及开口率，提升显示面板的显示品质。
在一实施例中，所述源极151与栅极121重叠区域长度为L1，所述源极151与栅极121非重叠区域的长度为L2；所述漏极152与栅极121重叠区域长度为L3，所述漏极152与栅极121非重叠区域长度为L4；所述L1小于L2，所述L3小于L4。
源极151与栅极121重叠区域长度小于源极151与栅极121非重叠区域的长度，漏极152与栅极121重叠区域长度小于漏极152与栅极121非重叠区域的长度。栅极121与源极151、漏极152重叠区域面积减小，栅极121与源极151、漏极152之间产生的寄生电容减小，有利于显示面板的高分辨及开口率，提升显示面板的显示品质。
在一实施例中，所述L1和L3的数值范围为0.5μm至3μm。
L1和L3的数值范围为0.5μm至3μm，例如该数值范围，L1和L3的数值范围为0.5μm、1μm、2μm或3μm时，可以保证黄光对位精度，栅极121与源极151、漏极152重叠区域长度既不会过长，寄生电容小，又不会过短，重叠区域长度充足，栅极121与源极151、漏极152重叠区域之间的半导体层14充，源极151和漏极152导通效果好。
在一实施例中，所述L1是L2的四分之一至三分之二；所述L3是L4的四分之一至三分之二。
本方案中，L1是L2的四分之一至三分之二，L3是L4的四分之一至三分之二，例如为四分之一、三分之一、二分之一、三分之二时，栅极121与源极151、漏极152重叠区域长度既不会过长，寄生电容小，又不会过短，重叠区域长度充足，栅极121与源极151、漏极152重叠区域之间的半导体层14充分，源极151和漏极152导通效果好。
在一实施例中，所述栅极121与源极151重叠区域宽度为W1，所述源极151的宽度为W2；所述栅极121与漏极152重叠区域宽度为W3，所述漏极152宽度为W4；所述W1小于W2，所述W3小于W4。
本方案中，栅极121与源极151重叠区域宽度小于栅极121与源 极151非重叠区域的宽度，栅极121与漏极152重叠区域宽度小于栅极121与漏极152非重叠区域的宽度，栅极121与源极151、漏极152重叠区域面积减小，栅极121与源极151、漏极152之间产生的寄生电容减小，有利于显示面板的高分辨及开口率，提升显示面板的显示品质。
在一实施例中，所述栅极121与源极151重叠区域的厚度为D1，所述栅极121与漏极152重叠区域的厚度为D2，所述栅极121与源极151、漏极152非重叠区域的厚度为D3；所述D1和D2小于D3。
栅极121与源极151重叠区域的厚度和栅极121与漏极152重叠区域的厚度小于栅极121与源极151、漏极152非重叠区域的厚度，栅极121和源极151、漏极152重叠区域之间的距离增大，寄生电容可以进一步减少，有利于显示面板的高分辨及开口率，提升显示面板的显示品质。
在一实施例中，所述源极151上与栅极121重叠区域的厚度为H1，所述源极151上与栅极121非重叠区域的厚度为H2；所述漏极152上与栅极121重叠区域的厚度为H3，所述漏极152上与栅极121非重叠区域的厚度为H4；所述H2大于H1，所述H4大于H3。
源极151上与栅极121重叠区域的厚度小于与栅极121非重叠区域的厚度，漏极152上与栅极121重叠区域的厚度小于与栅极121非重叠区域的厚度，栅极121和源极151、漏极152重叠区域之间的距离增大，寄生电容可以进一步减少，有利于显示面板的高分辨及开口率，提升显示面板的显示品质。
在一实施例中，所述D1是D3的三分之一至三分之二，所述D2是D3的三分之一至三分之二。
D1是D3的三分之一至三分之二，例如为三分之一、二分之一、三分之二时；D2是D3的三分之一至三分之二，例如为三分之一、二分之一、三分之二时，栅极121上与源极151、漏极152重叠区域的厚度适当，既可以增加重叠区域之间距离，寄生电容可以进一步减少，有利于显示面板的高分辨及开口率，提升显示面板的显示品质；又能保证重叠区域不容易因为过 薄而断裂或者损坏，保证半导体层14正常导通。
在一实施例中，所述H1是H2的三分之一至三分之二，所述H3是H4的三分之一至三分之二。
本方案中，H1是H2的三分之一至三分之二，例如为三分之一、二分之一、三分之二时；H3是H4的三分之一至三分之二，例如为三分之一、二分之一、三分之二时，源极151上、漏极152上与栅极121重叠区域的厚度适当，既可以增加重叠区域之间距离，寄生电容可以进一步减少，有利于显示面板的高分辨及开口率，提升显示面板的显示品质；又能保证重叠区域不容易因为过薄而断裂或者损坏，保证半导体层14正常导通。
在本申请的另一实施例中，参考图1至图5所示，公开了一种显示面板，所述显示面板包括阵列基板10，所述阵列基板10包括包括基底11、设置在基底11表面的第一金属层12、设置在第一金属层12表面的绝缘层13、设置在绝缘层13表面的半导体层14、设置在半导体层14表面的第二金属层15；所述第一金属层12与第二金属层15之间存在重叠区域；所述第一金属层12与第二金属层15重叠区域的面积小于第一金属层12与第二金属层15非重叠区域的面积。
显示面板的阵列基板10主要采用的是底栅结构(Bottom Gate TFT)，这种结构的阵列基板10，第一金属层12与第二金属层15的重叠区域面积较大，薄膜晶体管(TFT)寄生电容相对较大，不利于显示面板的高分辨及开口率，影响显示面板的显示品质。本申请中，第一金属层12位于第二金属层15之下，第一金属层与第二金属层15重叠区域的面积小于第一金属层12与第二金属层15非重叠区域的面积，重叠区域面积减小，第一金属层12与第二金属层15之间产生的寄生电容减小，有利于显示面板的高分辨及开口率，提升显示面板的显示品质。
在本申请的另一实施例中，公开了一种阵列基板10的制作方法，包括基底11上形成第一金属层12、绝缘层13、半导体层14、第二金属层15、钝化层、ITO层的步骤；
其中，在形成第一金属层12以及形成第二金属层15的步骤中，使得在第一金属层12与第二金属层15重叠区域的面积小于第一金属层12与第二金属层15非重叠区域的面积。
本方法可以使得第一金属层12与第二金属层15重叠区域的面积小于第一金属层12与第二金属层15非重叠区域的面积，重叠区域面积减小，第一金属层12与第二金属层15之间产生的寄生电容减小，有利于显示面板的高分辨及开口率，提升显示面板的显示品质。
本申请的面板可以是TN面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS面板(In-PaneSwitcing，平面转换)、VA面板(Multi-domain Vertica Aignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (19)

  1. 一种阵列基板，所述阵列基板包括：
    基底；
    第一金属层，设置在基底表面；
    绝缘层，设置在第一金属层表面；
    半导体层，设置在绝缘层表面；
    以及第二金属层，设置在半导体层表面；
    所述第一金属层与第二金属层之间存在重叠区域；
    所述第一金属层与第二金属层重叠区域的面积小于第一金属层与第二金属层非重叠区域的面积。
  2. 如权利要求1所述的一种阵列基板，其中，所述第一金属层包括栅极，设置在基底表面，所述第二金属层包括源极、漏极，所述源极设置在半导体层的一侧上，所述漏极设置在半导体层的另一侧；
    所述栅极与源极之间存在重叠区域，栅极与漏极之间存在重叠区域；
    所述源极与栅极重叠区域的面积小于源极与栅极非重叠区域的面积，所述漏极与栅极重叠区域面积小于漏极与栅极非重叠区域的面积。
  3. 如权利要求2所述的一种阵列基板，其中，所述源极与栅极重叠区域长度小于所述源极与栅极非重叠区域的长度；所述漏极与栅极重叠区域长度小于所述漏极与栅极非重叠区域长度。
  4. 如权利要求3所述的一种阵列基板，其中，所述源极与栅极重叠区域长度为0.5μm至3μm；所述漏极与栅极重叠区域长度的数值范围为0.5μm至3μm。
  5. 如权利要求3所述的一种阵列基板，其中，所述源极与栅极重叠区域长度是所述源极与栅极非重叠区域的长度的四分之一至三分之二；所述漏极与栅极重叠区域长度是所述漏极与栅极非重叠区域长度的四分之一至三分之二。
  6. 如权利要求2所述的一种阵列基板，其中，所述栅极与源极重叠区域宽度小于所述源极的宽度；所述栅极与漏极重叠区域宽度小于所述漏极宽度。
  7. 如权利要求3所述的一种阵列基板，其中，所述栅极与源极重叠区域的厚度是所述栅极与源极、漏极非重叠区域厚度的的三分之一至三分之二；所述栅极与漏极重叠区域的厚度是所述栅极与源极、漏极非重叠区域厚度的的三分之一至三分之二。
  8. 如权利要求3所述的一种阵列基板，其中，所述源极上与栅极重叠区域的厚度大于所述源极上与栅极非重叠区域的厚度；所述漏极上与栅极重叠区域的厚度大于所述漏极上与栅极非重叠区域的厚度。
  9. 如权利要求8所述的一种阵列基板，其中，所述源极上与栅极重叠区域的厚度是所述源极上与栅极非重叠区域的厚度的三分之一至三分之二，所述漏极上与栅极重叠区域的厚度是所述漏极上与栅极非重叠区域的厚度的三分之一至三分之二。
  10. 一种阵列基板的制作方法，包括基底上形成第一金属层、绝缘层、半导 体层、第二金属层、钝化层和ITO层的步骤；
    其中，在形成第一金属层以及形成第二金属层的步骤中，使得在第一金属层与第二金属层重叠区域的面积小于第一金属层与第二金属层非重叠区域的面积。
  11. 一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
    基底；
    第一金属层，设置在基底表面；
    绝缘层，设置在第一金属层表面；
    半导体层，设置在绝缘层表面；
    以及第二金属层，设置在半导体层表面；
    所述第一金属层与第二金属层之间存在重叠区域；
    所述第一金属层与第二金属层重叠区域的面积小于第一金属层与第二金属层非重叠区域的面积；
    所述第一金属层包括栅极，设置在基底表面，所述第二金属层包括源极、漏极，所述源极设置在半导体层的一侧上，所述漏极设置在半导体层的另一侧。
  12. 如权利要求11所述的一种显示面板，其中，所述第一金属层包括栅极，设置在基底表面，所述第二金属层包括源极、漏极，所述源极设置在半导体层的一侧上，所述漏极设置在半导体层的另一侧；
    所述栅极与源极之间存在重叠区域，栅极与漏极之间存在重叠区域；
    所述源极与栅极重叠区域的面积小于源极与栅极非重叠区域的面积，所述漏极与栅极重叠区域面积小于漏极与栅极非重叠区域的面积。
  13. 如权利要求12所述的一种显示面板，其中，所述源极与栅极重叠区域长度小于所述源极与栅极非重叠区域的长度；所述漏极与栅极重叠区域长度小于所述漏极与栅极非重叠区域长度。
  14. 如权利要求13所述的一种显示面板，其中，所述源极与栅极重叠区域长度为0.5μm至3μm；所述漏极与栅极重叠区域长度的数值范围为0.5μm至3μm。
  15. 如权利要求13所述的一种显示面板，其中，所述源极与栅极重叠区域长度是所述源极与栅极非重叠区域的长度的四分之一至三分之二；所述漏极与栅极重叠区域长度是所述漏极与栅极非重叠区域长度的四分之一至三分之二。
  16. 如权利要求12所述的一种显示面板，其中，所述栅极与源极重叠区域宽度小于所述源极的宽度；所述栅极与漏极重叠区域宽度小于所述漏极宽度。
  17. 如权利要求13所述的一种显示面板，其中，所述栅极与源极重叠区域的厚度是所述栅极与源极、漏极非重叠区域厚度的的三分之一至三分之二；所述栅极与漏极重叠区域的厚度是所述栅极与源极、漏极非重叠区域厚度的的三分之一至三分之二。
  18. 如权利要求13所述的一种显示面板，其中，所述源极上与栅极重叠区域的厚度大于所述源极上与栅极非重叠区域的厚度；所述漏极上与栅极重叠区域的厚度大于所述漏极上与栅极非重叠区域的厚度。
  19. 如权利要求18所述的一种显示面板，其中，所述源极上与栅极重叠区域的厚度是所述源极上与栅极非重叠区域的厚度的三分之一至三分之二，所述漏 极上与栅极重叠区域的厚度是所述漏极上与栅极非重叠区域的厚度的三分之一至三分。
PCT/CN2018/112864 2018-09-13 2018-10-31 一种阵列基板及显示面板 WO2020052019A1 (zh)

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