WO2020050588A1 - Dispositif neuromorphique faisant appel à une structure de mémoire à entrées croisées - Google Patents

Dispositif neuromorphique faisant appel à une structure de mémoire à entrées croisées Download PDF

Info

Publication number
WO2020050588A1
WO2020050588A1 PCT/KR2019/011325 KR2019011325W WO2020050588A1 WO 2020050588 A1 WO2020050588 A1 WO 2020050588A1 KR 2019011325 W KR2019011325 W KR 2019011325W WO 2020050588 A1 WO2020050588 A1 WO 2020050588A1
Authority
WO
WIPO (PCT)
Prior art keywords
forming
electrodes
layer
gate
charge storage
Prior art date
Application number
PCT/KR2019/011325
Other languages
English (en)
Korean (ko)
Inventor
박진홍
오세용
서승환
Original Assignee
성균관대학교산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 성균관대학교산학협력단 filed Critical 성균관대학교산학협력단
Publication of WO2020050588A1 publication Critical patent/WO2020050588A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type

Definitions

  • the present invention relates to a vertical transistor based neuromorphic device using a crossbar memory structure.
  • the neuromorphic device mimics the structure of neurons and synapses that make up the brain system of the living body, and has a structure of pre-synaptic neurons (pre-synapses), synapses, and post-synaptic neurons (post-synapses) located before synapses.
  • pre-synapses pre-synaptic neurons
  • post-synapses post-synaptic neurons
  • Crossbar memories are synapses based on two-terminal memory elements such as resistive random access memory, phase-change random access memory, and conductive bridging random access memory. It is the most used structure in device research.
  • the crossbar memory architecture is ideal for neuromorphic synaptic devices because of its simple structure and the high density of device arrays.
  • two-terminal memory-based synaptic devices with crossbar arrays use one terminal as ground and apply a voltage pulse to the other terminal to change the internal resistance of the device to learn the synapse and then apply voltage again. Verify the device by reading the resistance value of the synaptic device.
  • the present invention is to solve the above-described problems of the prior art, some embodiments of the present invention provides a three-terminal based synaptic device that can complement the performance of the two-terminal device-based synaptic device, cross-bar memory structure vertical It is an object of the present invention to provide a neuromorphic device and a method for manufacturing the same that can be provided in the form of a transistor to ensure stable performance of the device and increase the device density.
  • a neuromorphic device using a crossbar memory structure includes a plurality of gate electrodes extending parallel to each other in a first direction, and each other in a first direction
  • a plurality of drain electrodes extending side by side and disposed to intersect the first direction between the gate electrodes and the drain electrodes, and at a crossing point of the plurality of source electrodes, the gate electrodes, and the source electrodes formed to extend side by side
  • the tunneling insulating layer, the charge storage layer and the gate insulating layers sequentially stacked in the order adjacent to the source electrode, include the n-type semiconductor layer and the P-type semiconductor layers heterogeneously bonded as a channel layer at the intersection of the drain electrodes and the source electrodes.
  • the source electrodes are presynaptic neuron connectors.
  • Function, and a drain electrode are also functions as a connection terminal postsynaptic neurons, the gate electrode to control the amount of charge stored in the charge storage layer performs the function of regulating the synaptic weights.
  • a method of manufacturing a neuromorphic device using a crossbar memory structure includes forming a plurality of gate electrodes on a substrate so as to extend side by side in a first direction; Forming a gate insulating film at a point where the gate electrodes intersect with the source electrodes below; Forming a charge storage layer on the gate insulating film; Forming a tunneling insulating layer on the charge storage layer; Forming a plurality of source electrodes disposed to intersect the first direction and extending in parallel with each other on an upper portion of the tunneling insulating film; Forming a channel layer on the source electrodes at a point to intersect with drain electrodes below; And forming a plurality of drain electrodes so as to intersect the source electrodes and extend parallel to each other in a first direction on the top of the channel layer, wherein the source electrodes function as a neuron pre-synaptic connector, and the drain electrode After they function as synaptic neurons, the gate electrode controls the amount of charge stored in
  • a method of manufacturing a neuromorphic device using a crossbar memory structure includes forming a plurality of drain electrodes on a substrate so as to extend side by side in a first direction; Forming a channel layer on top of the drain electrodes at a point to intersect with the following source electrodes; Forming a plurality of source electrodes disposed to intersect the first direction and extending parallel to each other on top of the channel layer; Forming a tunneling insulating layer at a point where the gate electrodes intersect with the gate electrodes below the source electrodes; Forming a charge storage layer on top of the tunneling insulating film; Forming a gate insulating film on the charge storage layer; It is disposed to intersect with the source electrodes, and forming a plurality of gate electrodes so as to extend parallel to each other in a first direction on the upper portion of the gate insulating film, wherein the source electrodes function as a neuron pre-synaptic connector, and the drain electrodes After synaps
  • the present invention implements a new type of vertical transistor-based synaptic array by using a crossbar array structure to overcome the limitation of the performance of the existing two-terminal device and at the same time high density of the device. It is effective to secure.
  • FIG. 1 is a perspective view of a neuromorphic device using a crossbar memory structure according to an embodiment of the present invention.
  • FIG. 2 is a diagram illustrating a two-dimensional synaptic device structure of a neuromorphic device according to an exemplary embodiment of the present invention.
  • 3 is a view for explaining the basic operation principle of the conventional vertical transistor.
  • FIG. 4 is a view illustrating a learning principle of a synaptic device implemented by a neuromorphic device according to an exemplary embodiment of the present invention.
  • FIG. 5 is a flowchart illustrating a method of manufacturing a neuromorphic device using a crossbar memory structure according to the first aspect of the present invention.
  • FIG. 6 is a diagram illustrating a detailed process for describing a method of manufacturing a neuromorphic device using the crossbar memory structure of FIG. 5 in detail.
  • FIG. 7 is a flowchart illustrating a method of manufacturing a neuromorphic device using a crossbar memory structure according to a second aspect of the present invention.
  • FIG. 8 is a diagram illustrating a detailed process for describing a method of manufacturing a neuromorphic device using the crossbar memory structure of FIG. 7 in detail.
  • FIG. 9 is a diagram illustrating an energy band diagram of a channel layer of a neuromorphic device according to an embodiment of the present invention.
  • FIG. 10 illustrates a principle for solving a problem of a sneak path occurring in a crossbar array of a neuromorphic device according to an exemplary embodiment of the present invention.
  • FIG. 1 is a perspective view of a neuromorphic device using a crossbar memory structure according to an embodiment of the present invention.
  • FIG. 1A shows a crossbar array structure of a neuromorphic device
  • FIG. 1B shows only one synaptic element part in the crossbar error structure.
  • a neuromorphic device using a crossbar memory structure includes a plurality of gate electrodes extending parallel to each other in a first direction, a plurality of drain electrodes 108 extending parallel to each other in a first direction, and a gate.
  • the drain electrodes 108 and the source electrodes (sequentially stacked in the order adjacent to the source electrode 105)
  • the drain electrodes 108 and the source electrodes At the point of intersection of 105, it comprises n-type semiconductor layers 107 and P-type semiconductor layers 106 heterogeneously bonded as channel layers, wherein source electrodes 105 function as pre-synaptic neuron connectors and drain electrodes.
  • Field 108 is a postsynaptic neuron connector.
  • the gate electrode 101 adjusts the amount of charge stored in the charge storage layer 103 to adjust the synaptic weight.
  • the neuromorphic device using a crossbar memory structure includes an n-type semiconductor layer or a single semiconductor layer of the P-type, in place of the n-type semiconductor layer 107 and the P-type semiconductor layers 106 that are heterogeneously bonded as a channel layer. can do.
  • the tunneling insulating layer 104 may be formed by growing, depositing, or directly transferring silicon dioxide, aluminum oxide, hafnium oxide, hexagonal boron nitride (h-BN), an organic insulator, or the like, and having a thickness below a preset tunneling thickness. Log thickness may be limited.
  • the charge storage layer 103 may be formed by growing, depositing, or coating graphene, reduced graphene oxide (rGO), or gold nanoparticles (AuNPs).
  • the charge storage layer 103 may be formed through a plasma treatment using oxygen (O 2) or carbon tetrafluoride (CF 4) gas on the gate insulating layer 102.
  • FIG. 2 is a diagram illustrating a two-dimensional synaptic device structure of a neuromorphic device according to an exemplary embodiment of the present invention.
  • the neuromorphic device of the present invention uses the channel conductivity based on the output current ID output from the drain electrodes 108 according to an input voltage VS signal applied to the source electrodes 105.
  • the controller may further include a controller (not shown) for checking and adjusting the voltage VG to be applied to the gate electrode 101.
  • the source electrodes 105 may be formed of graphene or reduced graphene oxide whose work function may be adjusted through the gate voltage VG.
  • the controller determines whether the channel conductivity is increased or decreased according to a hardware-based backpropagation algorithm, and when the channel conductivity is increased, a positive voltage is applied to the gate electrode 101, and the channel conductivity is decreased. If is required, a negative voltage may be applied to the gate electrode 101.
  • the control unit (not shown) Determines whether to increase or decrease the channel conductivity according to a hardware-based backpropagation algorithm, applies a negative voltage to the gate electrode 101 when an increase in channel conductivity is required, and the gate electrode 101 when a decrease in channel conductivity is required. Positive voltage can be applied.
  • 3 is a view for explaining the basic operation principle of the conventional vertical transistor.
  • FIG. 4 is a view illustrating a learning principle of a synaptic device implemented by a neuromorphic device according to an exemplary embodiment of the present invention.
  • the synaptic weight updating
  • the spike signal generated in both neurons memoryizing
  • the actual biological synaptic activity is achieved by the interaction of two terminals (presynaptic and postsynaptic neurons).
  • the basic operation of the neuromorphic device using the crossbar memory structure proposed in the present invention is the same as the operation principle of the vertical three-terminal transistor.
  • the vertical transistor uses a material whose Fermi level can be adjusted by an electric field, such as graphene, as the source electrode 105, and the p-type and n-type semiconductor layers (channel layers, 106-107) are used as the source electrode.
  • the current control is performed by the gate electrode 101, the electric field formed by the gate electrode 101 changes the Fermi level of the source electrode 105.
  • the potential barrier height between the source electrode 105 and the channel layers 106-107 changes, and as a result, the current flowing from the source electrode 105 to the channel layers 106-107 is controlled.
  • the neuromorphic synaptic device proposed in the present invention is a vertical three-terminal device, which is composed of a source electrode 105, a drain electrode 108, and a gate electrode 101.
  • the source electrode 105 may function as a presynaptic neuron connection terminal
  • the drain electrode 108 may function as a postsynaptic neuron connection terminal.
  • the heterojunction structure of the p-type semiconductor 106 and the n-type semiconductor 107 is used as the channel layer 106-107 of the synaptic element and at the same time solves the sneak path problem of the crossbar array structure. Can function as a selector to solve.
  • the sneak pass resolution by the heterojunction structure of the P-type semiconductor 106 and the n-type semiconductor 107 will be described later with reference to FIGS. 9 and 10.
  • the tunneling insulating layer 104 and the charge storage layer 103 are inserted between the source electrode 105 and the gate electrode 101 to store charge, thereby allowing the synaptic element of the present invention to have a memory function.
  • the gate electrode 101 may function as a terminal for controlling the weight control function of the synapse by adjusting the amount of charge in the charge storage layer 103.
  • the learning of synaptic devices is accomplished in two steps.
  • the first step is to read the channel's conductivity (synaptic weight or weight) through the device's input, and the second step is to readjust the weight using the read weight.
  • the output current flows through the drain electrode 105 (post-synaptic neuron) according to the input voltage (VS) signal applied to the source electrode (pre-synaptic neuron).
  • the conductivity of the read channel is calculated by using a hardware-based BP algorithm to determine the size and direction of weight control.
  • the controller may be configured based on a hardware-based backpropagation algorithm. If it is determined that the conductivity should be increased, a positive gate voltage may be applied. On the contrary, if it is determined that the conductivity should be reduced, a negative gate voltage may be applied.
  • a voltage VG signal (weight adjustment signal) calculated through the determined weight adjustment value is applied to the gate electrode 101 (weight adjustment terminal). Accordingly, an electron tunneling phenomenon occurs between the material of the source electrode 105 and the charge storage layer 103, and as a result, the charge amount of the charge storage layer 103 is changed to perform a weight control function, and to the charge storage layer 103. The stored charge is retained until the next weight control signal is applied, performing a memory function.
  • the present invention can implement a new type of vertical transistor-based synaptic array using a crossbar array structure to overcome the limitations of the performance of the conventional two-terminal device and at the same time ensure a high device density.
  • the gate electrodes 101 are located on the bottom surface, the drain electrodes 108 are located on the top surface, and the gate insulating films are sequentially formed from the top surfaces of the gate electrodes 101. 102, the charge storage layer 103 and the tunneling insulating film 104 may be stacked.
  • the method of manufacturing the neuromorphic device in which the gate electrode 101 is disposed on the bottom surface and the drain electrode 108 is positioned on the upper surface will be described later with reference to FIGS. 5 and 6.
  • the drain electrodes 108 may be positioned on the bottom surface, the gate electrodes 101 may be positioned on the top surface, and the tunneling insulating layer 104 and the charge storage layer may be sequentially formed from the top surfaces of the drain electrodes 108. 103 and the gate insulating layer 102 may be stacked.
  • a method of manufacturing a neuromorphic device in which the drain electrode 108 is positioned on the bottom surface and the gate electrode 101 is positioned on the top surface will be described later with reference to FIGS. 7 and 8.
  • FIGS. 5 and 6 a method of manufacturing a neuromorphic device using a crossbar memory structure according to the first aspect of the present invention will be described with reference to FIGS. 5 and 6.
  • FIG. 5 is a flowchart illustrating a method of manufacturing a neuromorphic device using a crossbar memory structure according to the first aspect of the present invention.
  • FIG. 6 is a diagram illustrating a detailed process for describing a method of manufacturing a neuromorphic device using the crossbar memory structure of FIG. 5 in detail.
  • a method of manufacturing a neuromorphic device using a crossbar memory structure includes a plurality of gate electrodes 101 to extend parallel to each other in a first direction on the substrate 100
  • Forming S110
  • Forming a charge storage layer 103 (S130), forming a tunneling insulating film 104 on top of the charge storage layer 103 (S140), disposed to intersect with the first direction, and tunneling insulating film 104
  • Board to extend side by
  • the source electrodes 105 function as presynaptic neuron connectors
  • the drain electrodes 108 function as postsynaptic neuron connectors
  • the gate electrode 101 stores the amount of charge stored in the charge storage layer 103. It can adjust the synaptic weight by adjusting the function.
  • the tunneling insulating film 104 is made of the same material as the gate insulating film 102, and may be formed to a thickness ( ⁇ 5nm) to the extent that tunneling is possible.
  • the channel layers 106-107 are composed of a P-type semiconductor layer 106 and an n-type semiconductor layer 107, and include silicon, germanium, group III-V semiconductors, oxide semiconductors, organic semiconductors, and transition metal chalcogen compounds ( It can be formed of any semiconductor material, such as transition metal dichalcogenide) or black phosphorus (phosphorene).
  • 6 (a) to 6 (h) are cross-sectional views showing the cross section of the F portion shown in FIG. 1 (b) on the upper side and a cross section of the S portion on the lower side.
  • the substrate 100 may be formed of silicon (Si), germanium (Ge) substrate or glass, in which a gate insulating layer such as silicon dioxide (SiO 2), aluminum oxide (Al 2 O 3), hafnium oxide (HfO 2) is grown or deposited, It may be formed of a PET film or the like.
  • a gate insulating layer such as silicon dioxide (SiO 2), aluminum oxide (Al 2 O 3), hafnium oxide (HfO 2) is grown or deposited, It may be formed of a PET film or the like.
  • the gate electrodes 101 are deposited on a titanium (Ti) having a large adhesion to the substrate 100 together with metals commonly used as electrodes in a semiconductor process such as platinum (Pt), gold (Au), and palladium (Pd). Can be formed.
  • the gate insulating layer 102 is formed to cross the source electrodes 105 shown in FIG. 4E on the gate electrodes 101.
  • the gate insulating layer 102 may be formed at one point.
  • the gate insulating layer 102 may be formed by growing, depositing, or directly transferring silicon dioxide, aluminum oxide, hafnium oxide, hexagonal boron nitride (h-BN), an organic insulator, or the like.
  • the thickness can be formed in various thicknesses from several nm to several hundred um.
  • the charge storage layer 103 may be formed on the gate insulating layer 102.
  • graphene, reduced graphene oxide (rGO), and gold nanoparticles (AuNPs) may be grown, deposited, or coated to form the charge storage layer 103.
  • graphene may be formed by wet transfer on the gate insulating layer 102, and reduced graphene oxide may be formed by coating on the gate insulating layer 102, and gold nanoparticles may be formed by the gate insulating layer 102. It can be used by being deposited or coated on it.
  • the charge storage layer 103 may be formed on the gate insulating layer 102 by plasma treatment using oxygen (O 2) or carbon tetrafluoride (CF 4) gas.
  • O 2 oxygen
  • CF 4 carbon tetrafluoride
  • a tunneling dielectric 104 may be formed on the charge storage layer 103.
  • the tunneling insulating film 104 is formed by growing, depositing, or directly transferring silicon dioxide, aluminum oxide, hafnium oxide, hexagonal boron nitride (h-BN), or an organic insulator, and having a thickness less than or equal to a preset tunneling thickness. Thickness may be limited.
  • the tunneling insulating layer 104 may have a thickness ( ⁇ 5 nm) such that charges existing in the channel layers 106-107 can tunnel through the gate insulating layer 102 to the charge storage layer 103.
  • step S140 may be performed before step S130. That is, the tunneling insulating film 104 may be formed on the gate insulating film 102, and the charge storage layer 103 may be formed on the tunneling insulating film 104 based on the above-described physical processing.
  • the partial charge storage layer 103 may be formed on the tunneling insulating film 104 through physical treatment, and preferably, an insulating film having a thickness of 20 nm is formed, and the charge storage layer 103 having a thickness of 15 nm is physically processed. And a 5 nm thick tunneling insulating film 104 can be formed.
  • the tunneling insulating film 104 may be formed, and an insulating film may be formed on the tunneling insulating film 104 to form the insulating film as the charge storage layer 103 through physical processing.
  • the gate electrodes 101 are arranged to intersect with the gate electrodes 101 in the first direction and are parallel to each other on the tunneling insulating layer 104. It is possible to form a plurality of source electrodes 105 to extend.
  • the source electrodes 105 may be formed of graphene or reduced graphene oxide whose work function may be adjusted through the gate voltage VG.
  • graphene and reduced graphene oxide can be formed through the transfer and coating process described above.
  • the source electrodes 105 may be disposed on the upper portion of FIG. 6H.
  • the p-type semiconductor layer 106 and the n-type semiconductor layer 107 are sequentially stacked in the order in which the p-type semiconductor layer 106 and the n-type semiconductor layer 107 are intersected in the order in which they are mentioned, or in the reverse order of the mentioned order. -107). That is, in step S160, the process order of the p-type semiconductor layer 106 and the n-type semiconductor layer 107 may be reversed.
  • the p-type semiconductor layer 106 and the n-type semiconductor layer 107 may be formed in various thicknesses from several tens of nm to several hundred um, silicon, germanium, group III-V semiconductor, oxide semiconductor, organic semiconductor, transition It can be formed of any semiconductor material operating in p-type and n-type, such as transition metal dichalcogenide, black phosphorus (phosphorene).
  • silicon, germanium, group III-V semiconductors, oxide semiconductors, organic semiconductors, and the like can be formed using thermal evaporation, e-beam evaporation, sputtering, or the like.
  • a two-dimensional semiconductor material such as a transition metal chalcogen compound, black lean, etc. may be formed by a wet or dry transfer method after growth using a stripping method using a tape and a chemical vacuum deposition method such as CVD.
  • the gate electrodes 101 are perpendicular to the source electrodes 105 on the channel layers 106-107.
  • the drain electrodes 108 may be formed in a direction coincident with the.
  • the drain electrodes 108 may include p-type semiconductor layer 106 in a semiconductor process, such as platinum (Pt), gold (Au), and palladium (Pd) having high work function energy. It may be formed of a metal that is used when forming Ohmic junction.
  • the degenerate n-type semiconductor layer 107 generally has a low work function energy such as titanium (Ti), aluminum (Al), erbium (Er), and the like, when forming ohmic junctions in the n-type semiconductor layer 107 in a semiconductor process. It may be formed of a metal used.
  • the drain electrodes 108 may be formed of a transparent electrode such as graphene or indium tin oxide (ITO).
  • FIGS. 7 and 8 a method of manufacturing a neuromorphic device using a crossbar memory structure according to the second aspect of the present invention will be described with reference to FIGS. 7 and 8. In the case of the configuration to perform the same function among the configuration shown in Figures 5 and 6 described above will be omitted.
  • FIG. 7 is a flowchart illustrating a method of manufacturing a neuromorphic device using a crossbar memory structure according to a second aspect of the present invention.
  • FIG. 8 is a diagram illustrating a detailed process for describing a method of manufacturing a neuromorphic device using the crossbar memory structure of FIG. 7 in detail.
  • a method of manufacturing a neuromorphic device using a crossbar memory structure includes a plurality of drain electrodes to extend parallel to each other in a first direction on the substrate 300 ( Forming 301 (S310), forming a channel layer 302-303 at a point where the drain electrodes 301 intersect with the following source electrodes 304 (S320), first direction And forming a plurality of source electrodes 304 so as to extend parallel to each other on an upper portion of the channel layers 302-303 (S330), and a gate electrode below the upper portions of the source electrodes 304.
  • Forming a gate insulating film 307 on the upper portion of (S360) is disposed to cross the source electrodes 304, Such that the first direction in parallel to each other extending to the top of the tree insulating film 307, and a step (S370) of forming a plurality of gate electrodes (308).
  • the source electrodes 304 function as presynaptic neuron connectors
  • the drain electrodes 301 function as postsynaptic neuron connectors
  • the gate electrode 308 is the amount of charge stored in the charge storage layer 306. It can adjust the synaptic weight by adjusting the function.
  • the method for manufacturing a neuromorphic device using the crossbar memory structure according to the second aspect of the present invention performs the manufacturing process of the neuromorphic device using the crossbar memory structure according to the first aspect of the present invention in the reverse order. It may be one.
  • 8 (a) to 8 (h) are cross-sectional views showing the cross section of the F portion shown in FIG. 1 (b) on the upper side and a cross section of the S portion on the lower side.
  • a plurality of drain electrodes 301 may be formed on the substrate 300 to extend in parallel with each other in the first direction.
  • the channel layers 302 to 303 may be formed by sequentially stacking the n-type semiconductor layer 302 and the P-type semiconductor layers 303 in the aforementioned order or in the reverse order of the aforementioned order. That is, in step S320, the order of the processes of the n-type semiconductor layer 302 and the P-type semiconductor layer 303 may be reversed. In addition, in step S320, instead of stacking the n-type semiconductor layer 302 and the P-type semiconductor layers 303, a single semiconductor layer of n-type or P-type may be formed to form a channel layer.
  • the drain electrodes 301 of the first direction intersect with the channel layers 302-303 formed of the n-type semiconductor layer 302 and the p-type semiconductor layer 303.
  • the source electrodes 304 may be formed so as to extend in parallel with each other.
  • a tunneling insulating layer 305 may be formed on the source electrodes 304 at the point where the gate electrodes 308 intersect with the gate electrodes 308 shown in FIG. 6H. .
  • the charge storage layer 306 may be formed on the tunneling insulating layer 305.
  • a gate insulating layer 307 may be formed on the charge storage layer 306.
  • the gate electrodes 307 intersect the source electrodes 304 on the gate insulating layer 307, and extend in parallel with the drain electrodes 301 in the first direction.
  • a plurality of gate electrodes 308 may be formed.
  • FIG. 9 is a diagram illustrating an energy band diagram of a channel layer of a neuromorphic device according to an embodiment of the present invention.
  • FIG. 10 illustrates a principle for solving a problem of a sneak path occurring in a crossbar array of a neuromorphic device according to an exemplary embodiment of the present invention.
  • the sneak pass means that current flows in an unintended path in the crossbar array structure.
  • the selector is integrated in a synaptic device by forming a channel layer of the neuromorphic device of the present invention as a heterojunction structure (pn junction diode structure) of the p-type semiconductor 106 and the n-type semiconductor 107.
  • the sneak pass problem of the array can be solved.
  • the selector of the neuromorphic device of the present invention corresponds to the channel layer 106-107 formed of the heterojunction structure of the p-type semiconductor 106 and the n-type semiconductor 107.
  • FIG. 9A when the reverse voltage Vd> 0 is applied to the drain electrode 108, a potential barrier between the p-type semiconductor 106 and the n-type semiconductor 107 is obtained. This builds up, which disrupts charge flow and restricts current flow (high resistance).
  • FIG. 9B when the forward voltage Vd ⁇ 0 is applied to the drain electrode 108, the potential barrier between the p-type semiconductor 106 and the n-type semiconductor 107 is lowered and facilitated. This causes the charge to flow and the current flow increases with increasing voltage (low resistance).
  • the present invention when the voltage is applied to a crossbar synaptic array in which a selector is integrated, the present invention may be configured in a forward-reverse-forward direction to three channel layers (three selectors) existing in a sneak path. Voltage is applied. At this time, the device has a very high resistance by the reverse voltage (indicated by the arrow) and prevents current flow, thereby blocking the current to the sneak pass. As a result, the current can only flow in the intended current path and the sneak pass disappears.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Neurology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Molecular Biology (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Health & Medical Sciences (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne, selon un premier aspect, un dispositif neuromorphique faisant appel à une structure de mémoire à entrées croisées comprenant : une pluralité d'électrodes de grille s'étendant en parallèle les unes avec les autres dans une première direction ; une pluralité d'électrodes de drain s'étendant en parallèle les unes avec les autres dans la première direction ; une pluralité d'électrodes de source agencées pour couper la première direction entre les électrodes de grille et les électrodes de drain et s'étendant en parallèle les unes avec les autres ; des films d'isolation à effet tunnel empilés successivement au niveau des intersections des électrodes de grille et des électrodes de source dans un ordre en fonction des contiguïtés des films d'isolation à effet tunnel vers les électrodes de source ; une couche de stockage de charge ; des films d'isolation de grille ; et des couches semi-conductrices de type n et des couches semi-conductrices de type p qui sont reliées de sorte à former une hétérojonction en tant que couche de canal au niveau des intersections des électrodes de drain et des électrodes de source ou une couche semi-conductrice unique de type n ou de type p, les électrodes de source fonctionnant comme des terminaisons de connexion de neurones pré-synaptiques, les électrodes de drain fonctionnant comme des terminaisons de connexion de neurones post-synaptiques et les électrodes de grille remplissant une fonction de régulation des poids synaptiques par la régulation de la quantité de charge stockée dans la couche de stockage de charge.
PCT/KR2019/011325 2018-09-03 2019-09-03 Dispositif neuromorphique faisant appel à une structure de mémoire à entrées croisées WO2020050588A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2018-0104819 2018-09-03
KR1020180104819A KR102167125B1 (ko) 2018-09-03 2018-09-03 크로스바 메모리 구조를 이용한 뉴로모픽 소자

Publications (1)

Publication Number Publication Date
WO2020050588A1 true WO2020050588A1 (fr) 2020-03-12

Family

ID=69722924

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2019/011325 WO2020050588A1 (fr) 2018-09-03 2019-09-03 Dispositif neuromorphique faisant appel à une structure de mémoire à entrées croisées

Country Status (2)

Country Link
KR (1) KR102167125B1 (fr)
WO (1) WO2020050588A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102128474B1 (ko) * 2019-04-26 2020-06-30 삼성전자주식회사 자발 분극 동작 원리를 이용한 뉴런 소자
KR102322131B1 (ko) * 2020-05-04 2021-11-05 고려대학교 산학협력단 확률 가변 멤리스티브 인공 시냅스 소자 및 그 제조 방법
KR102538496B1 (ko) * 2021-02-15 2023-05-30 포항공과대학교 산학협력단 3단자 시냅스 소자를 이용한 뉴로모픽 시스템
KR102544394B1 (ko) * 2021-08-05 2023-06-16 포항공과대학교 산학협력단 3차원 수직형 메모리 소자 및 그 제조 방법
KR102590585B1 (ko) * 2021-08-10 2023-10-16 고려대학교 산학협력단 3 전극 대각 멤트랜지스터 시스템, 이를 이용한 컨볼루션 네트워크 연산 장치 및 방법
KR102645354B1 (ko) * 2021-08-17 2024-03-11 서울대학교산학협력단 3차원 적층형 시냅스 스트링 및 이를 이용한 3차원 적층형 시냅스 어레이 및 3차원 적층형 시냅스 스트링의 제조 방법
KR20230101577A (ko) 2021-12-29 2023-07-06 한국전자통신연구원 대규모 입력 뉴런 처리가 가능한 크로스바 기반의 뉴로모픽 컴퓨팅 장치 및 이를 이용한 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180035251A (ko) * 2016-09-28 2018-04-06 포항공과대학교 산학협력단 가중치 소자 및 이의 방법
KR20180072942A (ko) * 2016-12-22 2018-07-02 서울대학교산학협력단 반도체 물질의 입계를 전하저장소로 이용하는 반도체 소자
US10026896B2 (en) * 2015-02-13 2018-07-17 Hewlett Packard Enterprise Development Lp Multilayered memristors
KR20180086152A (ko) * 2017-01-20 2018-07-30 한양대학교 산학협력단 3차원 뉴로모픽 소자 및 그 제조방법
KR20180093687A (ko) * 2017-02-14 2018-08-22 서울대학교산학협력단 뉴로모픽 시스템, 및 기억 장치

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101328261B1 (ko) * 2012-01-20 2013-11-14 세종대학교산학협력단 3차원 저항 변화 메모리 및 그 구동방법
KR101517915B1 (ko) 2014-01-29 2015-05-06 서울대학교산학협력단 셀 스트링 및 이를 이용한 어레이
KR102609301B1 (ko) * 2015-12-30 2023-12-05 에스케이하이닉스 주식회사 서로 다른 폭들을 갖는 게이팅 라인들을 포함하는 뉴로모픽 소자
KR101766659B1 (ko) * 2016-06-30 2017-08-09 명지대학교 산학협력단 저항 스위칭 및 이력현상의 변화를 이용한 코티솔 검출용 바이오센서, 이의 제조방법 및 응용

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10026896B2 (en) * 2015-02-13 2018-07-17 Hewlett Packard Enterprise Development Lp Multilayered memristors
KR20180035251A (ko) * 2016-09-28 2018-04-06 포항공과대학교 산학협력단 가중치 소자 및 이의 방법
KR20180072942A (ko) * 2016-12-22 2018-07-02 서울대학교산학협력단 반도체 물질의 입계를 전하저장소로 이용하는 반도체 소자
KR20180086152A (ko) * 2017-01-20 2018-07-30 한양대학교 산학협력단 3차원 뉴로모픽 소자 및 그 제조방법
KR20180093687A (ko) * 2017-02-14 2018-08-22 서울대학교산학협력단 뉴로모픽 시스템, 및 기억 장치

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BING CHEN: "Highly Compact and Well Behaved Nano-Pillar Transistor Controlled Resistive Switching Cell for Neuromorphic System Application", SCIENTIFIC REPORTS, vol. 4, 31 October 2014 (2014-10-31), pages 6863, XP055689741, Retrieved from the Internet <URL:https://www.nature.com/articles/srep06863.pdf?platform=oscar&draft=collection> *

Also Published As

Publication number Publication date
KR20200026626A (ko) 2020-03-11
KR102167125B1 (ko) 2020-10-16

Similar Documents

Publication Publication Date Title
WO2020050588A1 (fr) Dispositif neuromorphique faisant appel à une structure de mémoire à entrées croisées
Sun et al. Synaptic devices based neuromorphic computing applications in artificial intelligence
Zhang et al. Recent progress in photonic synapses for neuromorphic systems
Jiang et al. Emerging synaptic devices: from two-terminal memristors to multiterminal neuromorphic transistors
Wang et al. Reconfigurable optoelectronic memristor for in-sensor computing applications
Ham et al. One-dimensional organic artificial multi-synapses enabling electronic textile neural network for wearable neuromorphic applications
Song et al. Recent advances and future prospects for memristive materials, devices, and systems
US10083974B1 (en) Floating memristor
KR101695737B1 (ko) 흥분/억제 기능을 포함하는 신경 모방 소자
WO2021033906A1 (fr) Dispositif neuromorphique tridimensionnel ayant de multiples synapses par neurone
Bian et al. Neuromorphic computing: Devices, hardware, and system application facilitated by two-dimensional materials
US20180293487A1 (en) Architecture for an electrochemical artificial neural network
US10768502B2 (en) Synaptic electronic devices with electrochromic device
US20210026601A1 (en) Semiconductor device and multiply-accumulate operation device
Cheng et al. Proton conductor gated synaptic transistor based on transparent IGZO for realizing electrical and UV light stimulus
KR102009569B1 (ko) 3차원 구조의 시냅스 소자 및 이의 제조 방법
Li et al. Synaptic and gradual conductance switching behaviors in CeO2/Nb–SrTiO3 heterojunction memristors for electrocardiogram signal recognition
US11121259B2 (en) Metal-oxide-based neuromorphic device
US11586899B2 (en) Neuromorphic device with oxygen scavenging gate
Pereira et al. Flexible active crossbar arrays using amorphous oxide semiconductor technology toward artificial neural networks hardware
Chen et al. Intelligent Optoelectronic Devices for Next‐Generation Artificial Machine Vision
KR20220155699A (ko) 인공 시냅스 모방 이종 인터페이스 포토트랜지스터 및 이의 제조 방법
WO2023018177A1 (fr) Système de memtransistor diagonal à trois électrodes, et dispositif de fonctionnement de réseau à convolution et procédé de fonctionnement qui utilisent ce dernier
KR20180052819A (ko) 재구성 가능한 신경모방 소자 및 어레이
WO2021054728A1 (fr) Procédé de fabrication d&#39;élément de résistance différentielle négative

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19858286

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19858286

Country of ref document: EP

Kind code of ref document: A1