WO2020043218A1 - 一种瞬态电压抑制器件及其制造方法 - Google Patents

一种瞬态电压抑制器件及其制造方法 Download PDF

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Publication number
WO2020043218A1
WO2020043218A1 PCT/CN2019/104395 CN2019104395W WO2020043218A1 WO 2020043218 A1 WO2020043218 A1 WO 2020043218A1 CN 2019104395 W CN2019104395 W CN 2019104395W WO 2020043218 A1 WO2020043218 A1 WO 2020043218A1
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well
doped region
region
conductivity type
doped
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PCT/CN2019/104395
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English (en)
French (fr)
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程诗康
顾炎
张森
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无锡华润上华科技有限公司
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Priority to JP2021510014A priority Critical patent/JP7077478B2/ja
Priority to US17/265,541 priority patent/US11233045B2/en
Publication of WO2020043218A1 publication Critical patent/WO2020043218A1/zh

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66098—Breakdown diodes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a transient voltage suppression device, and also relates to a method for manufacturing a transient voltage suppression device.
  • TVS Transient Voltage Suppressor, transient voltage suppressor
  • I / O interfaces the high-speed interface represented by HDMI (High-Definition Multimedia Interface) is getting faster and faster, even up to 5Gbps.
  • HDMI High-Definition Multimedia Interface
  • the capacitors for ESD protection at the interface have extremely strict Requirements; in addition, there are hundreds of pins in the actual driver chip, each of which has ESD risk. In order to protect as many I / O ports as possible while not occupying too much area, this There are higher requirements for TVS integration.
  • the traditional TVS capacitor composed of a single avalanche diode is quite large, usually at least tens of picofarads. As the ESD capability increases, the capacitance value also increases in proportion. When used for high-speed interfaces, higher capacitance values will seriously affect the data. Integrity.
  • the solution is usually to connect a low-capacitance diode in series with a TVS avalanche diode to achieve a unidirectional low-capacitance TVS.
  • both the front and back of the chip need to introduce metal electrodes to ground.
  • the front and back electrodes are shorted together and grounded together through metal wires during packaging.
  • the increase of the length of the wire leads to the increase of its parasitic resistance and inductance, and the performance of the chip will decrease under high frequency operation.
  • a transient voltage suppression device includes: a substrate of a second conductivity type; a well region of a first conductivity type provided on the substrate including a first well and a second well; and a third well provided in the The substrate is of a second conductivity type, and the bottom of the third well extends to the substrate; the first conductivity type and the second conductivity type are opposite conductivity types; a fourth well is provided on the substrate The first well is of a second conductivity type; an isolation structure includes a first isolation portion provided between the first well and a second well, and an isolation structure provided between the first well and the first well.
  • a method for manufacturing a transient voltage suppression device includes: forming a mask layer on a substrate of a second conductivity type, and then photolithography and etching the mask layer to expose a well region of the second conductivity type.
  • a doped window ; doping a second conductivity type ion through the second conductivity type well region doping window to form a second region on the substrate surface; growing an oxide layer on the second region as a doping barrier layer; Removing the mask layer, doping a first conductivity type ion at a position on the substrate surface not covered by the doping barrier layer to form a first region; the first conductivity type and the second conductivity type are opposite conductivity types; removing
  • the doping barrier layer forms an isolation structure, the isolation structure includes a second isolation portion extending downward from a boundary between the first region and the second region, and partitioning the first region into two A portion of the first isolation portion; a thermal push well to diffuse the first region to form a first well and a second well separated by the first isolation portion to diffuse
  • the metal connection layer includes a first metal connection and a second metal connection.
  • the first metal connection electrically connects the first doped region and the sixth doped region.
  • the second connection is used as the first potential terminal, and the second metal connection is used to electrically connect the second doped region, the third doped region, and the fourth doped region as the second potential terminal;
  • the well is of a second conductivity type and is formed in the first well;
  • the first doped region is of a first conductivity type and is formed in the second well;
  • the second doped region is of a second conductivity type Is formed in the third well;
  • the third doped region is of the second conductivity type and is formed in the fourth well;
  • the fourth doped region is of the first conductivity type and is formed in the first well Four wells;
  • the fifth doped region is of a first conductivity type, extends from the fourth well to the outside of the fourth well, and a portion outside the fourth well is located in the first well
  • the sixth doping is a second
  • the diode D1 formed by the first doped region, the second well, the substrate, the third well, and the second doped region is in the forward direction.
  • the bleeder current can be drawn out directly through the metal wiring layer on the front of the chip to avoid parasitic resistance and inductance from affecting the chip performance due to the addition of metal lead wires on the back of the substrate.
  • FIG. 1 is a schematic structural diagram of a transient voltage suppression device in an embodiment
  • FIG. 2 is a schematic diagram of an equivalent circuit of the transient voltage suppression device of FIG. 1;
  • FIG. 3 is a flowchart of a method for manufacturing a transient voltage suppression device according to an embodiment
  • 4a to 4d are schematic cross-sectional views of the transient voltage suppression device manufactured by the method shown in FIG. 3 during the manufacturing process.
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present invention should not be limited to the specific shape of the region shown here, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle generally has round or curved features and / or implanted concentration gradients at its edges, rather than a binary change from the implanted region to the non-implanted region. Likewise, a buried area formed by implantation may result in some implantation in the area between the buried area and the surface through which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • P + type is simply referred to as P-type with heavy doping concentration.
  • P-type doping concentration P-type represents lightly doped P-type
  • N + type represents heavily doped N-type
  • N-type represents medium-doped N-type
  • N-type represents lightly-doped N type.
  • FIG. 1 is a schematic structural diagram of a transient voltage suppression device according to an embodiment, including a substrate 112, a first well 122, a second well 124, a third well 132, a fourth well 134, a first isolation portion 172, and a second isolation. Portion 174, first doped region 142, second doped region 152, third doped region 154, fourth doped region 144, fifth doped region 146, sixth doped region 156, seventh doped region 157.
  • the first metal connection 162 and the second metal connection 164 are examples of a transient voltage suppression device according to an embodiment, including a substrate 112, a first well 122, a second well 124, a third well 132, a fourth well 134, a first isolation portion 172, and a second isolation. Portion 174, first doped region 142, second doped region 152, third doped region 154, fourth doped region 144, fifth doped region 146, sixth doped region 156, seventh doped region
  • the substrate 112 is of a second conductivity type.
  • the first well 122, the second well 124, and the third well 132 are disposed on the substrate 112, and the bottom of the third well 132 extends downward to the substrate 112.
  • the fourth well 134 is disposed in the first well 122.
  • the first isolation portion 172 is disposed between the first well 122 and the second well 124, and the second isolation portion 174 is disposed between the first well 122 and the third well 132.
  • the first isolation portion 172 is used to isolate the first well 122 and the second well 124, and the second isolation portion 174 is used to isolate the first well 122 and the third well 132.
  • the first doped region 142 is a first conductivity type (doped region) and is provided in the second well 124; the second doped region 152 is a second conductivity type and is provided in the third well 132; the third doped region
  • the region 154 is of the second conductivity type and is provided in the fourth well 134; the fourth doped region 144 is of the first conductivity type and is provided in the fourth well 134; the fifth doped region 146 is of the first conductivity type, from the first
  • the four wells 134 extend outside the fourth well 134, and a portion outside the fourth well 134 is located in the first well 122, that is, a portion of the fifth doped region 146 is located in 134, and a portion is located in the first portion outside the fourth well 134.
  • the sixth doped region 156 is of the second conductivity type and is provided in the first well 122; the seventh doped region 157 is of the second conductivity type and is provided under the fifth doped region 146; 122; and the fifth doped region 146 is provided between the fourth doped region 144 and the sixth doped region 156, and the fourth doped region 144 is provided between the third doped region 154 and the fifth doped region 146 between.
  • the sixth doped region 156 is of the second conductivity type and is provided in the first well 122;
  • the seventh doped region 157 is of the second conductivity type and is provided under the fifth doped region 146; 122; and the fifth doped region 146 is provided between the fourth doped region 144 and the sixth doped region 156, and the fourth doped region 144 is provided between the third doped region 154 and the fifth doped region 146 between.
  • FIG. 2 is a schematic diagram of an equivalent circuit of the transient voltage suppression device of FIG. 1.
  • the first doped region 142 serves as the cathode region of the diode D1
  • the second doped region 152 serves as the anode region of the diode D1
  • the sixth doped region 156 serves as the emitter region of the PNP transistor
  • the fifth doped region 146 serves as PNP.
  • a parasitic resistance R1 is equivalently formed between the seventh doped region 157 and the third doped region 154, and a sixth diode 156 and the fifth doped region 146 are equivalently formed with a diode D2.
  • the PNP transistor and the NPN transistor are equivalent to a SCR.
  • the bleeder current can be drawn out directly through the metal wiring layer on the front side of the chip, so as to avoid the metal extraction on the back side of the substrate. Line, causing parasitic resistance and inductance to affect chip performance.
  • the thyristor current capability (the ability to leak and amplify current) is stronger than ordinary PIN diodes and Zener diodes, the current capability of negative pulse ESD can be greatly improved.
  • the transient voltage suppression device further includes an epitaxial layer 114 provided on the substrate 112, the first well 122 and the second well 124 are provided in the epitaxial layer 114, and the epitaxial layer 114 is the second For a conductive type epitaxial layer, the doping concentration of the substrate 112 is greater than that of the epitaxial layer 114.
  • the epitaxial layer 114 is a P-epitaxial layer.
  • the first conductivity type well region ie, the first well 122 and the second well 124) are both deep N wells (DN), and the second conductivity type well region (including the third well 132). Both are deep P-wells (DP).
  • DN deep N wells
  • DP deep P-wells
  • the first isolation portion 172 and the second isolation portion 174 are isolation structures filled with an insulating material in the isolation trenches.
  • the insulating material may be silicon dioxide, polysilicon, or the like, or a combination thereof.
  • the isolation structure may adopt a single-slot structure of the second isolation portion 174, or a dual-slot structure of the first isolation portion 172, or even a multi-slot structure. Generally, it is considered that more than two slots are more effective than a single-slot isolation. it is good.
  • the groove depth of the second isolation portion 174 is greater than or equal to the well depth of the third well 126 to obtain a better isolation effect.
  • an insulating structure is provided on the fifth doped region 146.
  • FIG. 3 is a flowchart of a method for manufacturing a transient voltage suppression device according to an embodiment, including the following steps:
  • a mask layer is formed on the substrate, and the mask layer is lithographically and etched to expose the doped window of the second conductivity type well region.
  • FIG. 4a and FIG. 4b Please refer to FIG. 4a and FIG. 4b together.
  • a layer of photoresist 184 on the surface of the mask layer 182, and then expose and develop the photoresist 184 to form a second layer.
  • the conductive type well region is doped with a pattern of the window, and then the mask layer 182 not covered by the photoresist is etched to expose the second conductive type well region doped window.
  • an epitaxial layer 114 is further formed on the substrate 112, and the doping concentration of the substrate 112 is greater than that of the epitaxial layer 114.
  • a mask layer 182 is formed on the epitaxial layer 114.
  • the mask layer 182 is a hard mask.
  • the hard mask may be a silicon nitride layer.
  • a sacrificial oxide layer 171 may be further formed on the surface of the substrate 112 before the hard mask is formed.
  • the sacrificial oxide layer 171 at the corresponding position needs to be removed.
  • the hard mask may be formed by depositing silicon nitride, and the sacrificial oxide layer 171 may be formed by thermally growing an oxide layer.
  • the substrate 112 is a semiconductor substrate, and the material thereof may be undoped single crystal silicon, impurity-doped single crystal silicon, silicon on insulator (SOI), silicon on insulator (SSOI), Silicon germanium (S-SiGeOI), silicon germanium (SiGeOI) on insulator and germanium on insulator (GeOI) are laminated on the insulator.
  • SOI silicon on insulator
  • SSOI silicon on insulator
  • SiGeOI Silicon germanium
  • SiGeOI silicon germanium
  • germanium (SiGeOI) on insulator and germanium on insulator (GeOI) are laminated on the insulator.
  • P-type impurity ions are implanted through an ion implantation process to form a second region 131 on the surface of the epitaxial layer 114, as shown in FIG. 4b.
  • An oxide layer is grown on the second region as a doping barrier layer.
  • an oxide layer is grown on the surface of the epitaxial layer 114 after the photoresist 184 is removed. Since the region outside the doped window of the second conductivity type well region is covered by the mask layer 182 (difficult to be oxidized), it will only A doped barrier layer 173 is formed in the doped window of the second conductivity type well region, see FIG. 4c.
  • step S330 is to grow silicon dioxide with a thickness of 3000 angstroms to 5000 angstroms on the surface of the epitaxial layer 114.
  • S340 Remove the mask layer, and dope a first conductivity type ion to form a first region.
  • N-type impurity ions are implanted through an ion implantation process.
  • the first region 121 is formed only at a position outside the second region 131. It can be understood that, in other embodiments, the first region 121 may also be formed by implanting P-type ions, and the second region is correspondingly formed by implanting N-type ions.
  • the isolation structure includes a second isolation portion formed at a junction of the first region 121 and the second region 131, and a first isolation portion that divides the first region 121 into two parts.
  • S360 The well is pushed hot, so that the first region and the second region are diffused to form a well region.
  • the first region 121 is diffused to form a first well 122 and a second well 124 separated by the first isolation portion 172 by thermally pushing the well, and the second region 131 is diffused to form a third well 132.
  • the first isolation portion 172 and the second isolation portion 174 are both isolation structures filled with an insulating material in the isolation trenches.
  • the insulating material may be silicon dioxide, polysilicon, or the like, or a combination thereof.
  • the isolation structure may adopt a single-slot structure of the second isolation portion 174, or a dual-slot structure of the first isolation portion 172, or even a multi-slot structure. Generally, it is considered that more than two slots are more effective than a single-slot isolation. it is good.
  • the bottom of the third well 132 extends to the substrate 112 after the thermal push well is completed.
  • the first doped region 142 is a first conductivity type (doped region) and is provided in the second well 124; the second doped region 152 is a second conductivity type and is provided in the third well 132;
  • the third doped region 154 is of the second conductivity type and is provided in the fourth well 134;
  • the fourth doped region 144 is of the first conductivity type and is provided in the fourth well 134;
  • the fifth doped region 146 is of the first conductivity Type, extending from the fourth well 134 to the fourth well 134, and a portion outside the fourth well 134 is located in the first well 122, that is, a portion of the fifth doped region 146 is located in 134 and a portion is located in the fourth well
  • the sixth doped region 156 is of the second conductivity type and is provided in the first well 122;
  • the seventh doped region 157 is of the second conductivity type and is provided under the fifth doped region 146 And the first well
  • the metal connection layer includes a first metal connection 162 and a second metal connection 164.
  • the first metal connection 162 electrically connects the first doped region 142 and the sixth doped region 156 as a first potential terminal
  • the second metal connection 164 connects the second doped region 152, the third doped region 154
  • the fourth doped region 144 is electrically connected as a second potential terminal.
  • the doping concentration of the third well 132 is 5E18 cm -3 to 5E19 cm -3 .
  • the electronic current passes from the input / output port I / O through the first doped region 142, the second well 124, the epitaxial layer 114, the substrate 112, and the third well 132. 2.
  • the second doped region 132 enters the ground GND.
  • the third well 132 (DP) is connected to the substrate 122 (P +)
  • the epitaxial layer 114 is between the second well 124 and the substrate 112, when the diode D1 is reverse biased, the reverse PN junction concentration formed by the second well 124 and the epitaxial layer 114 is very light. Depletion will be sufficient and the parasitic capacitance generated will be small.
  • the doping concentration of the first well 122 and the second well 124 is 1E14cm -3 to 1E15cm -3
  • the doping concentration of the epitaxial layer 114 is 1E14cm -3 to 1E15cm -3 .
  • step S370 specifically includes:
  • the first implantation lithography is used to lithography and implant P-type ions, and then the well is pushed to form a fourth well 134; the photoresist is removed, and the second implantation lithography is used to etch and implant P-type ions to form a second dopant.
  • the photoresist is removed, and a third implantation lithography is used to lithography and N-type ions are implanted to form a first doped region 142 and a fourth doped region.
  • the impurity region 144 and the fifth doped region 146 are removed.
  • the photoresist is removed, photolithography is performed using a fourth implantation reticle, and P-type ions are implanted to form a seventh doped region 157.
  • step S380 includes: photolithography and etching, forming a second isolation trench at the boundary of the first region 121 and the second region 131, and forming a first separating the first region 121 into two parts. Isolation trench; filling the trench with insulating material.
  • step S350 before photolithography, in step S350, a layer of silicon dioxide is deposited, followed by coating, exposure, and development to form an etched area of the isolation trench, and dry etching is performed to form a deep trench, and then to The deep trench is filled with insulating material, and then the filled insulating material is dry-etched back to flatten the wafer surface.
  • the third well 132 and the first well 122 are completely isolated, so that during the process of pushing the well at high temperature, the lateral diffusion becomes larger due to the high concentration of the third well 132, which increases the area required by the chip. .
  • the implantation dose of the seventh doped region 157 by ion implantation in step S370 is 1E14 cm -2 to 5E14 cm -2 .
  • the implantation dose of the fourth well 134 by ion implantation is 5E12 cm -2 to 5E13 cm -2 .
  • step S370 and before step S380 the following steps are further included:
  • a dielectric layer is formed.
  • an interlayer dielectric ILD
  • ILD interlayer dielectric
  • a contact hole is formed, and a conductive material is filled in the contact hole.
  • the contact layer may be formed by etching the dielectric layer after photolithography.
  • the conductive material may be any suitable conductive material well known to those skilled in the art, including but not limited to metal materials; wherein the metal materials may include Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti Or Ta, W, and Al. In one embodiment, a dry etching process is used to etch the dielectric layer.
  • step S380 forms a metal wiring layer on the dielectric layer. Specifically, after the metal is deposited, the metal layer is lithographically and etched to form a metal wiring layer. In one embodiment, the metal layer is etched by a dry etching process.
  • the method further includes a step of forming a passivation layer, and a step of photolithography and etching the passivation layer to form a metal electrode.
  • the interlayer dielectric may be a silicon oxide layer, including doped or undoped silicon oxide formed using a thermal chemical vapor deposition (CVD) manufacturing process or a high-density plasma (HDP) manufacturing process.
  • Material layers such as undoped silica glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG).
  • the interlayer dielectric may also be boron or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetra-ethoxysilane (PTEOS). Ethoxysilane (BTEOS).
  • the deposited interlayer dielectric may be planarized by a planarization method (such as chemical mechanical polishing CMP), so that the interlayer dielectric has a flat surface.
  • a planarization method such as chemical mechanical polishing CMP

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Abstract

一种瞬态电压抑制器件及其制造方法，所述瞬态电压抑制器件包括：衬底（112）；第一导电类型阱区，设于衬底（112）中，包括第一阱（122）、第二阱（124）；第三阱（132），设于衬底（112）上，第三阱（132）的底部延伸至衬底（112）；第四阱（134），设于第一阱（122）中；第一掺杂区（142），设于第二阱（124）中；第二掺杂区（152），设于第三阱（132）中；第三掺杂区（154），设于第四阱（134）中；第四掺杂区（144），设于第四阱（134）中；第五掺杂区（154），从第四阱（134）中延伸至第四阱（134）外，且位于第四阱（134）外的部分位于第一阱（122）中；第六掺杂区（156），设于第一阱（122）中；第七掺杂区（157），设于第五掺杂区（146）下方、第一阱（122）中。

Description

一种瞬态电压抑制器件及其制造方法 技术领域
本发明涉及半导体制造领域，特别是涉及一种瞬态电压抑制器件，还涉及一种瞬态电压抑制器件的制造方法。
背景技术
在整机和系统中常常会遇到意外的电压瞬变和浪涌，造成整机和系统中的半导体器件被烧毁或击穿，从而导致整机和系统的损坏。因此TVS(Transient Voltage Suppressor，瞬态电压抑制器)作为一种PN结高效保护器件，由于其响应时间快、抗ESD能力强，被广泛的应用于各类I/O接口。目前以HDMI(High-Definition Multimedia Interface，高清晰度多媒体接口)为代表的高速接口传输速率越来越快，甚至高达5Gbps，为了保证数据完整性，对于接口处ESD防护的电容有着及其严格的要求；另外在实际的驱动芯片中，管脚数目有的多达几百个，其中每个管脚都存在ESD风险，为了尽量保护更多的I/O口同时不占用太大的面积，这对于TVS的集成度有了更高的要求。
传统的由单一雪崩二极管构成的TVS电容相当大，一般至少几十皮法，随着ESD能力的增大，电容值也同比例增大，用于高速接口时较高的电容值会严重影响数据的完整性。解决办法通常是将一个低电容的二极管与TVS雪崩二极管串联，来实现单向低电容TVS。
在一种传统的瞬态电压抑制器件结构中，芯片的正面和背面都需要引入金属电极进行接地，封装时一般通过金属线将正面和背面的电极进行短接并一起接地，此时由于金属键合线长度的增加，导致其寄生的电阻、电感的增大，芯片在高频工作下性能会下降。
发明内容
基于此，有必要提供一种新型结构的瞬态电压抑制器件及其制造方法。
一种瞬态电压抑制器件，包括：衬底，为第二导电类型；第一导电类型阱区，设于所述衬底上，包括第一阱和第二阱；第三阱，设于所述衬底上，为第二导电类型，所述第三阱的底部延伸至所述衬底；所述第一导电类型和第二导电类型为相反的导电类型；第四阱，设于所述第一阱中，为第二导电类型；隔离结构，所述隔离结构包括设于所述第一阱和第二阱之间的第一隔离部，以及设于所述第一阱和所述第三阱之间的第二隔离部，所述第一隔离部用于将所述第一阱和第二阱相隔离，所述第二隔离部用于将所述第一阱和第三阱相隔离；第一掺杂区，为第一导电类型，设于所述第二阱中；第二掺杂区，为第二导电类型，设于所述第三阱中；第三掺杂区，为第二导电类型，设于所述第四阱中；第四掺杂区，为第一导电类型，设于所述第四阱中；第五掺杂区，为第一导电类型，从所述第四阱中延伸至所述第四阱外，且位于第四阱外的部分位于所述第一阱中；第六掺杂区，为第二导电类型，设于所述第一阱中；第七掺杂区，为第二导电类型，设于所述第五掺杂区下方、所述第一阱中；所述第五掺杂区设于所述第四掺杂区和第六掺杂区之间，所述第四掺杂区设于所述第三掺杂区和第五掺杂区之间；金属连线层，包括第一金属连线和第二金属连线，位于所述衬底上，所述第一金属连线电性连接所述第一掺杂区和第六掺杂区作为第一电位端，所述第二金属连线电性连接所述第二掺杂区、第三掺杂区和第四掺杂区作为第二电位端。
一种瞬态电压抑制器件的制造方法，所述方法包括：在第二导电类型的衬底上形成掩膜层，然后光刻并刻蚀所述掩膜层，露出第二导电类型阱区掺杂窗口；通过所述第二导电类型阱区掺杂窗口掺杂第二导电类型离子，在所述衬底表面形成第二区域；在所述第二区域上生长氧化层作为掺杂阻挡层；去除所述掩膜层，在衬底表面未被掺杂阻挡层覆盖的位置掺杂第一导电类型离子形成第一区域；所述第一导电类型和第二导电类型为相反的导电类型； 去除所述掺杂阻挡层，并形成隔离结构，所述隔离结构包括从所述第一区域和第二区域的交界处向下延伸的第二隔离部，以及将所述第一区域分隔成两个部分的第一隔离部；热推阱，使所述第一区域扩散形成被所述第一隔离部分隔开的第一阱和第二阱，使所述第二区域扩散形成第三阱；通过光刻和掺杂，分别形成第四阱、第一掺杂区、第二掺杂区、第三掺杂区、第四掺杂区、第五掺杂区、第六掺杂区及第七掺杂区；在所述衬底上形成金属连线层，所述金属连线层包括第一金属连线和第二金属连线，所述第一金属连线将所述第一掺杂区和第六掺杂区电性连接作为第一电位端，所述第二金属连线将所述第二掺杂区、第三掺杂区和第四掺杂区电性连接作为第二电位端；其中，所述第四阱为第二导电类型，形成于所述第一阱中；所述第一掺杂区为第一导电类型，形成于所述第二阱中；所述第二掺杂区为第二导电类型，形成于所述第三阱中；所述第三掺杂区为第二导电类型，形成于所述第四阱中；所述第四掺杂区为第一导电类型，形成于所述第四阱中；所述第五掺杂区为第一导电类型，从所述第四阱中延伸至所述第四阱外，且位于第四阱外的部分位于所述第一阱中；所述第六掺杂为第二导电类型，形成于所述第一阱中；所述第七掺杂区为第二导电类型，形成于所述第五掺杂区下方、所述第一阱中；所述第五掺杂区形成于所述第四掺杂区和第六掺杂区之间，所述第四掺杂区形成于所述第三掺杂区和第五掺杂区之间。
上述瞬态电压抑制器件及其制造方法，由于第三阱与衬底连接，在由第一掺杂区、第二阱、衬底、第三阱、第二掺杂区构成的二极管D1正向偏置时，可直接通过芯片正面的金属连线层将泄放电流引出，避免由于在衬底背面增加金属引出线，导致寄生的电阻和电感影响芯片性能。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式 中的任何一者的范围的限制。
图1是一实施例中瞬态电压抑制器件的结构示意图；
图2为图1的瞬态电压抑制器件的等效电路原理示意图；
图3是一实施例中瞬态电压抑制器件的制造方法的流程图；
图4a～图4d是采用图3所示方法制造的瞬态电压抑制器件在制造过程中的剖面示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与为本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重 掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中瞬态电压抑制器件的结构示意图，包括衬底112、第一阱122、第二阱124、第三阱132、第四阱134、第一隔离部172、第二隔离部174、第一掺杂区142、第二掺杂区152、第三掺杂区154、第四掺杂区144、第五掺杂区146、第六掺杂区156、第七掺杂区157、第一金属连线162、第二金属连线164。
其中衬底112为第二导电类型。第一阱122、第二阱124及第三阱132设于衬底112上，第三阱132的底部向下延伸至衬底112。第四阱134设于第一阱122中。
第一隔离部172设于第一阱122和第二阱124之间，第二隔离部174设于第一阱122和第三阱132之间。第一隔离部172用于将第一阱122和第二阱124相隔离，第二隔离部174用于将第一阱122和第三阱132相隔离。
第一掺杂区142为第一导电类型(的掺杂区)，设于第二阱124中；第二掺杂区152为第二导电类型，设于第三阱132中；第三掺杂区154为第二导电类型，设于第四阱134中；第四掺杂区144为第一导电类型，设于第四阱134中；第五掺杂区146为第一导电类型，从第四阱134中延伸至第四阱134外，且位于第四阱134外的部分位于第一阱122中，即第五掺杂区146的一部分位于134中，一部分位于第四阱134外的第一阱122中；第六掺杂区156为第二导电类型，设于第一阱中122；第七掺杂区157为第二导电类型，设于第五掺杂区146下方、第一阱122中；且第五掺杂区146设于第四掺杂区144和第六掺杂区156之间，第四掺杂区144设于第三掺杂区154和第五掺杂区146之间。在图1所示的实施例中，第一导电类型为N型，第二导电类型为P型，衬底112为重掺杂P型(P+)衬底，第一阱122、第二阱124为N阱，第三阱132、第四阱134阱区为P阱；在其他实施例中，也可以是第一导电类型为P型，第二导电类型为N型。
在衬底上形成有金属连线层，金属连线层包括第一金属连线162和第二金属连线164，第一金属连线162位于衬底112上，电性连接第一掺杂区142 和第六掺杂区156作为第一电位端，用于连接电性连接输入输出端口(I/O端口)；第二金属连线164位于衬底112上，电性连接第二掺杂区152、第三掺杂区154和第四掺杂区144作为第二电位端，用于接地(GND)。
图2为图1的瞬态电压抑制器件的等效电路原理示意图。其中，第一掺杂区142作为二极管D1的阴极区，第二掺杂区152作为二极管D1的阳极区，第六掺杂区156作为PNP三极管的发射极区，第五掺杂区146作为PNP三极管的基极区(同时作为NPN三极管的集电极区和齐纳二极管Z1的阴极区)，第七掺杂区157作为PNP三极管的集电极区(同时作为NPN三极管的基极区和齐纳二极管Z1的阳极区)，第四掺杂区144作为NPN三极管的发射极区。另外，第七掺杂区157和第三掺杂区154之间等效形成有寄生电阻R1，第六掺杂区156和第五掺杂区146等效形成有一个二极管D2。PNP三极管和NPN三极管等效为一个可控硅(SCR)。
上述瞬态电压抑制器件能够实现输入输出端口I/O到地GND的防护。当正的瞬时脉冲信号从输入输出端口I/O进入，此时二极管D1和齐纳二极管Z1都是反向偏置。对于应用在5V工作电压(VDD)的TVS产品，齐纳二极管Z1的耐压通常设置在6～7V，由于二极管D1反向击穿耐压很高，而齐纳二极管Z1反向击穿耐压电压较低，因此在正的脉冲信号的作用下PNP三极管将首先开启，此时PNP三极管的集电极电流将流向地GND。但是在空穴电流流过的地方，由于寄生电阻的R1存在，使得NPN三极管的发射极和基极之间会产生正的电势差。当电势差达到一定值时(例如0.7～0.8V)，NPN三极管将开启，此时由PNP三极管和NPN三极管组合构成的可控硅将完全开启，电流的泄放能力将变得更强。当负的瞬时脉冲信号从输入输出端口I/O进入，由于二极管D1正向偏置，PNP三极管的PN结是反向偏置，因此信号首先流过二极管D1，最终流向地GND。
上述瞬态电压抑制器件，由于第三阱与衬底连接，在二极管D1正向偏置时，可直接通过芯片正面的金属连线层将泄放电流引出，避免由于在衬底背面增加金属引出线，导致寄生的电阻和电感影响芯片性能。且由于可控硅电 流能力(泄放大电流的能力)比普通的PIN二极管和齐纳二极管更强，因此可大幅度提升负脉冲ESD的电流能力。
在图1所示的实施例中，瞬态电压抑制器件还包括设于衬底112上的外延层114，第一阱122和第二阱124设于外延层114中，外延层114为第二导电类型外延层，衬底112的掺杂浓度大于外延层114的掺杂浓度。在图1所示实施例中，外延层114为P-外延层。
在图1所示的实施例中，第一导电类型阱区(即第一阱122和第二阱124)均为深N阱(DN)，第二导电类型阱区(包括第三阱132)均为深P阱(DP)。
在图1所示的实施例中，第一隔离部172和第二隔离部174是在隔离槽内填充了绝缘材料的隔离结构。绝缘材料可以是二氧化硅、多晶硅等或者它们的结合。参见图1，隔离结构可以采用第二隔离部174的单槽结构，也可以采用第一隔离部172的双槽结构，甚至多槽结构，一般认为两个以上的槽比单槽的隔离效果更好。
在一个实施例中，第二隔离部174的槽深大于或等于第三阱126的阱深，以获得更好的隔离效果。
在图1所示的实施例中，第五掺杂区146上设有绝缘结构。
还有必要提供一种瞬态电压抑制器件的制造方法，可以用来制造上述任一实施例的瞬态电压抑制器件。
图3是一实施例中瞬态电压抑制器件的制造方法的流程图，包括下列步骤：
S310，在衬底上形成掩膜层，光刻并刻蚀掩膜层，露出第二导电类型阱区掺杂窗口。
请一并参阅图4a和图4b，在衬底上形成一层掩膜层182后，在掩膜层182表面涂覆一层光刻胶184，然后曝光、显影使光刻胶184形成第二导电类型阱区掺杂窗口的图案，然后刻蚀掉未被光刻胶覆盖的掩膜层182，露出第二导电类型阱区掺杂窗口。
在图4a所示的实施例中，衬底112上还形成有外延层114，衬底112的 掺杂浓度大于外延层114的掺杂浓度。掩膜层182是形成在外延层114上。
在图4a所示的实施例中，掩膜层182为硬掩膜。在一个实施例中，硬掩膜可以为氮化硅层。在图4a所示的实施例中，形成硬掩膜之前还可以在衬底112表面形成牺牲氧化层171，步骤S310刻蚀时需要将相应位置处的牺牲氧化层171也去除。在一个实施例中，硬掩膜可以通过淀积氮化硅形成，牺牲氧化层171可以通过热生长氧化层形成。
在一个实施例中，衬底112为半导体衬底，其材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
S320，通过掺杂窗口掺杂第二导电类型离子，在衬底表面形成第二区域。
在本实施例中，是通过离子注入工艺，注入P型杂质离子，在外延层114表面形成第二区域131，参见图4b。
S330，在第二区域上生长氧化层作为掺杂阻挡层。
在本实施例中，是去除光刻胶184后在外延层114表面生长氧化层，由于第二导电类型阱区掺杂窗口以外的区域被掩膜层182覆盖(难以被氧化)，因此只会在第二导电类型阱区掺杂窗口形成掺杂阻挡层173，参见图4c。
在一个实施例中，步骤S330是在外延层114表面生长3000埃～5000埃厚的二氧化硅。
S340，去除掩膜层，掺杂第一导电类型离子形成第一区域。
在本实施例中，去除掩膜层182后通过离子注入工艺，注入N型杂质离子。参见图4c，第二导电类型阱区掺杂窗口处由于形成了掺杂阻挡层173，因此只会在第二区域131之外的位置形成第一区域121。可以理解的，在其他实施例中，第一区域121也可以是通过注入P型离子形成，第二区域相应地是注入N型离子形成。
S350，去除掺杂阻挡层，并形成隔离结构。
在一个实施例中，隔离结构包括在第一区域121和第二区域131的交界 处形成的第二隔离部，以及将第一区域121分隔成两个部分的第一隔离部。
S360，热推阱，使第一区域和第二区域扩散形成阱区。
参见图4d，通过热推阱使第一区域121扩散形成被第一隔离部172分隔开的第一阱122和第二阱124，使第二区域131扩散形成第三阱132。在图4d所示的实施例中，第一隔离部172和第二隔离部174均为在隔离槽内填充绝缘材料的隔离结构。绝缘材料可以是二氧化硅、多晶硅等或者它们的结合。参见图1，隔离结构可以采用第二隔离部174的单槽结构，也可以采用第一隔离部172的双槽结构，甚至多槽结构，一般认为两个以上的槽比单槽的隔离效果更好。
在图4d所示的实施例中，热推阱完成后第三阱132的底部延伸至衬底112。
S370，通过光刻和掺杂形成第四阱以及第一至第七掺杂区。
参见图1，第一掺杂区142为第一导电类型(的掺杂区)，设于第二阱124中；第二掺杂区152为第二导电类型，设于第三阱132中；第三掺杂区154为第二导电类型，设于第四阱134中；第四掺杂区144为第一导电类型，设于第四阱134中；第五掺杂区146为第一导电类型，从第四阱134中延伸至第四阱134外，且位于第四阱134外的部分位于第一阱122中，即第五掺杂区146的一部分位于134中，一部分位于第四阱134外的第一阱122中；第六掺杂区156为第二导电类型，设于第一阱中122；第七掺杂区157为第二导电类型，设于第五掺杂区146下方、第一阱122中；且第五掺杂区146设于第四掺杂区144和第六掺杂区156之间，第四掺杂区144设于第三掺杂区154和第五掺杂区146之间。
S380，在衬底上形成金属连线层。
在一个实施例中，金属连线层包括第一金属连线162和第二金属连线164。第一金属连线162将第一掺杂区142和第六掺杂区156电性连接作为第一电位端，第二金属连线164将第二掺杂区152、第三掺杂区154和第四掺杂区144电性连接作为第二电位端。
上述瞬态电压抑制器件的制造方法，采用推阱的方式形成低电容TVS器件，所需的外延次数更少，成本更低，工艺控制更简单，适合大规模量产。并且，DP(包括第三阱132)和DN(包括第一阱122和第二阱124)的注入只需一块光刻版即可形成，可以节省一块光刻版。
在一个实施例中，第三阱132的掺杂浓度为5E18cm -3至5E19cm -3。参见图1，当二极管D1正向偏置泄放电流时，电子电流从输入输出端口I/O通过第一掺杂区142、第二阱124、外延层114、衬底112、第三阱132、第二掺杂区132进入地GND，由于第三阱132(DP)与衬底122(P+)连接，高浓度的第三阱132降低了二极管D1的串联电阻，由公式P＝I 2R可知，在功率P不变的情况下，电阻R越小，流过的电流I可以更大。
在一个实施例中，由于第二阱124与衬底112中间是外延层114，当二极管D1在反向偏置时，第二阱124和外延层114构成的反向PN结浓度都很淡，耗尽会很充分，产生的寄生电容很小。在一个实施例中，第一阱122和第二阱124的掺杂浓度为1E14cm -3至1E15cm -3，外延层114的掺杂浓度为1E14cm -3至1E15cm -3。
在一个实施例中，步骤S370具体包括：
使用第一注入光刻版光刻并注入P型离子，然后推阱以形成第四阱134；接着去除光刻胶，使用第二注入光刻版光刻并注入P型离子以形成第二掺杂区152、第三掺杂区154及第六掺杂区156；接着去除光刻胶，使用第三注入光刻版光刻并注入N型离子以形成第一掺杂区142、第四掺杂区144及第五掺杂区146；接着去除光刻胶，使用第四注入光刻版光刻并注入P型离子以形成第七掺杂区157。
在一个实施例中，步骤S380包括：光刻并刻蚀，在第一区域121和第二区域131的交界处形成第二隔离槽，以及形成将第一区域121分隔成两个部分的第一隔离槽；向沟槽内填充绝缘材料。
在一个实施例中，步骤S350在光刻之前，先淀积一层二氧化硅，然后再涂胶、曝光、显影形成隔离槽的刻蚀区，并进行干法刻蚀形成深槽，接着向 深槽内填充绝缘材料，然后干法回刻填充的绝缘材料，使得晶圆表面平坦化。通过采用深槽隔离技术，使得第三阱132和第一阱122完全隔离，避免在高温推阱的过程中，由于第三阱132浓度很高，导致横向扩散变大而增大芯片所需面积。
在一个实施例中，步骤S370离子注入形成第七掺杂区157的注入剂量为1E14cm -2至5E14cm -2。离子注入形成第四阱134的注入剂量是5E12cm -2至5E13cm -2。通过调整离子注入形成第七掺杂区157的注入剂量，可以精确调整SCR的触发电压，实现不同档位(即适用于不同工作电压)的TVS保护器件。
在一个实施例中，步骤S370之后、S380之前，还包括以下步骤：
形成介质层。具体地，可以采用淀积工艺形成层间介质(ILD)。
形成接触孔，并在接触孔内填充导电材料。具体地，可以光刻后刻蚀介质层形成接触孔。其中，所述导电材料可以为本领域技术人员熟知的任何适合的导电材料，包括但不限于金属材料；其中，所述金属材料可以包括Ag、Au、Cu、Pd、Pt、Cr、Mo、Ti、Ta、W和Al中的一种或几种。在一个实施例中，刻蚀介质层采用干法刻蚀工艺。
在一个实施例中，步骤S380在介质层上形成金属连线层。具体地，可以淀积金属后，光刻并刻蚀金属层形成金属连线层。在一个实施例中，刻蚀金属层采用干法刻蚀工艺。
在一个实施例中，形成金属互联线之后还包括形成钝化层的步骤，以及光刻并腐蚀钝化层，形成金属电极引出的步骤。
在一个实施例中，层间介质可为氧化硅层，包括利用热化学气相沉积(thermal CVD)制造工艺或高密度等离子体(HDP)制造工艺形成的有掺杂或未掺杂的氧化硅的材料层，例如未经掺杂的硅玻璃(USG)、磷硅玻璃(PSG)或硼磷硅玻璃(BPSG)。此外，层间介质也可以是掺杂硼或掺杂磷的自旋涂布式玻璃(spin-on-glass，SOG)、掺杂磷的四乙氧基硅烷(PTEOS)或掺杂硼的四乙氧基硅烷(BTEOS)。
在一个实施例中，还可以通过平坦化的方法(例如化学机械研磨CMP) 对沉积的层间介质进行平坦化，以使层间介质具有平坦的表面。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都为本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种瞬态电压抑制器件，其中包括：
    衬底，为第二导电类型；
    第一导电类型阱区，设于所述衬底上，包括第一阱和第二阱；
    第三阱，设于所述衬底上，为第二导电类型，所述第三阱的底部延伸至所述衬底；所述第一导电类型和第二导电类型为相反的导电类型；
    第四阱，设于所述第一阱中，为第二导电类型；
    隔离结构，所述隔离结构包括设于所述第一阱和第二阱之间的第一隔离部，以及设于所述第一阱和所述第三阱之间的第二隔离部，所述第一隔离部用于将所述第一阱和第二阱相隔离，所述第二隔离部用于将所述第一阱和第三阱相隔离；
    第一掺杂区，为第一导电类型，设于所述第二阱中；
    第二掺杂区，为第二导电类型，设于所述第三阱中；
    第三掺杂区，为第二导电类型，设于所述第四阱中；
    第四掺杂区，为第一导电类型，设于所述第四阱中；
    第五掺杂区，为第一导电类型，从所述第四阱中延伸至所述第四阱外，且位于第四阱外的部分位于所述第一阱中；
    第六掺杂区，为第二导电类型，设于所述第一阱中；
    第七掺杂区，为第二导电类型，设于所述第五掺杂区下方、所述第一阱中；所述第五掺杂区设于所述第四掺杂区和第六掺杂区之间，所述第四掺杂区设于所述第三掺杂区和第五掺杂区之间；
    金属连线层，包括第一金属连线和第二金属连线，位于所述衬底上，所述第一金属连线电性连接所述第一掺杂区和第六掺杂区作为第一电位端，所述第二金属连线电性连接所述第二掺杂区、第三掺杂区和第四掺杂区作为第二电位端。
  2. 根据权利要求1所述的瞬态电压抑制器件，其中所述第一电位端用于 电性连接输入输出端口，所述第二电位端用于接地。
  3. 根据权利要求1所述的瞬态电压抑制器件，其中还包括设于所述衬底上的外延层，所述第一导电类型阱区设于所述外延层中，所述外延层为第二导电类型，所述衬底的掺杂浓度大于所述外延层的掺杂浓度。
  4. 根据权利要求1所述的瞬态电压抑制器件，其中所述隔离结构是在隔离槽内填充了绝缘材料的隔离结构。
  5. 根据权利要求4所述的瞬态电压抑制器件，其中所述第二隔离部的槽深大于或等于所述第三阱的阱深。
  6. 根据权利要求1所述的瞬态电压抑制器件，其中，所述第一掺杂区作为二极管D1的阴极区，所述第二掺杂区作为所述二极管D1的阳极区，所述第六掺杂区作为PNP三极管的发射极区，所述第五掺杂区作为所述PNP三极管的基极区、并作为NPN三极管的集电极区和齐纳二极管Z1的阴极区，所述第七掺杂区作为所述PNP三极管的集电极区、并作为所述NPN三极管的基极区和所述齐纳二极管Z1的阳极区，所述第四掺杂区作为NPN三极管的发射极区；所述第七掺杂区和第三掺杂区之间等效形成有寄生电阻R1，所述第六掺杂区和第五掺杂区等效形成二极管D2；所述PNP三极管和NPN三极管等效为一个可控硅。
  7. 根据权利要求1所述的瞬态电压抑制器件，其中，还包括设于所述第五掺杂区上的绝缘结构。
  8. 根据权利要求1所述的瞬态电压抑制器件，其中，所述第三阱的掺杂浓度为5E18cm -3至5E19cm -3。
  9. 根据权利要求3所述的瞬态电压抑制器件，其中，所述第一阱和第二阱的掺杂浓度为1E14cm -3至1E15cm -3，所述外延层的掺杂浓度为1E14cm -3至1E15cm -3。
  10. 一种瞬态电压抑制器件的制造方法，所述方法包括：
    在第二导电类型的衬底上形成掩膜层，然后光刻并刻蚀所述掩膜层，露出第二导电类型阱区掺杂窗口；
    通过所述第二导电类型阱区掺杂窗口掺杂第二导电类型离子，在所述衬底表面形成第二区域；
    在所述第二区域上生长氧化层作为掺杂阻挡层；
    去除所述掩膜层，在衬底表面未被掺杂阻挡层覆盖的位置掺杂第一导电类型离子形成第一区域；所述第一导电类型和第二导电类型为相反的导电类型；
    去除所述掺杂阻挡层，并形成隔离结构，所述隔离结构包括从所述第一区域和第二区域的交界处向下延伸的第二隔离部，以及将所述第一区域分隔成两个部分的第一隔离部；
    热推阱，使所述第一区域扩散形成被所述第一隔离部分隔开的第一阱和第二阱，使所述第二区域扩散形成第三阱；
    通过光刻和掺杂，分别形成第四阱、第一掺杂区、第二掺杂区、第三掺杂区、第四掺杂区、第五掺杂区、第六掺杂区及第七掺杂区；
    在所述衬底上形成金属连线层，所述金属连线层包括第一金属连线和第二金属连线，所述第一金属连线将所述第一掺杂区和第六掺杂区电性连接作为第一电位端，所述第二金属连线将所述第二掺杂区、第三掺杂区和第四掺杂区电性连接作为第二电位端；
    其中，所述第四阱为第二导电类型，形成于所述第一阱中；所述第一掺杂区为第一导电类型，形成于所述第二阱中；所述第二掺杂区为第二导电类型，形成于所述第三阱中；所述第三掺杂区为第二导电类型，形成于所述第四阱中；所述第四掺杂区为第一导电类型，形成于所述第四阱中；所述第五掺杂区为第一导电类型，从所述第四阱中延伸至所述第四阱外，且位于第四阱外的部分位于所述第一阱中；所述第六掺杂为第二导电类型，形成于所述第一阱中；所述第七掺杂区为第二导电类型，形成于所述第五掺杂区下方、所述第一阱中；所述第五掺杂区形成于所述第四掺杂区和第六掺杂区之间，所述第四掺杂区形成于所述第三掺杂区和第五掺杂区之间。
  11. 根据权利要求10所述的瞬态电压抑制器件的制造方法，其中所述衬 底包括底层衬底和所述底层衬底上的外延衬底，所述底层衬底的掺杂浓度大于所述外延衬底的掺杂浓度；所述热推阱的步骤形成的第三阱底部延伸至所述底层衬底，第一阱和第二阱是形成于所述外延衬底中，所述在所述衬底上形成金属连线层的步骤，是在所述外延衬底上形成金属连线层。
  12. 根据权利要求10所述的瞬态电压抑制器件的制造方法，其中所述在第二导电类型的衬底上形成掩膜层，是淀积形成氮化硅层。
  13. 根据权利要求10所述的瞬态电压抑制器件的制造方法，其中所述第一导电类型为N型，所述第二导电类型为P型；所述通过光刻和掺杂，分别形成第四阱、第一掺杂区、第二掺杂区、第三掺杂区、第四掺杂区、第五掺杂区、第六掺杂区及第七掺杂区的步骤包括：
    使用第一注入光刻版光刻并离子注入，然后推阱以形成第四阱；
    使用第二注入光刻版光刻并离子注入以形成第二掺杂区、第三掺杂区及第六掺杂区；
    使用第三注入光刻版光刻并离子注入以形成第一掺杂区、第四掺杂区及第五掺杂区；
    使用第四注入光刻版光刻并离子注入以形成第七掺杂区。
  14. 根据权利要求13所述的瞬态电压抑制器件的制造方法，其中，所述使用第一注入光刻版光刻并离子注入的注入剂量是5E12cm -2至5E13cm -2；所述使用第四注入光刻版光刻并离子注入的注入剂量为1E14cm -2至5E14cm -2。
  15. 根据权利要求10所述的瞬态电压抑制器件的制造方法，其中所述形成隔离结构的步骤包括：
    光刻并刻蚀，在所述第一区域和第二区域的交界处形成第二隔离槽，以及形成将第一区域分隔成两个部分的第一隔离槽；
    向沟槽内填充绝缘材料。
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