WO2020042914A1 - 瞬态电压抑制器件及其制造方法 - Google Patents

瞬态电压抑制器件及其制造方法 Download PDF

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Publication number
WO2020042914A1
WO2020042914A1 PCT/CN2019/100690 CN2019100690W WO2020042914A1 WO 2020042914 A1 WO2020042914 A1 WO 2020042914A1 CN 2019100690 W CN2019100690 W CN 2019100690W WO 2020042914 A1 WO2020042914 A1 WO 2020042914A1
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well
region
doped region
conductivity type
doped
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PCT/CN2019/100690
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English (en)
French (fr)
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程诗康
顾炎
张森
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无锡华润上华科技有限公司
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Priority to EP19855237.4A priority Critical patent/EP3846207A4/en
Priority to US17/265,549 priority patent/US20230122120A1/en
Publication of WO2020042914A1 publication Critical patent/WO2020042914A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/784—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66098—Breakdown diodes
    • H01L29/66106—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a transient voltage suppression device, and also relates to a method for manufacturing a transient voltage suppression device.
  • TVS Transient Voltage Suppressor, transient voltage suppressor
  • I / O interfaces the high-speed interface represented by HDMI (High-Definition Multimedia Interface) is getting faster and faster, even up to 5Gbps.
  • HDMI High-Definition Multimedia Interface
  • the capacitors for ESD protection at the interface have extremely strict Requirements; in addition, there are hundreds of pins in the actual driver chip, each of which has ESD risk. In order to protect as many I / O ports as possible while not occupying too much area, this There are higher requirements for TVS integration.
  • a transient voltage suppression device includes: a substrate of a second conductivity type; a well region of a first conductivity type provided in the substrate including a first well and a second well; and a well region of a second conductivity type, Provided in the substrate, including a third well and a fourth well, the third well being provided between the first well and the second well so as to isolate the first well from the second well, and The second well is disposed between the third well and the fourth well; the first conductivity type and the second conductivity type are opposite conductivity types; a zener active region is provided in the fourth well Is a second conductivity type; a first doped region is a first conductivity type and is disposed in the first well; a second doped region is a second conductivity type and is disposed in the first well; The three doped regions are of the first conductivity type and are provided in the second well; the fourth doped region is of the second conductivity type and are provided in the second well; the fifth doped region is of the first conductivity type A conductivity
  • the transient voltage suppression device includes a first diode, a second diode, and a Zener diode.
  • the anode of the first diode and the second diode The cathode of the electrode tube is electrically connected as a first potential terminal, and the cathode of the first diode and the cathode of the Zener diode are electrically connected as a second potential terminal, and the anode of the second diode and The anode of the Zener diode is electrically connected as a third potential terminal.
  • the method includes: forming a mask layer on a substrate of the second conductivity type, and then photolithography and etching the mask layer to expose the first conductive layer.
  • Type well region doped window doping a first conductivity type ion through the first conductivity type well region doping window to form a first region on the substrate surface; growing an oxide layer on the first region as a doping Impurity barrier layer; removing the mask layer, doping a second conductivity type ion at a position on the substrate surface that is not covered by the doped barrier layer to form a second region; the first conductivity type and the second conductivity type are opposite Conductivity type; hot push well, so that the first Area diffusion forms a first well and a second well, and the second area diffuses to form a third well and a fourth well, and the third well is located between the first well and the second well to thereby form the first well It is isolated from the second well, and the second well is located between the third well and the fourth well; after removing the doping barrier layer, a first doped region is formed by photolithography and doping, respectively; A second doped region, a third doped region, a fourth doped region, a fifth doped region,
  • FIG. 1 is a schematic structural diagram of a transient voltage suppression device in an embodiment
  • FIG. 2 is a schematic diagram of an equivalent circuit of the transient voltage suppression device of FIG. 1;
  • FIG. 3 is a flowchart of a method for manufacturing a transient voltage suppression device according to an embodiment
  • 4a to 4c are schematic cross-sectional views of a transient voltage suppression device manufactured by the method shown in FIG. 3 during the manufacturing process.
  • Spatial relation terms such as “below”, “below”, “below”, “below”, “above”, “above”, etc., in It may be used here for convenience of description to describe the relationship between one element or feature and other elements or features shown in the figure. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is turned over, then the element or feature described as “below” or “beneath” other elements or features would then be oriented “above” the other element or feature. Thus, the exemplary terms “below” and “below” can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptors used herein are interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional views which are schematic views of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present invention should not be limited to the specific shape of the region shown here, but include shape deviations due to, for example, manufacturing.
  • an implanted region shown as a rectangle generally has round or curved features and / or implanted concentration gradients at its edges, rather than a binary change from the implanted region to the non-implanted region.
  • a buried area formed by implantation may result in some implantation in the area between the buried area and the surface through which the implantation proceeds.
  • the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • P + type is simply referred to as P-type with heavy doping concentration.
  • P-type doping concentration P-type represents lightly doped P-type
  • N + type represents heavily doped N-type
  • N-type represents medium-doped N-type
  • N-type represents lightly-doped N type.
  • the traditional TVS capacitor composed of a single avalanche diode is quite large, usually at least tens of picofarads. As the ESD capability increases, the capacitance value also increases in proportion. When used for high-speed interfaces, higher capacitance values will seriously affect the data. Integrity.
  • the solution is usually to connect a low-capacitance diode in series with a TVS avalanche diode to achieve a unidirectional low-capacitance TVS.
  • one method is to embed a buried layer and grow a high resistivity epitaxy.
  • FIG. 1 is a schematic structural diagram of a transient voltage suppression device according to an embodiment, including a substrate 110, a first conductivity type well region, a second conductivity type well region, a zener active region 139, a first doped region 141, The second doped region 142, the third doped region 151, the fourth doped region 152, the fifth doped region 161, and the sixth doped region 162.
  • the first conductivity type well region includes a first well 122 and a second well 124
  • the second conductivity type well region includes a third well 132 and a fourth well 134.
  • the substrate 110 is of a second conductivity type.
  • a first conductivity type well region and a second conductivity type well region are provided in the substrate 110.
  • the zener active region 139 is disposed in the fourth well 134 and is of the second conductivity type.
  • the first doped region 141 is a first conductivity type and is provided in the first well 122;
  • the second doped region 142 is a second conductivity type and is provided in the first well 122;
  • the third doped region 151 is a first conductivity Type, provided in the second well 124;
  • the fourth doped region 152 is of the second conductivity type, provided in the second well 124;
  • the fifth doped region 161 is of the first conductivity type, provided in the zener active region 139;
  • the sixth doped region 162 is of the second conductivity type and is disposed in the Zener active region 139.
  • the first conductivity type is N type
  • the second conductivity type is P type
  • the substrate 110 is a P type substrate
  • the first conductivity type well region is an N well
  • the second conductivity type well is The region is a P-well; in other embodiments, the first conductivity type may be a P-type, and the second conductivity type may be an N-type.
  • FIG. 1 also shows the equivalent connection of the doped regions electrically connected through the metal interconnection line as a transient voltage suppression device (the dots at the intersection of the wires indicate the connection, and the absence of the dots indicates no connection).
  • the fourth doped region 152 serves as the anode region of the first diode D1
  • the first doped region 141 serves as the cathode region of the second diode D2
  • the first doped region 141 and the fourth doped region 152 are electrically
  • the sexual connection is used as a first potential terminal, and is used to connect an electrical connection to an input / output port (I / O port).
  • the third doped region 151 serves as the cathode region of the first diode D1
  • the fifth doped region 161 serves as the cathode region of the Zener diode D3
  • the third doped region 151 and the fifth doped region 161 are electrically connected as the first Two potential terminals for electrically connecting the working voltage terminal (VDD terminal).
  • the second doped region 142 serves as the anode region of the second diode D2
  • the sixth doped region 162 serves as the anode region of the Zener diode D3
  • the second doped region 142 and the sixth doped region 162 are electrically connected as the first Three potential terminal for ground (GND).
  • FIG. 2 is a schematic diagram of an equivalent circuit of the transient voltage suppression device of FIG. 1.
  • the transient voltage suppression device described above isolates the first well 122 and the second well 124 through the third well 132 (that is, isolates each doped region in the first well 122 and each doped region in the second well 124). ), which is equivalent to isolating the first diode D1 and the second diode D2.
  • the isolation effect is good, and the parasitic BJT is prevented from turning on. Therefore, the ESD is highly robust and easy to integrate.
  • the transient voltage suppression device can achieve protection from the working voltage terminal VDD to the ground GND (path 1), and protection of the input / output port I / O to the ground GND (path 2 and path 3).
  • path 1 the working voltage terminal
  • path 2 protection of the input / output port I / O to the ground GND
  • path 3 protection of the input / output port I / O to the ground GND
  • V BR V D1 + V D3
  • V D1 represents the forward voltage drop of the first diode D1, which is about 0.6 ⁇ 0.7V at normal temperature
  • V D3 represents the reverse breakdown voltage of the Zener diode D3.
  • V D3 is usually controlled between 5 and 8V, so the voltage of the input / output port I / O is clamped within the safe voltage range, which plays a good protective role .
  • the second conductivity type well region further includes a fifth well 136, and the first well 122 is disposed between the third well 132 and the fifth well 136.
  • the junction depth of the first conductive type well region and the second conductive type well region is 7 ⁇ m to 15 ⁇ m.
  • the first conductivity type well regions are both deep N wells (DN)
  • the second conductivity type well regions are both deep P wells (DP).
  • DN deep N wells
  • DP deep P wells
  • the first conductivity type well region and the second conductivity type well region are formed by pushing wells at high temperature for a long time, so the doping concentration is lower than that of the well region of a conventional transient voltage suppression device, which is beneficial Further reduce parasitic capacitance.
  • two second doped regions 142 are provided in the first well 122 as anode regions of the second diode D2, and two third doped regions are provided in the second well 124.
  • 151 serves as a cathode region of the first diode D1
  • two sixth doped regions 162 are provided in the fourth well 134 as anode regions of the Zener diode D3.
  • an isolation structure may be provided between the structures in which the active regions need to be isolated from each other.
  • an isolation structure 170 is provided between the first doped region 141 and the second doped region 142 for isolation, and an isolation structure is provided between the third doped region 151 and the fourth doped region 152. 170 for isolation.
  • the two closest doped regions in the first well region 122 and the second well region 124 are isolated by the isolation structure 170, that is, the second doped region 142 (a second doped region 142 on the right in FIG. 1)
  • An isolation structure 170 is provided for isolation from the third doped region 151 (a third doped region 151 to the left in FIG. 1) for isolation.
  • the two closest doped regions in the second well region 124 and the fourth well region 134 are isolated by the isolation structure 170, that is, the third doped region 151 in FIG. 1 (a third doped region to the right in FIG. 1)
  • An isolation structure 170 is provided between the region 151) and the sixth doped region 162 (a sixth doped region 162 to the left in FIG. 1) for isolation.
  • the isolation structure is made of an oxide insulating material, such as silicon oxide.
  • the isolation structure 170 is a LOCOS (Local Oxidation Isolation of Silicon) structure.
  • an isolation structure 170 is provided on a surface area of the substrate 110 except for each doped region and the zener active region 139.
  • the second conductive type well region is formed on the surface of the substrate 110 except for the first conductive type well region.
  • FIG. 3 is a flowchart of a method for manufacturing a transient voltage suppression device according to an embodiment, including the following steps:
  • a mask layer is formed on the substrate, and the mask layer is lithographically and etched to expose the doped window of the first conductivity type well region.
  • the mask layer is a hard mask 182.
  • the hard mask 182 may be a silicon nitride layer.
  • a sacrificial oxide layer 171 may be further formed on the surface of the substrate 110 before the hard mask 182 is formed, and the sacrificial oxide layer 171 at a corresponding position needs to be removed during etching.
  • the hard mask 182 may be formed by depositing silicon nitride, and the sacrificial oxide layer 171 may be formed by thermally growing an oxide layer.
  • the substrate 110 is a semiconductor substrate, and the material thereof may be undoped single crystal silicon, doped single crystal silicon, silicon on insulator (SOI), silicon on insulator (SSOI), Silicon germanium (S-SiGeOI), silicon germanium (SiGeOI) on insulator and germanium on insulator (GeOI) are laminated on the insulator.
  • SOI silicon on insulator
  • SSOI silicon on insulator
  • SiGeOI Silicon germanium
  • SiGeOI silicon germanium
  • germanium (SiGeOI) on insulator and germanium on insulator (GeOI) are laminated on the insulator.
  • S320 Doping a first conductivity type ion through a doping window to form a first region on a substrate surface.
  • an N-type impurity ion is implanted through an ion implantation process to form a first region (including a region 121 and a region 123) on the substrate surface, as shown in FIG. 4a.
  • An oxide layer is grown on the first region as a doping barrier layer.
  • an oxide layer is grown on the surface of the substrate 110 after the photoresist is removed. Since the area outside the doped window of the first conductivity type well region is covered by the mask layer (difficult to be oxidized), it will only A conductive type well region doped window forms a doped barrier layer.
  • P-type impurity ions are implanted through an ion implantation process after removing the mask layer.
  • the second region (including the region 131, the region 133, and the region 135) will be formed only outside the first region. It can be understood that, in other embodiments, the first region may also be formed by implanting P-type ions, and the second region may be formed by implanting N-type ions accordingly.
  • S350 The thermal push well diffuses the first region and the second region to form a well region.
  • the region 121 is diffused to form the first well 122
  • the region 123 is diffused to form the second well 124
  • the region 131 is diffused to form the third well 132
  • the region 133 is diffused to form the fourth well 134
  • the region 135 is diffused.
  • a fifth well 136 is formed, see FIG. 4c.
  • the temperature of the thermal push trap is 1000-1300 degrees Celsius, and the time is 250-350 minutes. Due to the high temperature and long time of pushing the well, the depth of the well region obtained is deeper and the doping concentration is lower. Therefore, when a voltage is applied to the electrode of the device, the depletion layer will be broadened, which is equivalent to the distance between the electrode plates becoming larger, so the parasitic capacitance is reduced.
  • the dose of ion implantation in step S340 is slightly higher than the dose of ion implantation in step S320; further, the dose of ion implantation in steps S320 and S340 is 5E11cm -2 to 5E12cm -2 .
  • the first doped region 141, the second doped region 142, The third doped region 151, the fourth doped region 152, the fifth doped region 161, the sixth doped region 162, and the zener active region 139 are N-type doped regions, the second doped region 142, the fourth doped region 152, and the sixth doped region.
  • the impurity region 162 is a P-type doped region, and the zener active region 139 is a P-type.
  • an N-type doped region is formed first, then a P-type doped region is formed, and then a Zener active region 139 is formed.
  • a step of forming an isolation structure is further included between steps S350 and S360.
  • the isolation structure 170 may be formed by a LOCOS process after photolithography, as shown in FIG. 1.
  • the photoresist is removed, and then photolithography is performed using a first implantation photoresist to expose the locations where N-type doped regions need to be implanted, and N-type ions are implanted to form N-type doped Then, the photoresist is removed, and then photolithography is performed using a second implantation lithography to expose the position where the P-type doped region needs to be implanted, and P-type ions are implanted to form the P-type doped region; and then the photoresist is removed. , Using a third implantation lithography lithography and implanting P-type ions to form a zener active region. Referring to FIG.
  • a zener active region 139 is formed in the fourth well 134; a first doped region 141 is formed in the first well 122; a second doped region 142 is formed in the first well 122; a third doped region
  • the impurity region 151 is formed in the second well 124; the fourth doped region 152 is formed in the second well 124; the fifth doped region 161 is formed in the zener active region 139; the sixth doped region 162 is formed in Zener active area 139.
  • step S360 the method further includes the following steps:
  • a dielectric layer is formed.
  • an interlayer dielectric ILD
  • ILD interlayer dielectric
  • a contact hole is formed, and a conductive material is filled in the contact hole.
  • the contact layer may be formed by etching the dielectric layer after photolithography.
  • the conductive material may be any suitable conductive material well known to those skilled in the art, including but not limited to metal materials; wherein the metal materials may include Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti Or Ta, W, and Al. In one embodiment, a dry etching process is used to etch the dielectric layer.
  • Metal interconnection lines are formed on the dielectric layer. Specifically, after the metal layer is deposited, the metal layer is lithographically and etched to form metal interconnection lines. In one embodiment, the deposited metal layer has a thickness of 3 microns. In one embodiment, the metal layer is etched by a dry etching process.
  • the method further includes a step of forming a passivation layer, and a step of photolithography and etching the passivation layer to form a metal electrode.
  • the interlayer dielectric may be a silicon oxide layer, including doped or undoped silicon oxide formed using a thermal chemical vapor deposition (CVD) manufacturing process or a high-density plasma (HDP) manufacturing process.
  • Material layers such as undoped silica glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG).
  • the interlayer dielectric may also be boron or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetra-ethoxysilane (PTEOS). Ethoxysilane (BTEOS).
  • the deposited interlayer dielectric may also be planarized by a planarization method, such as chemical mechanical polishing (CMP), so that the interlayer dielectric has a flat surface.
  • CMP chemical mechanical polishing
  • the manufacturing method of the transient voltage suppression device described above uses the third well to isolate the first well and the second well, which is equivalent to isolating the first diode and the second diode.
  • the isolation effect is good and the parasitic BJT is avoided.
  • ESD is highly robust and easy to integrate.
  • the N-well and the P-well are formed by pushing the wells simultaneously in step S350, which can reduce the lateral expansion of the wells, significantly reduce the TVS chip integration area, and effectively reduce the manufacturing cost.
  • the step S360 of forming the Zener active region 139 is specifically implanting phosphorus ions and boron ions, and the implantation concentration of the boron ions is greater than the implantation concentration of the phosphorus ions.
  • the Zener active region 139 is formed by implanting phosphorus ions of 1E14 cm -2 at an implantation energy of 160 keV, and implanting boron ions of 3.8 E14 cm -2 by an implantation energy of 180 keV. Because the Zener diode D3 is a tube that needs a large current, many Zener diodes D3 are usually connected in parallel on the layout, resulting in a large layout area. However, due to process fluctuations, if the breakdown point of the Zener diode is close to the substrate surface, the breakdown will be unstable and the device will be easily burned in advance. This embodiment adds a higher concentration of phosphorus ion implantation.
  • step S320 is implanting 5E15cm -2 arsenic ions and 1E14cm -2 phosphorus ions.
  • step S340 is implanting 2.5E15 cm -2 boron difluoride.
  • the doped barrier layer 173 is removed by a wet etching process.
  • the method for manufacturing a transient voltage suppression device includes seven photolithography steps: photolithography in step 310, photolithography for forming an isolation structure 170, and forming an N-type doped region using a first implanted photoresist. Photolithography, using a second implantation lithography to form a P-type doped region, using a third implantation lithography to form a zener active area, forming contact lithography, and forming metal interconnection lines Lithography.

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Abstract

一种瞬态电压抑制器件及其制造方法，所述瞬态电压抑制器件包括：衬底(110)；第一导电类型阱区，包括第一阱(122)和第二阱(124)；第二导电类型阱区，包括第三阱(132)和第四阱(134)，第三阱(132)设于所述第一阱(122)和第二阱(124)之间从而将第一阱(122)和第二阱(124)相隔离，第二阱(124)设于第三阱(132)和第四阱(134)之间；齐纳管有源区(139)；第一掺杂区(142)，设于所述第一阱(122)中；第二掺杂区(142)，设于所述第一阱(122)中；第三掺杂区(151)，设于所述第二阱(124)中；第四掺杂区(152)，设于所述第二阱(124)中；第五掺杂区(161)，设于所述齐纳管有源区(139)中；第六掺杂区(162)，设于所述齐纳管有源区(139)中。

Description

瞬态电压抑制器件及其制造方法 技术领域
本发明涉及半导体制造领域，特别是涉及一种瞬态电压抑制器件，还涉及一种瞬态电压抑制器件的制造方法。
背景技术
在整机和系统中常常会遇到意外的电压瞬变和浪涌，造成整机和系统中的半导体器件被烧毁或击穿，从而导致整机和系统的损坏。因此TVS(Transient Voltage Suppressor，瞬态电压抑制器)作为一种PN结高效保护器件，由于其响应时间快、抗ESD能力强，被广泛的应用于各类I/O接口。目前以HDMI(High-Definition Multimedia Interface，高清晰度多媒体接口)为代表的高速接口传输速率越来越快，甚至高达5Gbps，为了保证数据完整性，对于接口处ESD防护的电容有着及其严格的要求；另外在实际的驱动芯片中，管脚数目有的多达几百个，其中每个管脚都存在ESD风险，为了尽量保护更多的I/O口同时不占用太大的面积，这对于TVS的集成度有了更高的要求。
发明内容
基于此，有必要提供一种新型结构的瞬态电压抑制器件及其制造方法。
一种瞬态电压抑制器件，包括：衬底，为第二导电类型；第一导电类型阱区，设于所述衬底中，包括第一阱和第二阱；第二导电类型阱区，设于所述衬底中，包括第三阱和第四阱，所述第三阱设于所述第一阱和第二阱之间从而将所述第一阱和第二阱相隔离，所述第二阱设于所述第三阱和第四阱之间；所述第一导电类型和第二导电类型为相反的导电类型；齐纳管有源区， 设于所述第四阱中，为第二导电类型；第一掺杂区，为第一导电类型，设于所述第一阱中；第二掺杂区，为第二导电类型，设于所述第一阱中；第三掺杂区，为第一导电类型，设于所述第二阱中；第四掺杂区，为第二导电类型，设于所述第二阱中；第五掺杂区，为第一导电类型，设于所述齐纳管有源区中；第六掺杂区，为第二导电类型，设于所述齐纳管有源区中；其中，所述第四掺杂区作为第一二极管的阳极区，所述第一掺杂区作为第二二极管的阴极区，所述第一掺杂区和所述第四掺杂区电性连接作为第一电位端；所述第三掺杂区作为所述第一二极管的阴极区，所述第五掺杂区作为齐纳二极管的阴极区，所述第三掺杂区和所述第五掺杂区电性连接作为第二电位端；所述第二掺杂区作为所述第二二极管的阳极区，所述第六掺杂区作为所述齐纳二极管的阳极区，所述第二掺杂区和所述第六掺杂区电性连接作为第三电位端。
一种瞬态电压抑制器件的制造方法，所述瞬态电压抑制器件包括第一二极管、第二二极管及齐纳二极管，所述第一二极管的阳极和所述第二二极管的阴极电性连接作为第一电位端，所述第一二极管的阴极和所述齐纳二极管的阴极电性连接作为第二电位端，所述第二二极管的阳极和所述齐纳二极管的阳极电性连接作为第三电位端，所述方法包括：在第二导电类型的衬底上形成掩膜层，然后光刻并刻蚀所述掩膜层，露出第一导电类型阱区掺杂窗口；通过所述第一导电类型阱区掺杂窗口掺杂第一导电类型离子，在所述衬底表面形成第一区域；在所述第一区域上生长氧化层作为掺杂阻挡层；去除所述掩膜层，在衬底表面未被掺杂阻挡层覆盖的位置掺杂第二导电类型离子形成第二区域；所述第一导电类型和第二导电类型为相反的导电类型；热推阱，使所述第一区域扩散形成第一阱和第二阱、所述第二区域扩散形成第三阱和第四阱，所述第三阱位于所述第一阱和第二阱之间从而将所述第一阱和第二阱相隔离，所述第二阱位于所述第三阱和第四阱之间；在去除所述掺杂阻挡层之后，通过光刻和掺杂，分别形成第一掺杂区、第二掺杂区、第三掺杂区、第四掺杂区、第五掺杂区、第六掺杂区及齐纳管有源区；其中，齐纳管有源区位于所述第四阱中，为第二导电类型；第一掺杂区为第一导电类型，位于 所述第一阱中；第二掺杂区为第二导电类型，设于所述第一阱中；第三掺杂区为第一导电类型，设于所述第二阱中；第四掺杂区为第二导电类型，设于所述第二阱中；第五掺杂区为第一导电类型，设于所述齐纳管有源区中；第六掺杂区为第二导电类型，设于所述齐纳管有源区中。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中瞬态电压抑制器件的结构示意图；
图2为图1的瞬态电压抑制器件的等效电路原理示意图；
图3是一实施例中瞬态电压抑制器件的制造方法的流程图；
图4a～图4c是采用图3所示方法制造的瞬态电压抑制器件在制造过程中的剖面示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与为本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组 合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来 描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
传统的由单一雪崩二极管构成的TVS电容相当大，一般至少几十皮法，随着ESD能力的增大，电容值也同比例增大，用于高速接口时较高的电容值会严重影响数据的完整性。解决办法通常是将一个低电容的二极管与TVS雪崩二极管串联，来实现单向低电容TVS。作为示例性的TVS器件，一种是采用注入埋层和生长高电阻率外延的方式，将低电容的二极管与TVS雪崩二极管集成在同一块芯片上，但是成本较高；另一种方式则采用常规的CMOS工艺，将二极管分布在芯片表面。图1是一实施例中瞬态电压抑制器件的结构示意图，包括衬底110、第一导电类型阱区、第二导电类型阱区、齐纳管有源区139、第一掺杂区141、第二掺杂区142、第三掺杂区151、第四掺杂区152、第五掺杂区161及第六掺杂区162。第一导电类型阱区包括第一阱122和第二阱124，第二导电类型阱区包括第三阱132和第四阱134。
其中衬底110为第二导电类型。第一导电类型阱区和第二导电类型阱区设于衬底110中。齐纳管有源区139设于第四阱134中，为第二导电类型。第一掺杂区141为第一导电类型，设于第一阱122中；第二掺杂区142为第二导电类型，设于第一阱122中；第三掺杂区151为第一导电类型，设于第 二阱124中；第四掺杂区152为第二导电类型，设于第二阱124中；第五掺杂区161为第一导电类型，设于齐纳管有源区139中；第六掺杂区162为第二导电类型，设于齐纳管有源区139中。在图1所示的实施例中，第一导电类型为N型，第二导电类型为P型，衬底110为P型衬底，第一导电类型阱区为N阱，第二导电类型阱区为P阱；在其他实施例中，也可以是第一导电类型为P型，第二导电类型为N型。
图1还示出了各掺杂区通过金属互联线电性连接作为瞬态电压抑制器件的等效连接示意(导线相交处有圆点表示连接，无圆点表示不连接)。其中，第四掺杂区152作为第一二极管D1的阳极区，第一掺杂区141作为第二二极管D2的阴极区，第一掺杂区141和第四掺杂区152电性连接作为第一电位端，用于连接电性连接输入输出端口(I/O端口)。第三掺杂区151作为第一二极管D1的阴极区，第五掺杂区161作为齐纳二极管D3的阴极区，第三掺杂区151和第五掺杂区161电性连接作为第二电位端，用于电性连接工作电压端(VDD端)。第二掺杂区142作为第二二极管D2的阳极区，第六掺杂区162作为齐纳二极管D3的阳极区，第二掺杂区142和第六掺杂区162电性连接作为第三电位端，用于接地(GND)。图2为图1的瞬态电压抑制器件的等效电路原理示意图。
上述瞬态电压抑制器件，通过第三阱132对第一阱122和第二阱124进行隔离(即对第一阱122中的各掺杂区和第二阱124中的各掺杂区进行隔离)，相当于对第一二极管D1和第二二极管D2进行隔离，隔离效果好，避免了寄生BJT开启，因此ESD鲁棒性高、便于集成。
参见图2，上述瞬态电压抑制器件能够实现工作电压端VDD到地GND的防护(路径1)、输入输出端口I/O到地GND的防护(路径2和路径3)。当正的瞬时脉冲信号从输入输出端口I/O进入，由于第一二极管D1正向偏置，第二二极管D2反向偏置，因此信号首先流过第一二极管D1，再经过齐纳二极管D3，最终流向地GND。输入输出端口I/O的电压被钳位在V BR，其中V BR＝V D1+V D3，V D1表示第一二极管D1的正向压降，常温下约为0.6～0.7V，V D3表示齐纳二极 管D3的反向击穿耐压，通过控制齐纳管有源区139和第五掺杂区161的掺杂浓度可以得到不同应用范围的电压值，对于应用在工作电压(VDD)为5V的TVS产品(例如应用在HDMI中)，V D3通常控制在5～8V之间，因此输入输出端口I/O的电压被钳位在安全电压范围内，起到了很好的防护作用。当负的瞬时脉冲信号从输入输出端口I/O进入，由于第二二极管D2正向偏置，第一二极管D1反向偏置，信号首先流过D2二极管，最终流向地端GND。
在图1所示的实施例中，第二导电类型阱区还包括第五阱136，第一阱122设于第三阱132和第五阱136之间。
在一个实施例中，第一导电类型阱区和第二导电类型阱区的结深为7微米～15微米。
在图1所示的实施例中，第一导电类型阱区(即第一阱122和第二阱124)均为深N阱(DN)，第二导电类型阱区(即第三阱132、第四阱134、第五阱136)均为深P阱(DP)。由于阱区为深阱，当器件的电极加上电压时，耗尽层的展宽会更大(相对于传统瞬态电压抑制器件中结深较浅的阱的耗尽层展宽更大)，相当于电极极板之间的距离变大，因此寄生电容减小。进一步地，在一个实施例中，第一导电类型阱区和第二导电类型阱区是高温长时间推阱形成，因此掺杂浓度比传统瞬态电压抑制器件的阱区更低，这有利于进一步减小寄生电容。
在图1所示的实施例中，第一阱122内设有两个第二掺杂区142作为第二二极管D2的阳极区，第二阱124内设有两个第三掺杂区151作为第一二极管D1的阴极区，第四阱134内设有两个第六掺杂区162作为齐纳二极管D3的阳极区。
在一个实施例中，可以在有源区需要相互隔离的结构之间设置隔离结构。在图1所示的实施例中，第一掺杂区141和第二掺杂区142之间设置隔离结构170进行隔离，第三掺杂区151与第四掺杂区152之间设置隔离结构170进行隔离。第一阱区122和第二阱区124中靠得最近的两个掺杂区被隔离结构170所隔离，即第二掺杂区142(图1中靠右的一个第二掺杂区142)与第 三掺杂区151(图1中靠左的一个第三掺杂区151)之间设置隔离结构170进行隔离。第二阱区124和第四阱区134中靠得最近的两个掺杂区被隔离结构170所隔离，即图1中第三掺杂区151(图1中靠右的一个第三掺杂区151)与第六掺杂区162(图1中靠左的一个第六掺杂区162)之间设置隔离结构170进行隔离。
在一个实施例中，隔离结构为氧化绝缘材质，例如为氧化硅。在一个实施例中，隔离结构170为LOCOS(硅局部氧化隔离)结构。
在图1所示的实施例中，除各掺杂区和齐纳管有源区139之外的衬底110表面区域都设有隔离结构170。
在一个实施例中，衬底110表面除第一导电类型阱区之外的位置都形成了第二导电类型阱区。
图3是一实施例中瞬态电压抑制器件的制造方法的流程图，包括下列步骤：
S310，在衬底上形成掩膜层，光刻并刻蚀掩膜层，露出第一导电类型阱区掺杂窗口。
在衬底上形成一层掩膜层后，在掩膜层表面涂覆一层光刻胶，然后曝光、显影使光刻胶形成第一导电类型阱区掺杂窗口的图案，然后刻蚀掉未被光刻胶覆盖的掩膜层，露出第一导电类型阱区掺杂窗口。在图1所示的实施例中，掩膜层为硬掩膜182。在一个实施例中，硬掩膜182可以为氮化硅层。在图1所示的实施例中，形成硬掩膜182之前还可以在衬底110表面形成牺牲氧化层171，刻蚀时需要将相应位置处的牺牲氧化层171也去除。在一个实施例中，硬掩膜182可以通过淀积氮化硅形成，牺牲氧化层171可以通过热生长氧化层形成。
在一个实施例中，衬底110为半导体衬底，其材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
S320，通过掺杂窗口掺杂第一导电类型离子，在衬底表面形成第一区域。
在本实施例中，是通过离子注入工艺，注入N型杂质离子，在衬底表面形成第一区域(包括区域121和区域123)，参见图4a。
S330，在第一区域上生长氧化层作为掺杂阻挡层。
在本实施例中，是去除光刻胶后在衬底110表面生长氧化层，由于第一导电类型阱区掺杂窗口以外的区域被掩膜层覆盖(难以被氧化)，因此只会在第一导电类型阱区掺杂窗口形成掺杂阻挡层。
S340，去除掩膜层，掺杂第二导电类型离子形成第二区域。
在本实施例中，去除掩膜层后通过离子注入工艺，注入P型杂质离子。参见图4b，第一导电类型阱区掺杂窗口处由于形成了掺杂阻挡层173，因此只会在第一区域之外的位置形成第二区域(包括区域131、区域133和区域135)。可以理解的，在其他实施例中，第一区域也可以是通过注入P型离子形成，第二区域相应地是注入N型离子形成。
S350，热推阱使第一区域和第二区域扩散形成阱区。
在本实施例中，通过高温推阱使区域121扩散形成第一阱122，区域123扩散形成第二阱124，区域131扩散形成第三阱132，区域133扩散形成第四阱134，区域135扩散形成第五阱136，参见图4c。
在一个实施例中，热推阱的温度为1000～1300摄氏度，时间为250～350分钟。由于推阱的温度高、时间长，得到的阱区结深更深、掺杂浓度更低。因此当器件的电极加入电压时，耗尽层的展宽会更大，相当于电极极板之间的距离变大，因此寄生电容减小。在一个实施例中，步骤S340的离子注入的剂量要略高于步骤S320的离子注入的剂量；进一步地，步骤S320和S340的离子注入的剂量为5E11cm -2至5E12cm -2。
S360，通过光刻和掺杂形成第一至第六掺杂区，以及齐纳管有源区。
在去除掺杂阻挡层173之后(本实施例中在热推阱之前就去除掺杂阻挡层173)，通过光刻和掺杂，分别形成第一掺杂区141、第二掺杂区142、第三掺杂区151、第四掺杂区152、第五掺杂区161、第六掺杂区162及齐纳管 有源区139。在本实施例中，第一掺杂区141、第三掺杂区151、第五掺杂区161为N型掺杂区，第二掺杂区142、第四掺杂区152、第六掺杂区162为P型掺杂区，齐纳管有源区139为P型。在本实施例中，是先形成N型掺杂区，然后形成P型掺杂区，再形成齐纳管有源区139。
在一个实施例中，步骤S350和S360之间还包括形成隔离结构的步骤。具体可以是光刻后通过LOCOS工艺形成隔离结构170，参见图1。
在一个实施例中，形成隔离结构170之后，去除光刻胶，然后使用第一注入光刻版进行光刻，露出需要注入N型掺杂区的位置，注入N型离子以形成N型掺杂区；接着去除光刻胶，然后使用第二注入光刻版光刻进行光刻，露出需要注入P型掺杂区的位置，注入P型离子以形成P型掺杂区；再去除光刻胶，使用第三注入光刻版光刻并注入P型离子以形成齐纳管有源区。参见图1，齐纳管有源区139形成于第四阱134中；第一掺杂区141形成于第一阱122中；第二掺杂区142形成于第一阱122中；第三掺杂区151形成于第二阱124中；第四掺杂区152形成于第二阱124中；第五掺杂区161形成于齐纳管有源区139中；第六掺杂区162形成于齐纳管有源区139中。
在一个实施例中，步骤S360之后，还包括以下步骤：
形成介质层。具体地，可以采用淀积工艺形成层间介质(ILD)。
形成接触孔，并在接触孔内填充导电材料。具体地，可以光刻后刻蚀介质层形成接触孔。其中，所述导电材料可以为本领域技术人员熟知的任何适合的导电材料，包括但不限于金属材料；其中，所述金属材料可以包括Ag、Au、Cu、Pd、Pt、Cr、Mo、Ti、Ta、W和Al中的一种或几种。在一个实施例中，刻蚀介质层采用干法刻蚀工艺。
在介质层上形成金属互联线。具体地，可以淀积金属层后，光刻并刻蚀金属层形成金属互联线。在一个实施例中，淀积的金属层厚度为3微米。在一个实施例中，刻蚀金属层采用干法刻蚀工艺。
在一个实施例中，形成金属互联线之后还包括形成钝化层的步骤，以及光刻并腐蚀钝化层，形成金属电极引出的步骤。
在一个实施例中，层间介质可为氧化硅层，包括利用热化学气相沉积(thermal CVD)制造工艺或高密度等离子体(HDP)制造工艺形成的有掺杂或未掺杂的氧化硅的材料层，例如未经掺杂的硅玻璃(USG)、磷硅玻璃(PSG)或硼磷硅玻璃(BPSG)。此外，层间介质也可以是掺杂硼或掺杂磷的自旋涂布式玻璃(spin-on-glass，SOG)、掺杂磷的四乙氧基硅烷(PTEOS)或掺杂硼的四乙氧基硅烷(BTEOS)。
在一个实施例中，还可以通过平坦化的方法(例如化学机械研磨CMP)对沉积的层间介质进行平坦化，以使层间介质具有平坦的表面。
上述瞬态电压抑制器件的制造方法，通过第三阱对第一阱和第二阱进行隔离，相当于对第一二极管和第二二极管进行隔离，隔离效果好，避免了寄生BJT开启，因此ESD鲁棒性高、便于集成。且N阱和P阱是在步骤S350中同时推阱形成，可以减少阱的横扩尺寸，显著降低TVS芯片集成面积，有效降低了制造成本。
在一个实施例中，步骤S360形成齐纳管有源区139具体是注入磷离子和硼离子，硼离子的注入浓度大于磷离子的注入浓度。
在一个实施例中，形成齐纳管有源区139是以160keV的注入能量注入1E14cm -2的磷离子，并以180keV的注入能量注入3.8E14cm -2的硼离子。由于齐纳二极管D3是需要走大电流的管，所以通常在版图上会将很多齐纳二极管D3并联，导致版图面积很大。但是由于工艺的波动，如果齐纳二极管的击穿点靠近衬底表面，击穿会不稳定，并且容易提前烧毁器件。该实施例加入了一个较高浓度的磷离子注入，由于磷比砷的质量小，离子注入更深，并且热扩散比砷要快，因此可以将击穿点钳位在衬底中更深的地方，从而增加器件的可靠性(鲁棒性)。
在一个实施例中，步骤S320是注入5E15cm -2的砷离子和1E14cm -2的磷离子。
在一个实施例中，步骤S340是注入2.5E15cm -2的二氟化硼。
在一个实施例中，去除掺杂阻挡层173是采用湿法腐蚀工艺。
在一个实施例中，瞬态电压抑制器件的制造方法包括七道光刻工序：步骤310中的光刻，用于形成隔离结构170的光刻，使用第一注入光刻版形成N型掺杂区的光刻，使用第二注入光刻版形成P型掺杂区的光刻，使用第三注入光刻版形成齐纳管有源区的光刻，形成接触孔的光刻，形成金属互联线的光刻。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都为本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种瞬态电压抑制器件，包括：
    衬底，为第二导电类型；
    第一导电类型阱区，设于所述衬底中，包括第一阱和第二阱；
    第二导电类型阱区，设于所述衬底中，包括第三阱和第四阱，所述第三阱设于所述第一阱和第二阱之间从而将所述第一阱和第二阱相隔离，所述第二阱设于所述第三阱和第四阱之间；所述第一导电类型和第二导电类型为相反的导电类型；
    齐纳管有源区，设于所述第四阱中，为第二导电类型；
    第一掺杂区，为第一导电类型，设于所述第一阱中；
    第二掺杂区，为第二导电类型，设于所述第一阱中；
    第三掺杂区，为第一导电类型，设于所述第二阱中；
    第四掺杂区，为第二导电类型，设于所述第二阱中；
    第五掺杂区，为第一导电类型，设于所述齐纳管有源区中；及
    第六掺杂区，为第二导电类型，设于所述齐纳管有源区中；
    其中，所述第四掺杂区作为第一二极管的阳极区，所述第一掺杂区作为第二二极管的阴极区，所述第一掺杂区和所述第四掺杂区电性连接作为第一电位端；所述第三掺杂区作为所述第一二极管的阴极区，所述第五掺杂区作为齐纳二极管的阴极区，所述第三掺杂区和所述第五掺杂区电性连接作为第二电位端；所述第二掺杂区作为所述第二二极管的阳极区，所述第六掺杂区作为所述齐纳二极管的阳极区，所述第二掺杂区和所述第六掺杂区电性连接作为第三电位端。
  2. 根据权利要求1所述的瞬态电压抑制器件，其中，所述第一电位端用于电性连接输入输出端口，所述第二电位端用于电性连接工作电压端，所述第三电位端用于接地。
  3. 根据权利要求1所述的瞬态电压抑制器件，其中，所述第一导电类型 阱区和第二导电类型阱区的结深为7微米～15微米。
  4. 根据权利要求1所述的瞬态电压抑制器件，其中，所述第一导电类型为N型，所述第二导电类型为P型。
  5. 根据权利要求1所述的瞬态电压抑制器件，其中，所述第二导电类型阱区还包括第五阱，所述第一阱设于所述第三阱和第五阱之间。
  6. 根据权利要求1所述的瞬态电压抑制器件，其中，所述第一阱内设有两个所述第二掺杂区，所述第二阱内设有两个所述第三掺杂区，所述第四阱内设有两个所述第六掺杂区。
  7. 根据权利要求1所述的瞬态电压抑制器件，其中，还包括：
    设置于所述第一掺杂区和第二掺杂区之间将它们隔离的隔离结构；
    设置于所述第三掺杂区与第四掺杂区之间将它们隔离的隔离结构；
    设置于所述第一阱区和第二阱区中靠得最近的两个掺杂区之间、将所述两个掺杂区隔离的隔离结构；及
    设置于所述第二阱区和第四阱区中靠得最近的两个掺杂区之间、将这两个掺杂区隔离的隔离结构。
  8. 根据权利要求7所述的瞬态电压抑制器件，其中，各所述隔离结构为氧化绝缘材质。
  9. 一种瞬态电压抑制器件的制造方法，所述瞬态电压抑制器件包括第一二极管、第二二极管及齐纳二极管，所述第一二极管的阳极和所述第二二极管的阴极电性连接作为第一电位端，所述第一二极管的阴极和所述齐纳二极管的阴极电性连接作为第二电位端，所述第二二极管的阳极和所述齐纳二极管的阳极电性连接作为第三电位端，其中，所述方法包括：
    在第二导电类型的衬底上形成掩膜层，然后光刻并刻蚀所述掩膜层，露出第一导电类型阱区掺杂窗口；
    通过所述第一导电类型阱区掺杂窗口掺杂第一导电类型离子，在所述衬底表面形成第一区域；
    在所述第一区域上生长氧化层作为掺杂阻挡层；
    去除所述掩膜层，在衬底表面未被掺杂阻挡层覆盖的位置掺杂第二导电类型离子形成第二区域；所述第一导电类型和第二导电类型为相反的导电类型；
    热推阱，使所述第一区域扩散形成第一阱和第二阱、所述第二区域扩散形成第三阱和第四阱，所述第三阱位于所述第一阱和第二阱之间从而将所述第一阱和第二阱相隔离，所述第二阱位于所述第三阱和第四阱之间；及
    在去除所述掺杂阻挡层之后，通过光刻和掺杂，分别形成第一掺杂区、第二掺杂区、第三掺杂区、第四掺杂区、第五掺杂区、第六掺杂区及齐纳管有源区；
    其中，所述齐纳管有源区位于所述第四阱中，为第二导电类型；所述第一掺杂区为第一导电类型，位于所述第一阱中；所述第二掺杂区为第二导电类型，设于所述第一阱中；所述第三掺杂区为第一导电类型，设于所述第二阱中；所述第四掺杂区为第二导电类型，设于所述第二阱中；所述第五掺杂区为第一导电类型，设于所述齐纳管有源区中；所述第六掺杂区为第二导电类型，设于所述齐纳管有源区中。
  10. 根据权利要求9所述的方法，其中，所述热推阱的温度为1000～1300摄氏度，时间为250分钟～350分钟。
  11. 根据权利要求9所述的方法，其中，所述在第二导电类型的衬底上形成掩膜层，是淀积形成氮化硅层。
  12. 根据权利要求9所述的方法，其中，所述第一导电类型为N型，所述第二导电类型为P型；所述通过光刻和掺杂，分别形成第一掺杂区、第二掺杂区、第三掺杂区、第四掺杂区、第五掺杂区、第六掺杂区及齐纳管有源区的步骤包括：
    使用第一注入光刻版光刻并离子注入以形成第一掺杂区、第三掺杂区及第五掺杂区；
    使用第二注入光刻版光刻并离子注入以形成第二掺杂区、第四掺杂区及第六掺杂区；及
    使用第三注入光刻版光刻并离子注入以形成齐纳管有源区，包括注入磷离子和硼离子，所述硼离子的注入浓度大于所述磷离子的注入浓度。
  13. 根据权利要求12所述的瞬态电压抑制器件的制造方法，其中，所述形成齐纳管有源区的步骤是以160keV的注入能量注入1E14cm -2的磷离子、以180keV的注入能量注入3.8E14cm -2的硼离子。
  14. 根据权利要求9所述的方法，其中，所述去除所述掺杂阻挡层的步骤之后，所述通过光刻和掺杂，分别形成第一掺杂区、第二掺杂区、第三掺杂区、第四掺杂区、第五掺杂区、第六掺杂区及齐纳管有源区的步骤之前，还包括形成隔离结构的步骤，所述隔离结构用于将所述第一掺杂区与第二掺杂区相隔离，将所述第三掺杂区与第四掺杂区相隔离，将所述第一阱区和第二阱区中靠得最近的两个掺杂区相隔离，以及将所述第二阱区和第四阱区中靠得最近的两个掺杂区相隔离。
  15. 根据权利要求9所述的方法，其中，所述分别形成第一掺杂区、第二掺杂区、第三掺杂区、第四掺杂区、第五掺杂区、第六掺杂区及齐纳管有源区的步骤之后，还包括：
    形成介质层；
    形成接触孔，并在所述接触孔内填充导电材料；及
    在所述介质层上形成金属互联线，将所述第一二极管的阳极和所述第二二极管的阴极电性连接作为第一电位端，将所述第一二极管的阴极和所述齐纳二极管的阴极电性连接作为第二电位端，将所述第二二极管的阳极和所述齐纳二极管的阳极电性连接作为第三电位端。
PCT/CN2019/100690 2018-08-31 2019-08-15 瞬态电压抑制器件及其制造方法 WO2020042914A1 (zh)

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