WO2020042239A1 - 有机半导体器件的制备方法 - Google Patents

有机半导体器件的制备方法 Download PDF

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Publication number
WO2020042239A1
WO2020042239A1 PCT/CN2018/105621 CN2018105621W WO2020042239A1 WO 2020042239 A1 WO2020042239 A1 WO 2020042239A1 CN 2018105621 W CN2018105621 W CN 2018105621W WO 2020042239 A1 WO2020042239 A1 WO 2020042239A1
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organic semiconductor
patterned
layer
sacrificial layer
forming
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French (fr)
Inventor
陈黎暄
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/462,530 priority Critical patent/US10797254B2/en
Publication of WO2020042239A1 publication Critical patent/WO2020042239A1/zh
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40Organic transistors
    • H10K10/46Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462Insulated gate field-effect transistors [IGFETs]
    • H10K10/464Lateral top-gate IGFETs comprising only a single gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40Organic transistors
    • H10K10/46Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462Insulated gate field-effect transistors [IGFETs]
    • H10K10/468Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/471Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40Organic transistors
    • H10K10/46Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462Insulated gate field-effect transistors [IGFETs]
    • H10K10/481Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80Constructional details
    • H10K10/82Electrodes
    • H10K10/84Ohmic electrodes, e.g. source or drain electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10Deposition of organic active material
    • H10K71/12Deposition of organic active material using liquid deposition, e.g. spin coating

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a method for manufacturing an organic semiconductor device.
  • a method for preparing an organic semiconductor device uses an organic substance and a copper mask as a protective layer to protect the organic semiconductor layer.
  • an additional organic substance coating and a thermal evaporation process of a copper mask are added, which is relatively complicated.
  • the present disclosure provides a method for manufacturing an organic semiconductor device.
  • the method includes providing a substrate, forming a sacrificial layer on the substrate, performing patterned surface treatment on the sacrificial layer, forming a patterned lyophobic region on the sacrificial layer, and forming a sacrificial layer on the sacrificial layer.
  • a patterned organic semiconductor layer is formed thereon, an insulating layer is formed on the patterned organic semiconductor layer, a gate electrode is formed on the insulating layer, and the sacrificial layer and the semiconductor layer are separated from the patterned organic semiconductor layer.
  • the pattern of the patterned lyophobic region of the sacrificial layer is the same as or complementary to the pattern of the patterned organic semiconductor layer.
  • the insulating layer is an organic insulating layer.
  • the source-drain electrodes are patterned nano-silver wires or patterned carbon nanotubes.
  • the method further includes etching the sacrificial layer using a fluorine-containing gas.
  • the method further includes using octadecyltrichlorosilane (octadecyltrichlorosilane, OTS) performing a patterned surface treatment on the sacrificial layer.
  • octadecyltrichlorosilane octadecyltrichlorosilane, OTS
  • the method further includes forming an organic substrate on the gate electrode.
  • the present disclosure also provides a method for manufacturing an organic semiconductor device.
  • the method includes providing a substrate, forming a sacrificial layer on the substrate, forming a patterned organic semiconductor layer on the sacrificial layer, forming an insulating layer on the patterned organic semiconductor layer, and insulating the insulating layer.
  • a gate electrode is formed on the layer, the sacrificial layer and the substrate are separated from the patterned organic semiconductor layer, and a source-drain electrode is formed on the patterned organic semiconductor layer.
  • the method further includes performing a patterned surface treatment on the sacrificial layer.
  • the method further includes etching the sacrificial layer using a fluorine-containing gas.
  • the method further includes using octadecyltrichlorosilane (octadecyltrichlorosilane, OTS) performing a patterned surface treatment on the sacrificial layer.
  • octadecyltrichlorosilane octadecyltrichlorosilane, OTS
  • the method further includes forming a patterned lyophobic region on the sacrificial layer.
  • a pattern of the patterned lyophobic region of the sacrificial layer is the same as a pattern of the patterned organic semiconductor layer.
  • a pattern of the patterned lyophobic region of the sacrificial layer is complementary to a pattern of the patterned organic semiconductor layer.
  • the method further includes forming an organic substrate on the gate electrode.
  • the insulating layer is an organic insulating layer.
  • the source-drain electrodes are patterned nano-silver wires or patterned carbon nanotubes.
  • a method for preparing an organic semiconductor device in the embodiments of the present disclosure includes providing a substrate, forming a sacrificial layer on the substrate, and forming a patterned organic semiconductor layer on the sacrificial layer , Forming an insulating layer on the patterned organic semiconductor layer, forming a gate electrode on the insulating layer, separating the sacrificial layer and the substrate from the patterned organic semiconductor layer, and forming a source-drain electrode on the patterned organic semiconductor layer, Therefore, a simple and effective method for manufacturing an organic semiconductor device can be provided.
  • FIG. 1 shows a flowchart of a method for manufacturing an organic semiconductor device according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing a method for manufacturing an organic semiconductor device according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a method for manufacturing an organic semiconductor device according to an embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of a method for manufacturing an organic semiconductor device according to an embodiment of the disclosure
  • FIG. 5 shows a schematic diagram of a method for manufacturing an organic semiconductor device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a method for manufacturing an organic semiconductor device according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a method for manufacturing an organic semiconductor device, including the following steps.
  • step 1 provides a substrate 100.
  • the material of the substrate 100 includes, for example, silicon (Si) or silicon dioxide (SiO2).
  • Step 2 A sacrificial layer 200 is formed on the substrate 100.
  • the entire surface of the sacrificial layer 200 is formed on the substrate 100.
  • a patterned surface treatment is performed on the sacrificial layer 200.
  • a patterned lyophobic region is formed on the sacrificial layer 200.
  • the sacrificial layer 200 is etched using a fluorine-containing gas.
  • a surface treatment for patterning the sacrificial layer 200 using octadecyltrichlorosilane (OTS) is used.
  • Step 3 A patterned organic semiconductor layer 300 is formed on the sacrificial layer 200.
  • the pattern of the patterned liquid-repellent region of the sacrificial layer 200 is the same as the pattern of the patterned organic semiconductor layer 300.
  • the pattern of the patterned lyophobic region of the sacrificial layer 200 is complementary to the pattern of the patterned organic semiconductor layer 300.
  • a patterned surface treatment is performed on the surface of the sacrificial layer 200 by spray printing. Since the surface of the sacrificial layer 200 is subjected to patterning pretreatment, the solution of the organic semiconductor layer 300 and the surface of the sacrificial layer 200 are affinitive. The difference is that the organic semiconductor layer 300 is easy to gather into a patterned shape, and then the solution of the semiconductor layer 300 is cured by heating or ultraviolet light to form the patterned organic semiconductor layer 300.
  • an insulating layer 400 is formed on the patterned organic semiconductor layer 300.
  • the insulating layer 400 is an organic insulating layer.
  • the organic semiconductor layer 300 is formed, other functional layers may be manufactured.
  • an organic semiconductor layer 300 is prepared on the entire surface of the organic semiconductor layer 300.
  • a gate electrode 500 is formed on the insulating layer 400.
  • step 6 the sacrificial layer 200 and the substrate 100 are separated from the patterned organic semiconductor layer 300.
  • the substrate 100 is peeled off through the sacrificial layer 200 so that the organic semiconductor layer 300 is exposed.
  • the method further includes forming an organic substrate 600 on the gate electrode 500.
  • a polyimide (PI) substrate is made as the organic substrate 600 by using a coating method.
  • a coated polystyrene-block-ethlene-block-styrene (SEBS) substrate is used as the organic substrate 600.
  • a source-drain electrode 700 is formed on the patterned organic semiconductor layer 300.
  • the source-drain electrode 700 is a patterned nano-silver wire or a patterned carbon nanotube.
  • the features of the embodiments of the present disclosure include forming a patterned organic semiconductor layer 300 on the substrate 100, and then forming an insulating layer 400 on the patterned organic semiconductor layer 300.
  • the gate electrode 500 can be formed on the entire insulating layer 400. This effectively protects the organic semiconductor layer 300. Thereafter, the substrate 100 is peeled off to expose the organic semiconductor layer 300 and a source-drain electrode 700 formed to contact the organic semiconductor layer 300.
  • the method for preparing an organic semiconductor device in the embodiments of the present disclosure is simple and effective, which is beneficial to improving efficiency when mass-producing flexible electronic devices.
  • the organic semiconductor device is, for example, a flexible organic semiconductor device.
  • the method for manufacturing an organic semiconductor device in the embodiments of the present disclosure includes providing a substrate, forming a sacrificial layer on the substrate, forming a patterned organic semiconductor layer on the sacrificial layer, and forming an insulating layer on the patterned organic semiconductor layer.
  • a gate electrode is formed on the insulating layer, a sacrificial layer and a substrate are separated from the patterned organic semiconductor layer, and a source-drain electrode is formed on the patterned organic semiconductor layer, so it can provide a simple and effective method for preparing an organic semiconductor device. .

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种有机半导体器件的制备方法,所述方法包括提供衬底(100),在衬底(100)上形成牺牲层(200),在牺牲层(200)上形成图案化的有机半导体层(300),在图案化的有机半导体层(300)上形成绝缘层(400),在绝缘层(400)上形成栅电极(500),从图案化的有机半导体层(300)上分离牺牲层(200)及衬底(100),以及在图案化的有机半导体层(300)上形成源漏电极(700),从而提供简单有效的有机半导体器件的制备方法。

Description

有机半导体器件的制备方法 技术领域
本揭示涉及显示技术领域,特别涉及一种有机半导体器件的制备方法。
背景技术
在现有技术中,有机半导体器件的制备方法使用有机物及铜掩模版作为保护层,以保护有机半导体层。现有技术的制备方案为了有效地保护有机半导体层,增加了额外的有机物涂布与铜掩模版的热蒸镀工艺,较为复杂。
故,有需要提供一种有机半导体器件的制备方法,以解决现有技术存在的问题。
技术问题
现有技术的制备方案为了有效地保护有机半导体层,增加了额外的有机物涂布与铜掩模版的热蒸镀工艺,较为复杂。
技术解决方案
为达成上述目的,本揭示提供了有机半导体器件的制备方法。所述方法包括提供衬底,在所述衬底上形成牺牲层,在所述牺牲层上进行图案化的表面处理,在所述牺牲层上形成图案化的疏液区,在所述牺牲层上形成图案化的有机半导体层,在所述图案化的有机半导体层上形成绝缘层,在所述绝缘层上形成栅电极,从所述图案化的有机半导体层上分离所述牺牲层及所述衬底,以及在所述图案化的有机半导体层上形成源漏电极。所述牺牲层的所述图案化的疏液区的图案与所述图案化的有机半导体层的图案相同或互补。所述绝缘层为有机绝缘层。所述源漏电极为图案化的纳米银线或图案化的碳纳米管。
于本揭示其中的一实施例中,所述方法还包括使用含氟气体蚀刻所述牺牲层。
于本揭示其中的一实施例中,所述方法还包括使用十八烷基三氯硅烷(octadecyltrichlorosilane, OTS)对所述牺牲层进行图案化的表面处理。
于本揭示其中的一实施例中,所述方法还包括在所述栅电极上形成有机衬底。
本揭示还提供了有机半导体器件的制备方法。所述方法包括提供衬底,在所述衬底上形成牺牲层,在所述牺牲层上形成图案化的有机半导体层,在所述图案化的有机半导体层上形成绝缘层,在所述绝缘层上形成栅电极,从所述图案化的有机半导体层上分离所述牺牲层及所述衬底,以及在所述图案化的有机半导体层上形成源漏电极。
于本揭示其中的一实施例中,所述方法还包括在所述牺牲层上进行图案化的表面处理。
于本揭示其中的一实施例中,所述方法还包括使用含氟气体蚀刻所述牺牲层。
于本揭示其中的一实施例中,所述方法还包括使用十八烷基三氯硅烷(octadecyltrichlorosilane, OTS)对所述牺牲层进行图案化的表面处理。
于本揭示其中的一实施例中,所述方法还包括在所述牺牲层上形成图案化的疏液区。
于本揭示其中的一实施例中,所述牺牲层的所述图案化的疏液区的图案与所述图案化的有机半导体层的图案相同。
于本揭示其中的一实施例中,所述牺牲层的所述图案化的疏液区的图案与所述图案化的有机半导体层的图案互补。
于本揭示其中的一实施例中,所述方法还包括在所述栅电极上形成有机衬底。
于本揭示其中的一实施例中,所述绝缘层为有机绝缘层。
于本揭示其中的一实施例中,所述源漏电极为图案化的纳米银线或图案化的碳纳米管。
有益效果
相较于现有技术,为解决上述技术问题,本揭示的实施例中的有机半导体器件的制备方法包括提供衬底,在衬底上形成牺牲层,在牺牲层上形成图案化的有机半导体层,在图案化的有机半导体层上形成绝缘层,在绝缘层上形成栅电极,从图案化的有机半导体层上分离牺牲层及衬底,以及在图案化的有机半导体层上形成源漏电极,因此能提供简单有效的有机半导体器件的制备方法。
附图说明
图1显示根据本揭示的一实施例的有机半导体器件的制备方法的流程图;
图2显示根据本揭示的一实施例的有机半导体器件的制备方法的示意图;
图3显示根据本揭示的一实施例的有机半导体器件的制备方法的示意图;
图4显示根据本揭示的一实施例的有机半导体器件的制备方法的示意图;
图5显示根据本揭示的一实施例的有机半导体器件的制备方法的示意图;以及
图6显示根据本揭示的一实施例的有机半导体器件的制备方法的示意图。
本发明的最佳实施方式
以下各实施例的说明是参考附加的图式,用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂,下文将特举本揭示优选实施例,并配合所附图式,作详细说明如下。再者,本揭示所提到的方向用语,例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本揭示,而非用以限制本揭示。
在图中,结构相似的单元是以相同标号表示。
参照图1,本揭示的一实施例提供机半导体器件的制备方法,包括如下步骤。
参照图1及图2,步骤1、提供衬底100。衬底100的材料例如包括硅(Si)或二氧化硅(SiO2)。
步骤2、在衬底100上形成牺牲层200。
具体地,在衬底100上形成整面的牺牲层200。在牺牲层200上进行图案化的表面处理。在牺牲层200上形成图案化的疏液区。在一实施例中,使用含氟气体蚀刻牺牲层200。在另一实施例中,使用使用十八烷基三氯硅烷(octadecyltrichlorosilane, OTS)对牺牲层200进行图案化的表面处理。
步骤3、在牺牲层200上形成图案化的有机半导体层300。
具体地,在一实施例中,牺牲层200的图案化的疏液区的图案与图案化的有机半导体层300的图案相同。在另一实施例中,牺牲层200的图案化的疏液区的图案与图案化的有机半导体层300的图案互补。
具体地,通过喷印的方式在牺牲层200的表面进行图案化的表面处理,由于牺牲层200的表面进行了图案化的预处理,有机半导体层300的溶液与牺牲层200的表面亲疏性的区别,因此有机半导体层300容易聚集出图案化的形状,接着经过加热或紫外光固化半导体层300的溶液以形成图案化的有机半导体层300。
参照图1及图3,步骤4、在图案化的有机半导体层300上形成绝缘层400。
具体地,绝缘层400为有机绝缘层。具体而言,在有机半导体层300形成后,可进行其他功能层的制作,例如在有机半导体层300的上方整面制备一层有机半导体层300。
参照图1及图4,步骤5、在绝缘层400上形成栅电极500。
参照图1及图5,步骤6、从图案化的有机半导体层300上分离牺牲层200及衬底100。
具体地,通过牺牲层200剥离掉衬底100,使得有机半导体层300露出。
具体地,所述方法还包括在栅电极500上形成有机衬底600。具体地,例如使用涂布的方式制作聚亚酰胺(polyimide, PI) 衬底做为有机衬底600。例如使用涂布的方式制作氢化橡胶(polystyrene-block-ethlene-block-styrene,SEBS)衬底做为有机衬底600。
参照图1及图6,步骤7、在图案化的有机半导体层300上形成源漏电极700。
具体地,源漏电极700为图案化的纳米银线或图案化的碳纳米管。
本揭示的实施例的特征包括,在衬底100上形成图案化的有机半导体层300,然后在图案化的有机半导体层300上形成绝缘层400,通过整面绝缘层400可以在形成栅电极500时有效保护有机半导体层300。之后再剥离衬底100,露出有机半导体层300及形成接触有机半导体层300的源漏电极700。本揭示的实施例中的有机半导体器件的制备方法简单有效,有利于在大规模生产柔性电子器件时提高效率。
至此,即完成了有机半导体器件的制备方法。有机半导体器件例如为柔性有机半导体器件。
由于本揭示的实施例中的有机半导体器件的制备方法包括提供衬底,在衬底上形成牺牲层,在牺牲层上形成图案化的有机半导体层,在图案化的有机半导体层上形成绝缘层,在绝缘层上形成栅电极,从图案化的有机半导体层上分离牺牲层及衬底,以及在图案化的有机半导体层上形成源漏电极,因此能提供简单有效的有机半导体器件的制备方法。
尽管已经相对于一个或多个实现方式示出并描述了本揭示,但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型,并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能,用于描述这样的组件的术语旨在对应于执行所述组件的指定功能(例如其在功能上是等价的)的任意组件(除非另外指示),即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外,尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开,但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且,就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言,这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式,应当指出,对于本领域普通技术人员,在不脱离本揭示原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本揭示的保护范围。

Claims (14)

  1. 一种有机半导体器件的制备方法,包括:
    提供衬底;
    在所述衬底上形成牺牲层;
    在所述牺牲层上进行图案化的表面处理,在所述牺牲层上形成图案化的疏液区;
    在所述牺牲层上形成图案化的有机半导体层,所述牺牲层的所述图案化的疏液区的图案与所述图案化的有机半导体层的图案相同或互补;
    在所述图案化的有机半导体层上形成绝缘层,所述绝缘层为有机绝缘层;
    在所述绝缘层上形成栅电极;
    从所述图案化的有机半导体层上分离所述牺牲层及所述衬底;以及
    在所述图案化的有机半导体层上形成源漏电极,所述源漏电极为图案化的纳米银线或图案化的碳纳米管。
  2. 如权利要求1所述的有机半导体器件的制备方法,还包括使用含氟气体蚀刻所述牺牲层。
  3. 如权利要求1所述的有机半导体器件的制备方法,还包括使用十八烷基三氯硅烷对所述牺牲层进行图案化的表面处理。
  4. 如权利要求1所述的有机半导体器件的制备方法,还包括在所述栅电极上形成有机衬底。
  5. 一种有机半导体器件的制备方法,包括:
    提供衬底;
    在所述衬底上形成牺牲层;
    在所述牺牲层上形成图案化的有机半导体层;
    在所述图案化的有机半导体层上形成绝缘层;
    在所述绝缘层上形成栅电极;
    从所述图案化的有机半导体层上分离所述牺牲层及所述衬底;以及
    在所述图案化的有机半导体层上形成源漏电极。
  6. 如权利要求5所述的有机半导体器件的制备方法,还包括在所述牺牲层上进行图案化的表面处理。
  7. 如权利要求6所述的有机半导体器件的制备方法,还包括使用含氟气体蚀刻所述牺牲层。
  8. 如权利要求6所述的有机半导体器件的制备方法,还包括使用十八烷基三氯硅烷对所述牺牲层进行图案化的表面处理。
  9. 如权利要求6所述的有机半导体器件的制备方法,还包括在所述牺牲层上形成图案化的疏液区。
  10. 如权利要求9所述的有机半导体器件的制备方法,其中所述牺牲层的所述图案化的疏液区的图案与所述图案化的有机半导体层的图案相同。
  11. 如权利要求9所述的有机半导体器件的制备方法,其中所述牺牲层的所述图案化的疏液区的图案与所述图案化的有机半导体层的图案互补。
  12. 如权利要求5所述的有机半导体器件的制备方法,还包括在所述栅电极上形成有机衬底。
  13. 如权利要求1所述的有机半导体器件的制备方法,其中所述绝缘层为有机绝缘层。
  14.     如权利要求5所述的有机半导体器件的制备方法,其中所述源漏电极为图案化的纳米银线或图案化的碳纳米管。
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