WO2020024382A1 - Unité goa et procédé de pilotage de celle-ci - Google Patents

Unité goa et procédé de pilotage de celle-ci Download PDF

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Publication number
WO2020024382A1
WO2020024382A1 PCT/CN2018/105697 CN2018105697W WO2020024382A1 WO 2020024382 A1 WO2020024382 A1 WO 2020024382A1 CN 2018105697 W CN2018105697 W CN 2018105697W WO 2020024382 A1 WO2020024382 A1 WO 2020024382A1
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Prior art keywords
thin film
film transistor
electrically connected
unit
goa unit
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Application number
PCT/CN2018/105697
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English (en)
Chinese (zh)
Inventor
朱静
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2020024382A1 publication Critical patent/WO2020024382A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to a GOA unit and a driving method thereof, and in particular to a GOA unit and a driving method thereof for improving a cut-angle voltage.
  • Liquid crystal display referred to as liquid crystal panel
  • LCD has many advantages such as thin body, power saving, no radiation, etc., and has been widely used, for example: LCD TV, smart phone, digital camera, tablet computer, computer Screens, or laptop screens, dominate the flat panel display space.
  • the working principle of a liquid crystal panel is based on a thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate) and a color filter substrate (Color Filter (CF) is filled with liquid crystal molecules, and a driving voltage is applied to the two substrates to control the rotation direction of the liquid crystal molecules, and the light of the backlight module is refracted to generate a picture.
  • a thin film transistor array substrate Thin Film Transistor Array Substrate, TFT Array Substrate
  • CF Color Filter
  • the liquid crystal panel has a plurality of pixels arranged in an array. Each pixel is electrically connected to a thin film transistor (TFT), a gate of the thin film transistor is connected to a horizontal scanning line, and a source is connected to a vertical direction. The drain line is connected to the pixel electrode. Applying sufficient voltage on the horizontal scanning line will cause all TFTs electrically connected to the horizontal scanning line to be turned on, so that the signal voltage on the data line can be written into the pixel, controlling the transmittance of different liquid crystals to achieve color control With the effect of brightness.
  • TFT thin film transistor
  • Gate Driver on Array is a method of integrating a gate line scan driving circuit on a TFT array substrate by using an existing Array process of a thin film transistor liquid crystal panel to realize a driving method for scanning a gate.
  • GOA driver circuits instead of traditional gate drive chips (ICs) has the opportunity to increase productivity and reduce product costs, and can make LCD panels more suitable for making narrow-frame or borderless display products.
  • the existing GOA circuit usually includes a plurality of cascaded GOA units, and each stage of the GOA unit drives a horizontal scanning line correspondingly.
  • the main structure of the GOA unit includes a pull-up unit, a pull-up control unit, a pull-down unit and a pull-down maintenance unit, and a bootstrap capacitor that is responsible for raising the potential;
  • the pull-up unit is mainly responsible for outputting the clock signal (Clock) as Gate signal;
  • the pull-up control unit is responsible for controlling the opening time of the pull-up unit, which is generally connected to the stage signal or gate signal passed from the previous stage GOA circuit;
  • the pull-down unit is responsible for pulling the gate signal to a low potential at the first time , That is, the gate signal is turned off;
  • the pull-down maintenance unit is responsible for maintaining the gate output signal and the gate signal of the pull-up unit (usually referred to as the Q point) in a closed state (that is, a negative potential); Second lift, which is good for G (n
  • the gate line (Gate Line) has a heavy resistance and capacitance load (RC Loading), which causes gate distortion (Distortion) of the gate pulse signal (Distortion) is very serious, and the variation of the superimposed process results in the uniformity of the voltage Vft is particularly poor; It is set to a fixed value, so it cannot cover every position of the panel. As a result, the quality of the panel is poor, such as crosstalk and flicker.
  • An object of the present invention is to provide a GOA unit and a driving method thereof, by setting a pair of thin film transistors to adjust a charge ratio of two thin film transistors, so as to realize a cut angle function of a gate pulse and improve the cut angle. Voltage.
  • the present invention provides a GOA unit, wherein the GOA unit includes a pull-up control unit, a pull-up unit, a pull-down unit, a pull-down maintenance unit, and a bootstrap capacitor (Cb);
  • a third thin film transistor (T21) of the pull-up unit forms a pair of charge with a pair of thin film transistors to adjust a ratio of a charge of the third thin film transistor (T21) and the pair of thin film transistors.
  • the n-th GOA unit controls the charging of the n-th horizontal scanning line.
  • the counter-charge thin film transistor is a sixth thin film transistor (T23); the pull-up unit, the pull-down unit, the pull-down sustain unit, and the bootstrap capacitor (Cb) And the sixth thin film transistor (T23) is electrically connected to a gate signal output terminal (G (n)) of the n-th GOA unit; the pull-up control unit and the pull-down unit are connected to the n-th GOA
  • the gate signal point (Q (n)) of the unit is electrically connected;
  • a gate of the sixth thin film transistor (T23) is electrically connected to a gate signal output terminal (G ( n + 3)), the source of the sixth thin film transistor (T23) is electrically connected to the gate signal output terminal (G (n)), and the drain of the sixth thin film transistor (T23) is electrically connected A working voltage (VSSG).
  • the pull-up control unit includes: a first thin film transistor (T11), a gate of which is electrically connected to a first-level signal output terminal of a nm-level GOA unit, and a drain of which is electrically connected A gate signal output terminal of the nm-level GOA unit, m is a natural number; and a second thin film transistor (T22), the gate of which is electrically connected to the source of the first thin film transistor (T11), and the source is electrically The first-stage signal output terminal connected to the n-th GOA unit, and the drain is electrically connected to a clock signal (CK).
  • a gate of the third thin film transistor (T21) is electrically connected to a gate signal point (Q (n)) of the n-th GOA unit, and the third thin film transistor (T The source of T21) is electrically connected to the gate signal output terminal (G (n)) of the n-th GOA unit, and the drain of the third thin film transistor (T21) is electrically connected to a clock signal (CK).
  • the pull-down unit includes a fourth thin film transistor (T41), the gate of which is connected to the gate signal output terminal of the n + m-th GOA unit, m is a natural number, and the drain is electrically A gate signal point (Q (n)) connected to the n-th GOA unit, a source electrically connected to an operating voltage (VSSQ); and a fifth thin film transistor (T31), the gate of which is connected to the n + mth
  • the gate signal output terminal of the stage GOA unit, the drain electrode is electrically connected to the gate signal output terminal (G (n)), and the source electrode is electrically connected to the operating voltage (VSSG).
  • the pull-up unit, the pull-down unit, the pull-down sustaining unit, and the bootstrap capacitor (Cb) are respectively connected to a gate signal output terminal (G) of the n-th GOA unit.
  • the pull-down unit includes a fourth thin film transistor (T41) and a fifth thin film transistor (T31), the counter-charge thin film transistor is a fifth thin film transistor (T31), wherein the gate of the fourth thin film transistor (T41) is connected to the n + m-th GOA unit
  • the gate signal output terminal, m is a natural number, and the drain of the fourth thin film transistor (T41) is electrically connected to the gate signal point (Q (n)) of the n-th GOA unit, and the fourth thin film transistor
  • the source of (T41) is electrically connected to an operating voltage (VSSQ); the
  • a source of the fifth thin film transistor (T31) is electrically connected to the operating voltage (VSSG).
  • a source of the fifth thin film transistor (T31) is electrically connected to a clock signal (CK2).
  • the invention provides a driving method.
  • the driving method includes the steps of: a turning-on step: turning on a stage signal output terminal of a first-level GOA unit and a gate signal output terminal of a first-level GOA unit, so that the n-stage GOA
  • the gate signal point (Q (n)) of the cell is a high-potential signal
  • a clock signal input step input a clock signal (CK) to make the gate signal point (Q (n) of the n-th GOA cell) ) Is pulled high and is output by a gate signal output terminal (G (n)) of the n-th GOA unit
  • a pair of charging steps when the gate signal output terminal (G (n)) is turned on, all The gate signal output terminal (G (n)) is still outputting a pulse signal, a low potential signal is output through a pair of thin film transistors, and the clock signal and the gate signal output terminal of the n + 3 level GOA unit (G (n + 3)) within a time (
  • the power-to-charge ratio is a width-to-length ratio of a waveform of signals output by the pair of thin-film transistors and the third thin-film transistor (T21).
  • the present invention provides a GOA unit, wherein the GOA unit includes a pull-up control unit, a pull-up unit, a pull-down unit, a pull-down maintenance unit, and a bootstrap capacitor (Cb);
  • a third thin film transistor (T21) of the pull-up unit forms a pair of charge with a pair of thin film transistors to adjust a ratio of a charge of the third thin film transistor (T21) and the pair of thin film transistors. , And output an output waveform with different cut-angle voltages.
  • the counter-charge thin film transistor is a sixth thin film transistor (T23); the pull-up unit, the pull-down unit, the pull-down sustain unit, and the bootstrap capacitor (Cb) And the sixth thin film transistor (T23) is electrically connected to a gate signal output terminal (G (n)) of the n-th GOA unit; the pull-up control unit and the pull-down unit are connected to the n-th GOA
  • the gate signal point (Q (n)) of the unit is electrically connected;
  • a gate of the sixth thin film transistor (T23) is electrically connected to a gate signal output terminal (G ( n + 3)), the source of the sixth thin film transistor (T23) is electrically connected to the gate signal output terminal (G (n)), and the drain of the sixth thin film transistor (T23) is electrically connected A working voltage (VSSG).
  • the pull-up control unit includes: a first thin film transistor (T11), a gate of which is electrically connected to a first-level signal output terminal of a nm-level GOA unit, and a drain of which is electrically connected A gate signal output terminal of the nm-level GOA unit, m is a natural number; and a second thin film transistor (T22), the gate of which is electrically connected to the source of the first thin film transistor (T11), and the source is electrically The first-stage signal output terminal connected to the n-th GOA unit, and the drain is electrically connected to a clock signal (CK).
  • a gate of the third thin film transistor (T21) is electrically connected to a gate signal point (Q (n)) of the n-th GOA unit, and the third thin film transistor (T The source of T21) is electrically connected to the gate signal output terminal (G (n)) of the n-th GOA unit, and the drain of the third thin film transistor (T21) is electrically connected to a clock signal (CK).
  • the pull-down unit includes a fourth thin film transistor (T41), the gate of which is connected to the gate signal output terminal of the n + m-th GOA unit, m is a natural number, and the drain is electrically A gate signal point (Q (n)) connected to the n-th GOA unit, a source electrically connected to an operating voltage (VSSQ); and a fifth thin film transistor (T31), the gate of which is connected to the n + mth
  • the gate signal output terminal of the stage GOA unit, the drain electrode is electrically connected to the gate signal output terminal (G (n)), and the source electrode is electrically connected to the operating voltage (VSSG).
  • the pull-up unit, the pull-down unit, the pull-down sustaining unit, and the bootstrap capacitor (Cb) are respectively connected to a gate signal output terminal (G) of the n-th GOA unit.
  • the pull-down unit includes a fourth thin film transistor (T41) and a fifth thin film transistor (T31), the counter-charge thin film transistor is a fifth thin film transistor (T31), wherein the gate of the fourth thin film transistor (T41) is connected to the n + m-th GOA unit
  • the gate signal output terminal, m is a natural number, and the drain of the fourth thin film transistor (T41) is electrically connected to the gate signal point (Q (n)) of the n-th GOA unit, and the fourth thin film transistor
  • the source of (T41) is electrically connected to an operating voltage (VSSQ); the
  • a source of the fifth thin film transistor (T31) is electrically connected to the operating voltage (VSSG).
  • a source of the fifth thin film transistor (T31) is electrically connected to a clock signal (CK2).
  • the beneficial effect of the present invention is that the present invention sets up the pair of thin film transistors on the basis of the existing GOA circuit, and uses the existing signals, such as the working voltage VSSG and the gate signal output terminal as signal sources, so as to realize The cut angle function of the gate pulse, wherein the cut angle time can be adjusted according to the resolution of the product and the number and duty cycle of the clock signal, and the cut angle voltage can be adjusted by adjusting the pair of thin film transistors and the first
  • the three thin-film transistors have different width-to-length ratios to achieve different cut-angle voltages, so that it is possible to implement the cut-angle function without the back-end chip, reduce the volume integrated in the panel circuit, and reduce the cost of the chip.
  • FIG. 1 is a schematic structural diagram of a first preferred embodiment of a GOA unit according to the present invention.
  • FIG. 2 is a waveform diagram of a GOA unit according to a first preferred embodiment of the present invention.
  • FIG. 3 is a flowchart of a first preferred embodiment of a driving method of a GOA unit according to the present invention.
  • FIGS. 4 and 5 are schematic diagrams of an architecture of a second preferred embodiment of the GOA unit of the present invention.
  • FIG. 1 is a schematic structural diagram of a GOA unit according to a preferred embodiment of the present invention.
  • the GOA circuit of the present invention includes a plurality of cascaded GOA units, wherein the n-th GOA unit controls the charging of the n-th horizontal scanning line, and the n-th GOA unit includes a pull-up control unit 2 and a pull-up Unit 3, pull-down unit 4, pull-down sustain unit 5, a bootstrap capacitor Cb, and a sixth thin film transistor T23, where the sixth thin film transistor T23 is a pair of thin film transistors, and the present invention will be described in detail below.
  • Example The detailed structure, assembly relationship and operation principle of the above components.
  • the pull-up unit 3, the pull-down unit 4, the pull-down sustaining unit 5, the bootstrap capacitor Cb, and the sixth thin film transistor T23 are each one of the n-th GOA unit.
  • the gate signal output terminal G (n) is electrically connected, and the pull-up control unit 2 and the pull-down unit 4 are electrically connected to the gate signal point Q (n) of the n-th GOA unit.
  • a gate of the sixth thin film transistor T23 is electrically connected to a gate signal output terminal G (n + 3) of the n + 3 level GOA unit, and a source of the sixth thin film transistor T23 is electrically connected.
  • the gate signal output terminal G (n) and a drain of the sixth thin film transistor T23 are electrically connected to a working voltage VSSG.
  • the pull-up control unit 2 includes a first thin film transistor T11 and a second thin film transistor T22, wherein a gate of the first thin film transistor T11 is electrically connected to the nm-level GOA unit.
  • a first-level signal output terminal for example: ST (n-4)
  • a drain of the first thin film transistor T11 is electrically connected to a gate signal output terminal of the nm-level GOA unit, for example: G (n-4 ), Where m is a natural number.
  • a gate of the second thin film transistor T22 is electrically connected to a source of the first thin film transistor T11 and a gate signal point Q (n) of the n-th GOA unit, and the second thin film A source of the transistor T22 is electrically connected to a first-stage signal output terminal of the n-th GOA unit, for example, ST (n), and a drain of the second thin film transistor T22 is electrically connected to a clock signal CK.
  • the pull-up unit 3 includes a third thin film transistor T21, wherein a gate of the third thin film transistor T21 is electrically connected to a gate signal point Q of the n-th GOA unit ( n), a source of the third thin film transistor T21 is electrically connected to a gate signal output terminal G (n) of the n-th GOA unit, and a drain of the third thin film transistor T21 is electrically connected to a Clock signal CK.
  • the pull-down unit includes a fourth thin film transistor T41 and a fifth thin film transistor T31, wherein a gate of the fourth thin film transistor T41 is connected to a gate signal of an n + m-th GOA unit.
  • the output end is, for example, G (n + 4), where m is a natural number, a drain of the fourth thin film transistor T41 is electrically connected to the n-th gate signal point Q (n), and the fourth thin film A source of the transistor T41 is electrically connected to an operating voltage VSSQ.
  • a gate of the fifth thin film transistor T31 is connected to a gate signal output terminal of the n + m-th GOA unit, for example, G (n + 4), and a drain of the fifth thin film transistor T31 is electrically The gate signal output terminal G (n) is connected, and a source of the fifth thin film transistor T31 is electrically connected to the working voltage VSSG.
  • the present invention can provide a GOA circuit, and the GOA circuit includes a plurality of cascaded GOA units.
  • the present invention can also provide a display device including the GOA circuit.
  • the low potential of the stage signal output terminal ST (n) is an operating voltage VSSQ
  • the gate signal output terminal G (n) The low potential is an operating voltage VSSG that turns on the first-stage signal output terminal ST1 of a first-stage GOA unit and the gate signal output terminal G1 of the first-stage GOA unit, so that the n-th gate signal point Q (n) is turned on.
  • a clock signal CK is input so that the n-th gate signal point Q (n) is pulled up and output by a gate signal output terminal G (n) of the n-th GOA unit And when the gate signal output terminal G (n) is turned on, the gate signal output terminal G (n) is still outputting a pulse signal, and a low potential signal is output through a sixth thin film transistor T23.
  • the clock signal and the gate signal output terminal G (n + 3) of the n + 3 level GOA unit are overlapped within a time T, so that the sixth thin film transistor T23 and a third thin film transistor T21 of the pull-up unit perform
  • the amount of charge is finally adjusted by adjusting the ratio of an amount of charge of the sixth thin film transistor T23 and the third thin film transistor T21 to output different values.
  • An output waveform of the cut-off voltage In this embodiment, the ratio of the amount of electricity to the charge of the waveform of the sixth thin film transistor T23, that is, the width-to-length ratio (W / L Ratio) is about 60, and the gate of the sixth thin film transistor T23 can be implemented.
  • the output angle-cut voltage is about 3V.
  • the width-to-length ratio (W / L Ratio) of the sixth thin film transistor T23 is adjusted to about 200, the output cut-off voltage of the gate is about 5V.
  • the present invention provides the sixth thin film transistor T23 on the basis of the existing GOA circuit, and uses the existing signals, such as the operating voltage VSSG and the gate signal output terminal G (n + 3) As a signal source, in order to realize the gate pulse (Gate Pulse) cut angle function (Function), wherein the cut angle time can be based on the product's resolution and the number of clock signals CK and the duty ratio (Duty Ratio)
  • the cut-angle voltage can be adjusted by adjusting the width / length ratio of the sixth thin film transistor T23 and the third thin-film transistor T21 to achieve different cut-angle voltages, so that it is not necessary to use a rear chip. Executing the angle cut function reduces the volume integrated in the panel circuit and reduces the cost of the chip.
  • FIG. 3 is a preferred embodiment of a driving method of a GOA unit according to the present invention, which is driven by using the GOA unit.
  • the driving method includes an opening step S201 and a clock signal input step S202.
  • the present invention will explain the operation principle of each step in detail below.
  • the first-stage signal output terminal ST1 of a first-stage GOA unit and the gate signal output terminal G1 of the first-stage GOA unit are turned on. , So that the n-th gate signal point Q (n) is a high-potential signal.
  • a clock signal CK is input so that the n-th gate signal point Q (n) is pulled up and the n-th GOA unit A gate signal output terminal G (n) is output.
  • a sixth thin film transistor T23 is set as a pair of thin film transistors.
  • the gate signal output terminal G (n) is turned on, all the The gate signal output terminal G (n) is still outputting a pulse signal, a low potential signal is output through the sixth thin film transistor T23, and the clock signal and the gate signal output terminal of the n + 3 level GOA unit Within a time T (shown in FIG. 2) where G (n + 3) overlaps, the sixth thin film transistor T23 and a third thin film transistor T21 of the pull-up unit are charged with electricity.
  • the adjustment step S204 by adjusting a charge-to-charge ratio of the sixth thin film transistor T23 and the third thin film transistor T21 to output an output with different cut-angle voltages Waveform.
  • the power-to-charge ratio is a width-to-length ratio of waveforms of signals output by the sixth thin film transistor T23 and the third thin film transistor T21.
  • the present invention provides the sixth thin film transistor T23 on the basis of the existing GOA circuit, and uses the existing signals, such as the operating voltage VSSG and the gate signal output terminal G (n + 3) As a signal source, in order to realize the gate pulse (Gate Pulse) cut angle function (Function), wherein the cut angle time can be based on the product's resolution and the number of clock signals CK and the duty ratio (Duty Ratio)
  • the cut-angle voltage can be adjusted by adjusting the width / length ratio of the sixth thin film transistor T23 and the third thin-film transistor T21 to achieve different cut-angle voltages, so that it is not necessary to use a rear chip. Executing the angle cut function reduces the volume integrated in the panel circuit and reduces the cost of the chip.
  • FIG. 4 and FIG. 5 is a GOA unit according to a second preferred embodiment of the present invention, which is similar to the first preferred embodiment of the present invention and generally uses the same component name and drawing number, wherein the GOA unit includes one Pull control unit 2, a pull-up unit 3, a pull-down unit 4, a pull-down maintenance unit 5, and a bootstrap capacitor Cb.
  • the difference of the second embodiment of the present invention is that a gate signal of the pull-up unit 3, the pull-down unit 4, the pull-down sustain unit 5, and the bootstrap capacitor Cb and the n-th GOA unit are respectively
  • the output terminal G (n) is electrically connected; the pull-up control unit 2 and the pull-down unit 4 are electrically connected to the gate signal point Q (n) of the n-th GOA unit.
  • the pull-down unit 4 includes a fourth thin film transistor T41 and a fifth thin film transistor T31, and the counter charge thin film transistor is a fifth thin film transistor T31, wherein a gate of the fourth thin film transistor T41 is connected to the n + mth stage
  • the gate signal output terminal of the GOA unit, m is a natural number
  • the drain of the fourth thin film transistor T41 is electrically connected to the gate signal point Q (n) of the n-th GOA unit
  • the fourth thin film transistor T41 The source of the fifth thin film transistor T31 is electrically connected to a working voltage VSSQ;
  • the gate of the fifth thin film transistor T31 is connected to the gate signal output terminal of the n + m-1 level GOA unit, and the drain of the fifth thin film transistor T31 is electrically
  • the gate signal output terminal G (n) is connected.
  • the source of the fifth thin film transistor T31 is electrically connected to the operating voltage VSSG.
  • a source of the fifth thin film transistor T31 is electrically connected
  • the present invention sets up the pair of thin film transistors on the basis of the existing GOA circuit, and uses the existing signals, such as the operating voltage VSSG and the gate signal output terminal as the signal source, so as to realize the gate pulse.
  • Angle-cutting function wherein the angle-cutting time can be adjusted according to the resolution of the product and the number and duty cycle of the clock signal, and the angle-cutting voltage can be adjusted by adjusting the pair of thin film transistors and the third thin film transistor
  • the ratio of width to length is used to achieve different cutting angle voltages, so it is possible to implement the cutting angle function without the back-end chip, reduce the volume integrated in the panel circuit, and reduce the cost of the chip.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

L'invention concerne une unité GOA et un procédé de pilotage de celle-ci. L'unité GOA comprend une unité de commande d'excursion haute (2), une unité d'excursion haute (3), une unité d'excursion basse (4), une unité de maintien d'excursion basse (5), et un condensateur d'amorçage (Cb). Dans l'invention, un troisième transistor à couches minces (T21) de l'unité d'excursion haute (3) et un transistor à couches minces de charge subissent une charge de manière à ajuster un rapport de charge du troisième transistor à couches minces (T21) par rapport au transistor à couches minces de charge, ce qui produit des formes d'onde de sortie de tensions de pentes différentes, et réalise une fonction de réglage de pente d'une impulsion de grille.
PCT/CN2018/105697 2018-08-03 2018-09-14 Unité goa et procédé de pilotage de celle-ci WO2020024382A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810879730.1 2018-08-03
CN201810879730.1A CN109036310A (zh) 2018-08-03 2018-08-03 Goa单元及其驱动方法

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WO2020024382A1 true WO2020024382A1 (fr) 2020-02-06

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109410886A (zh) * 2018-12-27 2019-03-01 深圳市华星光电半导体显示技术有限公司 Goa电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010145446A (ja) * 2008-12-16 2010-07-01 Sony Corp 表示装置、表示装置の駆動方法および電子機器
CN103366822A (zh) * 2013-02-07 2013-10-23 友达光电股份有限公司 移位寄存电路以及削角波形产生方法
US20150091885A1 (en) * 2013-09-30 2015-04-02 Novatek Microelectronics Corp. Power Saving Method and Related Waveform-Shaping Circuit
CN106057116A (zh) * 2016-06-20 2016-10-26 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN106098101A (zh) * 2016-06-06 2016-11-09 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN107705761A (zh) * 2017-09-27 2018-02-16 深圳市华星光电技术有限公司 一种goa电路及液晶显示器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104123918B (zh) * 2013-06-11 2016-06-29 深超光电（深圳）有限公司 移位寄存器与液晶显示装置
CN103559867A (zh) * 2013-10-12 2014-02-05 深圳市华星光电技术有限公司 一种栅极驱动电路及其阵列基板和显示面板
CN104008739B (zh) * 2014-05-20 2017-04-12 深圳市华星光电技术有限公司 一种扫描驱动电路和一种液晶显示装置
CN106128380B (zh) * 2016-08-16 2019-01-01 深圳市华星光电技术有限公司 Goa电路
CN106157916A (zh) * 2016-08-31 2016-11-23 深圳市华星光电技术有限公司 一种栅极驱动单元及驱动电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010145446A (ja) * 2008-12-16 2010-07-01 Sony Corp 表示装置、表示装置の駆動方法および電子機器
CN103366822A (zh) * 2013-02-07 2013-10-23 友达光电股份有限公司 移位寄存电路以及削角波形产生方法
US20150091885A1 (en) * 2013-09-30 2015-04-02 Novatek Microelectronics Corp. Power Saving Method and Related Waveform-Shaping Circuit
CN106098101A (zh) * 2016-06-06 2016-11-09 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN106057116A (zh) * 2016-06-20 2016-10-26 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN107705761A (zh) * 2017-09-27 2018-02-16 深圳市华星光电技术有限公司 一种goa电路及液晶显示器

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