WO2020010721A1 - 一种便于测试电阻的半导体晶圆凸块 - Google Patents

一种便于测试电阻的半导体晶圆凸块 Download PDF

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Publication number
WO2020010721A1
WO2020010721A1 PCT/CN2018/108201 CN2018108201W WO2020010721A1 WO 2020010721 A1 WO2020010721 A1 WO 2020010721A1 CN 2018108201 W CN2018108201 W CN 2018108201W WO 2020010721 A1 WO2020010721 A1 WO 2020010721A1
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WIPO (PCT)
Prior art keywords
bump
protective film
chip pad
resistance testing
semiconductor wafer
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PCT/CN2018/108201
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English (en)
French (fr)
Inventor
杨雪松
王倩
蔡道库
袁泉
孙健
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江苏纳沛斯半导体有限公司
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Publication of WO2020010721A1 publication Critical patent/WO2020010721A1/zh

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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Definitions

  • the utility model belongs to the field of semiconductor technology, and particularly relates to a semiconductor wafer bump which is convenient for testing resistance.
  • Wafer refers to the silicon wafer used in the production of silicon semiconductor integrated circuits. Because its shape is circular, it is called a wafer. At present, the sizes of the wafers produced are 8 inches and 12 inches.
  • the bumps are fixed on the round surface to facilitate the connection of the circuit.
  • the current bumps have a smaller exposed surface after being fixed on the wafer surface, which makes it difficult to conduct resistance testing. It is difficult for staff to locate the inspection and spend more time. In view of the problems exposed during the use of current wafer bumps, it is necessary to redesign and improve the structure of the wafer bumps. To this end, we propose a semiconductor wafer bump that is convenient for testing resistance.
  • This utility model is to provide a semiconductor wafer bump that is convenient for testing resistance, so as to solve the problem that the current bump proposed in the background art is not easy to perform resistance because the contact surface exposed after fixing on the wafer surface is small. During testing, it is not easy for staff to locate when testing, and it takes more time.
  • a semiconductor wafer bump that is convenient for testing resistance includes a silicon wafer base, and a chip pad is disposed on an upper surface of the silicon wafer base, and an upper surface of the chip pad A colloidal protective film is provided, and the bottom surface of the colloidal protective film is in contact with the upper surface of the silicon wafer base and the chip pad.
  • a nickel layer is disposed above the colloidal protective film, and the bottom end of the nickel layer penetrates the upper surface of the colloidal protective film and reaches below the colloidal protective film.
  • the bottom surface of the nickel layer is in contact with the upper surface of the chip pad, and the upper surface of the nickel layer is provided with a gold layer.
  • a copper bump is provided on an upper surface of the gold layer, and a groove is symmetrically provided on an outer surface of the copper bump.
  • a silver-tin alloy is provided at a top end of the copper bump, and a positioning groove is symmetrically provided on an outer surface of the silver-tin alloy.
  • the utility model has the beneficial effect that the side of the copper bump is provided with a groove by die casting, and a worker can use a fixing fixture to quickly fix the copper bump when performing resistance detection on the bump. Improve the detection efficiency of workers.
  • Silver-tin alloys are welded on the copper bumps, and the sides of the silver-tin alloy are also cut. It is convenient for the workers to perform different connection methods between multiple contacts for different connection methods. Resistance test improves the accuracy of resistance measurement.
  • FIG. 1 is a schematic cross-sectional structure diagram of the present invention
  • FIG. 2 is a schematic structural plan view of the present invention
  • FIG. 3 is a schematic cross-sectional structure view of a copper bump of the present invention.
  • a semiconductor wafer bump which is convenient for testing resistance, includes a silicon wafer base 1, and an upper surface of the silicon wafer base 1 is bonded by glue. There is a chip pad 2. The upper surface of the chip pad 2 is coated with a gel protective film 3. The bottom surface of the gel protective film 3 is in contact with the upper surfaces of the silicon wafer base 1 and the chip pad 2.
  • a nickel layer 4 is provided above the colloidal protective film 3, and the bottom end of the nickel layer 4 penetrates the upper surface of the colloidal protective film 3 and reaches the colloidal protective film 3 Below.
  • the bottom surface of the nickel layer 4 is in contact with the upper surface of the chip pad 2.
  • the upper surface of the nickel layer 4 is provided with a gold layer 5, and the gold layer 5 is provided on the nickel layer by stacking. 4 ⁇ ⁇ 4 upper surface.
  • the upper surface of the gold layer 5 is provided with a copper bump 6, and the outer surface of the copper bump 6 is provided with a groove 7 symmetrically by casting.
  • a silver tin alloy 8 is provided on the top end of the copper bump 6, and a positioning groove 9 is provided on the outer surface of the silver tin alloy 8 symmetrically by casting.
  • a semiconductor wafer bump which is convenient for testing resistance, includes a silicon wafer base 1, and an upper surface of the silicon wafer base 1 is bonded by glue.
  • a chip pad 2 is provided, and a gel protective film 3 is spray-coated on the upper surface of the chip pad 2. The bottom surface of the gel protective film 3 is in contact with the upper surfaces of the silicon wafer base 1 and the chip pad 2.
  • a nickel layer 4 is provided above the colloidal protective film 3, and the bottom end of the nickel layer 4 penetrates the upper surface of the colloidal protective film 3 and reaches the colloidal protective film 3 Below.
  • the bottom surface of the nickel layer 4 is in contact with the upper surface of the chip pad 2.
  • the upper surface of the nickel layer 4 is provided with a gold layer 5, and the gold layer 5 is provided on the nickel layer by stacking. 4 ⁇ ⁇ 4 upper surface.
  • the upper surface of the gold layer 5 is provided with a copper bump 6, and the outer surface of the copper bump 6 is cut symmetrically with a groove 7.
  • a silver tin alloy 8 is provided on the top end of the copper bump 6, and a positioning groove 9 is symmetrically formed on the outer surface of the silver tin alloy 8 by cutting.
  • the working principle and use process of the utility model When the device needs to perform resistance detection after installation, a worker uses a fixture to contact and fix the side surface of the copper bump 6, and the worker brings the side surface of the fixture to the side of the groove 7 Surface contact, the curved surface of the groove 7 is convenient for contact with the fixture, and at the same time, it is convenient for the fixture to fix the copper bump 6.
  • the worker can simultaneously detect and conduct the electrical conductivity of the copper bump 6 and the silver-tin alloy 8 during the inspection process.
  • One end of the fixture is pushed into the groove 7 on the side of the copper bump 6, and the other grip is pushed on the positioning groove 9 on the side of the silver-tin alloy 8.
  • the staff can perform the resistance test on the wafer bump from different positions.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

一种便于测试电阻的半导体晶圆凸块，包括硅片底座（1），硅片底座（1）的上表面设置有芯片垫（2），芯片垫（2）的上表面设置有胶质防护膜（3），胶质防护膜（3）的底面与硅片底座（1）与芯片垫（2）的上表面都接触，胶质防护膜（3）的上方设置有镍层（4），镍层（4）的底端贯穿胶质防护膜（3）的上表面到达胶质防护膜（3）的下方；铜凸块（6）的侧面通过压铸设置有凹槽（7），工作人员在对凸块进行电阻检测时可以使用固定夹具快速地将铜凸块（6）固定住，提升工作人员的检测效率，铜凸块（6）上方焊接有银锡合金（8），且银锡合金（8）的侧面同样进行了切割处理，在检测时便于工作人员针对不同的连接方式进行多触点之间不同连接方式的电阻测试，提升了电阻测量的精准度。

Description

一种便于测试电阻的半导体晶圆凸块 技术领域
本实用新型属于半导体技术领域，具体涉及一种便于测试电阻的半导体晶圆凸块。
背景技术
晶圆是指硅半导体集成电路制作所用的硅晶片，由于其形状为圆形，故称为晶圆；目前生产晶圆的尺寸都在8英寸以及12英寸，晶圆在生产过程中需要在晶圆的表面固定凸块，便于电路的连接，目前的凸块在固定在晶圆表面后因暴露出来的接触面较小，不易进行电阻测试，工作人员在进行检测时不易定位，花费时间较多，针对目前的晶圆凸块使用时所暴露的问题，有必要对晶圆凸块的结构进行重新设计并改进，为此我们提出一种便于测试电阻的半导体晶圆凸块。
实用新型内容
本实用新型的目的在于提供一种便于测试电阻的半导体晶圆凸块，以解决上述背景技术中提出的目前的凸块在固定在晶圆表面后因暴露出来的接触面较小，不易进行电阻测试，工作人员在进行检测时不易定位，花费时间较多问题。
为实现上述目的，本实用新型提供如下技术方案：一种便于测试电阻的半导体晶圆凸块，包括硅片底座，所述硅片底座的上表面设置有芯片垫，所述芯片垫的上表面设置有胶质防护膜，所述胶质防护膜的底面与硅片底座与芯片垫的上表面都接触。
优选的，所述胶质防护膜的上方设置有镍层，所述镍层的底端贯穿胶质防护膜的上表面到达胶质防护膜的下方。
优选的，所述镍层的底面与芯片垫的上表面接触，所述镍层的上表面设置有金层。
优选的，所述金层的上表面设置有铜凸块，所述铜凸块的外侧表面对称设置有凹槽。
优选的，所述铜凸块的顶端设置有银锡合金，所述银锡合金的外侧表面对称设置有定位槽。与现有技术相比，本实用新型的有益效果是：铜凸块的侧面通过压铸设置有凹槽，工作人员在对凸块进行电阻检测时可以使用固定夹具快速的将铜凸块固定住，提升工作人员的检测效率，铜凸块上方焊接有银锡合金，且银锡合金的侧面同样进行了切割处理，在检测时便于工作人员针对不同的连接方式进行多触点之间不同连接方式的电阻测试，提升了电阻测量的精准度。
附图说明
图1为本实用新型的截面结构示意图；
图2为本实用新型的俯视结构示意图；
图3为本实用新型的铜凸块剖视结构示意图；
图中：1、硅片底座；2、芯片垫；3、胶质防护膜；4、镍层；5、金层；6、铜凸块；7、凹槽；8、银锡合金；9、定位槽。
具体实施方式
下面将结合本实用新型实施例中的附图，对本实用新型实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本实用新型一部分实施例，而不是全部的实施例。基于本实用新型中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本实用新型保护的范围。
实施例1
请参阅图1、图2和图3，本实用新型提供一种技术方案：一种便于测试电阻的半导体晶圆凸块，包括硅片底座1，硅片底座1的上表面通过胶水粘接设有芯片垫2，芯片垫2的上表面涂抹设有胶质防护膜3，胶质防护膜3的底面与硅片底座1与芯片垫2的上表面都接触。
为了便于对晶圆的加工，本实施例中，优选的，胶质防护膜3的上方设有镍层4，镍层4的底端贯穿胶质防护膜3的上表面到达胶质防护膜3的下方。
为了便于晶圆的使用，本实施例中，优选的，镍层4的底面与芯片垫2的上表面接触，镍层4的上表面设有金层5，金层5通过堆栈设在镍层4上表面。
为了便于工作人员进行电阻检测，本实施例中，优选的，金层5的上表面设有铜凸块6，铜凸块6的外侧表面通过浇铸对称设有凹槽7。
为了便于工作人员进行全方位的电阻检测，本实施例中，优选的，铜凸块6的顶端设有银锡合金8，银锡合金8的外侧表面通过浇铸对称设有定位槽9。
实施例2
请参阅图1、图2和图3，本实用新型提供一种技术方案：一种便于测试电阻的半导体晶圆凸块，包括硅片底座1，硅片底座1的上表面通过胶水粘接设有芯片垫2，芯片垫2的上表面喷涂设有胶质防护膜3，胶质防护膜3的底面与硅片底座1与芯片垫2的上表面都接触。
为了便于对晶圆的加工，本实施例中，优选的，胶质防护膜3的上方设有镍层4，镍层4的底端贯穿胶质防护膜3的上表面到达胶质防护膜3的下方。
为了便于晶圆的使用，本实施例中，优选的，镍层4的底面与芯片垫2的上表面接触，镍层4的上表面设有金层5，金层5通过堆栈设在镍层4上表面。
为了便于工作人员进行电阻检测，本实施例中，优选的，金层5的上表面设有铜凸块6，铜凸块6的外侧表面对称切割设有凹槽7。
为了便于工作人员进行全方位的电阻检测，本实施例中，优选的，铜凸块6的顶端设有银锡 合金8，银锡合金8的外侧表面通过切割对称设有定位槽9。
本实用新型的工作原理及使用流程：该设备在安装之后需要进行电阻检测时工作人员使用夹具对铜凸块6的侧表面进行接触并固定，工作人员将夹具的侧表面与凹槽7的侧表面接触，凹槽7的弧形表面便于与夹具接触，同时便于夹具对铜凸块6的固定，工作人员在检测过程中可以对铜凸块6与银锡合金8的导电性同时检测，工作人员使用夹具一端顶到铜凸块6侧面的凹槽7内部，另一个夹具顶到银锡合金8侧面的定位槽9上，工作人员可以从不同的位置对圆晶凸块进行电阻测试。
尽管已经示出和描述了本实用新型的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本实用新型的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本实用新型的范围由所附权利要求及其等同物限定。

Claims (5)

  1. 一种便于测试电阻的半导体晶圆凸块，包括硅片底座(1)，其特征在于：所述硅片底座(1)的上表面设置有芯片垫(2)，所述芯片垫(2)的上表面设置有胶质防护膜(3)，所述胶质防护膜(3)的底面与硅片底座(1)与芯片垫(2)的上表面都接触。
  2. 根据权利要求1所述的一种便于测试电阻的半导体晶圆凸块，其特征在于：所述胶质防护膜(3)的上方设置有镍层(4)，所述镍层(4)的底端贯穿胶质防护膜(3)的上表面到达胶质防护膜(3)的下方。
  3. 根据权利要求2所述的一种便于测试电阻的半导体晶圆凸块，其特征在于：所述镍层(4)的底面与芯片垫(2)的上表面接触，所述镍层(4)的上表面设置有金层(5)。
  4. 根据权利要求3所述的一种便于测试电阻的半导体晶圆凸块，其特征在于：所述金层(5)的上表面设置有铜凸块(6)，所述铜凸块(6)的外侧表面对称设置有凹槽(7)。
  5. 根据权利要求4所述的一种便于测试电阻的半导体晶圆凸块，其特征在于：所述铜凸块(6)的顶端设置有银锡合金(8)，所述银锡合金(8)的外侧表面对称设置有定位槽(9)。
PCT/CN2018/108201 2018-07-09 2018-09-28 一种便于测试电阻的半导体晶圆凸块 WO2020010721A1 (zh)

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Publication number Priority date Publication date Assignee Title
JP2008218884A (ja) * 2007-03-07 2008-09-18 Citizen Holdings Co Ltd 半導体装置およびその製造方法
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JP2008218884A (ja) * 2007-03-07 2008-09-18 Citizen Holdings Co Ltd 半導体装置およびその製造方法
CN102044454A (zh) * 2009-10-09 2011-05-04 中芯国际集成电路制造(上海)有限公司 凸点及其形成方法
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