WO2020006854A1 - 一种像素驱动电路及显示面板 - Google Patents

一种像素驱动电路及显示面板 Download PDF

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Publication number
WO2020006854A1
WO2020006854A1 PCT/CN2018/103900 CN2018103900W WO2020006854A1 WO 2020006854 A1 WO2020006854 A1 WO 2020006854A1 CN 2018103900 W CN2018103900 W CN 2018103900W WO 2020006854 A1 WO2020006854 A1 WO 2020006854A1
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Prior art keywords
voltage
input terminal
transistor
node
scan signal
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Ceased
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PCT/CN2018/103900
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English (en)
French (fr)
Inventor
邓宇帆
许神贤
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2020006854A1 publication Critical patent/WO2020006854A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of display technology, and in particular, to a pixel driving circuit and a display panel.
  • Organic light-emitting display panels use organic light-emitting diodes Lighting Emitting Diode (OLED for short) display image is a kind of active light-emitting love panel. Its display method is different from the traditional thin film transistor display panel (English Thin Film Transistor liquid crystal display, TFT-LCD for short). Backlight, and has many advantages such as high contrast, fast response, thin and light. Therefore, the organic light emitting display panel is known as a new generation display panel that can replace a thin film transistor display panel.
  • Organic light-emitting display panels are divided into passive matrix organic light-emitting display panels (full English name) Passive Matrix Organic Lighting Emitting Display PMOLED) and active matrix organic light-emitting display panel (full name in English) Active Matrix Organic Lighting Emitting Display AMOLED), an active matrix organic light emitting display panel is also called an active matrix organic light emitting display panel.
  • the active matrix organic light-emitting display panel uses a thin-film transistor to control the current flowing through the light-emitting diode to achieve the display effect.
  • the thin-film transistor is affected by factors such as light and source-drain voltage stress during use, which causes its threshold voltage to be biased. Shift, which in turn affects the current flowing through the light emitting diodes, resulting in uneven display on the display panel.
  • the invention provides a pixel driving circuit and a display panel, which can increase the gate-drain voltage of a thin film transistor, thereby improving the display quality of the display panel.
  • the invention provides a pixel driving circuit, which includes: a first input module, a second input module, a driving module, a light emitting diode, a first capacitor, and a second capacitor;
  • the first input module is connected to a first scan signal input terminal, a data signal input terminal, a second voltage input terminal, a first node, and a second node, and is used for the first scan signal at the first scan signal input terminal. Under control, pull the voltage of the first node to the voltage of the data signal input terminal, and pull the voltage of the second node to the voltage of the second voltage input terminal;
  • the second input module is connected to a second scan signal input terminal, a third voltage input terminal, and the second node, and is configured to control the second scan signal under the control of the second scan signal at the second scan signal input terminal.
  • the voltage of the node is aligned with the voltage of the third voltage input terminal;
  • the driving module is connected to the first node, a first voltage input terminal and an anode of the light emitting diode, a cathode of the light emitting diode is connected to the second voltage input terminal, and the driving module is configured to Driving the light emitting diode to emit light under the control of the voltage of the node;
  • a first pole of the first capacitor is connected to the first node, a second stage of the first capacitor is connected to the second node; a first pole of the second capacitor is connected to the first voltage input terminal, A second pole of the second capacitor is connected to the first node;
  • the first input module includes a first transistor and a third transistor
  • a first terminal of the first transistor is connected to the data signal input terminal, a second terminal of the first transistor is connected to the first node, and a gate of the first transistor is connected to the first scan signal input terminal.
  • a first terminal of the third transistor is connected to the second voltage input terminal, a second terminal of the third transistor is connected to the second node, and a gate of the third transistor is connected to the first scan signal input. end;
  • the second input module includes: a fourth transistor
  • a first terminal of the fourth transistor is connected to the third voltage input terminal, a second terminal of the fourth transistor is connected to the second node, and a gate of the fourth transistor is connected to the second scan signal input. end.
  • the driving module includes: a second transistor
  • a first terminal of the second transistor is connected to the first voltage input terminal, a second terminal of the second transistor is connected to an anode of the light emitting diode, and a gate of the second transistor is connected to the first node.
  • each transistor is an NMOS transistor.
  • the first voltage input terminal and the second voltage input terminal are used to provide a driving voltage of the light emitting diode, and the third voltage input terminal is used to provide a reference voltage.
  • a voltage value of the third voltage input terminal is greater than a voltage value of the second voltage input terminal.
  • the driving timing of the pixel driving circuit includes: a first time period and a second time period;
  • the first scan signal at the first scan signal input terminal is high level
  • the second scan signal at the second scan signal input terminal is low level
  • the first transistor and the The third transistor is turned on, the fourth transistor is turned off, the voltage of the first node is aligned with the voltage of the data signal input terminal, and the voltage of the second node is aligned with the voltage of the second voltage input terminal;
  • the first scan signal at the first scan signal input terminal is at a low level
  • the second scan signal at the second scan signal input terminal is at a high level
  • the first transistor and the first The three transistors are turned off
  • the fourth transistor is turned on
  • the voltage of the second node is aligned with the voltage of the third voltage input terminal.
  • the potential of the first node is raised so that the The second transistor is turned on to drive the light emitting diode to emit light.
  • V data ' V data + C1 (Vref-OVSS) / (Cst + C1), where V dat a is the data signal
  • Vref the voltage at the third voltage input terminal
  • C1 the capacitance value of the first capacitor
  • Cst the capacitance value of the second capacitor
  • OCSS the voltage of the second voltage input terminal.
  • the invention provides a pixel driving circuit, which includes: a first input module, a second input module, a driving module, a light emitting diode, a first capacitor, and a second capacitor;
  • the first input module is connected to a first scan signal input terminal, a data signal input terminal, a second voltage input terminal, a first node, and a second node, and is used for the first scan signal at the first scan signal input terminal. Under control, pull the voltage of the first node to the voltage of the data signal input terminal, and pull the voltage of the second node to the voltage of the second voltage input terminal;
  • the second input module is connected to a second scan signal input terminal, a third voltage input terminal, and the second node, and is configured to control the second scan signal under the control of the second scan signal at the second scan signal input terminal.
  • the voltage of the node is aligned with the voltage of the third voltage input terminal;
  • the driving module is connected to the first node, a first voltage input terminal and an anode of the light emitting diode, a cathode of the light emitting diode is connected to the second voltage input terminal, and the driving module is configured to Driving the light emitting diode to emit light under the control of the voltage of the node;
  • a first pole of the first capacitor is connected to the first node, a second stage of the first capacitor is connected to the second node; a first pole of the second capacitor is connected to the first voltage input terminal, A second pole of the second capacitor is connected to the first node.
  • the first input module includes a first transistor and a third transistor
  • a first terminal of the first transistor is connected to the data signal input terminal, a second terminal of the first transistor is connected to the first node, and a gate of the first transistor is connected to the first scan signal input terminal.
  • a first terminal of the third transistor is connected to the second voltage input terminal, a second terminal of the third transistor is connected to the second node, and a gate of the third transistor is connected to the first scan signal input. end.
  • the second input module includes: a fourth transistor
  • a first terminal of the fourth transistor is connected to the third voltage input terminal, a second terminal of the fourth transistor is connected to the second node, and a gate of the fourth transistor is connected to the second scan signal input. end.
  • the driving module includes: a second transistor
  • a first terminal of the second transistor is connected to the first voltage input terminal, a second terminal of the second transistor is connected to an anode of the light emitting diode, and a gate of the second transistor is connected to the first node.
  • each transistor is an NMOS transistor.
  • the first voltage input terminal and the second voltage input terminal are used to provide a driving voltage of the light emitting diode, and the third voltage input terminal is used to provide a reference voltage.
  • a voltage value of the third voltage input terminal is greater than a voltage value of the second voltage input terminal.
  • the driving timing of the pixel driving circuit includes: a first time period and a second time period;
  • the first scan signal at the first scan signal input terminal is high level
  • the second scan signal at the second scan signal input terminal is low level
  • the first transistor and the The third transistor is turned on, the fourth transistor is turned off, the voltage of the first node is aligned with the voltage of the data signal input terminal, and the voltage of the second node is aligned with the voltage of the second voltage input terminal;
  • the first scan signal at the first scan signal input terminal is at a low level
  • the second scan signal at the second scan signal input terminal is at a high level
  • the first transistor and the first The three transistors are turned off
  • the fourth transistor is turned on
  • the voltage of the second node is aligned with the voltage of the third voltage input terminal.
  • the potential of the first node is raised so that the The second transistor is turned on to drive the light emitting diode to emit light.
  • V data ' V data + C1 (Vref-OVSS) / (Cst + C1), where V data is the data signal input Vref is the voltage of the third voltage input terminal, C1 is the capacitance value of the first capacitor, Cst is the capacitance value of the second capacitor, and OCSS is the voltage of the second voltage input terminal.
  • the present invention also provides a display panel including a pixel driving circuit, the pixel circuit including: a first input module, a second input module, a driving module, a light emitting diode, a first capacitor, and a second capacitor;
  • the first input module is connected to a first scan signal input terminal, a data signal input terminal, a second voltage input terminal, a first node, and a second node, and is used for the first scan signal at the first scan signal input terminal. Under control, pull the voltage of the first node to the voltage of the data signal input terminal, and pull the voltage of the second node to the voltage of the second voltage input terminal;
  • the second input module is connected to a second scan signal input terminal, a third voltage input terminal, and the second node, and is configured to control the second scan signal under the control of the second scan signal at the second scan signal input terminal.
  • the voltage of the node is aligned with the voltage of the third voltage input terminal;
  • the driving module is connected to the first node, a first voltage input terminal and an anode of the light emitting diode, a cathode of the light emitting diode is connected to the second voltage input terminal, and the driving module is configured to Driving the light emitting diode to emit light under the control of the voltage of the node;
  • a first pole of the first capacitor is connected to the first node, a second stage of the first capacitor is connected to the second node; a first pole of the second capacitor is connected to the first voltage input terminal, A second pole of the second capacitor is connected to the first node.
  • the first input module includes a first transistor and a third transistor
  • a first terminal of the first transistor is connected to the data signal input terminal, a second terminal of the first transistor is connected to the first node, and a gate of the first transistor is connected to the first scan signal input terminal.
  • a first terminal of the third transistor is connected to the second voltage input terminal, a second terminal of the third transistor is connected to the second node, and a gate of the third transistor is connected to the first scan signal input. end.
  • the second input module includes: a fourth transistor
  • a first terminal of the fourth transistor is connected to the third voltage input terminal, a second terminal of the fourth transistor is connected to the second node, and a gate of the fourth transistor is connected to the second scan signal input. end.
  • the driving module includes: a second transistor
  • a first terminal of the second transistor is connected to the first voltage input terminal, a second terminal of the second transistor is connected to an anode of the light emitting diode, and a gate of the second transistor is connected to the first node.
  • the beneficial effect of the present invention is that the pixel driving circuit and the display panel provided by the present invention include a first input module, a second input module, a driving module, a light emitting diode, a first capacitor, and a second capacitor.
  • the potential of the first node is raised by the capacitive coupling effect, thereby increasing the gate-drain voltage of the thin film transistor, thereby improving the display quality of the display panel.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention
  • FIG. 2 is a circuit diagram of a pixel driving circuit according to an embodiment of the present invention.
  • FIG. 3 is a driving timing diagram of the pixel driving circuit provided by the present invention.
  • the transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. According to their role in the circuit, the transistors used in the embodiments of the present invention are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain of the switching transistor are interchangeable. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate, the source is referred to as a first terminal and the drain is referred to as a second terminal. According to the form in the figure, the middle end of the transistor is specified as the gate, the input signal end is the source, and the output signal end is the drain. In addition, the switching transistor used in the embodiment of the present invention is turned on when the gate is at a high level, and turned off when the gate is at a low level.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention.
  • an embodiment of the present invention provides a pixel driving circuit, which includes: a first input module 101, a second input module 102, a driving module 103, a light emitting diode OLED, a first capacitor C1, and a second capacitor Cst;
  • the first input module 101 is connected to the first scanning signal input terminal Gate N, the data signal input terminal, the second voltage input terminal OVSS terminal, the first node A and the second node B, and is used for Under the control of the first scanning signal, the voltage of the first node A is aligned with the voltage of the data signal input terminal, and the voltage of the second node B is aligned with the voltage of the second voltage input terminal OVSS;
  • the second input module 102 is connected to the first scan signal input terminal Gate N + 1, the third voltage input terminal Vref, and the second node B, and is used to be controlled by the second scan signal of the first scan signal input terminal Gate N + 1. To align the voltage of the second node B with the voltage of the third voltage input terminal Vref;
  • the driving module 103 is connected to the first node A, the first voltage input terminal OVDD and the anode of the light emitting diode OLED, and the cathode of the light emitting diode OLED is connected to the second voltage input terminal OVSS.
  • the driving module 103 is used to control the voltage of the first node A. To drive the light emitting diode OLED to emit light;
  • the first pole of the first capacitor C1 is connected to the first node A, the second stage of the first capacitor C1 is connected to the second node B; the first pole of the second capacitor Cst is connected to the first voltage input terminal OVDD, and the first pole of the second capacitor Cst is The second pole is connected to the first node A.
  • sharing a signal terminal by multiple modules can reduce the number of signal terminals in the GOA circuit.
  • these modules can also be connected to different signal terminals as long as the signal terminals can provide similar signals. .
  • the first input module 101 includes a first transistor T1 and a third transistor T3; a first terminal of the first transistor T1 is connected to a data signal input terminal, a second terminal of the first transistor T1 is connected to a first node A, and a first transistor
  • the gate of T1 is connected to the first scanning signal input Gate N; the first terminal of the third transistor T3 is connected to the second voltage input OVSS; the second terminal of the third transistor T3 is connected to the second node B; the gate of the third transistor T3 Is connected to Gate N, the first scanning signal input terminal.
  • the second input module 102 includes: a fourth transistor T4; a first terminal of the fourth transistor T4 is connected to the third voltage input terminal Vref, a second terminal of the fourth transistor T4 is connected to the second node B, and a gate of the fourth transistor T4 is connected The first scanning signal input terminal Gate N + 1.
  • the driving module 103 includes: a second transistor T2; a first terminal of the second transistor T2 is connected to the first voltage input terminal OVDD, a second terminal of the second transistor T2 is connected to the anode of the light emitting diode OLED, and a gate of the second transistor T2 is connected to the first A node A.
  • the first voltage input terminal OVDD and the second voltage input terminal OVSS are used to provide a driving voltage of the light emitting diode OLED, and the third voltage input terminal Vref is used to provide a reference voltage.
  • the voltage value of the third voltage input terminal Vref is greater than the voltage value of the second voltage input terminal OVSS.
  • each transistor in the embodiment of the present invention is an NMOS transistor, that is, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all NMOS transistors.
  • the NMOS transistor is turned on when the gate is at a high level. On and off when the gate is low.
  • FIG. 3 is a driving timing diagram of a pixel driving circuit provided by the present invention.
  • the driving timing of the pixel driving circuit provided by the embodiment of the present invention includes a first time period t1 and a second time period t2.
  • the first scanning signal of the first scanning signal input terminal Gate N is at a high level, and the first scanning signal input terminal Gate is at a high level.
  • the second scanning signal of N + 1 is at a low level, the first transistor T1 and the third transistor T3 are turned on, the fourth transistor T4 is turned off, the voltage VA of the first node A is aligned with the voltage Vdata of the data signal input terminal, and the second The voltage of the node B is equal to the voltage of the second voltage input terminal OVSS.
  • the first scan signal of the first scan signal input Gate N is at a low level, and the first scan signal input of the Gate Gate is low.
  • the second scanning signal of N + 1 is high level, the first transistor T1 and the third transistor T3 are turned off, and the fourth transistor T4 is turned on.
  • the voltage of the second node B is equal to the voltage of the third voltage input terminal Vref. With the capacitive coupling effect, the potential of the first node A will be raised, so that the second transistor T2 is turned on to drive the light emitting diode OLED to emit light.
  • V data ' V data + C1 (Vref-OVSS) / (Cst + C1), where V data is the voltage at the data signal input terminal and Vref is the third voltage input
  • Vref the voltage at the terminal Vref
  • C1 is the capacitance of the first capacitor C1
  • Cst is the capacitance of the second capacitor Cst
  • OVSS is the voltage of the second voltage input terminal OVSS.
  • the pixel driving circuit provided by the present invention includes a first input module 101, a second input module 102, a driving module 103, a light emitting diode OLED, a first capacitor C1, and a second capacitor Cst.
  • Gate N + 1 is provided at a first scanning signal input terminal. Under the control of the second scanning signal, the potential of the first node A is raised by the capacitive coupling effect, thereby increasing the gate-drain voltage of the thin film transistor, thereby improving the display quality of the display panel.
  • An embodiment of the present invention further provides a display panel including the pixel driving circuit described above.
  • a display panel including the pixel driving circuit described above.
  • pixel driving circuit described above For details, refer to the pixel driving circuit described above, and details are not described herein.
  • a pixel driving circuit and a display panel provided by the present invention include a first input module 101, a second input module 102, a driving module 103, a light emitting diode OLED, a first capacitor C1, and a second capacitor Cst.
  • the potential of the first node A is raised by the capacitive coupling effect, thereby increasing the gate-drain voltage of the thin film transistor, thereby improving the display quality of the display panel.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本发明提供的像素驱动电路及显示面板，包括第一输入模块、第二输入模块、驱动模块、发光二极管、第一电容以及第二电容，在第二扫描信号输入端的第二扫描信号的控制下，通过电容耦合作用抬升第一节点的电位，从而提升薄膜晶体管的栅漏极电压，进而提升显示面板的显示品质。

Description

一种像素驱动电路及显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种像素驱动电路及显示面板。
 背景技术
有机发光显示面板利用有机发光二极管(英文全称Organic Lighting Emitting Diode，简称OLED) 显示图像，是一种主动发光的相爱时面板，其显示方式与传统的薄膜晶体管显示面板(英文全称Thin Film Transistor liquid crystal display，简称 TFT-LCD) 显示方式不同，无需背光灯，而且，具有对比度高、响应速度快、轻薄等诸多优点。因此，有机发光显示面板被誉为可以取代薄膜晶体管显示面板的新一代的显示面板。
根据驱动方式的不同，有机发光显示面板分为被动矩阵有机发光显示面板 (英文全称 Passive Matrix Organic Lighting Emitting Display，简称 PMOLED) 和主动矩阵有机发光显示面板(英文全称 Active Matrix Organic Lighting Emitting Display，简称 AMOLED)，主动矩阵有机发光显示面板也称为有源矩阵有机发光显示面板。
有源矩阵有机发光显示面板是通过薄膜晶体管控制流过发光二极管的电流实现显示效果，然而，薄膜晶体管在使用过程中由于受到照光、源漏极电压应力等因素影响，导致其阈值电压的产生偏移，进而影响流过发光二极管的电流，导致显示面板的显示不均。
 技术问题
本发明提供一种像素驱动电路及显示面板，能够提升薄膜晶体管的栅漏极电压，进而提升显示面板的显示品质。
 技术解决方案
本发明提供一种像素驱动电路，其包括：第一输入模块、第二输入模块、驱动模块、发光二极管、第一电容以及第二电容；
所述第一输入模块连接第一扫描信号输入端、数据信号输入端、第二电压输入端端、第一节点和第二节点，用于在所述第一扫描信号输入端的第一扫描信号的控制下，将所述第一节点的电压与所述数据信号输入端的电压拉齐，以及将所述第二节点的电压与所述第二电压输入端的电压拉齐；
所述第二输入模块连接第二扫描信号输入端、第三电压输入端以及所述第二节点，用于在所述第二扫描信号输入端的第二扫描信号的控制下，将所述第二节点的电压与所述第三电压输入端的电压拉齐；
所述驱动模块连接所述第一节点、第一电压输入端和所述发光二极管的阳极，所述发光二极管的阴极连接所述第二电压输入端，所述驱动模块用于在所述第一节点的电压的控制下，驱动所述发光二极管发光；
所述第一电容的第一极连接所述第一节点，所述第一电容的第二级连接所述第二节点；所述第二电容的第一极连接所述第一电压输入端，所述第二电容的第二极连接所述第一节点；
其中，所述第一输入模块包括第一晶体管和第三晶体管；
所述第一晶体管的第一端连接所述数据信号输入端，所述第一晶体管的第二端连接所述第一节点，所述第一晶体管的栅极连接所述第一扫描信号输入端；
所述第三晶体管的第一端连接所述第二电压输入端，所述第三晶体管的第二端连接所述第二节点，所述第三晶体管的栅极连接所述第一扫描信号输入端；
所述第二输入模块包括：第四晶体管；
所述第四晶体管的第一端连接所述第三电压输入端，所述第四晶体管的第二端连接所述第二节点，所述第四晶体管的栅极连接所述第二扫描信号输入端。
在本发明的像素驱动电路中，所述驱动模块包括：第二晶体管；
所述第二晶体管的第一端连接所述第一电压输入端，所述第二晶体管的第二端连接所述发光二极管的阳极，所述第二晶体管的栅极连接所述第一节点。
在本发明的像素驱动电路中，各个晶体管均为NMOS管。
在本发明的像素驱动电路中，所述第一电压输入端和所述第二电压输入端用于提供所述发光二极管的驱动电压，所述第三电压输入端用于提供参考电压。
在本发明的像素驱动电路中，所述第三电压输入端的电压值大于所述第二电压输入端的电压值。
在本发明的像素驱动电路中，所述像素驱动电路的驱动时序包括：第一时间段和第二时间段；
在所述第一时间段，所述第一扫描信号输入端的第一扫描信号为高电平，所述第二扫描信号输入端的第二扫描信号为低电平，所述第一晶体管和所述第三晶体管导通，所述第四晶体管关闭，所述第一节点的电压与所述数据信号输入端的电压拉齐，所述第二节点的电压与所述第二电压输入端的电压拉齐；
在所述第二时间段，所述第一扫描信号输入端的第一扫描信号为低电平，所述第二扫描信号输入端的第二扫描信号高电平，所述第一晶体管和所述第三晶体管关闭，所述第四晶体管导通，所述第二节点的电压与所述第三电压输入端的电压拉齐，同时由于电容耦合作用，所述第一节点电位会被抬升，以使得所述第二晶体管导通驱动发光二极管发光。
在本发明的像素驱动电路中，所述第一节点被抬升后的电压：V data ’=V data+C1(Vref-OVSS)/(Cst+C1)，其中，V data为所述数据信号输入端的电压，Vref为所述第三电压输入端的电压，C1为所述第一电容的电容值，Cst为所述第二电容的电容值，OCSS为所述第二电压输入端的电压。
本发明提供一种像素驱动电路，其包括：第一输入模块、第二输入模块、驱动模块、发光二极管、第一电容以及第二电容；
所述第一输入模块连接第一扫描信号输入端、数据信号输入端、第二电压输入端端、第一节点和第二节点，用于在所述第一扫描信号输入端的第一扫描信号的控制下，将所述第一节点的电压与所述数据信号输入端的电压拉齐，以及将所述第二节点的电压与所述第二电压输入端的电压拉齐；
所述第二输入模块连接第二扫描信号输入端、第三电压输入端以及所述第二节点，用于在所述第二扫描信号输入端的第二扫描信号的控制下，将所述第二节点的电压与所述第三电压输入端的电压拉齐；
所述驱动模块连接所述第一节点、第一电压输入端和所述发光二极管的阳极，所述发光二极管的阴极连接所述第二电压输入端，所述驱动模块用于在所述第一节点的电压的控制下，驱动所述发光二极管发光；
所述第一电容的第一极连接所述第一节点，所述第一电容的第二级连接所述第二节点；所述第二电容的第一极连接所述第一电压输入端，所述第二电容的第二极连接所述第一节点。
在本发明的像素驱动电路中，所述第一输入模块包括第一晶体管和第三晶体管；
所述第一晶体管的第一端连接所述数据信号输入端，所述第一晶体管的第二端连接所述第一节点，所述第一晶体管的栅极连接所述第一扫描信号输入端；
所述第三晶体管的第一端连接所述第二电压输入端，所述第三晶体管的第二端连接所述第二节点，所述第三晶体管的栅极连接所述第一扫描信号输入端。
在本发明的像素驱动电路中，所述第二输入模块包括：第四晶体管；
所述第四晶体管的第一端连接所述第三电压输入端，所述第四晶体管的第二端连接所述第二节点，所述第四晶体管的栅极连接所述第二扫描信号输入端。
在本发明的像素驱动电路中，所述驱动模块包括：第二晶体管；
所述第二晶体管的第一端连接所述第一电压输入端，所述第二晶体管的第二端连接所述发光二极管的阳极，所述第二晶体管的栅极连接所述第一节点。
在本发明的像素驱动电路中，各个晶体管均为为NMOS管。
在本发明的像素驱动电路中，所述第一电压输入端和所述第二电压输入端用于提供所述发光二极管的驱动电压，所述第三电压输入端用于提供参考电压。
在本发明的像素驱动电路中，所述第三电压输入端的电压值大于所述第二电压输入端的电压值。
在本发明的像素驱动电路中，所述像素驱动电路的驱动时序包括：第一时间段和第二时间段；
在所述第一时间段，所述第一扫描信号输入端的第一扫描信号为高电平，所述第二扫描信号输入端的第二扫描信号为低电平，所述第一晶体管和所述第三晶体管导通，所述第四晶体管关闭，所述第一节点的电压与所述数据信号输入端的电压拉齐，所述第二节点的电压与所述第二电压输入端的电压拉齐；
在所述第二时间段，所述第一扫描信号输入端的第一扫描信号为低电平，所述第二扫描信号输入端的第二扫描信号高电平，所述第一晶体管和所述第三晶体管关闭，所述第四晶体管导通，所述第二节点的电压与所述第三电压输入端的电压拉齐，同时由于电容耦合作用，所述第一节点电位会被抬升，以使得所述第二晶体管导通驱动发光二极管发光。
在本发明的像素驱动电路中，所述第一节点被抬升后的电压：V data ’=V data+C1(Vref-OVSS)/(Cst+C1)，其中，V data为所述数据信号输入端的电压，Vref为所述第三电压输入端的电压，C1为所述第一电容的电容值，Cst为所述第二电容的电容值，OCSS为所述第二电压输入端的电压。
本发明还提供一种显示面板，其包括像素驱动电路，所述像素电路包括：第一输入模块、第二输入模块、驱动模块、发光二极管、第一电容以及第二电容；
所述第一输入模块连接第一扫描信号输入端、数据信号输入端、第二电压输入端端、第一节点和第二节点，用于在所述第一扫描信号输入端的第一扫描信号的控制下，将所述第一节点的电压与所述数据信号输入端的电压拉齐，以及将所述第二节点的电压与所述第二电压输入端的电压拉齐；
所述第二输入模块连接第二扫描信号输入端、第三电压输入端以及所述第二节点，用于在所述第二扫描信号输入端的第二扫描信号的控制下，将所述第二节点的电压与所述第三电压输入端的电压拉齐；
所述驱动模块连接所述第一节点、第一电压输入端和所述发光二极管的阳极，所述发光二极管的阴极连接所述第二电压输入端，所述驱动模块用于在所述第一节点的电压的控制下，驱动所述发光二极管发光；
所述第一电容的第一极连接所述第一节点，所述第一电容的第二级连接所述第二节点；所述第二电容的第一极连接所述第一电压输入端，所述第二电容的第二极连接所述第一节点。
在本发明的显示面板中，所述第一输入模块包括第一晶体管和第三晶体管；
所述第一晶体管的第一端连接所述数据信号输入端，所述第一晶体管的第二端连接所述第一节点，所述第一晶体管的栅极连接所述第一扫描信号输入端；
所述第三晶体管的第一端连接所述第二电压输入端，所述第三晶体管的第二端连接所述第二节点，所述第三晶体管的栅极连接所述第一扫描信号输入端。
在本发明的显示面板中，所述第二输入模块包括：第四晶体管；
所述第四晶体管的第一端连接所述第三电压输入端，所述第四晶体管的第二端连接所述第二节点，所述第四晶体管的栅极连接所述第二扫描信号输入端。
在本发明的显示面板中，所述驱动模块包括：第二晶体管；
所述第二晶体管的第一端连接所述第一电压输入端，所述第二晶体管的第二端连接所述发光二极管的阳极，所述第二晶体管的栅极连接所述第一节点。
 有益效果
本发明的有益效果为：本发明提供的像素驱动电路及显示面板，包括第一输入模块、第二输入模块、驱动模块、发光二极管、第一电容以及第二电容，在第二扫描信号输入端的第二扫描信号的控制下，通过电容耦合作用抬升第一节点的电位，从而提升薄膜晶体管的栅漏极电压，进而提升显示面板的显示品质。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的像素驱动电路的示意性结构图；
图2为本发明实施例提供的像素驱动电路的电路图；
图3为本发明实施提供的像素驱动电路的驱动时序图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本发明的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本发明实施例中，为区分晶体管除栅极之外的两极，将其中源极称为第一端，漏极称为第二端。按附图中的形态规定晶体管的中间端为栅极、输入信号端为源极、输出信号端为漏极。此外本发明实施例所采用的开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
需要说明的是，需要说明的是，本申请中的“第一”、“第二”等字样仅仅是为了对功能和作用基本相同的相同项或相似项进行区分，“第一”、“第二”等字样并不是在对数量和执行次序进行限定。
请参阅图1，图1为本发明实施例提供的像素驱动电路的示意性结构图。如图1所示，本发明实施例提供一种像素驱动电路，其包括：第一输入模块101、第二输入模块102、驱动模块103、发光二极管OLED、第一电容C1以及第二电容Cst；
第一输入模块101连接第一扫描信号输入端Gate N、数据信号输入端、第二电压输入端OVSS端、第一节点A和第二节点B，用于在第一扫描信号输入端Gate N的第一扫描信号的控制下，将第一节点A的电压与数据信号输入端的电压拉齐，以及将第二节点B的电压与第二电压输入端OVSS的电压拉齐；
第二输入模块102连接第一扫描信号输入端Gate N+1、第三电压输入端Vref以及第二节点B，用于在第一扫描信号输入端Gate N+1的第二扫描信号的控制下，将第二节点B的电压与第三电压输入端Vref的电压拉齐；
驱动模块103连接第一节点A、第一电压输入端OVDD和发光二极管OLED的阳极，发光二极管OLED的阴极连接第二电压输入端OVSS，驱动模块103用于在第一节点A的电压的控制下，驱动发光二极管OLED发光；
第一电容C1的第一极连接第一节点A，第一电容C1的第二级连接第二节点B；第二电容Cst的第一极连接第一电压输入端OVDD，第二电容Cst的第二极连接第一节点A。
需要说明的是，上述实施例中，多个模块共用一个信号端可以减少GOA电路中信号端的数量，当然，这些模块还可以分别连接不同的信号端，只要该信号端可以提供类似的信号即可。
请参阅图2，图2为本发明实施例提供的像素驱动电路的电路图。具体的，第一输入模块101包括第一晶体管T1和第三晶体管T3；第一晶体管T1的第一端连接数据信号输入端，第一晶体管T1的第二端连接第一节点A，第一晶体管T1的栅极连接第一扫描信号输入端Gate N；第三晶体管T3的第一端连接第二电压输入端OVSS，第三晶体管T3的第二端连接第二节点B，第三晶体管T3的栅极连接第一扫描信号输入端Gate N。
第二输入模块102包括：第四晶体管T4；第四晶体管T4的第一端连接第三电压输入端Vref，第四晶体管T4的第二端连接第二节点B，第四晶体管T4的栅极连接第一扫描信号输入端Gate N+1。
驱动模块103包括：第二晶体管T2；第二晶体管T2的第一端连接第一电压输入端OVDD，第二晶体管T2的第二端连接发光二极管OLED的阳极，第二晶体管T2的栅极连接第一节点A。
其中，第一电压输入端OVDD和第二电压输入端OVSS用于提供发光二极管OLED的驱动电压，第三电压输入端Vref用于提供参考电压。，第三电压输入端Vref的电压值大于第二电压输入端OVSS的电压值。
进一步的，本发明实施例中的各个晶体管均为NMOS管，即第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4均为NMOS管，NMOS管在栅极为高电平时导通，在栅极为低电平时截止。
请参阅图3，图3为本发明实施提供的像素驱动电路的驱动时序图。如图3所示，本发明实施例提供的像素驱动电路的驱动时序包括：第一时间段t1、和第二时间段t2。
其中，在第一时间段，第一扫描信号输入端Gate N的第一扫描信号为高电平，第一扫描信号输入端Gate N+1的第二扫描信号为低电平，第一晶体管T1和第三晶体管T3导通，第四晶体管T4关闭，第一节点A的电压VA与数据信号输入端的电压Vdata拉齐，第二节点B的电压与第二电压输入端OVSS的电压拉齐。
在第二时间段，第一扫描信号输入端Gate N的第一扫描信号为低电平，第一扫描信号输入端Gate N+1的第二扫描信号高电平，第一晶体管T1和第三晶体管T3关闭，第四晶体管T4导通，第二节点B的电压与第三电压输入端Vref的电压拉齐，同时由于电容耦合作用，第一节点A的电位会被抬升，以使得第二晶体管T2导通驱动发光二极管OLED发光。
具体的，第一节点A被抬升后的电压：         V data ’=V data+C1(Vref-OVSS)/(Cst+C1)，其中，V data为数据信号输入端的电压，Vref为第三电压输入端Vref的电压，C1为第一电容C1的电容值，Cst为第二电容Cst的电容值，OVSS为第二电压输入端OVSS的电压。
本发明提供的像素驱动电路，包括第一输入模块101、第二输入模块102、驱动模块103、发光二极管OLED、第一电容C1以及第二电容Cst，在第一扫描信号输入端Gate N+1的第二扫描信号的控制下，通过电容耦合作用抬升第一节点A的电位，从而提升薄膜晶体管的栅漏极电压，进而提升显示面板的显示品质。
本发明实施例还提供一种显示面板，其包括以上所述的像素驱动电路，具体可参照以上所描述的像素驱动电路，在此不做赘述。
本发明提供的像素驱动电路及显示面板，包括第一输入模块101、第二输入模块102、驱动模块103、发光二极管OLED、第一电容C1以及第二电容Cst，在第一扫描信号输入端Gate N+1的第二扫描信号的控制下，通过电容耦合作用抬升第一节点A的电位，从而提升薄膜晶体管的栅漏极电压，进而提升显示面板的显示品质。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种像素驱动电路，其包括：第一输入模块、第二输入模块、驱动模块、发光二极管、第一电容以及第二电容；
    所述第一输入模块连接第一扫描信号输入端、数据信号输入端、第二电压输入端端、第一节点和第二节点，用于在所述第一扫描信号输入端的第一扫描信号的控制下，将所述第一节点的电压与所述数据信号输入端的电压拉齐，以及将所述第二节点的电压与所述第二电压输入端的电压拉齐；
    所述第二输入模块连接第二扫描信号输入端、第三电压输入端以及所述第二节点，用于在所述第二扫描信号输入端的第二扫描信号的控制下，将所述第二节点的电压与所述第三电压输入端的电压拉齐；
    所述驱动模块连接所述第一节点、第一电压输入端和所述发光二极管的阳极，所述发光二极管的阴极连接所述第二电压输入端，所述驱动模块用于在所述第一节点的电压的控制下，驱动所述发光二极管发光；
    所述第一电容的第一极连接所述第一节点，所述第一电容的第二级连接所述第二节点；所述第二电容的第一极连接所述第一电压输入端，所述第二电容的第二极连接所述第一节点；
    其中，所述第一输入模块包括第一晶体管和第三晶体管；
    所述第一晶体管的第一端连接所述数据信号输入端，所述第一晶体管的第二端连接所述第一节点，所述第一晶体管的栅极连接所述第一扫描信号输入端；
    所述第三晶体管的第一端连接所述第二电压输入端，所述第三晶体管的第二端连接所述第二节点，所述第三晶体管的栅极连接所述第一扫描信号输入端；
    所述第二输入模块包括：第四晶体管；
    所述第四晶体管的第一端连接所述第三电压输入端，所述第四晶体管的第二端连接所述第二节点，所述第四晶体管的栅极连接所述第二扫描信号输入端。
  2. 根据权利要求1所述的像素驱动电路，其中，所述驱动模块包括：第二晶体管；
    所述第二晶体管的第一端连接所述第一电压输入端，所述第二晶体管的第二端连接所述发光二极管的阳极，所述第二晶体管的栅极连接所述第一节点。
  3. 根据权利要求2所述的像素驱动电路，其中，各个晶体管均为NMOS管。
  4. 根据权利要求1所述的像素电压，其中，所述第一电压输入端和所述第二电压输入端用于提供所述发光二极管的驱动电压，所述第三电压输入端用于提供参考电压。
  5. 根据权利要求4所述的像素驱动电路，其中，所述第三电压输入端的电压值大于所述第二电压输入端的电压值。
  6. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路的驱动时序包括：第一时间段和第二时间段；
    在所述第一时间段，所述第一扫描信号输入端的第一扫描信号为高电平，所述第二扫描信号输入端的第二扫描信号为低电平，所述第一晶体管和所述第三晶体管导通，所述第四晶体管关闭，所述第一节点的电压与所述数据信号输入端的电压拉齐，所述第二节点的电压与所述第二电压输入端的电压拉齐；
    在所述第二时间段，所述第一扫描信号输入端的第一扫描信号为低电平，所述第二扫描信号输入端的第二扫描信号高电平，所述第一晶体管和所述第三晶体管关闭，所述第四晶体管导通，所述第二节点的电压与所述第三电压输入端的电压拉齐，同时由于电容耦合作用，所述第一节点电位会被抬升，以使得所述第二晶体管导通驱动发光二极管发光。
  7. 根据权利要求6所述的像素驱动电路，其中，所述第一节点被抬升后的电压：                 Vdata’=Vdata+C1(Vref-OVSS)/(Cst+C1)，其中，Vdata为所述数据信号输入端的电压，Vref为所述第三电压输入端的电压，C1为所述第一电容的电容值，Cst为所述第二电容的电容值，OCSS为所述第二电压输入端的电压。
  8. 一种像素驱动电路，其包括：第一输入模块、第二输入模块、驱动模块、发光二极管、第一电容以及第二电容；
    所述第一输入模块连接第一扫描信号输入端、数据信号输入端、第二电压输入端端、第一节点和第二节点，用于在所述第一扫描信号输入端的第一扫描信号的控制下，将所述第一节点的电压与所述数据信号输入端的电压拉齐，以及将所述第二节点的电压与所述第二电压输入端的电压拉齐；
    所述第二输入模块连接第二扫描信号输入端、第三电压输入端以及所述第二节点，用于在所述第二扫描信号输入端的第二扫描信号的控制下，将所述第二节点的电压与所述第三电压输入端的电压拉齐；
    所述驱动模块连接所述第一节点、第一电压输入端和所述发光二极管的阳极，所述发光二极管的阴极连接所述第二电压输入端，所述驱动模块用于在所述第一节点的电压的控制下，驱动所述发光二极管发光；
    所述第一电容的第一极连接所述第一节点，所述第一电容的第二级连接所述第二节点；所述第二电容的第一极连接所述第一电压输入端，所述第二电容的第二极连接所述第一节点。
  9. 根据权利要求8所述的像素驱动电路，其中，所述第一输入模块包括第一晶体管和第三晶体管；
    所述第一晶体管的第一端连接所述数据信号输入端，所述第一晶体管的第二端连接所述第一节点，所述第一晶体管的栅极连接所述第一扫描信号输入端；
    所述第三晶体管的第一端连接所述第二电压输入端，所述第三晶体管的第二端连接所述第二节点，所述第三晶体管的栅极连接所述第一扫描信号输入端。
  10. 根据权利要求8所述的像素驱动电路，其中，所述第二输入模块包括：第四晶体管；
    所述第四晶体管的第一端连接所述第三电压输入端，所述第四晶体管的第二端连接所述第二节点，所述第四晶体管的栅极连接所述第二扫描信号输入端。
  11. 根据权利要求8所述的像素驱动电路，其中，所述驱动模块包括：第二晶体管；
    所述第二晶体管的第一端连接所述第一电压输入端，所述第二晶体管的第二端连接所述发光二极管的阳极，所述第二晶体管的栅极连接所述第一节点。
  12. 根据权利要求11所述的像素驱动电路，其中，各个晶体管均为NMOS管。
  13. 根据权利要求8所述的像素电压，其中，所述第一电压输入端和所述第二电压输入端用于提供所述发光二极管的驱动电压，所述第三电压输入端用于提供参考电压。
  14. 根据权利要求13所述的像素驱动电路，其中，所述第三电压输入端的电压值大于所述第二电压输入端的电压值。
  15. 根据权利要求8所述的像素驱动电路，其中，所述像素驱动电路的驱动时序包括：第一时间段和第二时间段；
    在所述第一时间段，所述第一扫描信号输入端的第一扫描信号为高电平，所述第二扫描信号输入端的第二扫描信号为低电平，所述第一晶体管和所述第三晶体管导通，所述第四晶体管关闭，所述第一节点的电压与所述数据信号输入端的电压拉齐，所述第二节点的电压与所述第二电压输入端的电压拉齐；
    在所述第二时间段，所述第一扫描信号输入端的第一扫描信号为低电平，所述第二扫描信号输入端的第二扫描信号高电平，所述第一晶体管和所述第三晶体管关闭，所述第四晶体管导通，所述第二节点的电压与所述第三电压输入端的电压拉齐，同时由于电容耦合作用，所述第一节点电位会被抬升，以使得所述第二晶体管导通驱动发光二极管发光。
  16. 根据权利要求15所述的像素驱动电路，其中，所述第一节点被抬升后的电压：                 Vdata’=Vdata+C1(Vref-OVSS)/(Cst+C1)，其中，Vdata为所述数据信号输入端的电压，Vref为所述第三电压输入端的电压，C1为所述第一电容的电容值，Cst为所述第二电容的电容值，OCSS为所述第二电压输入端的电压。
  17. 一种显示面板，其包括像素驱动电路，所述像素电路包括：第一输入模块、第二输入模块、驱动模块、发光二极管、第一电容以及第二电容；
    所述第一输入模块连接第一扫描信号输入端、数据信号输入端、第二电压输入端端、第一节点和第二节点，用于在所述第一扫描信号输入端的第一扫描信号的控制下，将所述第一节点的电压与所述数据信号输入端的电压拉齐，以及将所述第二节点的电压与所述第二电压输入端的电压拉齐；
    所述第二输入模块连接第二扫描信号输入端、第三电压输入端以及所述第二节点，用于在所述第二扫描信号输入端的第二扫描信号的控制下，将所述第二节点的电压与所述第三电压输入端的电压拉齐；
    所述驱动模块连接所述第一节点、第一电压输入端和所述发光二极管的阳极，所述发光二极管的阴极连接所述第二电压输入端，所述驱动模块用于在所述第一节点的电压的控制下，驱动所述发光二极管发光；
    所述第一电容的第一极连接所述第一节点，所述第一电容的第二级连接所述第二节点；所述第二电容的第一极连接所述第一电压输入端，所述第二电容的第二极连接所述第一节点。
  18. 根据权利要求17所述的显示面板，其中，所述第一输入模块包括第一晶体管和第三晶体管；
    所述第一晶体管的第一端连接所述数据信号输入端，所述第一晶体管的第二端连接所述第一节点，所述第一晶体管的栅极连接所述第一扫描信号输入端；
    所述第三晶体管的第一端连接所述第二电压输入端，所述第三晶体管的第二端连接所述第二节点，所述第三晶体管的栅极连接所述第一扫描信号输入端。
  19. 根据权利要求17所述的显示面板，其中，所述第二输入模块包括：第四晶体管；
    所述第四晶体管的第一端连接所述第三电压输入端，所述第四晶体管的第二端连接所述第二节点，所述第四晶体管的栅极连接所述第二扫描信号输入端。
  20. 根据权利要求17所述的显示面板，其中，所述驱动模块包括：第二晶体管；
    所述第二晶体管的第一端连接所述第一电压输入端，所述第二晶体管的第二端连接所述发光二极管的阳极，所述第二晶体管的栅极连接所述第一节点。
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