WO2020000629A1 - 阵列基板及其制作方法、显示面板 - Google Patents

阵列基板及其制作方法、显示面板 Download PDF

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Publication number
WO2020000629A1
WO2020000629A1 PCT/CN2018/103269 CN2018103269W WO2020000629A1 WO 2020000629 A1 WO2020000629 A1 WO 2020000629A1 CN 2018103269 W CN2018103269 W CN 2018103269W WO 2020000629 A1 WO2020000629 A1 WO 2020000629A1
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Prior art keywords
layer
source
drain
gate
base
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French (fr)
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夏慧
谭志威
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/304,325 priority Critical patent/US20210225884A1/en
Publication of WO2020000629A1 publication Critical patent/WO2020000629A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0142—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating

Definitions

  • the present application relates to the field of panel manufacturing, and in particular, to an array substrate, a manufacturing method thereof, and a display panel.
  • common TFT Thin Film Transistor (Thin Film Transistor) driver classification mainly includes a-Si TFT (amorphous silicon), LTPS TFT (low temperature polysilicon), and IGZO TFT (indium gallium zinc oxide).
  • IGZO is a new type of semiconductor material with higher electron mobility and on-state current than amorphous silicon (a-Si), and is widely used in display industry TFT devices.
  • the present application provides an array substrate, a manufacturing method thereof, and a display panel to simplify the IGZO manufacturing process and reduce costs in the prior art.
  • This application proposes a method for manufacturing an array substrate, which includes steps:
  • the dielectric layer covers the gate and the base substrate
  • An active layer is formed on the dielectric layer.
  • a passivation layer is formed on the active layer.
  • the plating base layer includes a first base layer, a second base layer, and a third base layer, and the second base layer is located between the first base layer and the third base layer.
  • the gate is formed on the second base layer, and the source and drain are formed on the first base layer and the third base layer.
  • the step S40 includes:
  • the dielectric layer covers the active layer and the source and drain;
  • the gate and the source and drain are made in a same process.
  • the gate and the source and drain are made by a metal plating process.
  • a potential required to form the source and drain is greater than a potential required to form the gate.
  • the thickness of the source and drain is greater than the thickness of the gate.
  • the present application also proposes an array substrate, wherein the array substrate is prepared by the following manufacturing method, and the manufacturing method includes:
  • the thickness of the source and drain is greater than the thickness of the gate
  • the dielectric layer covers the gate and the base substrate
  • An active layer is formed on the dielectric layer.
  • a passivation layer is formed on the active layer.
  • the plating base layer includes a first base layer, a second base layer, and a third base layer, and the second base layer is located between the first base layer and the third base layer.
  • the gate is formed on the second base layer, and the source and drain are formed on the first base layer and the third base layer.
  • the step S40 includes:
  • the dielectric layer covers the active layer and the source and drain;
  • the gate and the source and drain are made in a same process.
  • the gate and the source and drain are made in a same process, and a potential required to form the source and drain is greater than a potential required to form the gate.
  • the present application also proposes a display panel including an array substrate, wherein the array substrate is prepared by using the following manufacturing method, and the manufacturing method includes:
  • the dielectric layer covers the gate and the base substrate
  • An active layer is formed on the dielectric layer.
  • a passivation layer is formed on the active layer.
  • the plating base layer includes a first base layer, a second base layer, and a third base layer, and the second base layer is located between the first base layer and the third base layer.
  • the gate is formed on the second base layer, and the source and drain are formed on the first base layer and the third base layer.
  • the step S40 includes:
  • the dielectric layer covers the active layer and the source and drain;
  • the gate and the source and drain are made in a same process.
  • the gate and the source and drain are made in a same process, and a potential required to form the source and drain is greater than a potential required to form the gate.
  • a gate electrode, a source electrode, and a drain electrode having different thicknesses are formed on a plating base layer by using a metal plating process, and a difference in height between the gate electrode and the source electrode and drain electrode is used to form a dielectric covering the gate electrode and exposing the source and drain electrodes on the substrate.
  • FIG. 1 is a flowchart of steps of an array substrate manufacturing method of the present application
  • FIGS. 2A-2H are process flow diagrams of an array substrate manufacturing method according to the present application.
  • FIG. 1 is a flowchart of the steps of a method for manufacturing an array substrate according to a preferred embodiment of the present application.
  • the manufacturing method includes:
  • a base substrate 101 is provided, and a raw material of the base substrate 101 may be one of a glass substrate, a quartz substrate, and a resin substrate;
  • a first metal layer 102 is formed on the base substrate 101.
  • the first metal layer is a plating seed layer.
  • the thickness of the metal layer is about 200 Angstroms.
  • the material of the layer 102 is preferably molybdenum;
  • a first photoresist layer is coated on the first metal layer 102, exposed using a mask (not shown), and subjected to patterning processes such as development and etching, and then the first metal layer 102 is processed. Patterning and peeling off the first photoresist layer, so that the first metal layer 102 forms a plating base layer;
  • the electroplated base layer includes a first base layer 103, a second base layer 104, and a third base layer 105, and the second base layer 104 is located between the first base layer 103 and the third base layer 105;
  • this step mainly uses a metal plating process, but is not limited to this method.
  • the gate 106 and the source and drain 107 of the array substrate are simultaneously formed on the plating base layer, that is, in the same process process.
  • the metal materials for preparing the gate 106 and the source / drain 107 are the same or different.
  • the metal materials can be metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper.
  • the metal plating process mainly places the structure shown in FIG. 2C in an electrolytic cell to plate the corresponding metal.
  • the first base layer 103 or the third base layer 105 and the second base layer 104 are connected to different potentials.
  • the potential of the third base layer 105 is the same; in this step, because a certain potential difference exists between different base layers, the rate of metal deposition between the base layers is different, as shown in FIG. 2D;
  • the potential required to form the source and drain 107 is greater than the potential required to form the gate 106. Therefore, at the same time, the potentials of the source and drain 107 on the first base layer 103 and the third base layer 105 are the same.
  • the thickness is larger than the thickness of the gate 105 on the second base layer 104; preferably, the thickness of the gate 106 is 5000 ⁇ , and the thickness of the source / drain 107 is 1 micron;
  • the gate 106 is located on the second base layer 104, and the source and drain 107 are located on the first base layer 103 and the third base layer 105.
  • a dielectric layer is formed on the gate, wherein the dielectric layer covers the gate and the base substrate to expose a portion of the source and drain;
  • a dielectric layer 108 is formed on the gate 106. This step is mainly realized by a chemical method, and an organic insulating material with better leveling property is deposited on the base substrate 101. A dielectric layer 108 covers the gate 106 and the base substrate 101 and exposes part of the source and drain 107.
  • An active layer is formed on the dielectric layer.
  • an active layer 109 is first formed on the dielectric layer 108 and the source and drain electrodes 107.
  • the active layer 109 is a metal oxide; secondly, in the step A first photoresist layer is formed on the active layer 109 and exposed with a mask (not shown). After the first photoresist layer is developed, the source and drain 107 and the source and drain 107 are retained. The first photoresist layer; again, an etching process is performed on the active layer 109 to retain the active layer 109 between the source and drain 107 and on the source and drain 107; as shown in FIG. 2G As shown, the active layer 109 covers the dielectric layer 108 between the source and drain 107 and the source and drain 107.
  • a passivation layer is formed on the active layer.
  • a passivation layer 110 is formed on the active layer 109 and the dielectric layer 108, and the passivation layer 110 covers the active layer 109 and the dielectric layer 108;
  • the material of the passivation layer 110 is usually a silicon nitride compound.
  • the present application also proposes an array substrate, wherein the array substrate is prepared by using the manufacturing method of the array substrate.
  • the present application also proposes a display panel, wherein the display panel includes the above-mentioned array substrate.
  • This application provides an array substrate, a manufacturing method thereof, and a display panel.
  • This application mainly uses a metal plating process to form gates and source and drain electrodes of different thicknesses on a plating base layer, and utilizes the height difference between the gate and source and drain electrodes.
  • a dielectric layer is formed on the substrate to cover the gate and expose the source and drain, so that the active layer is connected to the source and drain, and is isolated from the gate through the dielectric layer.
  • the etch barrier is removed and the IGZO is simplified. Process technology, saving costs.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请提出了一种阵列基板及其制作方法、显示面板，本申请通过金属电镀的工艺在电镀基层上形成不同厚度的栅极和源漏极，并利用栅极和源漏极的高度差，在基板上形成将栅极覆盖以及露出源漏极的介电层，使得有源层与源漏极连接导通，并通过介电层与栅极隔离，去掉了蚀刻阻挡层，简化了IGZO的制程工艺，节省了成本。

Description

阵列基板及其制作方法、显示面板 技术领域
本申请涉及面板制造领域，尤其涉及一种阵列基板及其制作方法、显示面板。
 背景技术
目前，常见的TFT（Thin Film Transistor，薄膜晶体管）驱动分类主要有a-Si TFT（非晶硅）、LTPS TFT（低温多晶硅）以及IGZO TFT（indium gallium zinc oxide，氧化铟镓锌）。简单来说，IGZO是一种新型半导体材料，有着比非晶硅（a-Si）更高的电子迁移率和开态电流，被广泛应用到显示行业TFT器件中。
现有常用的BCE（Back Channel Etching，背沟道蚀刻）底栅极IGZO TFT制程较为复杂，需要增加ESL（etching stop layer，蚀刻阻挡）层，用于避免在源漏极金属电极层湿刻时对沟道处的IGZO造成损伤而影响器件性能。
 技术问题
本申请提供了一种阵列基板及其制作方法、显示面板，以简化现有技术中IGZO的制程工艺，降低成本。
 技术解决方案
本申请提出了一种阵列基板的制作方法，其包括步骤：
S10、提供一衬底基板，在所述衬底基板上形成一金属层，通过图案化制程在所述衬底基板上形成电镀基层；
S20、在所述电镀基层上形成不同厚度的栅极和源漏极；
S30、在所述栅极上形成一介电层，
其中，所述介电层将所述栅极和所述衬底基板覆盖；
S40、在所述介电层上形成一有源层；
S50、在所述有源层上形成一钝化层。
在本申请的制作方法中，所述电镀基层包括第一基层、第二基层和第三基层，所述第二基层位于所述第一基层和所述第三基层之间。
在本申请的制作方法中，所述栅极形成所述第二基层上，所述源漏极形成于所述第一基层和所述第三基层上。
在本申请的制作方法中，所述步骤S40包括：
S401、在所述介电层上形成一所述有源层，
其中，所述介电层将所述有源层和所述源漏极覆盖；
S402、在所述有源层上涂布第一光阻层；
S403、对所述第一光阻层进行曝光、显影；
S404、对所述有源层进行蚀刻工艺，保留所述源漏极之间以及所述源漏极上的所述有源层；
S405、剥离所述第一光阻层。
在本申请的制作方法中，所述栅极和所述源漏极在同一道制程工艺中制成。
在本申请的制作方法中，所述栅极和所述源漏极通过金属电镀的工艺制成。
在本申请的制作方法中，形成所述源漏极所需的电位大于形成所述栅极所需的电位。
在本申请的制作方法中，所述源漏极的厚度大于所述栅极的厚度。
本申请还提出了一种阵列基板，其中，所述阵列基板采用如下制作方法制备而成，所述制作方法包括：
S10、提供一衬底基板，在所述衬底基板上形成一金属层，通过图案化制程在所述衬底基板上形成电镀基层；
S20、在所述电镀基层上形成不同厚度的栅极和源漏极，
其中，所述源漏极的厚度大于所述栅极的厚度；
S30、在所述栅极上形成一介电层，
其中，所述介电层将所述栅极和所述衬底基板覆盖；
S40、在所述介电层上形成一有源层；
S50、在所述有源层上形成一钝化层。
在本申请的阵列基板中，所述电镀基层包括第一基层、第二基层和第三基层，所述第二基层位于所述第一基层和所述第三基层之间。
在本申请的阵列基板中，所述栅极形成所述第二基层上，所述源漏极形成于所述第一基层和所述第三基层上。
在本申请的阵列基板中，所述步骤S40包括：
S401、在所述介电层上形成一所述有源层，
其中，所述介电层将所述有源层和所述源漏极覆盖；
S402、在所述有源层上涂布第一光阻层；
S403、对所述第一光阻层进行曝光、显影；
S404、对所述有源层进行蚀刻工艺，保留所述源漏极之间以及所述源漏极上的所述有源层；
S405、剥离所述第一光阻层。
在本申请的阵列基板中，所述栅极和所述源漏极在同一道制程工艺中制成。
在本申请的阵列基板中，所述栅极和所述源漏极在同一道制程工艺中制成，形成所述源漏极所需的电位大于形成所述栅极所需的电位。
本申请还提出了一种显示面板，包括阵列基板，其中，所述阵列基板采用如下制作方法制备而成，所述制作方法包括：
S10、提供一衬底基板，在所述衬底基板上形成一金属层，通过图案化制程在所述衬底基板上形成电镀基层；
S20、在所述电镀基层上形成不同厚度的栅极和源漏极；
S30、在所述栅极上形成一介电层，
其中，所述介电层将所述栅极和所述衬底基板覆盖；
S40、在所述介电层上形成一有源层；
S50、在所述有源层上形成一钝化层。
在本申请的显示面板中，所述电镀基层包括第一基层、第二基层和第三基层，所述第二基层位于所述第一基层和所述第三基层之间。
在本申请的显示面板中，所述栅极形成所述第二基层上，所述源漏极形成于所述第一基层和所述第三基层上。
在本申请的显示面板中，所述步骤S40包括：
S401、在所述介电层上形成一所述有源层，
其中，所述介电层将所述有源层和所述源漏极覆盖；
S402、在所述有源层上涂布第一光阻层；
S403、对所述第一光阻层进行曝光、显影；
S404、对所述有源层进行蚀刻工艺，保留所述源漏极之间以及所述源漏极上的所述有源层；
S405、剥离所述第一光阻层。
在本申请的显示面板中，所述栅极和所述源漏极在同一道制程工艺中制成。
在本申请的显示面板中，所述栅极和所述源漏极在同一道制程工艺中制成，形成所述源漏极所需的电位大于形成所述栅极所需的电位。
 有益效果
本申请通过金属电镀的工艺在电镀基层上形成不同厚度的栅极和源漏极，并利用栅极和源漏极的高度差，在基板上形成将栅极覆盖以及露出源漏极的介电层，使得有源层与源漏极连接导通，并通过介电层与栅极隔离，去掉了蚀刻阻挡层，简化了IGZO的制程工艺，节省了成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一种阵列基板制作方法步骤流程图；
图2A~2H本申请一种阵列基板制作方法工艺流程图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
图1所示为本申请优选实施例一种阵列基板阵列基板制作方法的步骤流程图，其中，所述制作方法包括：
S10、提供一衬底基板，在所述衬底基板上形成一金属层，通过图案化制程在所述衬底基板上形成电镀基层；
如图2A所示，首先，提供一衬底基板101，所述衬底基板101的原材料可以为玻璃基板、石英基板、树脂基板等中的一种；
如图2B所示，在所述衬底基板101上形成第一金属层102，所述第一金属层为电镀种子层，优选的，所述金属层的厚度在200埃米左右，第一金属层102的材料优选为钼；
如图2C所示，在第一金属层102上涂布第一光阻层，采用掩模板（未画出）进行曝光，经显影以及蚀刻等构图工艺处理后，将所述第一金属层102图案化，并剥离所述第一光阻层，使得第一金属层102形成电镀基层；
其中，所述电镀基层包括第一基层103、第二基层104以及第三基层105，所述第二基层104位于所述第一基层103和所述第三基层105之间；
S20、在所述电镀基层上形成不同厚度的栅极和源漏极；
如图2D所示，本步骤主要利用金属电镀的工艺，但不限定此方法，在所述电镀基层上同时形成所述阵列基板的栅极106和源漏极107，即在同一道制程工艺中所制成；
在本实施例中，制备栅极106和源漏极107的金属材料相同或不同，金属材料可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种金属材料的组合物；优选的，所述栅极106和所述源漏极107的材料为铜；
其中，金属电镀工艺主要将图2C中的结构放置在电解槽中镀相应的金属，所述第一基层103或第三基层105与所述第二基层104连接不同的电位，第一基层103与第三基层105的电位相同；此步骤中，由于不同基层之间存在一定的电位差，因此各基层之间沉积金属的速率不同，如图2D所示；
本实施例中，形成所述源漏极107所需的电位大于形成所述栅极106所需的电位，因此在相同时间内，第一基层103和第三基层105上的源漏极107的厚度较第二基层104上的栅极105的厚度大；优选的，所述栅极106的厚度为5000埃米，所述源漏极107的厚度为1微米；
另外，所述栅极106位于所述第二基层104上，所述源漏极107位于所述第一基层103和所述第三基层105上。
S30、在所述栅极上形成一介电层，其中，所述介电层将所述栅极和所述衬底基板覆盖，露出部分所述源漏极；
如图2E所示，在所述栅极106上形成一介电层108，此步骤主要利用化学方法实现，采用流平性较好的有机绝缘材料沉积在所述衬底基板101上，所述介电层108将所述栅极106和所述衬底基板101覆盖，并露出部分所述源漏极107。
S40、在所述介电层上形成一有源层；
如图2F所示，本步骤首先在所述介电层108和所述源漏极107上形成一有源层109，优选的，所述有源层109为金属氧化物；其次，在所述有源层109上形成第一光阻层，采用掩模板（未画出）曝光，所述第一光阻层经显影后，保留所述源漏极107之间和所述源漏极107上的所述第一光阻层；再次，对所述有源层109进行蚀刻工艺，保留所述源漏极107之间和所述源漏极107上的所述有源层109；如图2G所示，所述有源层109将所述源漏极107和所述源漏极107之间的所述介电层108覆盖。
S50、在所述有源层上形成一钝化层。
如图2H所示，在所述有源层109和所述介电层108上形成一钝化层110，所述钝化层110将所述有源层109以及介电层108覆盖；优选的，所述钝化层110材料通常为氮化矽化合物。
本申请还提出了一种阵列基板，其中，所述阵列基板采用上述阵列基板的制作方法制备而成。
本申请还提出了一种显示面板，其中，所述显示面板包括上述阵列基板。
本申请提供了一种阵列基板及其制作方法、显示面板，本申请主要通过金属电镀的工艺在电镀基层上形成不同厚度的栅极和源漏极，并利用栅极和源漏极的高度差，在基板上形成将栅极覆盖以及露出源漏极的介电层，使得有源层与源漏极连接导通，并通过介电层与栅极隔离，去掉了蚀刻阻挡层，简化了IGZO的制程工艺，节省了成本。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板的制作方法，其包括步骤：
    S10、提供一衬底基板，在所述衬底基板上形成一金属层，通过图案化制程在所述衬底基板上形成电镀基层；
    S20、在所述电镀基层上形成不同厚度的栅极和源漏极；
    S30、在所述栅极上形成一介电层，
    其中，所述介电层将所述栅极和所述衬底基板覆盖；
    S40、在所述介电层上形成一有源层；
    S50、在所述有源层上形成一钝化层。
  2. 根据权利要求1所述的制作方法，其中，所述电镀基层包括第一基层、第二基层和第三基层，所述第二基层位于所述第一基层和所述第三基层之间。
  3. 根据权利要求2所述的制作方法，其中，所述栅极形成所述第二基层上，所述源漏极形成于所述第一基层和所述第三基层上。
  4. 根据权利要求1所述的制作方法，其中，所述步骤S40包括：
    S401、在所述介电层上形成一所述有源层，
    其中，所述介电层将所述有源层和所述源漏极覆盖；
    S402、在所述有源层上涂布第一光阻层；
    S403、对所述第一光阻层进行曝光、显影；
    S404、对所述有源层进行蚀刻工艺，保留所述源漏极之间以及所述源漏极上的所述有源层；
    S405、剥离所述第一光阻层。
  5. 根据权利要求1所述的制作方法，其中，所述栅极和所述源漏极在同一道制程工艺中制成。
  6. 根据权利要求5所述的制作方法，其中，所述栅极和所述源漏极通过金属电镀的工艺制成。
  7. 根据权利要求6所述的制作方法，其中，形成所述源漏极所需的电位大于形成所述栅极所需的电位。
  8. 根据权利要求1所述的制作方法，其中，所述源漏极的厚度大于所述栅极的厚度。
  9. 一种阵列基板，其中，所述阵列基板采用如下制作方法制备而成，所述制作方法包括：
    S10、提供一衬底基板，在所述衬底基板上形成一金属层，通过图案化制程在所述衬底基板上形成电镀基层；
    S20、在所述电镀基层上形成不同厚度的栅极和源漏极，
    其中，所述源漏极的厚度大于所述栅极的厚度；
    S30、在所述栅极上形成一介电层，
    其中，所述介电层将所述栅极和所述衬底基板覆盖；
    S40、在所述介电层上形成一有源层；
    S50、在所述有源层上形成一钝化层。
  10. 根据权利要求9所述的阵列基板，其中，所述电镀基层包括第一基层、第二基层和第三基层，所述第二基层位于所述第一基层和所述第三基层之间。
  11. 根据权利要求10所述的阵列基板，其中，所述栅极形成所述第二基层上，所述源漏极形成于所述第一基层和所述第三基层上。
  12. 根据权利要求9所述的阵列基板，其中，所述步骤S40包括：
    S401、在所述介电层上形成一所述有源层，
    其中，所述介电层将所述有源层和所述源漏极覆盖；
    S402、在所述有源层上涂布第一光阻层；
    S403、对所述第一光阻层进行曝光、显影；
    S404、对所述有源层进行蚀刻工艺，保留所述源漏极之间以及所述源漏极上的所述有源层；
    S405、剥离所述第一光阻层。
  13. 根据权利要求9所述的阵列基板，其中，所述栅极和所述源漏极在同一道制程工艺中制成。
  14. 根据权利要求9所述的阵列基板，其中，所述栅极和所述源漏极在同一道制程工艺中制成，形成所述源漏极所需的电位大于形成所述栅极所需的电位。
  15. 一种显示面板，包括阵列基板，其中，所述阵列基板采用如下制作方法制备而成，所述制作方法包括：
    S10、提供一衬底基板，在所述衬底基板上形成一金属层，通过图案化制程在所述衬底基板上形成电镀基层；
    S20、在所述电镀基层上形成不同厚度的栅极和源漏极；
    S30、在所述栅极上形成一介电层，
    其中，所述介电层将所述栅极和所述衬底基板覆盖；
    S40、在所述介电层上形成一有源层；
    S50、在所述有源层上形成一钝化层。
  16. 根据权利要求15所述的显示面板，其中，所述电镀基层包括第一基层、第二基层和第三基层，所述第二基层位于所述第一基层和所述第三基层之间。
  17. 根据权利要求16所述的显示面板，其中，所述栅极形成所述第二基层上，所述源漏极形成于所述第一基层和所述第三基层上。
  18. 根据权利要求15所述的显示面板，其中，所述步骤S40包括：
    S401、在所述介电层上形成一所述有源层，
    其中，所述介电层将所述有源层和所述源漏极覆盖；
    S402、在所述有源层上涂布第一光阻层；
    S403、对所述第一光阻层进行曝光、显影；
    S404、对所述有源层进行蚀刻工艺，保留所述源漏极之间以及所述源漏极上的所述有源层；
    S405、剥离所述第一光阻层。
  19. 根据权利要求15所述的显示面板，其中，所述栅极和所述源漏极在同一道制程工艺中制成。
  20. 根据权利要求15所述的显示面板，其中，所述栅极和所述源漏极在同一道制程工艺中制成，形成所述源漏极所需的电位大于形成所述栅极所需的电位。
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