WO2019242079A1 - 一种相变存储器的擦写方法 - Google Patents

一种相变存储器的擦写方法 Download PDF

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Publication number
WO2019242079A1
WO2019242079A1 PCT/CN2018/099520 CN2018099520W WO2019242079A1 WO 2019242079 A1 WO2019242079 A1 WO 2019242079A1 CN 2018099520 W CN2018099520 W CN 2018099520W WO 2019242079 A1 WO2019242079 A1 WO 2019242079A1
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phase change
change memory
phase
state
change material
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PCT/CN2018/099520
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English (en)
French (fr)
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童浩
何明泽
缪向水
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华中科技大学
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides

Definitions

  • the invention belongs to the field of microelectronics, and more particularly, relates to a method for erasing and erasing that can reduce power consumption of a phase change memory, including a pre-operation and an erasing operation.
  • phase change memory has no theoretical physical limit, simple structure and fast erasing speed, it is considered as one of the candidates for the next generation of nonvolatile memory.
  • phase change memory As the most mature and most likely commercialized storage device in the next generation of non-volatile memory technology, phase change memory has received widespread attention. However, the higher operating current of the phase change memory has limited its application. At present, a series of work has been devoted to reducing the operating current of the phase change memory. For example, patent CN1763986A uses a special process to achieve a lower electrode contact area, thereby reducing the power consumption of phase change memory; patent CN102064276B uses asymmetric ring electrode contact to reduce operating power consumption. However, the structures of the above methods are more complicated, which will increase production costs.
  • the present invention provides a method for erasing and writing phase change memory, thereby solving the technical problems of complicated structure and high production cost in the existing way of reducing the operation current of phase change memory .
  • the present invention provides a method for erasing and writing a phase change memory, including:
  • Pre-operating the phase change memory causes the phase change material in the phase change memory to enter an intermediate state from an initial amorphous state, where the intermediate state is between the amorphous state and a stable crystalline state Metastable;
  • a second electrical pulse is applied to the phase change material in the phase change memory, so that the phase change material is in an intermediate state to implement a write operation.
  • the erasing operation and the writing operation can perform a cyclic operation through a reversible transition of the phase change material between the amorphous state and the intermediate state, and then through the amorphous state and the The difference in resistance between the intermediate states is used for data storage.
  • the pre-operation is to anneal or apply a pulse effect to the phase change memory, wherein the pulse effect includes an optical pulse, an electrical pulse, a magnetic field pulse, and a pressure pulse.
  • the pulse effect includes an optical pulse, an electrical pulse, a magnetic field pulse, and a pressure pulse.
  • the intermediate state is a metastable crystal phase capable of being stably present.
  • the phase change material is a sulfur-based compound.
  • the phase change material is brought into an intermediate state by performing a pre-operation on the phase change memory, and the phase change material is reversibly transformed between the intermediate state and the amorphous state, thereby realizing a high and low resistance state cycle of the phase change memory, compared with the traditional Phase change memory that operates phase change materials between crystalline and amorphous states, using the phase change memory of the present invention has a significantly reduced operating current, and the operating current is reduced to be able to be integrated with a two-terminal gate to achieve three-dimensional The degree of stacking.
  • the operation scheme of the invention is simple, suitable for phase change memories of various structures, and can reduce operating power consumption without changing the production process. It has the potential for large-scale applications and is suitable for industrial production and commercialization.
  • FIG. 1 is a schematic flowchart of a method for erasing and writing a phase change memory according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a phase-change memory after depositing an electrode material, which is a sectional view;
  • FIG. 3 is a top view of a substrate view of a phase change memory provided by an embodiment of the present invention.
  • FIG. 4 is a top view of a phase change memory after a bottom electrode is deposited according to an embodiment of the present invention
  • FIG. 5 is a top view of a phase change memory after an insulating layer is deposited according to an embodiment of the present invention
  • FIG. 6 is a top view of a phase change memory according to an embodiment of the present invention after performing small hole etching
  • FIG. 7 is a cross-sectional view of a phase change memory according to an embodiment of the present invention after performing small hole etching
  • FIG. 8 is a top view of a phase change memory after depositing a phase change material according to an embodiment of the present invention.
  • phase change memory 9 is a cross-sectional view of a phase change memory after depositing a phase change material according to an embodiment of the present invention.
  • FIG. 10 is a top view of a phase change memory after depositing an electrode material according to an embodiment of the present invention.
  • FIG. 11 is a voltage-current diagram during operation of a different pre-operation mode according to an embodiment of the present invention.
  • FIG. 12 is a resistance-voltage diagram in a wiping operation after a different operation mode according to an embodiment of the present invention.
  • the present invention provides a method for erasing a phase change memory, which is mainly applied to operation modes based on the characteristics of sulfur-based phase change materials, and is suitable for three-dimensional stacked column structure phase change memory This operation method is implemented in.
  • the columnar phase change memory used in the embodiments including etching and thin film deposition processes, has good process compatibility with modern semiconductor processes. Since the present invention relies on operating modes instead of adjusting the phase-change memory structure, there is no need to make any changes to the production process to reduce costs and achieve low power consumption operation, which has high versatility and practical value.
  • Sulfur-based phase change materials usually have an amorphous state (solid molecules, atoms or ions that do not form a regular spatial distribution of periodic solids during heating, and are isotropic) and a crystalline state (molecules, atoms or The ions have a regular spatial arrangement and are anisotropic) two more stable states. Through rapid heating and rapid cooling, they can quickly become amorphous after melting, and the resistance in both states There are large differences in rates. In addition, many phase change materials have metastable intermediate states between stable crystalline and amorphous states.
  • the structure of the phase change memory includes a columnar structure, a lateral bridge structure, a ring electrode structure in contact with a side wall, a mushroom structure, and the like.
  • the specific structure is not specifically limited in the embodiment of the present invention.
  • the pre-operation and subsequent cycle operations include electrical operation, thermal operation, and laser operation.
  • the specific operation mode is not limited in the embodiment of the present invention.
  • An embodiment of the present invention provides a method for manufacturing a columnar phase change memory, which includes the following steps:
  • Step 1 Deposit and prepare a bottom electrode on the substrate, the thickness of the electrode is from 1nm to 100um, and the electrode uses a conductive material, including gold, platinum, titanium nitride, etc .;
  • Step 2 deposit an insulating layer on the electrode material, the insulating layer has an insulating effect, and the material includes SiO 2 , SiN, etc .;
  • Step 3 forming a small hole structure in the isolation layer, and the size of the small hole pore size is 0.1 nm to 100um;
  • Step 4 Deposit a sulfur-based phase change material in the insulating small hole, with a thickness of 0.1 nm to 100 um;
  • Step 5 Deposit an electrode material over the phase change material.
  • the electrode uses a conductive material, including gold, platinum, titanium nitride, and the like.
  • the phase change material is a sulfur-based compound, which mainly includes a combination of IVA, VA and VIA elements in the periodic table of elements, such as Ge-Sb-Te material, Ge-Te material, Sb-Te material, Bi -Te material, Ge-Se material, Bi-Se material, Ge-Sb material, Si-Sb-Te material, and In-Sb-Te material.
  • the Ge-Sb-Te material has a metastable intermediate state between the stable hexagonal crystal orientation and the amorphous state.
  • the Ge-Sb-Te material in the phase change memory is placed in an intermediate state of a cubic phase by a pre-operation. Then, the Ge-Sb-Te material in the phase change memory is placed in an amorphous state using a pulse, thereby realizing the erase operation. It is also possible to use pulses to reset the Ge-Sb-Te material in the phase change memory to an intermediate state, thereby realizing a write operation.
  • the Ge-Sb-Te material in the phase change memory undergoes a reversible transition between the amorphous state and the intermediate state instead of between the amorphous state and the crystalline state. In this way of operation, the operating current and operating power consumption are reduced.
  • the Ge-Sb-Te material is brought into an intermediate state with a higher energy state, and then an electrical pulse operation is applied to the phase change memory to cause the phase change material to undergo a reversible transition between the intermediate state and the amorphous state. Realize high and low resistance change of phase change memory. During this operation, the operating current is very low, enabling low-power operation.
  • FIG. 1 is a schematic flowchart of a phase change memory erasing method provided by an embodiment of the present invention, including:
  • Pre-operating the phase change memory causes the phase change material in the phase change memory to enter an intermediate state from an initial amorphous state, where the intermediate state is a metastable state between an amorphous state and a stable crystalline state;
  • a second electrical pulse is applied to the phase change material in the phase change memory, so that the phase change material is in an intermediate state to implement a write operation.
  • the erasing operation and the writing operation can perform a cyclic operation through the reversible transformation of the phase change material between the amorphous state and the intermediate state, and further perform data storage through the difference in resistance between the amorphous state and the intermediate state.
  • phase change material is a sulfur-based compound.
  • the manner of performing the pre-operation of the phase change memory includes annealing or applying pulses, including laser pulses, electrical pulses, magnetic field pulses, and pressure pulses.
  • FIG. 2 is a schematic cross-sectional view of a columnar phase change memory according to an embodiment of the present invention, including a bottom electrode, a layer of separation and isolation, and processing.
  • the phase change material in the small holes of the isolation layer is an electrode material located above the isolation layer.
  • the substrate in the embodiment of the present invention is a silicon substrate, which can facilitate manufacturing compatible with the CMOS process.
  • its low current characteristic is suitable for integration with a two-terminal gate to realize three-dimensional stacking.
  • the resistance of the phase change memory is about 50 M ⁇ .
  • the pre-operation of this embodiment is implemented using electric pulses.
  • a current pulse of increasing step size is applied to the phase change memory, and there are 100 steps each time from 0A to the peak value.
  • the resistance of the phase change memory also decreases.
  • the voltage-current curve of this process is shown in Figure 11. In this process, the instrument used was a B1500A semiconductor device analyzer, and the operating mode was DC scanning.
  • phase change memories After performing a write operation through this series of scan pulses, several phase change memories are placed in different low-impedance states, and these cells that obtain different resistance values through different scan currents are named "A", “B”, and “C” ", Where the unit with a resistance value of 1.5K ⁇ obtained after a scanning current of 500 ⁇ A is unit” A ", the unit with a resistance value of 200 ⁇ obtained after a 3mA scan current is unit” B ", and the resistance value obtained after a 5mA scan current is The 100 ⁇ unit is the unit "C”.
  • the erase operation was performed using the same electrical pulse sequence.
  • the resistance-voltage curve during the wiping operation is shown in Figure 12. It can be seen that for the "A” unit with a higher resistance value, the voltage required to reach the high resistance state is lower, and for the "C” with the lowest resistance value The unit needs 5V electric pulse to realize the wiping operation.
  • the operating current is only about 500 ⁇ A. This huge operating voltage / current difference is achieved by a specific low-current write operation. This low-current write operation can make the Ge-Sb-Te material enter the cube. The crystalline phase makes its energy state higher, so the energy level for transforming it to a molten state to achieve a wiping operation is lower.
  • an electrical pulse with an amplitude of 1 V can be applied to the phase change memory to amorphize the phase change material, thereby realizing the erasing operation;
  • a scanning current of 500 ⁇ A amplitude is applied to the unit to make the phase change material enter the intermediate state again, thereby realizing the write operation.
  • the operating current of the phase change memory is reduced from 90MA / cm 2 to 1MA / cm 2 , thereby achieving low power consumption operation, and the extremely low current density enables it to be integrated with the gate, so that Three-dimensional integration becomes possible.
  • FIG. 2 to FIG. 10 are a processing process and an operation process provided by an example implementation of the present invention:
  • Step 1 As shown in FIG. 3 and FIG. 4, a DC magnetron sputtering method is used to grow a 10-nm-thick Ti layer on the silicon wafer 100 with a thermally-oxidized oxide layer as an adhesion layer to prevent platinum from passing through the silicon dioxide. On off. 100 nm thick platinum was subsequently deposited as the bottom electrode material 110 by sputtering. Magnetron sputtering is a common process method for physical vapor deposition of thin films. By adding a closed magnetic field parallel to the target surface in dipole sputtering, the secondary electrons are bound to Specific areas of the target surface enhance ionization efficiency, increase ion density and energy, thereby achieving high-rate sputtering processes. For DC magnetron sputtering, it is usually used for conductive materials.
  • Step 2 As shown in FIG. 5, a layer of SiO 2 is deposited as the insulating layer 120 by using a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Deposition, PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the use of PECVD is a common process method for physical vapor deposition of thin films.
  • the gas containing the constituent atoms of the film is ionized by microwave or radio frequency to form a plasma locally.
  • the plasma is highly chemically active and easily reacts.
  • a desired film is deposited on the wafer. In order to make the chemical reaction proceed at a lower temperature, the activity of the plasma is used to promote the reaction, so it is called plasma enhanced chemical vapor deposition PECVD.
  • Step 3 As shown in FIG. 6 and FIG. 7, an electron beam lithography (EBL) is used to make a lithographic pattern on a silicon wafer, and then a reaction-enhanced plasma etching (ICP) technique is used to etch the pattern. A small hole array 130 is shown. The top view is shown in FIG. 6.
  • the plasma etching technology is a common dry etching technology. The principle is that the gas exposed to the electron region forms a plasma. A gas composed of high-energy electrons, thereby forming a plasma or ion. When an ionized gas atom is accelerated by an electric field, it will release sufficient force and surface repelling force to tightly adhere to the material or etch the surface.
  • step four as shown in FIG. 8 and FIG. 9, a 150 nm thick Ge 2 Sb 2 Te 5 material is deposited as a phase change material layer 140 by pulsed laser deposition (PLD).
  • PLD pulsed laser deposition
  • PLD uses a laser to melt and vaporize the atoms on the target, and finally the vaporized atoms nucleate on the surface of the substrate to form a thin film.
  • Step 5 As shown in FIG. 10 and FIG. 2, a 150 nm thick TiW material is used as the upper electrode material 150 by magnetron sputtering.
  • FIG. 11 is a current-voltage diagram of the process of scanning and writing through different currents according to an embodiment of the present invention. It can be seen from FIG. 11 that by scanning currents of different amplitudes, unit samples of different resistance values can be obtained.
  • FIG. 12 is the application of exactly the same pulse sequence to these cells after different write operations, thereby realizing the erase operation.
  • the phase change memory based on the more common columnar structure is improved in operation mode, and an extremely low operating current is achieved, thereby reducing operating power consumption.
  • the operating current density is as low as 1MA / cm 2 , which has the potential to integrate with the existing two-terminal gate, thereby achieving vertical stacking and thus increasing storage density.

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Abstract

本发明公开了一种相变存储器的擦写方法，其擦写包括通过对于相变存储器进行预操作使相变材料进入中间态，并且将相变材料在中间态以及非晶态之间进行可逆转变从而实现相变存储器的高低阻态循环，相较于传统的将相变材料在晶态以及非晶态之间操作的相变存储器，使用本发明的相变存储器有着显著降低的操作电流，操作电流被降低至可以与二端选通管集成从而实现三维堆叠的程度。本发明操作方案简单，适用于各种结构的相变存储器，且可以在不改变生产流程的前提下降低操作功耗，有着大规模应用的潜力，适用于工业生产和产品化。

Description

一种相变存储器的擦写方法 【技术领域】
本发明属于微电子学领域，更具体地，涉及一种可以使相变存储器功耗降低的擦写方法，包括预操作以及擦写操作。
【背景技术】
现代社会对于低功耗、高密度存储的需求越来越高，而Flash技术面临着物理极限难以进一步发展。由于相变存储器没有理论上的物理极限，结构简单，擦写速度快，被人们认为是下一代非易失存储器的候选之一。
作为下一代非易失存储技术中最为成熟也最有可能商业化的存储器件，相变存储器一直受到广泛的关注。但是相变存储器较高的操作电流局限了其应用，目前已经有一系列的工作致力于降低相变存储器的操作电流。如：专利CN1763986A通过特殊工艺来实现较低的电极接触面积，从而降低相变存储器的功耗；专利CN102064276B利用非对称环状电极接触从而降低操作功耗。但是以上方式结构都较为复杂，从而会提高生产成本。
【发明内容】
针对现有技术的以上缺陷或改进需求，本发明提供了一种相变存储器的擦写方法，由此解决现有降低相变存储器操作电流的方式存在的结构复杂，生产成本较高的技术问题。
为实现上述目的，本发明提供了一种相变存储器的擦写方法，包括：
对相变存储器进行预操作使所述相变存储器中的相变材料从初始的非晶态进入中间态，其中，所述中间态是介于所述非晶态以及稳定的晶态之间的亚稳态；
对所述相变存储器中的相变材料施加第一电脉冲，使所述相变材料进 入非晶态，以实现擦操作；
对所述相变存储器中的相变材料施加第二电脉冲，使所述相变材料处于中间态，以实现写操作。
优选地，所述擦操作与所述写操作之间能够通过所述相变材料在所述非晶态以及所述中间态之间的可逆转变进行循环操作，进而通过所述非晶态以及所述中间态之间的阻值差异进行数据存储。
优选地，所述预操作为将所述相变存储器退火或施加脉冲作用，其中，所述脉冲作用包括光学脉冲、电学脉冲、磁场脉冲和压力脉冲。
优选地，所述中间态为能够稳定存在的亚稳态晶相。
优选地，所述相变材料为硫系化合物。
总体而言，通过本发明所构思的以上技术方案与现有技术相比，能够取得下列有益效果：
本发明通过对于相变存储器进行预操作使相变材料进入中间态，并且将相变材料在中间态以及非晶态之间进行可逆转变从而实现相变存储器的高低阻态循环，相较于传统的将相变材料在晶态以及非晶态之间操作的相变存储器，使用本发明的相变存储器有着显著降低的操作电流，操作电流被降低至可以与二端选通管集成从而实现三维堆叠的程度。本发明操作方案简单，适用于各种结构的相变存储器，且可以在不改变生产流程的前提下降低操作功耗，有着大规模应用的潜力，适用于工业生产和产品化。
【附图说明】
图1是本发明实施例提供的一种相变存储器的擦写方法的流程示意图；
图2是本发明实施例采用的一种相变存储器沉积上电极材料后的结构示意图，图为剖面图；
图3是本发明实施例提供的一种相变存储器的衬底图的俯视图；
图4是本发明实施例提供的一种相变存储器沉积底电极后的俯视图；
图5是本发明实施例提供的一种相变存储器沉积绝缘层后的俯视图；
图6是本发明实施例提供的一种相变存储器进行小孔刻蚀后的俯视图；
图7是本发明实施例提供的一种相变存储器进行小孔刻蚀后的剖面图；
图8是本发明实施例提供的一种相变存储器沉积相变材料后的俯视图；
图9是本发明实施例提供的一种相变存储器沉积相变材料后的剖面图；
图10是本发明实施例提供的一种相变存储器沉积上电极材料后的俯视图；
图11是本发明实施例提供的一种不同预操作模式操作过程中的电压-电流图；
图12是本发明实施例提供的一种不同操作模式后进行擦操作中的电阻-电压图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。此外，下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
本发明的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同对象，而非用于描述特定顺序。
针对低功耗高密度存储的需求，本发明提出了一种相变存储器的擦写方法，重点应用于基于硫系相变材料特性的操作方式，并且在适用于三维堆叠的柱状结构相变存储器中实施了该操作方法。在实施例中所采用的柱状结构相变存储器包括刻蚀和薄膜沉积等工艺均与现代半导体制程有很好的工艺兼容性。由于本发明依靠操作方式而不是调整相变存储器结构，所以不需要对于生产流程作出任何变动从而降低成本，实现低功耗操作，具有很高的通用性以及实用价值。
硫系相变材料在加热过程中通常具有非晶态(组成物质的分子、原子 或离子不成空间规律分布周期性排列的固体，为各向同性的)和晶态(组成物质的分子、原子或离子具有规则的空间排布，为各向异性的)两种较为稳定的状态，通过迅速的加热和迅速的降温，其在熔化后可以迅速的变成非晶态，在两种状态下其电阻率有着较大的差异。除此之外，还有不少相变材料在稳定的晶态以及非晶态之间存在着亚稳定的中间态。
其中，相变存储器的结构包括柱状结构，横向桥状结构，侧壁接触的环状电极结构及蘑菇型结构等，具体采用何种结构本发明实施例不做唯一性限定。
其中，预操作以及后续循环操作的方式包括电学操作、热学操作及激光操作等，具体采用何种操作方式本发明实施例不做唯一性限定。
本发明实施例提供了一种柱状结构相变存储器的制备方法，包括以下步骤：
步骤一：在衬底上沉积制备底电极，电极厚度为1nm～100um，电极使用导电材料，包括金、铂、氮化钛等；
步骤二：在电极材料上沉积绝缘层，绝缘层具有绝缘的效果，材料包括SiO 2，SiN等；
步骤三：在隔离层中形成小孔结构，小孔孔径大小为0.1nm～100um；
步骤四：绝缘小孔中沉积硫系相变材料，厚度为0.1nm～100um；
步骤五：在相变材料上方沉积电极材料，电极使用导电材料，包括金、铂、氮化钛等。
其中，在步骤四中，相变材料为硫系化合物，主要包括元素周期表中IVA、VA及VIA族元素的组合，如Ge-Sb-Te材料、Ge-Te材料、Sb-Te材料、Bi-Te材料、Ge-Se材料、Bi-Se材料、Ge-Sb材料、Si-Sb-Te材料及In-Sb-Te材料等。
以Ge-Sb-Te材料为例，Ge-Sb-Te材料在稳定的六方晶向以及非晶态之间便存在着立方晶相这一亚稳定的中间态。在本发明实施例中，通过预操 作将相变存储器中的Ge-Sb-Te材料置于立方晶相这一中间态。然后，使用脉冲将相变存储器中的Ge-Sb-Te材料置于非晶态，从而实现擦操作。也可以使用脉冲将相变存储器中的Ge-Sb-Te材料重新置于中间态，从而实现写操作。在擦写操作中，相变存储器中的Ge-Sb-Te材料是在非晶态以及中间态之间发生可逆转变而不是非晶态以及晶态之间。通过这种操作方式，操作电流以及操作功耗得以降低。通过低电流写操作，使得Ge-Sb-Te材料进入能量态较高的中间态，随后对于该相变存储器施加电脉冲操作，使相变材料在中间态以及非晶态之间发生可逆转变，实现相变存储器的高低阻变化。在这一操作过程中，操作电流非常低，从而实现低功耗操作。
如图1所示是本发明实施例提供的一种相变存储器的擦写方法的流程示意图，包括：
对相变存储器进行预操作使相变存储器中的相变材料从初始的非晶态进入中间态，其中，中间态是介于非晶态以及稳定的晶态之间的亚稳态；
对相变存储器中的相变材料施加第一电脉冲，使相变材料进入非晶态，以实现擦操作；
对相变存储器中的相变材料施加第二电脉冲，使相变材料处于中间态，以实现写操作。
进一步地，上述擦操作与上述写操作之间能够通过相变材料在非晶态以及中间态之间的可逆转变进行循环操作，进而通过非晶态以及中间态之间的阻值差异进行数据存储。
进一步地，上述相变材料为硫系化合物。
进一步地，将相变存储器进行预操作的方式中，包括退火或施加脉冲作用，包括激光脉冲、电学脉冲、磁场脉冲和压力脉冲等。
本发明实施例还提供了一种适用于该操作模式的相变存储器，图2中所示为本发明实施例的一种柱状相变存储器剖面示意图，包括底电极，一层分隔隔离层，处在隔离层小孔中的相变材料，位于隔离层上方的电极材 料。结合附图，对操作模式的详细解释如下：
本发明实施例中的衬底为硅衬底，可便于与CMOS工艺兼容的制造，尤其其低电流特性适用于与二端选通管集成从而实现三维堆叠。
在沉积态下，该相变存储器的阻值约为50MΩ。本实施例的预操作是使用电脉冲实现。对该相变存储器施加步长增长的电流脉冲，每次从0A到峰值均有100步。随着我们施加的扫描电流的峰值增大，该相变存储器的电阻也会降低，该过程的电压-电流曲线如图11所示。在该过程中，所使用的仪器为B1500A半导体器件分析仪，操作模式为直流扫描。
通过这一系列的扫描脉冲进行写操作后，数个相变存储器被置于不同的低阻态，并且将这些通过不同扫描电流获得不同阻值的单元分别命名为“A”“B”“C”，其中，经过500μA扫描电流获得的阻值为1.5KΩ的单元为单元“A”，经过3mA扫描电流获得的阻值为200Ω的单元为单元“B”，经过5mA扫描电流获得的阻值为100Ω的单元为单元“C”。
对于这三个经历了不同写操作获得的单元，分别使用完全相同的电脉冲序列进行了擦操作。
擦操作过程中的电阻-电压曲线如图12所示，可以看到，对于阻值较高的“A”单元，到达高阻态所需要的电压反而更低，对于阻值最低的“C”单元，需要5V的电脉冲才能实现擦操作。对于单元“A”，其操作电流仅为500μA左右，这一巨大的操作电压/电流差异是由特定的低电流写操作实现的，这一低电流写操作可以使得Ge-Sb-Te材料进入立方晶相，从而使其能量态更高，因此，将其转变到熔融态从而实现擦操作的能量水平便更低一些。
随后，对于单元“A”“B”“C”分别施加幅值为500μA、3mA以及5mA的扫描电流可以使得单元“A”“B”“C”重新回到预操作后的初始态。
特别地，针对单元“A”，在500μA幅值的预操作后，可以对相变存 储器施加幅值为1V的电脉冲，使相变材料非晶化，从而实现擦操作；然后对相变存储单元施加500μA幅值的扫描电流，使相变材料重新进入中间态，从而实现写操作。在这一操作方案中，该相变存储器的操作电流从90MA/cm 2降低至1MA/cm 2，从而实现低功耗操作，并且极低的电流密度使其可以与选通管进行集成，使得三维集成变得可能。
其中，图2至图10为本发明实例实施提供的一种加工工艺过程以及操作过程：
步骤一，如图3和图4所示，利用直流磁控溅射的方式，在有着热生成氧化层的硅片100上生长一层10nm厚的Ti作为粘附层，避免铂从二氧化硅上脱落。随后溅射沉积100nm厚的铂作为底电极材料110。磁控溅射是物理气相沉积薄膜的一种常见工艺手段，通过在二极溅射中增加一个平行于靶表面的封闭磁场，借助于靶表面上形成的正交电磁场，把二次电子束缚在靶表面特定区域来增强电离效率，增加离子密度和能量，从而实现高速率溅射的过程，而对于直流磁控溅射而言，其通常用于导体材料。
步骤二，如图5所示，利用等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉积一层SiO2作为绝缘层120。使用PECVD是物理气相沉积薄膜的一种常见工艺手段，是借助微波或射频等使含有薄膜组成原子的气体电离，在局部形成等离子体，而等离子体化学活性很强，很容易发生反应，在基片上沉积出所期望的薄膜。为了使化学反应能在较低的温度下进行，利用了等离子体的活性来促进反应，因而被称为等离子体增强化学气相沉积PECVD。
步骤三，如图6和图7所示，利用电子束光刻(Electron beam lithography，EBL)在硅片上作出光刻图形，再利用反应增强等离子体刻蚀(Inductively Coupled Plasma，ICP)技术刻出小孔阵列130，其俯视图为图6所示，等离子体刻蚀技术是一种常见的干法刻蚀技术，原理是暴露在电子区域的气体形成等离子体，由此产生的电离气体和释放高能电子组成的气体，从而形 成了等离子或离子，电离气体原子通过电场加速时，会释放足够的力量与表面驱逐力紧紧粘合材料或蚀刻表面。
步骤四，如图8和图9所示，通过激光脉冲沉积(Pulsed Laser Deposition，PLD)沉积出150nm厚的Ge 2Sb 2Te 5材料作为相变材料层140。PLD是利用激光将靶材上的原子融化并且气化，最终气化的原子在基片表面成核形成薄膜。
步骤五，如图10和图2所示，通过磁控溅射陈基础150nm厚的TiW材料作为上电极材料150。
图11为本发明实施例的通过不同电流扫描写操作，其过程的电流-电压图。可以从图11中看到，通过不同幅值的扫描电流，可以获得不同阻值的单元样品。
图12为对于这些经过不同写操作后的单元，施加完全相同的脉冲序列，从而实现擦操作。阻值越低的单元(使用了更大的电流进行写操作)需要更大的电压才能实现擦操作。
本发明实施例中基于较为常见的柱状结构相变存储器，进行了操作方式上的改进，实现了极低的操作电流，从而降低操作功耗。特别地，改进操作方案后，操作电流密度低至1MA/cm 2，完全有潜力与现有的二端选通管进行集成，从而实现垂直方向上的堆叠进而提升存储密度。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (5)

  1. 一种相变存储器的擦写方法，其特征在于，包括：
    对相变存储器进行预操作使所述相变存储器中的相变材料从初始的非晶态进入中间态，其中，所述中间态是介于所述非晶态以及稳定的晶态之间的亚稳态；
    对所述相变存储器中的相变材料施加第一电脉冲，使所述相变材料进入非晶态，以实现擦操作；
    对所述相变存储器中的相变材料施加第二电脉冲，使所述相变材料处于中间态，以实现写操作。
  2. 根据权利要求1所述的方法，其特征在于，所述擦操作与所述写操作之间能够通过所述相变材料在所述非晶态以及所述中间态之间的可逆转变进行循环操作，进而通过所述非晶态以及所述中间态之间的阻值差异进行数据存储。
  3. 根据权利要求1所述的方法，其特征在于，所述预操作为将所述相变存储器退火或施加脉冲作用，其中，所述脉冲作用包括光学脉冲、电学脉冲、磁场脉冲和压力脉冲。
  4. 根据权利要求1所述的方法，其特征在于，所述中间态为能够稳定存在的亚稳态晶相。
  5. 根据权利要求1至3任意一项所述的方法，其特征在于，所述相变材料为硫系化合物。
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