WO2019234547A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2019234547A1
WO2019234547A1 PCT/IB2019/054361 IB2019054361W WO2019234547A1 WO 2019234547 A1 WO2019234547 A1 WO 2019234547A1 IB 2019054361 W IB2019054361 W IB 2019054361W WO 2019234547 A1 WO2019234547 A1 WO 2019234547A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulator
oxide
conductor
region
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2019/054361
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
竹内敏彦
山出直人
岡崎豊
手塚祐朗
山崎舜平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to US17/056,072 priority Critical patent/US11495691B2/en
Priority to JP2020523839A priority patent/JP7161529B2/ja
Publication of WO2019234547A1 publication Critical patent/WO2019234547A1/ja
Anticipated expiration legal-status Critical
Priority to US17/895,126 priority patent/US11967649B2/en
Priority to JP2022165216A priority patent/JP7371201B2/ja
Priority to US18/638,997 priority patent/US12453134B2/en
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756—Amorphous oxide semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment

Definitions

  • One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • One embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device.
  • a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may have a semiconductor device. .
  • one embodiment of the present invention is not limited to the above technical field.
  • One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • the CPU is a collection of semiconductor elements each having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes serving as connection terminals.
  • a semiconductor circuit such as an LSI, a CPU, or a memory is mounted on a circuit board, for example, a printed wiring board, and is used as one of various electronic device components.
  • a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has been attracting attention.
  • the transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device).
  • IC integrated circuit
  • image display device also simply referred to as a display device.
  • a silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.
  • a transistor using an oxide semiconductor has extremely small leakage current in a non-conduction state.
  • a low power consumption CPU and the like using a characteristic in which a transistor using an oxide semiconductor has low leakage current are disclosed (see Patent Document 1).
  • a memory device or the like that can hold stored data for a long time by using a characteristic that a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 2).
  • An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity.
  • An object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high data writing speed.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom.
  • An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device.
  • One embodiment of the present invention includes first and second conductors, first to third insulators, and first to third oxides, and is exposed from an upper surface of the first insulator.
  • the first conductor is disposed, the first oxide is disposed on the first insulator and the first conductor, and the first oxide reaches the first conductor.
  • One opening is provided, and a second oxide is disposed on the first oxide, the second oxide comprising the first region, the second region, and the first region and the second region. And the resistance of the first region and the second region is lower than the resistance of the third region, and the second region of the second oxide has the first region
  • a third oxide is disposed on the second oxide so as to be at least partially overlapped with the third region through the opening and in contact with the upper surface of the first conductor.
  • the second insulator The second conductor is disposed on the second insulator, covers the first region and the second region, and is in contact with the upper surface of the first insulator, and the third insulator is disposed.
  • Another embodiment of the present invention includes first and second conductors, first to third insulators, and first to third oxides, and the first insulator
  • a first oxide is disposed on the first oxide
  • a first conductor is disposed exposed from an upper surface of the first oxide
  • a second oxide is disposed on the first oxide.
  • the second oxide has a first region, a second region, and a third region located between the first region and the second region, and the resistance of the first region and the second region Is lower than the resistance of the third region, the second region of the second oxide is in contact with the upper surface of the first conductor, and at least a part of the second region and the third region is on the second oxide.
  • a third oxide is disposed so as to overlap, a second insulator is disposed on the third oxide, a second conductor is disposed on the second insulator, and the first oxide Covering the area and the second area, In contact with the upper surface of the first insulator, a third insulator is arranged, which is a conductor device.
  • Another embodiment of the present invention includes first and second conductors, first to third insulators, and first to third oxides, and the first insulator
  • a first conductor is disposed exposed from the upper surface of the first oxide, a first oxide is disposed on the first insulator and the first conductor, and a second oxide is disposed on the first oxide;
  • the first oxide and the second oxide have a first region, a second region, and a third region located between the first region and the second region , The resistance of the first region and the second region is lower than the resistance of the third region, the second region of the first oxide is in contact with the upper surface of the first conductor, and the second oxide
  • a third oxide is disposed on the third oxide so that at least part of the third oxide overlaps with the third region, and a second insulator is disposed on the third oxide.
  • a second conductor is placed Covering the first region and the second region, in contact with the upper surface of the first insulator, a third insulator is arranged, which is a conduct
  • the first region and the second region include one of phosphorus and boron.
  • the first region and the second region may have more oxygen vacancies than the third region.
  • the first oxide and the second oxide preferably include In, an element M (M is Al, Ga, Y, or Sn), and Zn.
  • a capacitor may be provided under the first conductor, and one electrode of the capacitor may be electrically connected to the first conductor.
  • a transistor formed over a silicon substrate may be provided under the capacitor.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device with high on-state current can be provided.
  • a semiconductor device having high frequency characteristics can be provided.
  • a semiconductor device with favorable reliability can be provided.
  • a highly productive semiconductor device can be provided.
  • a semiconductor device capable of holding data for a long time can be provided.
  • a semiconductor device with high data writing speed can be provided.
  • a semiconductor device with high design freedom can be provided.
  • a semiconductor device capable of suppressing power consumption can be provided.
  • a novel semiconductor device can be provided.
  • FIG. 1A to 1D are a top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 3A to 3D are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4D are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 5A to 5D are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 6A to 6D are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7D are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 8A to 8D are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 9A to 9D are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 10A to 10D are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 11A to 11D are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 12A to 12D are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 13A to 13D are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 14A to 14D are a top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • 15A to 15D are a top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • 16A to 16D are a top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • 17A to 17D are a top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 19 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 20 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 21 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 19 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 22 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 23 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • 24A and 24B are a block diagram and a perspective view illustrating a structural example of a memory device according to one embodiment of the present invention.
  • 25A to 25H are circuit diagrams illustrating structural examples of memory devices according to one embodiment of the present invention.
  • 26A and 26B are a schematic view and a perspective view of a semiconductor device according to one embodiment of the present invention.
  • 27A to 27E are schematic views of a memory device according to one embodiment of the present invention.
  • 28A to 28H illustrate an electronic device according to one embodiment of the present invention.
  • a top view also referred to as a “plan view”
  • a perspective view a perspective view, and the like
  • some components may be omitted in order to facilitate understanding of the invention.
  • description of some hidden lines may be omitted.
  • the ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.
  • the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • the functions of the source and drain may be switched when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.
  • the channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) and the channel width shown in the top view of the transistor (Hereinafter also referred to as “apparent channel width”) may be different.
  • the effective channel width when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible.
  • the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.
  • channel width when it is simply described as a channel width, it may indicate an apparent channel width.
  • channel width in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the impurity of a semiconductor means the thing other than the main component which comprises a semiconductor, for example.
  • an element having a concentration of less than 0.1 atomic% can be said to be an impurity.
  • the impurities are included, for example, DOS (Density of States) of the semiconductor may increase or crystallinity may decrease.
  • examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor.
  • water may also function as an impurity.
  • oxygen vacancies may be formed, for example, by mixing impurities.
  • impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
  • silicon oxynitride has a higher oxygen content than nitrogen.
  • silicon nitride oxide has a composition containing more nitrogen than oxygen.
  • the term “insulator” can be referred to as an insulating film or an insulating layer.
  • the term “conductor” can be restated as a conductive film or a conductive layer.
  • the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.
  • parallel means a state in which two straight lines are arranged at an angle of ⁇ 10 degrees to 10 degrees. Therefore, the case of -5 degrees or more and 5 degrees or less is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 degrees to 30 degrees.
  • Vertical means a state in which two straight lines are arranged at an angle of 80 degrees to 100 degrees. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • substantially vertical means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • the barrier film refers to a film having a function of suppressing permeation of impurities such as water and hydrogen and oxygen.
  • the barrier film When the barrier film has conductivity, the barrier film Sometimes called.
  • a metal oxide is a metal oxide in a broad sense.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OS).
  • oxide semiconductors also referred to as oxide semiconductors or simply OS.
  • the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing an OS FET or an OS transistor, it can be said to be a transistor including an oxide or an oxide semiconductor.
  • normally-off means that when a potential is not applied to the gate or a ground potential is applied to the gate, a current per channel width of 1 ⁇ m flowing through the transistor is 1 ⁇ 10 ⁇ 20 at room temperature. A or lower, 1 ⁇ 10 ⁇ 18 A or lower at 85 ° C., or 1 ⁇ 10 ⁇ 16 A or lower at 125 ° C.
  • ⁇ Configuration example of semiconductor device> 1A, 1B, 1C, and 1D are a top view and a cross-sectional view of the transistor 200 and the periphery of the transistor 200 according to one embodiment of the present invention.
  • FIG. 1A is a top view of a semiconductor device having a transistor 200.
  • FIG. 1B, 1C, and 1D are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 1A and also a cross-sectional view in the channel length direction of the transistor 200.
  • FIG. 1C is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG. 1A and is a cross-sectional view in the channel width direction of the transistor 200.
  • 1D is a cross-sectional view taken along dashed-dotted line A5-A6 in FIG. 1A and is a cross-sectional view in the channel width direction of the source region or the drain region of the transistor 200.
  • the semiconductor device of one embodiment of the present invention includes an insulator 214 over a substrate (not shown), the transistor 200 over the insulator 214, the insulator 280 over the transistor 200, and the insulator 282 over the insulator 280. And an insulator 274 over the insulator 282 and an insulator 281 over the insulator 274.
  • the insulator 214, the insulator 280, the insulator 282, the insulator 274, and the insulator 281 function as an interlayer film.
  • a conductor 247 is provided so as to be embedded under the transistor 200.
  • the conductor 247 is electrically connected to the transistor 200 and functions as a plug.
  • a conductor 240 that is electrically connected to the transistor 200 and functions as a plug is provided. Note that an insulator 241 is provided in contact with a side surface of the conductor 240 functioning as a plug.
  • the insulator 256, the insulator 258, the insulator 280, the insulator 282, the insulator 274, and the insulator 241 are provided in contact with the inner wall of the opening of the insulator 281 and are in contact with the side surfaces of the conductor 240. 1 conductor is provided, and the second conductor of the conductor 240 is further provided inside.
  • the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be approximately the same.
  • the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When a structure has a laminated structure, an ordinal number may be given in order of formation to distinguish the structures.
  • the transistor 200 includes an insulator 216 over an insulator 214, a conductor 205 (a conductor 205 a and a conductor 205 b) arranged to be embedded in the insulator 216, and an insulator 216. And an insulator 222 on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide on the oxide 230b.
  • the conductor 260 has the conductor 260a and the conductor 260b, and the conductor 260a is arrange
  • the upper surface of the conductor 260 is disposed to substantially coincide with the upper surface of the oxide 230 c, the upper surface of the insulator 250, and the upper surface of the insulator 280.
  • the insulator 282 is in contact with the upper surfaces of the conductor 260, the oxide 230c, the insulator 250, and the insulator 280.
  • the oxide 230b has a region 249a and a region 249b that are spaced apart from each other.
  • the resistance of the region 249a and the region 249b is lower than the resistance of the region located between the region 249a and the region 249b.
  • the region 249a functions as one of a source region and a drain region of the transistor 200
  • a region 249b functions as the other of the source region and the drain region of the transistor 200.
  • the oxide 230c is disposed so that at least a part thereof overlaps with a region between the region 249a and the region 249b.
  • the region 249a and the region 249b may be collectively referred to as a region 249.
  • the conductor 247 is disposed so as to be exposed from the upper surface of the insulator 224.
  • the conductor 247 may be disposed so as to be embedded in openings formed in the insulator 214, the insulator 216, the insulator 222, and the insulator 224. At least part of the upper surface of the conductor 247 is exposed from the insulator 224, and it is preferable that the upper surface of the conductor 247 and the upper surface of the insulator 224 substantially coincide with each other.
  • the conductor 247 electrically connects a circuit element such as a switch, a transistor, a capacitor, an inductor, a resistor, and a diode, a wiring, an electrode, or a terminal provided below the insulator 214, and the transistor 200. Functions as a plug for connection.
  • the conductor 247 may be configured to be electrically connected to one of the electrodes of the capacitor provided below the insulator 214.
  • the conductor 247 may be electrically connected to the gate of a transistor provided below the insulator 214.
  • An opening 248 exposing at least a part of the conductor 247 is formed in the oxide 230a.
  • the oxide 230b is in contact with at least part of the upper surface of the conductor 247 through the opening 248 in the region 249b. In this manner, by connecting the region 249b of the oxide 230b and the conductor 247, electric resistance between the source or drain of the transistor 200 and the conductor 247 can be reduced.
  • the frequency characteristics of the semiconductor device including the transistor 200 can be improved and the electrical characteristics can be improved.
  • At least part of a circuit element such as a switch, a transistor, a capacitor, an inductor, a resistor, or a diode, a wiring, an electrode, or a terminal that is electrically connected to the conductor 247 overlaps with the oxide 230. It is preferable to do. Thus, the area occupied by the transistor 200, the circuit element, the wiring, the electrode, or the terminal in a top view can be reduced, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated. .
  • the conductor 247 is provided below the region 249b; however, the semiconductor device described in this embodiment is not limited thereto.
  • the conductor 247 may be provided below the region 249a, or the conductor 247 may be provided below both the region 249a and the region 249b.
  • the insulator 222, the insulator 258, and the insulator 282 preferably have a function of suppressing diffusion of hydrogen (for example, at least one of a hydrogen atom and a hydrogen molecule).
  • the insulator 222, the insulator 258, and the insulator 282 preferably have a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).
  • the insulator 222, the insulator 258, and the insulator 282 preferably have lower permeability of one or both of oxygen and hydrogen than the insulator 224, respectively.
  • the insulator 222, the insulator 258, and the insulator 282 preferably each have lower permeability of one or both of oxygen and hydrogen than the insulator 250.
  • the insulator 222, the insulator 258, and the insulator 282 preferably have lower permeability of one or both of oxygen and hydrogen than the insulator 280, respectively.
  • the oxide 230 includes the oxide 230a over the insulator 224, the oxide 230b over the oxide 230a, and the oxide 230c disposed over the oxide 230b and in contact with at least part of the top surface of the oxide 230b. It is preferable to have.
  • the oxide 230 has a structure in which a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers is provided. Also good.
  • each of the oxide 230a, the oxide 230b, and the oxide 230c may have a stacked structure of two or more layers.
  • the conductor 260 is illustrated as a two-layer structure, but the present invention is not limited to this.
  • the conductor 260 may have a single layer structure or a stacked structure of three or more layers.
  • the conductor 260 functions as a gate electrode of the transistor, and the region 249a and the region 249b function as a source region or a drain region, respectively.
  • a conductor 260 functioning as a gate electrode is formed in a self-aligning manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the region 249a and the region 249b without being aligned.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is used for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including a channel formation region. It is preferable to use it.
  • the transistor 200 using an oxide semiconductor in a channel formation region has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided.
  • An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200 included in a highly integrated semiconductor device.
  • the oxide 230 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium) It is preferable to use a metal oxide such as one or more selected from neodymium, hafnium, tantalum, tungsten, or magnesium.
  • the element M may be aluminum, gallium, yttrium, or tin.
  • an In—Ga oxide or an In—Zn oxide may be used as the oxide 230.
  • the oxide 230 may be added with an element that forms oxygen vacancies or an element that combines with oxygen vacancies, whereby the carrier density may increase and the resistance may be lowered.
  • Typical examples of such an element include boron and phosphorus.
  • hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas, and the like can be used.
  • rare gases include helium, neon, argon, krypton, and xenon.
  • the oxide 230 includes aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, and strontium. Any one or more metal elements selected from metal elements such as lanthanum may be added. Among the elements described above, boron and phosphorus are preferable as the added element. For the addition of boron and phosphorus, equipment of an amorphous silicon or low-temperature polysilicon production line can be used, so that capital investment can be suppressed. The concentration of the element may be measured by using secondary ion mass spectrometry (SIMS) or the like.
  • SIMS secondary ion mass spectrometry
  • an element to be added to the oxide 230 an element that easily forms an oxide is preferably used.
  • Typical examples of such elements include boron, phosphorus, aluminum, and magnesium.
  • the element added to the oxide 230 can take oxygen in the oxide 230 to form an oxide. As a result, many oxygen vacancies are generated in the oxide 230. The oxygen deficiency and hydrogen in the oxide 230 are combined with each other, so that carriers are generated and an extremely low resistance region is obtained.
  • the element added to the oxide 230 exists in the oxide 230 in a stable oxide state, the element is desorbed from the oxide 230 even if a process requiring a high temperature is performed in a subsequent process. Hateful. In other words, by using an element that easily forms an oxide as an element to be added to the oxide 230, a region in the oxide 230 that is difficult to increase in resistance even after a high-temperature process can be formed.
  • the oxide 230 includes a region 234 functioning as a channel formation region of the transistor 200 and a region 249 (region 249a and region 249b) functioning as a source region or a drain region.
  • 2 illustrates an example in which the oxide 230c has a stacked structure including the oxide 230c1 and the oxide 230c2, but this embodiment is not limited thereto.
  • the oxide 230c may have a single-layer structure or a stacked structure including three or more layers.
  • the region 249 is a region formed by adding the above element to the oxide 230b. As shown in FIGS. 1B and 2, the region 249a and the region 249b are formed to face each other with the conductor 260 interposed therebetween, and preferably have an upper surface in contact with the oxide 230c. In top view, it is preferable that the side surfaces of the regions 249 a and 249 b on the conductor 260 side coincide with the side surfaces of the conductor 260, or at least part of the regions 249 a and 249 b overlap with the conductor 260.
  • the concentration of the element in the region 249 is preferably higher than that in the region where the region 249 of the oxide 230 is not formed.
  • the amount of oxygen vacancies included in the region 249 is preferably higher than the amount of oxygen vacancies in the region where the region 249 of the oxide 230 is not formed. Accordingly, the region 249 has a higher carrier density and lower resistance than a region where the region 249 of the oxide 230 is not formed.
  • a region which overlaps with the conductor 260 and is sandwiched between the region 249a and the region 249b is a region 234.
  • the region 249 has a higher carrier density and lower resistance than the region 234.
  • the region 234 functions as a channel formation region of the transistor 200, and the region 249 functions as a source region or a drain region.
  • the conductor 240 and the conductor 247 functioning as plugs can be formed in the region 249 without providing a source electrode and a drain electrode formed of metal. Can be connected.
  • a source electrode and a drain electrode formed using a metal are provided in contact with the oxide 230, the source electrode and the drain electrode formed using a metal are oxidized when heat treatment is performed at a high temperature in a manufacturing process or a later process of the transistor 200.
  • the on-state current, S value, and frequency characteristics of the transistor 200 may be deteriorated.
  • a semiconductor device that exhibits favorable on-state current, S value, and frequency characteristics can be provided even when high-temperature heat treatment is performed in a manufacturing process or a post-process of the transistor 200.
  • a process in which high temperature is 450 to 800 ° C., typically 600 to 750 ° C. can be performed.
  • the conductor 260 can be disposed between the regions 249a and 249b in a self-aligning manner. Therefore, a semiconductor device having favorable electrical characteristics can be manufactured with high yield.
  • the region 249 is preferably formed by adding the above element as a dopant to the oxide 230 through the insulator 256. At this time, the dopant may be added not only to the oxide 230 but also to the insulator 256.
  • the dopant added to the region 249 of the oxide 230 is bonded to oxygen in the oxide 230, oxygen vacancies are generated in the oxide 230 in the region 249.
  • hydrogen contained in the region 234 of the oxide 230 diffuses into the region 249 and is captured by the oxygen vacancies. Therefore, the region 234 after hydrogen diffusion is considered to have a higher resistance than the resistance value of the region 234 immediately after the oxide 230 is formed.
  • the region 249 of the oxide 230 is considered to have a lower resistance than the resistance value after film formation because the oxygen vacancies capture the hydrogen.
  • the oxide 230 has high resistance in the region 249, and serves as a source region and a drain region. There is concern that it will not function well.
  • oxygen contained in the insulator 256 is captured by the dopant and fixed. Accordingly, release of oxygen from the insulator 256 is suppressed, and the resistance value of the oxide 230 in the region 249 can be kept lower than the resistance value after film formation.
  • the region 234 can maintain a high resistance value and function as a channel formation region, and the region 249 can maintain a low resistance value and function as a source region or a drain region. It is considered possible.
  • the concentrations of metal elements detected in the region 249 and impurity elements such as hydrogen and nitrogen do not need to be uniform in the region 249.
  • the concentration of a metal element detected in the region 249 and an impurity element such as hydrogen and nitrogen is highest in the vicinity of the interface between the oxide 230b and the insulator 256 or the oxide 230c, and approaches the oxide 230a.
  • the concentration may be lowered according to the above.
  • the resistance of the region 249b is preferably low so that a good contact with the conductor 247 is formed.
  • the region 249 is formed only in the oxide 230b; however, this embodiment is not limited to this.
  • the region 249 may be formed not only in the oxide 230b but also in the oxide 230a.
  • concentrations of metal elements detected in each region and impurity elements such as hydrogen and nitrogen are not limited to stepwise changes in each region, but also continuously change in each region (also referred to as gradation). May be. That is, the closer to the channel formation region, the lower the concentration of the metal element and impurity elements such as hydrogen and nitrogen.
  • a transistor including an oxide semiconductor if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, electric characteristics are likely to fluctuate and reliability may be deteriorated.
  • an oxygen vacancy is included in a region where a channel is formed in an oxide semiconductor, the transistor is likely to be normally on. Therefore, oxygen vacancies in the region 234 where a channel is formed are preferably reduced as much as possible.
  • the insulator 250 adjacent to the oxide 230 preferably contains more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition. Oxygen included in the insulator 250 can diffuse into the oxide 230, reduce oxygen vacancies in the oxide 230, and suppress normally-on of the transistor.
  • oxygen vacancies in the region 234 of the oxide 230 can be reduced by diffusion of oxygen included in the insulator 250 into the region 234 of the oxide 230. Further, oxygen vacancies in the region 234 of the oxide 230 can be reduced by diffusion of oxygen contained in the insulator 280 into the region 234 of the oxide 230 through the oxide 230c.
  • the oxide 230 c has a stacked structure including the oxide 230 c 1 and the oxide 230 c 2, and oxygen contained in the insulator 280 is supplied to the region 234 of the oxide 230 through the oxide 230 c 1. It may be configured to diffuse.
  • oxide 230c2 By using a material that does not easily transmit oxygen as the oxide 230c2, diffusion of oxygen in the insulator 280 to the insulator 250 or the conductor 260 can be suppressed, and the oxygen in the insulator 280 can be reduced to oxide. 230 can be efficiently supplied to the region 234.
  • the insulator 256 is preferably provided so as to cover the region 249a and the region 249b of the oxide 230b and the side surface of the oxide 230a and be in contact with the top surface of the insulator 224.
  • An insulator 258 is preferably disposed between the two.
  • the insulator 280 is separated from the insulator 256, the insulator 224, the oxide 230a, and the oxide 230b by the insulator 258. In this manner, by providing the insulator 258, oxygen contained in the insulator 280 can be suppressed from being injected from the top surfaces and side surfaces of the oxide 230a and the oxide 230b.
  • the transistor 200 which is one embodiment of the present invention has a structure in which the insulator 282 and the insulator 250 are in direct contact with each other, as illustrated in FIGS.
  • oxygen contained in the insulator 280 is hardly absorbed by the conductor 260. Therefore, oxygen contained in the insulator 280 can be efficiently injected into the oxide 230a and the oxide 230b through the oxide 230c, so that oxygen vacancies in the oxide 230a and the oxide 230b are reduced.
  • electrical characteristics and reliability of the transistor 200 can be improved. Further, since impurities such as hydrogen contained in the insulator 280 can be prevented from entering the insulator 250, adverse effects on electrical characteristics and reliability of the transistor 200 can be suppressed.
  • silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide can be used.
  • silicon nitride is particularly preferable.
  • the silicon nitride can suitably block impurities (for example, hydrogen, water, etc.) that can enter from the outside.
  • FIG. 1D is a cross-sectional view taken along the dashed-dotted line A5-A6 in FIG. 1A, and is also a cross-sectional view in the channel width direction of the source region or drain region of the transistor 200.
  • the top surface of the region 249b and the side surface of the region 249b are covered with the insulator 256 and the insulator 258, the side surface of the region 249b and the top surface direction of the region 249b are viewed. Diffusion of impurities such as hydrogen and water and oxygen into the region 249b can be suppressed.
  • the region 249a has the same effect.
  • diffusion of impurities such as hydrogen and water into the oxide 230a and the oxide 230b from the side surface of the oxide 230a and the side surface direction of the oxide 230b can be suppressed.
  • the bottom surface of the conductor 260 in a region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 with respect to the bottom surface of the insulator 224 is the oxide 230b. It is preferable that it is arrange
  • the difference between the bottom surface of the conductor 260 and the bottom surface of the oxide 230b in a region where the oxide 230b and the conductor 260 do not overlap with each other is 0 nm to 100 nm, preferably 3 nm to 50 nm, more preferably Is from 5 nm to 20 nm.
  • the conductor 260 functioning as a gate electrode has a structure in which the side surface and the upper surface of the oxide 230b in the channel formation region are covered with the oxide 230c and the insulator 250, and the electric field of the conductor 260 is channeled. This easily acts on the entire oxide 230b in the formation region. Thus, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved.
  • a miniaturized or highly integrated semiconductor device can be provided.
  • a semiconductor device including a transistor with high on-state current can be provided.
  • a semiconductor device including a transistor having high frequency characteristics can be provided.
  • a semiconductor device including a transistor with low off-state current can be provided.
  • the conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260.
  • the conductor 205 is preferably provided so as to be embedded in the insulator 214 and the insulator 216.
  • the conductor 260 may function as a first gate (also referred to as a top gate) electrode.
  • the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode.
  • Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without being interlocked.
  • Vth of the transistor 200 can be made higher than 0 V and off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when a negative potential is not applied.
  • the conductor 205 is preferably provided larger than the size of a region that does not overlap with the regions 249a and 249b of the oxide 230.
  • the conductor 205 is preferably extended also in a region outside the end portion intersecting with the channel width direction of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other with an insulator outside the side surface in the channel width direction of the oxide 230.
  • charge-up local charging may be reduced in the treatment using plasma in the manufacturing process after the conductor 205 is formed. Note that one embodiment of the present invention is not limited to this.
  • the conductor 205 may overlap with at least the oxide 230 located between the region 249a and the region 249b.
  • the channel formation region is electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode.
  • a transistor structure that electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • the first conductive layer of the conductor 205 is preferably a conductor that suppresses permeation of impurities such as water or hydrogen and oxygen.
  • a conductor that suppresses permeation of impurities such as water or hydrogen and oxygen.
  • titanium, titanium nitride, tantalum, or tantalum nitride can be used in a single layer or a stacked layer.
  • a conductor having good adhesion to the first conductive layer and the third conductive layer may be used.
  • the third conductive layer of the conductor 205 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Note that although the conductor 205 is illustrated as having three layers, it may have a single-layer structure, a two-layer structure, or a multilayer structure of four or more layers.
  • the insulator 214, the insulator 258, the insulator 282, and the insulator 281 function as barrier insulating films that prevent impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. Is preferred. Therefore, the insulator 214, the insulator 258, the insulator 282, and the insulator 281 include a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2, and the like), It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (it is difficult for the impurities to pass through). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit).
  • oxygen for example, at least one of oxygen atoms and oxygen molecules
  • silicon nitride or the like is preferably used for the insulator 214, the insulator 258, the insulator 282, and the insulator 281.
  • diffusion of impurities such as water or hydrogen from the substrate side to the transistor 200 side with respect to the insulator 214 can be suppressed.
  • diffusion of oxygen contained in the insulator 224 and the like to the substrate side with respect to the insulator 214 can be suppressed.
  • diffusion of impurities such as water or hydrogen from the insulator 280 or the like disposed above the insulator 258 to the transistor 200 side can be suppressed.
  • the resistivity of the insulator 214, the insulator 258, the insulator 282, and the insulator 281 is preferably 1 ⁇ 10 10 ⁇ cm to 1 ⁇ 10 15 ⁇ cm.
  • the insulator 214 may have a laminated structure.
  • a stacked structure of an aluminum oxide film and a silicon nitride film is preferably used for the insulator 214.
  • Oxygen can be supplied below the insulator 214 by the aluminum oxide film.
  • diffusion of impurities such as hydrogen and water which are diffused from the substrate side to the transistor 200 side can be suppressed by the silicon nitride film.
  • the insulator 216, the insulator 280, and the insulator 274 preferably have a lower dielectric constant than the insulator 214.
  • a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon, and nitrogen were added. Silicon oxide, silicon oxide having holes, or the like may be used as appropriate.
  • the insulator 222 and the insulator 224 have a function as a gate insulator.
  • the insulator 224 in contact with the oxide 230 desorbs oxygen by heating.
  • oxygen released by heating may be referred to as excess oxygen.
  • the insulator 224 may be formed using silicon oxide, silicon oxynitride, or the like as appropriate.
  • an oxide material from which part of oxygen is released by heating is preferably used as the insulator 224.
  • the oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen molecules is 1.0 ⁇ 10 18 molecules / cm 3 or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis.
  • the oxide film has a thickness of 0.0 ⁇ 10 19 molecules / cm 3 or more, more preferably 2.0 ⁇ 10 19 molecules / cm 3 or more, or 3.0 ⁇ 10 20 molecules / cm 3 or more.
  • the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.
  • the insulator 222 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side.
  • the insulator 222 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen is difficult to permeate).
  • the insulator 222 preferably has lower oxygen permeability than the insulator 224.
  • the insulator 222 has a function of suppressing diffusion of oxygen and impurities, which is preferable because oxygen included in the oxide 230 can be reduced from diffusing below the insulator 222.
  • the conductor 205 can be prevented from reacting with the oxygen included in the insulator 224 and the oxide 230.
  • an insulator containing one or both oxides of aluminum and hafnium which are insulating materials may be used.
  • the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • the insulator 222 suppresses release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230. Acts as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 222 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr) TiO 3 (BST).
  • An insulator including a so-called high-k material may be used as a single layer or a stacked layer. As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical film thickness.
  • the insulator 222 and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient.
  • the conductor 247 also includes a first conductive layer, a second conductive layer disposed inside the first conductive layer, and a third conductive layer disposed inside the second conductive layer. And a conductive layer.
  • the first conductive layer of the conductor 247 is preferably a conductor that suppresses permeation of impurities such as water or hydrogen and oxygen.
  • impurities such as water or hydrogen and oxygen.
  • titanium, titanium nitride, tantalum, or tantalum nitride can be used.
  • the second conductive layer of the conductor 247 may be a conductor that has good adhesion to the first conductive layer and the third conductive layer.
  • a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. Note that although the conductor 247 is illustrated with three layers, a single-layer structure or a two-layer structure may be used, or a multilayer structure with four or more layers may be used.
  • an insulator that suppresses diffusion of impurities such as hydrogen and water and oxygen similar to the insulator 241 may be provided on the side surface of the conductor 247.
  • the oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b.
  • the oxide 230c is arranged so that at least a part thereof overlaps with a region between the region 249a and the region 249b.
  • the oxide 230 preferably has a stacked structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent element is larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 230b. It is preferable. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. As the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.
  • the oxide 230b preferably has crystallinity.
  • a CAAC-OS c-axis aligned crystalline semiconductor
  • An oxide having crystallinity such as a CAAC-OS has a dense structure with few impurities and defects (such as oxygen vacancies) and high crystallinity. Accordingly, extraction of oxygen from the oxide 230b due to the source electrode or the drain electrode can be suppressed. Accordingly, extraction of oxygen from the oxide 230b can be reduced even when heat treatment is performed, so that the transistor 200 is stable at a high temperature in the manufacturing process (which may be referred to as a thermal budget).
  • the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c is higher than the energy at the lower end of the conduction band of the oxide 230b.
  • the electron affinity of the oxide 230a and the oxide 230c is preferably smaller than the electron affinity of the oxide 230b.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c is continuously changed or continuously joined.
  • the defect state density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c is preferably low.
  • the oxide 230c has a stacked structure
  • In: Ga: Zn 4: 2: 3 [atomic ratio] as the oxide 230c1
  • In: Ga: Zn 1 as the oxide 230c2.
  • a stack structure of Ga: Zn 2: 5 [atomic ratio] as the oxide 230c2.
  • the main path of the carrier is the oxide 230b.
  • the oxide 230a and the oxide 230c have the above structure, the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor 200 can obtain a high on-state current and a high frequency characteristic.
  • the oxide 230c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the oxide 230b and the oxide 230c, the oxide 230c has a constituent element on the insulator 250 side. It is expected to suppress diffusion.
  • the oxide 230c has a stacked structure, and an oxide that does not contain In or has a reduced In concentration is positioned above the stacked structure, so that In that can be diffused to the insulator 250 side is suppressed. can do. Since the insulator 250 functions as a gate insulator, when In is diffused, transistor characteristics are deteriorated. Therefore, with the stacked structure of the oxide 230c, a highly reliable semiconductor device can be provided.
  • the main path of carriers may be the interface between the oxide 230b and the oxide 230c1 and the vicinity thereof.
  • oxygen contained in the insulator 280 can be supplied to the channel formation region of the transistor 200 through the oxide 230c1.
  • oxygen contained in the insulator 280 can be prevented from being transmitted through the oxide 230c2 and absorbed by the insulator 250 or the conductor 260, so that oxygen can be efficiently contained in the channel formation region. Can be supplied.
  • the oxide 230 includes a region 249 and a region 234. Note that when the transistor 200 is turned on, one of the region 249a and the region 249b functions as a source region and the other functions as a drain region. On the other hand, at least part of the region 234 functions as a region where a channel is formed.
  • a metal oxide that functions as an oxide semiconductor is preferably used.
  • a material having an energy gap of 2 eV or more, preferably 2.5 eV or more is preferable to use. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a large energy gap. By using such a transistor, a semiconductor device with low power consumption can be provided.
  • the electron affinity or the energy level Ec at the bottom of the conduction band can be obtained from the ionization potential Ip, which is the difference between the vacuum level and the energy Ev at the top of the valence band, and the energy gap Eg.
  • the ionization potential Ip can be measured using, for example, an ultraviolet photoelectron spectroscopy (UPS) apparatus.
  • the energy gap Eg can be measured using, for example, a spectroscopic ellipsometer.
  • the insulator 250 functions as a gate insulator.
  • the insulator 250 is preferably provided in contact with the upper surface of the oxide 230c.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having a hole is used. be able to.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulator 250 may be formed using an insulator from which oxygen is released by heating.
  • the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced.
  • the thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.
  • a metal oxide may be provided between the insulator 250 and the conductor 260.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260.
  • the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Further, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.
  • the metal oxide may function as a part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide is preferably a metal oxide that is a high-k material with a high relative dielectric constant.
  • the gate insulator has a stacked structure of the insulator 250 and the metal oxide, a stacked structure having high relative dielectric constant and stability against heat can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of an insulator that functions as a gate insulator.
  • EOT equivalent oxide thickness
  • a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. it can.
  • the metal oxide may function as part of the gate electrode.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate electrode it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate electrode.
  • the above-described conductive material containing a metal element and nitrogen may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • the conductor 260 is shown as a two-layer structure in FIG. 1, but may have a single-layer structure or a laminated structure of three or more layers.
  • the conductor 260a has a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 ), a copper atom, and the like. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).
  • the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to prevent the conductivity of the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from being lowered.
  • tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used as the conductive material having a function of suppressing oxygen diffusion.
  • the conductor 260b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum.
  • a conductor having high conductivity is preferably used.
  • a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 260b may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the conductive material.
  • the insulator 256 preferably has a function as a protective film when the region 249 is formed.
  • the surface of the oxide 230 is not directly exposed to ions or plasma by providing the insulator 256 as a protective film. This is preferable because damage to the object 230 can be suppressed.
  • the damage of the oxide 230 refers to the formation of excessive oxygen vacancies in the oxide 230, excessive decrease in crystallinity of the oxide 230, or the like.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or oxide having a hole Silicon or the like can be used.
  • the insulator 256 a material that can be used for the oxide 230a may be used.
  • the insulator 256 may function as a barrier insulating film that suppresses entry of impurities such as water or hydrogen into the transistor 200 from the insulator 280 side, similarly to the insulator 214 and the like.
  • the insulator 256 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 256 may have a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).
  • the insulator 256 may have lower oxygen permeability than the insulator 280 or the insulator 224.
  • an insulator including an oxide of one or both of aluminum and hafnium may be formed.
  • the insulator including one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • the insulator 256 may have a laminated structure.
  • the second insulator may be formed using the ALD method over the first insulator formed using the sputtering method.
  • the first insulator and the second insulator may be made of the same material selected from the materials described above, or may be made of different materials.
  • aluminum oxide formed by a sputtering method may be used as the first insulator
  • aluminum oxide formed by an ALD method may be used as the second insulator.
  • a film formed by the ALD method has high coverage, and a film having high uniformity can be formed even on a step portion formed of a structure such as the oxide 230.
  • the insulator 224 and the oxide 230 are covered with the insulator 256 having a barrier property against hydrogen, so that the insulator 280 is separated from the insulator 224 and the oxide 230. Accordingly, intrusion of impurities such as hydrogen from the outside of the transistor 200 can be suppressed, so that favorable electrical characteristics and reliability can be given to the transistor 200.
  • the insulator 258 preferably functions as a barrier insulating film which prevents impurities such as water or hydrogen from entering the transistor 200 from the insulator 280 side, like the insulator 214 and the like.
  • the insulator 258 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 258 is preferably disposed so as to be in contact with the top surface of the insulator 256 and the side surface of the oxide 230c. With such a structure, hydrogen contained in the insulator 280 can be prevented from entering the oxide 230 and the insulator 224.
  • the insulator 256, the insulator 224, the insulator 250, and the oxide 230 are covered with the insulator 258 having a barrier property against hydrogen, so that the insulator 280 is formed of the insulator 256 and the insulator 224. , Oxide 230, and insulator 250. Accordingly, intrusion of impurities such as hydrogen from the outside of the transistor 200 can be suppressed, so that favorable electrical characteristics and reliability can be given to the transistor 200.
  • the insulator 258 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (the above-mentioned oxygen hardly transmits).
  • the insulator 258 preferably has lower oxygen permeability than the insulator 224. Since the insulator 258 has a function of suppressing oxygen diffusion, oxygen can be prevented from being directly injected from the insulator 280 into the oxide 230a and the oxide 230b.
  • a barrier insulating film that can be used for the insulator 256 may be used. Note that in the case where the insulator 256 has a sufficient barrier property against hydrogen, the insulator 258 is not necessarily provided with a barrier insulating film and may be configured without the insulator 258.
  • the insulator 280 is formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having holes. It is preferable to have. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having a hole is preferable because a region containing oxygen that is released by heating can be easily formed.
  • the insulator 280 In order to supply oxygen contained in the insulator 280 to the oxide 230b through the oxide 230c or the oxide 230c1, the insulator 280 preferably contains more oxygen, for example, stoichiometry. Preferably it contains more oxygen than the ratio. In order to increase the concentration of oxygen contained in the insulator 280, the deposition gas used for forming the insulator 280 preferably contains oxygen.
  • the concentration of impurities such as water or hydrogen in the insulator 280 is reduced.
  • a silicon oxide formed by a sputtering method using a target containing silicon or silicon oxide and a gas containing argon or oxygen is formed by a CVD method using a deposition gas containing hydrogen. Since the hydrogen concentration in the film is low as compared with silicon oxynitride, the insulator 280 is preferable.
  • the insulator 280 may be formed using a CVD method in consideration of a deposition rate when forming the insulator 280 and coverage with respect to a step portion by the oxide 230a, the oxide 230b, the opening 248, and the like. Good.
  • the insulator 280 may have a stacked structure of two or more layers, and silicon oxide formed by a sputtering method as a first layer is formed by a CVD method as a second layer. A stacked body including silicon oxynitride may be used. Further, the upper surface of the insulator 280 may be planarized.
  • the insulator 282 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the insulator 280 from above.
  • an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used.
  • an insulator 274 that functions as an interlayer film is preferably provided over the insulator 282.
  • the insulator 274 preferably has a reduced concentration of impurities such as water or hydrogen in the film.
  • the conductor 240 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Further, the conductor 240 may have a stacked structure.
  • the conductor 240 has a stacked structure
  • a conductive material having a function of suppressing permeation of impurities such as water or hydrogen is preferably used as the conductor in contact with the insulator 241.
  • tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used.
  • the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer.
  • oxygen added to the insulator 280 can be prevented from being absorbed by the conductor 240.
  • impurities such as water or hydrogen from an upper layer than the insulator 281 can be prevented from entering the oxide 230 through the conductor 240.
  • an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used. Since the insulator 241 is provided in contact with the insulator 281, the insulator 274, the insulator 282, the insulator 280, the insulator 258, and the insulator 256, impurities such as water or hydrogen can be transferred from the insulator 280 and the like. Mixing into the oxide 230 through the body 240 can be suppressed. Further, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240.
  • a conductor functioning as a wiring may be disposed in contact with the upper surface of the conductor 240.
  • a conductive material mainly containing tungsten, copper, or aluminum is preferably used.
  • the conductor may have a stacked structure, for example, a stack of titanium, titanium nitride, and the conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • an insulator substrate As a substrate over which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • a semiconductor substrate having an insulator region inside the above-described semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate in which a conductor or a semiconductor is provided on an insulator substrate a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like.
  • a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
  • the insulator examples include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.
  • the transistor when the transistor is miniaturized and highly integrated, problems such as leakage current may occur due to thinning of the gate insulator.
  • a high-k material for the insulator functioning as a gate insulator the voltage during transistor operation can be reduced while maintaining the physical film thickness.
  • a parasitic capacitance generated between wirings can be reduced by using a material having a low relative dielectric constant for the insulator functioning as an interlayer film. Therefore, the material may be selected according to the function of the insulator.
  • Insulators having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and hafnium.
  • an oxynitride having silicon, or a nitride having silicon and hafnium are examples of gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and hafnium.
  • Insulators having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and voids There is silicon oxide or resin.
  • a transistor including an oxide semiconductor can be stabilized in electrical characteristics of the transistor by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.
  • the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium.
  • An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, Alternatively, a metal oxide such as tantalum oxide, or a metal nitride such as aluminum nitride, aluminum nitride titanium, titanium nitride, silicon nitride oxide, or silicon nitride can be used.
  • the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating.
  • the oxide 230 By using a structure in which silicon oxide or silicon oxynitride including a region containing oxygen which is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.
  • Conductors aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum It is preferable to use a metal element selected from the above, an alloy including the above-described metal element as a component, an alloy combining the above-described metal elements, or the like.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used. It is preferable. Also, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize.
  • a conductive material or a material that maintains conductivity even when oxygen is absorbed is preferable.
  • a semiconductor with high electrical conductivity for example, silicide such as nickel silicide, which is typified by polycrystalline silicon containing an impurity element such as phosphorus, may be used.
  • a plurality of conductive layers formed of the above materials may be stacked.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed.
  • a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.
  • the conductor functioning as the gate electrode has a stacked structure in which the above-described material containing a metal element and the conductive material containing oxygen are combined. Is preferred.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate electrode it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate electrode.
  • the above-described conductive material containing a metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or silicon added Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • Metal oxide As the oxide 230, a metal oxide that functions as an oxide semiconductor is preferably used. Below, the metal oxide applicable to the oxide 230 which concerns on this invention is demonstrated.
  • the metal oxide preferably contains at least indium or zinc.
  • indium and zinc are preferably included.
  • aluminum, gallium, yttrium, tin, or the like is preferably contained.
  • One or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be included.
  • the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc is considered.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • the element M may be a combination of a plurality of the aforementioned elements.
  • metal oxides containing nitrogen may be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor.
  • the non-single-crystal oxide semiconductor for example, a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, a pseudo-amorphous oxide semiconductor (a-like OS), and an amorphous oxide are used.
  • the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and has a strain.
  • the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.
  • Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons.
  • a lattice arrangement such as a pentagon and a heptagon in the distortion.
  • it is difficult to check a clear crystal grain boundary also referred to as a grain boundary
  • the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Because.
  • the CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked.
  • In layer a layer containing indium and oxygen
  • M, Zn elements M, zinc, and oxygen
  • indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.
  • CAAC-OS is a metal oxide with high crystallinity.
  • CAAC-OS impurities and defects oxygen deficiency (V O:. Oxygen vacancy also referred) etc.) with less metal It can be said that it is an oxide. Therefore, the physical properties of the metal oxide including a CAAC-OS are stable. Therefore, a metal oxide including a CAAC-OS is resistant to heat and has high reliability.
  • Nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
  • indium-gallium-zinc oxide which is a kind of metal oxide including indium, gallium, and zinc
  • IGZO indium-gallium-zinc oxide
  • a crystal smaller than a large crystal here, a crystal of several millimeters or a crystal of several centimeters
  • it may be structurally stable.
  • A-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.
  • Oxide semiconductors have various structures and have different characteristics.
  • the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • the oxide semiconductor metal oxide
  • the semiconductor device have crystallinity.
  • the oxide 230 can have a CAAC-OS structure. When the oxide 230 has the above crystal structure, a highly reliable semiconductor device can be obtained.
  • the concentration of alkali metal or alkaline earth metal is set to 1 ⁇ 10 18 atoms. / Cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • hydrogen contained in the metal oxide reacts with oxygen bonded to metal atoms to become water, so that oxygen vacancies may be formed.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated.
  • a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including a metal oxide containing hydrogen is likely to be normally on.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • FIG. 1 ⁇ Method for Manufacturing Semiconductor Device>
  • A in each drawing shows a top view.
  • B in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200.
  • C in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200.
  • (D) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line in A5-A6 in (A), and is also a cross-sectional view in the channel width direction in the source region or drain region of the transistor 200. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.
  • a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate.
  • the insulator 214 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD method. (Atomic Layer Deposition) method or the like can be used.
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the plasma CVD method can obtain a high-quality film at a relatively low temperature.
  • the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma.
  • a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge.
  • plasma damage during film formation does not occur, so that a film with few defects can be obtained.
  • the ALD method utilizes the self-controllability that is the nature of atoms and can deposit atoms one layer at a time, so it is possible to form a very thin film, and to form a structure with a high aspect ratio. There are effects such as film formation with few defects such as holes, film formation with excellent coverage, and film formation at low temperature.
  • the ALD method also includes a film forming method PEALD (Plasma Enhanced ALD) method using plasma. Use of plasma may be preferable because it enables film formation at a lower temperature.
  • some precursors used in the ALD method include impurities such as carbon. Therefore, a film provided by the ALD method may contain a larger amount of impurities such as carbon than a film provided by another film formation method.
  • the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the source gases.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases.
  • a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film.
  • a silicon nitride film is formed as the insulator 214 by a CVD method.
  • a CVD method a CVD method.
  • the insulator 216 is formed over the insulator 214.
  • the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an opening reaching the insulator 214 is formed in the insulator 216.
  • the opening includes, for example, a groove and a slit. In some cases, the opening is pointed to a region where the opening is formed. Wet etching may be used to form the opening, but dry etching is preferable for fine processing.
  • an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove is preferably selected. For example, in the case where a silicon oxide film is used for the insulator 216 for forming the groove, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used as the insulator 214.
  • a conductive film to be the conductor 205 is formed.
  • the conductive film preferably includes a conductor having a function of suppressing permeation of oxygen.
  • tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
  • the conductive film to be the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 205 has a multilayer structure.
  • tantalum nitride is formed as a conductive film to be the conductor 205a by a sputtering method
  • titanium nitride is formed as a conductor 205b on the tantalum nitride by a CVD method.
  • a conductive film to be the conductor 205c is formed.
  • the conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a low-resistance conductive material such as tungsten or copper is formed as the conductive film to be the conductor 205c.
  • tungsten may be formed by a CVD method as the conductive film to be the conductor 205c.
  • the conductive film to be the conductor 205 is removed, and the insulator 216 is exposed (see FIG. 3).
  • the conductive film to be the conductor 205 remains only in the opening.
  • the conductor 205 (the conductor 205a, the conductor 205b, and the conductor 205c) having a flat upper surface can be formed.
  • part of the insulator 216 may be removed by the CMP treatment.
  • a conductive film to be the conductor 205 is formed over the insulator 214.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film can be a multilayer film. In this embodiment mode, tungsten is formed as the conductive film.
  • the conductive film is processed using a lithography method to form the conductor 205.
  • a resist is exposed through a mask.
  • a resist mask is formed by removing or leaving the exposed region using a developer.
  • a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens.
  • an electron beam or an ion beam may be used.
  • a mask is not necessary when an electron beam or an ion beam is used.
  • the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • an insulating film or a conductive film that is a hard mask material is formed over the conductive film that is to be the conductor 205, a resist mask is formed thereover, and the hard mask material is etched to have a desired shape.
  • a hard mask can be formed. Etching of the conductive film to be the conductor 205 may be performed after removing the resist mask, or may be performed with the resist mask remaining. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the conductive film is etched. On the other hand, when the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as the dry etching apparatus.
  • the capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes.
  • a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed.
  • mold electrode may be sufficient.
  • mold electrode may be sufficient.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP) etching apparatus can be used as the dry etching apparatus having a high-density plasma source.
  • an insulating film to be the insulator 216 is formed over the insulator 214 and the conductor 205.
  • the insulator to be the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide is formed by a CVD method as the insulating film to be the insulator 216.
  • the thickness of the insulating film to be the insulator 216 is preferably greater than or equal to the thickness of the conductor 205.
  • the thickness of the conductor 205 is 1, the thickness of the insulating film to be the insulator 216 is 1 or more and 3 or less.
  • the thickness of the conductor 205 is 150 nm, and the thickness of the insulating film to be the insulator 216 is 350 nm.
  • the conductor 205 and the insulator 216 having a flat upper surface can be formed.
  • the above is a method for forming the conductor 205 different from the above.
  • an insulator 222 is formed over the insulator 216 and the conductor 205.
  • an insulator including one or both of aluminum and hafnium may be formed.
  • the insulator including one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • An insulator including one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, diffusion of hydrogen and water contained in a structure provided around the transistor 200 to the inside of the transistor 200 through the insulator 222 is suppressed. In addition, generation of oxygen vacancies in the oxide 230 can be suppressed.
  • the insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 224 is formed over the insulator 222.
  • the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • openings are formed in the insulator 224, the insulator 222, the insulator 216, and the insulator 214.
  • Wet etching may be used to form the opening, but dry etching is preferable for fine processing.
  • a conductive film to be the conductor 247 is formed.
  • the conductive film to be the conductor 247 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductor 247 is formed in a structure similar to that of the conductor 205.
  • the conductive film to be the conductor 247a is formed by a method similar to the conductive film to be the conductor 205a
  • the conductive film to be the conductor 247b is formed by the same method as the conductive film to be the conductor 205b
  • a conductive film to be the conductor 247c is formed by a method similar to that of the conductive film to be the conductor 205c.
  • the conductor 247 (the conductor 247a, the conductor 247b, and the conductor 247c) having a flat upper surface can be formed.
  • part of the insulator 224 may be removed by the CMP treatment.
  • the heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.
  • the heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in a nitrogen or inert gas atmosphere. Good.
  • the treatment after performing a treatment for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere, the treatment is continuously performed for 1 hour at a temperature of 400 ° C. in an oxygen atmosphere.
  • impurities such as water and hydrogen contained in the insulator 224 can be removed.
  • the heat treatment may be performed after the insulator 222 is formed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • plasma treatment including oxygen may be performed in a reduced pressure state.
  • an apparatus having a power source that generates high-density plasma using microwaves for example.
  • a power source for applying RF Radio Frequency
  • high-density plasma high-density oxygen radicals can be generated.
  • RF Radio Frequency
  • oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. it can.
  • plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, heat treatment may not be performed.
  • an aluminum oxide film may be formed on the insulator 224 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 224.
  • CMP the surface of the insulator 224 can be planarized and the surface of the insulator 224 can be smoothed.
  • the end point of the CMP can be easily detected.
  • part of the insulator 224 is polished by CMP so that the thickness of the insulator 224 may be reduced; however, the thickness may be adjusted when the insulator 224 is formed.
  • planarizing and smoothing the surface of the insulator 224 By planarizing and smoothing the surface of the insulator 224, deterioration in coverage of an oxide to be formed later can be prevented, and reduction in yield of the semiconductor device can be prevented in some cases. Further, it is preferable to form aluminum oxide over the insulator 224 by a sputtering method because oxygen can be added to the insulator 224.
  • the oxide film 230A is formed on the insulator 224 (see FIG. 3).
  • the oxide film 230A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230A is formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
  • excess oxygen in the oxide film to be formed can be increased.
  • the oxide film is formed by a sputtering method
  • the In-M-Zn oxide target can be used.
  • part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A may be 70% or more, preferably 80% or more, more preferably 100%.
  • a mask 252 is formed on the oxide film 230A (see FIG. 3).
  • a resist mask or a hard mask can be used as the mask 252 .
  • an opening 248 exposing at least a part of the conductor 247 is formed in the oxide film 230A using the mask 252 (see FIG. 4).
  • the opening 248 may be formed by wet etching, but dry etching is preferable for fine processing.
  • the mask 252 is removed, and an oxide film 230B is formed (see FIG. 5).
  • the oxide film 230 ⁇ / b> B is in contact with the conductor 247 inside the opening 248.
  • the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230B is formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
  • excess oxygen in the oxide film to be formed can be increased.
  • the oxide film is formed by a sputtering method
  • the In-M-Zn oxide target can be used.
  • an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%.
  • the A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have a relatively high field-effect mobility.
  • Form a film is preferably formed in accordance with characteristics required for the oxide 230 by appropriately selecting a deposition condition and an atomic ratio.
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed.
  • the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.
  • the oxide film 230A and the oxide film 230B are processed into island shapes to form the oxide 230a and the oxide 230b (see FIG. 6). Note that in this step, the thickness of the region of the insulator 224 that does not overlap with the oxide 230a may be reduced.
  • the oxide 230a and the oxide 230b are formed so as to overlap with the conductor 205 at least partially.
  • the side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the upper surface of the insulator 222, when the plurality of transistors 200 are provided, the area can be reduced and the density can be increased. Alternatively, the oxide 230a and the oxide 230b and the top surface of the insulator 222 may have a small angle.
  • the angle formed between the side surfaces of the oxide 230a and the oxide 230b and the upper surface of the insulator 222 is preferably greater than or equal to 60 ° and less than 70 °.
  • the oxide film and the conductive film may be processed using a lithography method.
  • a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.
  • a curved surface is preferably provided between the side surface of the oxide 230b and the upper surface of the oxide 230b. That is, it is preferable that the end portion where the side surface and the upper surface intersect is curved (hereinafter, this curvature is also referred to as a round shape).
  • the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the oxide 230b. By not having a corner at the end, the coverage of the film in the subsequent film forming process is improved.
  • the oxide film may be processed using a lithography method.
  • a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.
  • an insulating film 256A is formed over the insulator 224, the oxide 230a, and the oxide 230b (see FIG. 6).
  • the insulating film 256A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film having a function of suppressing permeation of oxygen is preferably used.
  • silicon oxynitride may be formed by a CVD method.
  • silicon nitride, silicon oxide, or aluminum oxide may be formed by a sputtering method.
  • a material that can be used for the oxide 230a and the oxide 230b can be used.
  • the insulating film 256A may have a stacked structure.
  • an aluminum oxide film may be formed as a lower layer by a sputtering method, and a silicon nitride film may be formed as an upper layer by an ALD method.
  • a film to be the dummy gate 262A is formed on the insulating film 256A.
  • the film to be the dummy gate 262A is processed and used as a dummy gate.
  • a dummy gate is a temporary gate electrode. That is, a temporary gate electrode is formed by processing a film to be the dummy gate 262A, and the dummy gate is removed in a later process, and a gate electrode made of a conductive film or the like is formed instead. Therefore, it is preferable to use a film that becomes the dummy gate 262A because it can be easily finely processed and easily removed.
  • the film to be the dummy gate 262A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a sputtering method a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulator, a semiconductor, or a conductor can be used.
  • silicon such as polysilicon, microcrystalline silicon, or amorphous silicon, or a metal film such as aluminum, titanium, or tungsten may be used.
  • a film containing carbon, SOG (Spin On Glass), a resin film, or the like may be formed using a coating method.
  • photoresist polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, or the like
  • the SOG and resin films By forming the SOG and resin films by a coating method, the surface of the dummy gate film can be flattened. Thus, by making the surface of the dummy gate film flat, microfabrication is facilitated, and removal is also easy.
  • the dummy gate needs to protect the oxide 230 from the dopant when a dopant described later is added. For this reason, it is preferable that the film to be the dummy gate 262A has sufficient hardness.
  • a dummy gate film for example, a film containing carbon is suitable.
  • the film to be the dummy gate 262A can be a multilayer film using different film types.
  • the film to be the dummy gate 262A can be a film having a two-layer structure of a conductive film and a resin film formed over the conductive film.
  • the conductive film may function as a stopper film for CMP processing in a later CMP process.
  • the end point of the CMP process may be detected, and processing variations may be reduced.
  • the film to be the dummy gate 262A is etched by lithography to form the dummy gate 262A (see FIG. 7).
  • the dummy gate 262A is formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230b.
  • the dummy gate 262A may be cured by performing heat treatment after the dummy gate 262A is formed.
  • the dummy gate 262A has a high aspect ratio, deformation of the dummy gate 262A can be prevented by hardening the dummy gate 262A.
  • an insulating film 258A is formed to cover the insulating film 256A and the dummy gate 262A (see FIG. 7).
  • the insulating film 258A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film having a function of suppressing diffusion of impurities such as hydrogen and oxygen is preferably used.
  • impurities such as hydrogen and oxygen
  • the insulating film 258A having a uniform thickness can be formed even on the step portion generated by the oxide 230a, the oxide 230b, and the dummy gate 262A.
  • dopant 257 is added to oxide 230b using dummy gate 262A as a mask (see FIG. 7).
  • a region 249a and a region 249b including the dopant 257 are formed in a region of the oxide 230b that does not overlap with the dummy gate 262A.
  • an ion implantation method in which an ionized source gas is added by mass separation an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like is used. be able to.
  • mass separation the ionic species to be added and the concentration thereof can be strictly controlled.
  • mass separation is not performed, high-concentration ions can be added in a short time.
  • an ion doping method in which atomic or molecular clusters are generated and ionized may be used.
  • the dopant may be referred to as an ion, a donor, an acceptor, an impurity, an element, or the like.
  • an element that forms the above-described oxygen vacancies or an element that binds to oxygen vacancies may be used.
  • an element typically, boron or phosphorus can be given.
  • hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas, or the like may be used.
  • rare gases include helium, neon, argon, krypton, and xenon.
  • metals such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc. Any one or more metal elements selected from the elements may be added.
  • boron and phosphorus are preferable as the dopant 257. When boron or phosphorus is used as the dopant 257, equipment for an amorphous silicon or low-temperature polysilicon production line can be used, so that capital investment can be suppressed.
  • an element that easily forms an oxide is preferably used as the dopant 257.
  • Typical examples of such elements include boron, phosphorus, aluminum, and magnesium.
  • a gas containing the above impurity element can be used.
  • boron typically, B 2 H 6 gas, BF 3 gas, or the like can be used.
  • phosphorus typically PH 3 gas can be used.
  • a mixed gas obtained by diluting these source gases with a rare gas may be used.
  • the source gas CH 4 , N 2 , NH 3 , AlH 3 , AlCl 3 , SiH 4 , Si 2 H 6 , F 2 , HF, H 2, rare gas, and the like can be used.
  • the ion source is not limited to gas, and an ion source obtained by vaporizing a liquid or solid may be used.
  • the addition of the dopant 257 can be controlled by setting conditions such as an acceleration voltage and a dose amount in consideration of the composition, density, thickness, and the like of the insulating film 256A and the oxide 230b. In particular, it is preferable to give sufficient energy to the dopant 257 so that the dopant 257 can penetrate a portion of the insulating film 256A that is not in contact with the dummy gate 262A.
  • the dopant 257 is added substantially perpendicularly to the upper surface of the insulator 214.
  • the present invention is not limited to this, and the dopant 257 may be added while being inclined with respect to the upper surface of the insulator 214.
  • the region 249a and the region 249b can be easily formed in part of the region overlapping with the dummy gate 262A.
  • the dopant 257 is added to the oxide 230b through the insulating film 256A.
  • the dopant 257 is also added to the insulating film 256A. That is, both the oxide 230 and the insulating film 256 ⁇ / b> A have an element contained in the dopant 257.
  • the dopant 257 may be able to suppress the diffusion of excess oxygen to the outside.
  • the dopant 257 may be added to the oxide 230a, the insulator 224, and the insulator 222 provided under the oxide 230b and the insulating film 256A. Therefore, the oxide 230a, the insulator 224, and the insulator 222 may include an element contained in the dopant 257 in some cases.
  • the conductor 260 formed in a later step can be arranged in a self-aligned manner between the region 249a and the region 249b.
  • heat treatment may be performed after the addition of the dopant 257. Accordingly, since the dopant added to the oxide 230b can be diffused, the region 249a and the region 249b can be easily formed in part of the region overlapping with the dummy gate 262A. Further, by diffusing the dopant in the film thickness direction of the oxide 230b, the resistance is reduced from the surface of the oxide 230b to the vicinity of the boundary between the conductor 247 and the oxide 230b, and the contact resistance between the conductor 247 and the oxide 230b is reduced. Can be reduced. Further, in some cases, hydrogen included in the region 234 functioning as a channel formation region can be captured by oxygen vacancies included in the region 249 by the heat treatment. Thus, stable electrical characteristics can be given to the transistor 200, and reliability can be improved. Moreover, you may perform the said heat processing at a subsequent process.
  • an insulating film 280A is formed over the insulating film 258A (see FIG. 8).
  • the insulating film 280A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film 280A, the insulating film 258A, and a part of the dummy gate 262A are removed until a part of the dummy gate 262A is exposed to form the insulator 280, the insulator 258B, and the dummy gate 262 (FIG. 9). It is preferable to use a CMP process for forming the insulator 280, the insulator 258B, and the dummy gate 262.
  • the upper surface of the dummy gate 262 substantially coincides with the upper surfaces of the insulator 258B and the insulator 280.
  • the dummy gate 262 and portions of the insulating film 256A and the insulating film 258A exposed from the insulator 280 are removed to form openings (see FIG. 10).
  • the removal of the dummy gate 262, the insulating film 256A, and the insulating film 258A can be performed by wet etching, dry etching, ashing, or the like using the insulator 280 as a mask.
  • a combination of a plurality of the above processes may be performed as appropriate. For example, a wet etching process is performed after the ashing process.
  • the insulator 258 is formed by removing part of the insulating film 258A, and the insulator 256 is formed by removing part of the insulating film 256A.
  • the insulator 256A is formed by removing part of the insulating film 256A.
  • the dummy gate 262 and the portions of the insulating film 256A and the insulating film 258A that are exposed from the insulator 280 are not necessarily removed at once.
  • the dummy gate 262 and the portion of the insulating film 258A exposed from the insulator 280 may be removed, and then the portion of the insulating film 256A exposed from the insulator 280 may be removed.
  • heat treatment may be performed.
  • the heat treatment may be performed under reduced pressure, and the oxide film 230C may be continuously formed without being exposed to the atmosphere (see FIG. 11).
  • moisture and hydrogen adsorbed on the surface of the oxide 230b and the like can be removed, and further, the moisture concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be reduced.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In this embodiment mode, the temperature of the heat treatment is 200 ° C.
  • the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed using a film formation method similar to that for the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide film 230C.
  • the oxide film 230C may be a stacked layer.
  • the film may be formed using a target of [number ratio].
  • the ratio of oxygen contained in the sputtering gas for the oxide film 230C may be 70% or more, preferably 80% or more, more preferably 100%.
  • heat treatment may be performed.
  • the heat treatment may be performed under reduced pressure, and the insulating film 250A may be continuously formed without being exposed to the air (see FIG. 11).
  • moisture and hydrogen adsorbed on the surface of the oxide film 230C and the like are removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C are further reduced.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower.
  • the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxynitride is preferably formed by a CVD method.
  • the deposition temperature at the time of forming the insulating film 250A is preferably 350 ° C. or higher and lower than 450 ° C., particularly preferably around 400 ° C.
  • a conductive film 260A and a conductive film 260B are formed (see FIG. 11).
  • the conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a CVD method it is preferable to use a CVD method.
  • the conductive film 260A is formed using an ALD method
  • the conductive film 260B is formed using a CVD method.
  • the oxide film 230C, the insulator 250, and the conductor 260 are polished by CMP treatment until the insulator 280 is exposed by polishing the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B. And a conductor 260b) are formed (see FIG. 12).
  • heat treatment may be performed.
  • heat treatment is performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere.
  • moisture concentration and hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.
  • an insulating film to be the insulator 282 may be formed over the conductor 260, the oxide 230 c, the insulator 250, and the insulator 280.
  • the insulating film to be the insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • aluminum oxide is preferably formed by, for example, a sputtering method. In this manner, the insulator 282 is formed in contact with the upper surface of the conductor 260, whereby oxygen contained in the insulator 280 can be suppressed from being absorbed into the conductor 260 in the subsequent heat treatment. Therefore, it is preferable (see FIG. 13).
  • heat treatment may be performed.
  • treatment is performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere.
  • oxygen added by the formation of the insulator 282 can be injected into the insulator 280.
  • the oxygen can be injected into the oxide 230a and the oxide 230b through the oxide 230c.
  • an insulator to be the insulator 274 may be formed over the insulator 282 (see FIG. 13).
  • the insulating film to be the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulator to be the insulator 281 may be formed over the insulator 274 (see FIG. 13).
  • the insulating film to be the insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an opening reaching the region 249a is formed in the insulator 256, the insulator 258, the insulator 280, the insulator 282, the insulator 274, and the insulator 281.
  • the opening may be formed using a lithography method.
  • an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film having a function of suppressing permeation of oxygen is preferably used.
  • anisotropic etching for example, a dry etching method may be performed.
  • the conductive film to be the conductor 240 preferably has a stacked structure including a conductor having a function of suppressing transmission of impurities such as water and hydrogen.
  • a stack of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used.
  • the conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a part of the conductive film to be the conductor 240 is removed, and the insulator 281 is exposed.
  • the conductive film 240 can be formed only in the opening, whereby the conductor 240 having a flat upper surface can be formed (see FIG. 1).
  • part of the insulator 281 may be removed by the CMP treatment.
  • a conductor that is electrically connected to the conductor 240 may be formed.
  • the conductive film is processed by a lithography method, so that a conductor in contact with the upper surface of the conductor 240 is formed. Can do.
  • a semiconductor device including the transistor 200 illustrated in FIG. 1 can be manufactured. As illustrated in FIGS. 3 to 13, the transistor 200 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device with high on-state current can be provided.
  • a semiconductor device having high frequency characteristics can be provided.
  • a semiconductor device with favorable reliability can be provided.
  • a semiconductor device with low off-state current can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • a highly productive semiconductor device can be provided.
  • FIGS. 14 to 17 (A) in each figure shows a top view. Further, (B) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line A1-A2 shown in (A) in each drawing, and is also a cross-sectional view in the channel length direction of the transistor 200. Further, (C) in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in (A) in each drawing, and is also a cross-sectional view in the channel width direction of the transistor 200.
  • (D) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A5-A6 in (A) in each drawing, and is also a cross-sectional view in the channel width direction in the source region or drain region of the transistor 200. is there.
  • (A) in each figure some elements are omitted for clarity of the figure.
  • the transistor 200 illustrated in FIG. 14 is different from the transistor 200 illustrated in FIG. 1 in that a part of the conductor 247 is exposed from the top surface of the oxide 230a.
  • a part of the conductor 247 is preferably embedded in the opening formed in the oxide 230a.
  • the conductor 247 may be disposed so as to be embedded in an opening formed in the oxide 230a, the insulator 224, the insulator 222, the insulator 216, and the insulator 214.
  • the upper surface of the conductor 247 is exposed from the oxide 230a, and it is preferable that the upper surface of the conductor 247 and the upper surface of the oxide 230a substantially coincide with each other.
  • an opening is formed in the oxide film 230A, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 after forming the oxide film 230A illustrated in FIG.
  • the conductor 247 may be formed so as to fill the opening.
  • a transistor 200 illustrated in FIG. 15 is different from the transistor 200 illustrated in FIG. 1 in that a region 249a and a region 249b are formed in the oxide 230a and the oxide 230b. 1 is different from the transistor 200 in FIG. 1 in that the upper surface of the conductor 247 and the region 249b formed in the oxide 230a are in contact with each other.
  • the oxide 230b and the conductor 247 do not need to be in direct contact with each other, so that the step of forming an opening in the oxide 230a can be omitted. Therefore, the manufacturing process of the semiconductor device according to this embodiment can be simplified and productivity can be improved.
  • the insulator 256, the insulator 258, the insulator 280, the insulator 282, the insulator 274, and the insulator 281 have openings that overlap with the conductor 247, and are conductive so as to fill the openings. It differs from the transistor 200 shown in FIG. 15 in that the body 240b is arranged. The conductor 240b is in contact with the upper surface of the oxide 230b and the side surfaces of the oxide 230b and the oxide 230a in the channel width direction (A5-A6 direction).
  • the lower surface of the conductor 240b is in contact with the upper surface of the conductor 247 at a portion that does not overlap with the oxide 230a and the oxide 230b. Therefore, the lengths of the conductor 240b and the conductor 247 in the channel width direction are preferably longer than the lengths of the oxide 230a and the region 249b of the oxide 230b in the channel width direction.
  • the region 249b of the oxide 230a and the oxide 230b is in direct contact with the conductor 247 on the lower surface, and is electrically connected to the conductor 247 via the conductor 240b on the upper and side surfaces. Connected. Accordingly, the conductivity between the region 249b and the conductor 247 can be further improved.
  • an opening reaching the region 249a is formed in the insulator 256, the insulator 258, the insulator 280, the insulator 282, the insulator 274, and the insulator 281, and the conductor 240a is disposed so as to fill the opening.
  • the conductor 240a and the conductor 240b have the same configuration as the conductor 240. Note that the upper surface of the conductor 240a is connected to a wiring, an electrode, a terminal, or the like, but the upper surface of the conductor 240b is not necessarily connected to a wiring, an electrode, a terminal, or the like.
  • the conductor 240a and the conductor 240b may be a laminated film. In that case, a conductive material having high adhesion may be used for the lower layer.
  • the conductor 240a and the conductor 240b may be a conductive film in which titanium nitride and tungsten are stacked in this order.
  • the insulator 241 is not provided in contact with the side surfaces of the conductor 240a and the conductor 240b. Thereby, the contact between the conductor 240b and the oxide 230a and the oxide 230b can be improved.
  • the conductor 247 may be provided in the same layer as the conductor 205. That is, the conductor 247 is formed so as to be embedded in the insulator 216 similarly to the conductor 205.
  • the region 249 and the conductor 247 are not in direct contact but are electrically connected only through the conductor 240b. Therefore, in the transistor 200 illustrated in FIGS. 17A and 17B, the contact resistance between the conductor 240b and the conductor 247 is preferably sufficiently reduced.
  • the conductor 247 can be formed in the same process as the conductor 205, so that the manufacturing process of the semiconductor device according to this embodiment can be simplified and productivity can be improved. .
  • the region 249 is also formed in the oxide 230a; however, the present invention is not limited to this.
  • the region 249 may be formed only in the oxide 230b.
  • FIG. 18 illustrates an example of a semiconductor device (memory device) using a capacitor which is one embodiment of the present invention.
  • the transistor 200 is provided above the capacitor 100 and the transistor 300, and the capacitor 100 is provided above the transistor 300. It is preferable that at least part of the capacitor 100 or the transistor 300 overlap with the transistor 200. Accordingly, the area occupied by the capacitor 100, the transistor 200, and the transistor 300 in a top view can be reduced, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated.
  • the semiconductor device includes, for example, a logic circuit typified by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), a DRAM (Dynamic Random Access Memory), or an NVM (Non-Volatile Memory). It can be applied to memory circuits represented by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), a DRAM (Dynamic Random Access Memory), or an NVM (Non-Volatile Memory). It can be applied to memory circuits represented by
  • the transistor 200 described in the above embodiment can be used as the transistor 200. Therefore, the description of the above embodiment can be referred to for the transistor 200 and the layer including the transistor 200.
  • the transistor 200 has the same structure as the transistor 200 illustrated in FIG. 1, but is not limited thereto.
  • the transistor 200 or the like illustrated in FIGS. 14 to 17 may be used, and the same applies to the semiconductor devices illustrated in FIGS.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.
  • the transistor 200 has better electrical characteristics at high temperatures. For example, the transistor 200 exhibits favorable electrical characteristics even in the temperature range of 125 ° C. to 150 ° C. In the temperature range of 125 ° C. to 150 ° C., the transistor 200 has an on / off ratio of 10 digits or more. In other words, as compared with a transistor using silicon for a semiconductor layer, the transistor 200 has excellent transistor characteristics (such as on-state current and frequency characteristics) as the temperature increases.
  • the wiring 1001 is electrically connected to the source of the transistor 300
  • the wiring 1002 is electrically connected to the drain of the transistor 300
  • the wiring 1007 is electrically connected to the gate of the transistor 300.
  • the wiring 1003 is electrically connected to one of a source and a drain of the transistor 200
  • the wiring 1004 is electrically connected to the first gate of the transistor 200
  • the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the other of the source and the drain of the transistor 200 is electrically connected to one of the electrodes of the capacitor 100
  • the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100.
  • the semiconductor device illustrated in FIG. 18 has a characteristic that the electric charge charged in one of the electrodes of the capacitor 100 can be held by switching of the transistor 200, whereby information can be written, held, and read.
  • the transistor 200 is an element provided with a back gate in addition to a source, a gate (front gate), and a drain. That is, since it is a four-terminal element, MRAM (Magnetic Resistant Random Access Memory), ReRAM (Resistive Random Access Memory), phase change memory (second memory memory, etc.) that uses MTJ (Magnetic Tunnel Junction) characteristics Compared with a terminal element, it has a feature that input / output independent control can be easily performed.
  • MRAM Magnetic Resistant Random Access Memory
  • ReRAM Resistive Random Access Memory
  • phase change memory second memory memory, etc.
  • MTJ Magnetic Tunnel Junction
  • MRAM, ReRAM, and phase change memory may undergo structural changes at the atomic level when information is rewritten.
  • the semiconductor device shown in FIG. 18 has characteristics that it is excellent in repetitive rewriting resistance and has little structural change because it operates by recharging or discharging electrons using a transistor and a capacitor when rewriting information.
  • a memory cell array can be formed.
  • the transistor 300 can be used as a reading circuit or a driver circuit connected to the memory cell array.
  • the semiconductor device shown in FIG. 18 forms a memory cell array as described above.
  • an operating frequency of 200 MHz or more can be realized in a range where the drive voltage is 2.5 V and the evaluation environment temperature is ⁇ 40 ° C. to 85 ° C.
  • the transistor 300 is provided over the substrate 311 and functions as a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including a part of the substrate 311, and a source region or a drain region. It has a low resistance region 314a and a low resistance region 314b.
  • the insulator 315 is disposed over the semiconductor region 313, and the conductor 316 is disposed over the insulator 315.
  • the transistors 300 formed in the same layer are electrically isolated by an insulator 312 that functions as an element isolation insulating layer.
  • an insulator similar to the insulator 326 described later can be used.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the substrate 311 includes a semiconductor such as a silicon-based semiconductor in a region where a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a which serves as a source region or a drain region, a low resistance region 314b, and the like. It is preferable that it contains single crystal silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
  • HEMT High Electron Mobility Transistor
  • the low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.
  • the conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron.
  • a conductive material such as a material or a metal oxide material can be used.
  • the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.
  • a semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape.
  • a conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween.
  • Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate.
  • an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion.
  • the SOI substrate may be processed to form a semiconductor film having a convex shape.
  • transistor 300 illustrated in FIGS. 18A and 18B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • the semiconductor device includes the transistor 300 and the transistor 200 which are stacked.
  • the transistor 300 can be formed using a silicon-based semiconductor material
  • the transistor 200 can be formed using an oxide semiconductor.
  • the semiconductor device illustrated in FIG. 18 can be formed by mixing a silicon-based semiconductor material and an oxide semiconductor in different layers.
  • the semiconductor device illustrated in FIG. 18 can be manufactured through a process similar to that of a manufacturing apparatus used for a silicon-based semiconductor material, and can be highly integrated.
  • the capacitor 100 includes an insulator 114 over the insulator 364, an insulator 140 over the insulator 114, a conductor 110 disposed in an opening formed in the insulator 114 and the insulator 140, and a conductor 110 and the insulator 130 on the insulator 140, the conductor 120 on the insulator 130, and the insulator 150 on the conductor 120 and the insulator 130.
  • the conductor 110, the insulator 130, and the conductor 120 is disposed in the opening formed in the insulator 114 and the insulator 140.
  • the conductor 110 functions as a lower electrode of the capacitor 100
  • the conductor 120 functions as an upper electrode of the capacitor 100
  • the insulator 130 functions as a dielectric of the capacitor 100.
  • the capacitor element 100 In the opening of the insulator 114 and the insulator 140, the capacitor element 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric interposed therebetween, not only on the bottom surface but also on the side surface.
  • the capacity can be increased. Therefore, the capacitance of the capacitor 100 can be increased as the depth of the opening is increased.
  • the semiconductor device can be miniaturized or highly integrated.
  • an insulator that can be used for the insulator 280 may be used.
  • the insulator 140 preferably functions as an etching stopper when the opening of the insulator 114 is formed, and an insulator that can be used for the insulator 214 may be used.
  • the shape of the openings formed in the insulator 114 and the insulator 140 when viewed from the top may be a quadrilateral, a polygon other than a quadrangle, or a shape in which corners are curved in the polygon. Alternatively, a circular shape including an ellipse may be used.
  • the conductor 110 is disposed in contact with the opening formed in the insulator 140 and the insulator 114. It is preferable that the upper surface of the conductor 110 substantially coincides with the upper surface of the insulator 140.
  • the conductor 366 embedded in the opening of the insulator 364 is in contact with the lower surface of the conductor 110.
  • the conductor 110 is preferably formed by an ALD method, a CVD method, or the like. For example, a conductor that can be used for the conductor 205 may be used.
  • the insulator 130 is disposed so as to cover the conductor 110 and the insulator 140.
  • the insulator 130 is preferably formed using an ALD method, a CVD method, or the like.
  • the insulator 130 is formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or nitride Hafnium or the like may be used, and it can be provided as a stacked layer or a single layer.
  • an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used.
  • the insulator 130 is preferably made of a material having a high dielectric strength such as silicon oxynitride or a high dielectric constant (high-k) material (a material having a high relative dielectric constant).
  • a material having a high dielectric strength such as silicon oxynitride or a high dielectric constant (high-k) material (a material having a high relative dielectric constant).
  • high-k high dielectric constant
  • a stacked structure of a material having a high dielectric strength and a high dielectric constant (high-k) material may be used.
  • an insulator of a high dielectric constant (high-k) material gallium oxide, hafnium oxide, zirconium oxide, an oxide including aluminum and hafnium, an oxynitride including aluminum and hafnium, an oxide including silicon and hafnium And oxynitrides having silicon and hafnium or nitrides having silicon and hafnium.
  • high-k material gallium oxide, hafnium oxide, zirconium oxide, an oxide including aluminum and hafnium, an oxynitride including aluminum and hafnium, an oxide including silicon and hafnium And oxynitrides having silicon and hafnium or nitrides having silicon and hafnium.
  • materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and voids.
  • examples include silicon oxide or resin.
  • the conductor 120 is disposed so as to fill the openings formed in the insulator 140 and the insulator 114. Further, the conductor 247 is in contact with the upper surface of the conductor 120 through the opening of the insulator 150.
  • the conductor 120 is preferably formed using an ALD method, a CVD method, or the like. For example, a conductor that can be used for the conductor 205 may be used.
  • the transistor 200 since the transistor 200 has a structure using an oxide semiconductor, the transistor 200 has excellent compatibility with the capacitor 100. Specifically, since the transistor 200 including an oxide semiconductor has low off-state current, stored data can be held for a long time by being used in combination with the capacitor 100.
  • the capacitor element 100 described above may require high-temperature heat treatment exceeding 700 ° C. in the manufacturing process.
  • the oxide 230 may be affected by diffusion of impurities such as hydrogen or water, or oxygen, and the electrical characteristics of the transistor 200 may be deteriorated.
  • the transistor 200 is formed over the capacitor 100, so that the thermal history in the manufacturing process of the capacitor 100 does not affect the transistor 200.
  • deterioration of the electrical characteristics of the transistor 200 can be prevented, and a semiconductor device having stable electrical characteristics can be provided.
  • a wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided. Further, a plurality of wiring layers can be provided depending on the design.
  • a conductor having a function as a plug or a wiring may be provided with the same reference numeral by collecting a plurality of structures.
  • the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as an interlayer film.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the conductor 152 functioning as a terminal, a conductor 330, and the like. Note that the conductor 328 and the conductor 330 function as a plug or a wiring.
  • the insulator that functions as an interlayer film may function as a planarizing film that covers the concave and convex shapes below the insulator.
  • the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked.
  • a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.
  • the insulator 360 is disposed over the insulator 354, the insulator 362 is disposed over the insulator 360, the insulator 364 is disposed over the insulator 362, and the insulator 114 is disposed over the insulator 364. Is done.
  • An opening is formed in the insulator 364, and a conductor 366 is disposed in the opening.
  • the conductor 366 is in contact with the lower surface of the conductor 110. That is, the conductor 366 functions as a wiring connected to the other electrode of the capacitor 100.
  • an insulator that can be used for the conductor 356 or the like may be used.
  • the insulator 360, the insulator 362, the insulator 364, the insulator 114, the insulator 140, the insulator 130, and the insulator 150 include the conductor 112 and a conductor included in the capacitor 100 (conductor 120 , Conductor 110) and the like are embedded.
  • the conductor 112 has a function as a plug or a wiring for electrically connecting the transistor 300 and the conductor 152 functioning as a terminal.
  • the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 247, a conductor included in the transistor 200 (conductor 205), and the like.
  • the conductor 247 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
  • part of the conductor 247 is electrically connected to the conductor 120 that functions as the upper electrode of the capacitor 100.
  • another part of the conductor 247 functions as a plug or a wiring that electrically connects the transistor 300 and the conductor 152 functioning as a terminal.
  • a conductor 152 is provided over the insulator 281, and the conductor 152 is covered with the insulator 156.
  • the conductor 152 is in contact with the upper surface of the conductor 245 and functions as a terminal of the transistor 200 or the transistor 300.
  • an insulator that can be used as an interlayer film an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, and the like can be given.
  • an insulator functioning as an interlayer film can reduce parasitic capacitance generated between wirings by using a material having a low relative dielectric constant. Therefore, the material may be selected according to the function of the insulator.
  • the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or it is preferable to have resin etc.
  • the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having a hole And a laminated structure of resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • the resistivity of the insulator provided above or below the conductor 152 is 1.0 ⁇ 10 12 ⁇ cm to 1.0 ⁇ 10 15 ⁇ cm, preferably 5.0 ⁇ 10 12 ⁇ cm to 1.0 ⁇ 10. It is preferably 14 ⁇ cm or less, more preferably 1.0 ⁇ 10 13 ⁇ cm or more and 5.0 ⁇ 10 13 ⁇ cm or less.
  • the charge accumulated between the wirings can be dispersed and the characteristic failure and electrostatic breakdown of the transistor and the semiconductor device having the transistor due to the charge can be suppressed.
  • silicon nitride or silicon nitride oxide can be used as such an insulator.
  • the resistivity of the insulator 281 may be set in the above range.
  • a transistor including an oxide semiconductor can be stabilized in electrical characteristics of the transistor by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. Therefore, an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen can be used for the insulator 324, the insulator 350, the insulator 360, and the like.
  • Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium.
  • An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium.
  • a material containing one or more metal elements selected from ruthenium and the like can be used.
  • a semiconductor with high electrical conductivity for example, silicide such as nickel silicide, which is typified by polycrystalline silicon containing an impurity element such as phosphorus, may be used.
  • a metal material, an alloy material, a metal nitride material, or a metal formed using the above materials can be used as the conductor 328, the conductor 330, the conductor 356, the conductor 112, the conductor 247, the conductor 152, and the like.
  • a conductive material such as an oxide material can be used as a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.
  • an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor.
  • an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
  • the insulator 276 may be provided between the insulator 280 having excess oxygen and the conductor 245.
  • the conductor 245 corresponds to the conductor 240 described in the above embodiment
  • the insulator 276 corresponds to the insulator 241 described in the above embodiment.
  • the insulator 276 it is possible to suppress excess oxygen included in the insulator 280 from being absorbed by the conductor 245. In addition, with the insulator 276, diffusion of hydrogen as an impurity into the transistor 200 through the conductor 245 can be suppressed.
  • the conductor 245 has a function as a plug or a wiring electrically connected to the transistor 200 or the transistor 300.
  • a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated.
  • variation in electrical characteristics can be suppressed and reliability can be improved.
  • a transistor including an oxide semiconductor with high on-state current can be provided.
  • a transistor including an oxide semiconductor with low off-state current can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • FIG. 18 illustrates an example in which the conductor electrically connected to the wiring 1003 is in contact with at least part of the top surface of the conductor functioning as one of the source and the drain of the transistor 200;
  • the semiconductor device shown is not limited to this.
  • a conductor functioning as a wiring is provided below the transistor 200, and one of the source and the drain of the transistor 200 is an insulator 224, an insulator 222, an insulator 216, an insulator 214, and an insulator.
  • the structure may be in contact with at least part of the upper surface of the conductor that is electrically connected to the wiring 1003 through the body 212 and the conductor 247 provided in the opening formed in the insulator 210.
  • the insulator 360 is disposed over the insulator 354, the insulator 362 is disposed over the insulator 360, the insulator 364 is disposed over the insulator 362, and the insulator over the insulator 364. 210 is arranged.
  • the insulator 360 may be an insulator that can be used for the insulator 350 or the like.
  • the insulator 362 and the insulator 364 may be an insulator that can be used for the insulator 352 or the like.
  • an opening is formed in the insulator 364, and a conductor 366 is disposed in the opening.
  • the conductor 366 functions as a plug or a wiring.
  • the conductor 366 is electrically connected to one of a source and a drain of the transistor 200.
  • the conductor 366 also functions as a wiring connected to one of the source and the drain of the transistor 200.
  • a conductor that can be used for the conductor 356 or the like may be used.
  • the capacitor element 100 when the capacitor element 100 and the transistor 200 are viewed from above, the capacitor element 100 can have a larger area overlapping with the transistor 200, and the capacitance can be further increased.
  • FIG. 18 illustrates an example in which the capacitor 100 is provided under the transistor 200
  • the semiconductor device described in this embodiment is not limited thereto.
  • the capacitor 100a may be disposed over the transistor 200a and the capacitor 100b may be disposed under the transistor 200b in adjacent memory cells.
  • the semiconductor device illustrated in FIG. 20 has a structure similar to that of the semiconductor device illustrated in FIG. 18 except that the capacitor 100a is provided over the transistor 200.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003a is electrically connected to one of a source and a drain of the transistor 200a.
  • the other of the source and the drain of the transistor 200a is electrically connected to one of the electrodes of the capacitor 100a, and the wiring 1005a is electrically connected to the other of the electrodes of the capacitor 100a.
  • the wiring 1003b is electrically connected to one of a source and a drain of the transistor 200b.
  • the other of the source and the drain of the transistor 200b is electrically connected to one of the electrodes of the capacitor 100b, and the wiring 1005b is electrically connected to the other of the electrodes of the capacitor 100b.
  • FIG. 20 shows the transistor 200a and the capacitor 100a, and the transistor 200b and the capacitor 100b included in the memory cells adjacent to each other.
  • the transistors 200a and 200b have a structure similar to that of the transistor 200. However, since the transistor 200a is connected to the capacitor 100a disposed over the transistor 200a, the conductor 247 is not disposed under the transistor 200a.
  • the capacitive element 100 a and the capacitive element 100 b have the same configuration as the capacitive element 100. That is, the capacitor 100a includes the conductor 110a, the insulator 130a, and the conductor 120a, and the capacitor 100b includes the conductor 110b, the insulator 130b, and the conductor 120b.
  • the conductor 110a and the conductor 110b have a structure similar to that of the conductor 110.
  • the insulator 130a and the insulator 130b have a structure similar to that of the insulator 130.
  • the conductor 120a and the conductor 120b have a structure similar to that of the conductor 120.
  • the capacitor 100a preferably overlaps with the transistor 200a and the transistor 200b.
  • the capacitor 100a preferably overlaps with the channel formation region of the transistor 200a and the channel formation region of the transistor 200b.
  • the capacitor 100b preferably overlaps with the transistors 200a and 200b.
  • the capacitor 100b preferably overlaps with the channel formation region of the transistor 200a and the channel formation region of the transistor 200b.
  • the semiconductor device according to this embodiment can be miniaturized or highly integrated.
  • a plurality of openings for providing the capacitor element 100a and the capacitor element 100b may be provided.
  • the conductor 110a may be provided separately at each opening.
  • the conductor 110b may be provided separately at each opening.
  • the capacitive element 100a and the capacitive element 100b can be formed on the side surface of each opening. Therefore, the capacitance element 100a and the capacitance element 100b illustrated in FIG. 21 can have a larger capacitance with the same occupation area as the capacitance element 100a and the capacitance element 100b illustrated in FIG.
  • FIG. 22 illustrates an example of a semiconductor device (memory device) using a semiconductor device that is one embodiment of the present invention.
  • the semiconductor device illustrated in FIG. 22 includes the transistor 200, the transistor 300, and the capacitor 100 similarly to the semiconductor device illustrated in FIG. Note that in the semiconductor device illustrated in FIG. 22, the capacitor 100 is provided over the transistor 200, the capacitor 100 is a planar type, and the transistor 200 and the transistor 300 are electrically connected to each other through a conductor 247. Is different from the semiconductor device shown in FIG.
  • the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. It is preferable that at least part of the capacitor 100 or the transistor 300 overlap with the transistor 200. Accordingly, the area occupied by the capacitor 100, the transistor 200, and the transistor 300 in a top view can be reduced, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated.
  • the transistor 200 and the transistor 300 described above can be used as the transistor 200 and the transistor 300. Therefore, the above description can be referred to for the transistor 200, the transistor 300, and a layer including them.
  • the wiring 2001 is electrically connected to the source of the transistor 300, and the wiring 2002 is electrically connected to the drain of the transistor 300.
  • the wiring 2003 is electrically connected to one of a source and a drain of the transistor 200
  • the wiring 2004 is electrically connected to the first gate of the transistor 200
  • the wiring 2006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100
  • the wiring 2005 is electrically connected to the other of the electrodes of the capacitor 100.
  • a node connected to the gate of the transistor 300, the other of the source and the drain of the transistor 200, and one of the electrodes of the capacitor 100 may be referred to as a node FG.
  • the potential of the gate (node FG) of the transistor 300 can be held by switching of the transistor 200, whereby information can be written, held, and read.
  • the semiconductor device shown in FIG. 22 can be arranged in a matrix to constitute a memory cell array.
  • the layer including the transistor 300 has a structure similar to that of the semiconductor device illustrated in FIG. 18, the above description can be referred to for a structure below the insulator 354.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are disposed over the insulator 354.
  • the insulator 210 may be an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen.
  • a conductor 247 is embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216.
  • the conductor 247 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
  • the conductor 247 is electrically connected to the conductor 316 that functions as the gate electrode of the transistor 300.
  • the conductor 245 has a function as a plug or a wiring electrically connected to the transistor 200 or the transistor 300.
  • the conductor 245 electrically connects the region 249 b that functions as the other of the source and the drain of the transistor 200 and the conductor 110 that functions as one of the electrodes of the capacitor 100.
  • the capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Note that as the conductor 110, the conductor 120, and the insulator 130, those described in the above memory device 1 can be used.
  • a conductor 152 and a conductor 110 are provided in contact with the upper surface of the conductor 245.
  • the conductor 152 is in contact with the upper surface of the conductor 245 and functions as a terminal of the transistor 200 or the transistor 300.
  • the conductor 152 and the conductor 110 are covered with the insulator 130, and the conductor 120 is disposed so as to overlap the conductor 110 via the insulator 130. Further, an insulator 114 is disposed over the conductor 120 and the insulator 130.
  • FIG. 22 illustrates an example in which a planar capacitor is used as the capacitor 100, but the semiconductor device described in this embodiment is not limited thereto.
  • a cylinder-type capacitive element 100 as shown in FIG. 18 may be used as the capacitive element 100.
  • FIG. 23 a structure in which the conductor 152 is disposed over the conductor 245 and the conductor 112 is disposed over the conductor 152 is preferable. With such a structure, the electrical connection between the conductor 245 and the conductor 112 can be further ensured.
  • the insulator 154 may be an insulator that can be used for the insulator 281.
  • a conductor 153 is provided in contact with the upper surface of the conductor 112.
  • the conductor 153 is in contact with the upper surface of the conductor 112 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.
  • an insulator 156 is provided over the conductor 153 and the insulator 154.
  • an OS transistor a transistor using an oxide as a semiconductor
  • the storage device (hereinafter sometimes referred to as an OS memory device) is described.
  • An OS memory device is a storage device that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.
  • FIG. 24A illustrates an example of a structure of the OS memory device.
  • the memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470.
  • the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying a data signal read from the memory cell.
  • the wiring is a wiring connected to a memory cell included in the memory cell array 1470, which will be described in detail later.
  • the amplified data signal is output to the outside of the storage device 1400 through the output circuit 1440 as the data signal RDATA.
  • the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.
  • the storage device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 as power supply voltages from the outside.
  • control signals CE, WE, RE
  • an address signal ADDR and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.
  • the control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row decoder and the column decoder.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as necessary.
  • the memory cell array 1470 includes a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC included in one column, and the like. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, and the like.
  • FIG. 24A illustrates an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited thereto.
  • a memory cell array 1470 may be provided so as to overlap with part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap below the memory cell array 1470.
  • FIG. 25 illustrates a configuration example of a memory cell applicable to the memory cell MC described above.
  • [DOSRAM] 25A to 25C show circuit configuration examples of DRAM memory cells.
  • a DRAM using a memory cell of 1 OS transistor and 1 capacitor element type is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
  • a memory cell 1471 illustrated in FIG. 25A includes a transistor M1 and a capacitor CA. Note that the transistor M1 includes a gate (sometimes referred to as a front gate) and a back gate.
  • the first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 Is connected to the wiring BGL.
  • a second terminal of the capacitor element CA is connected to the wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA.
  • a low level potential is preferably applied to the wiring CAL at the time of writing and reading of data.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
  • the memory cell 1471 shown in FIG. 25A corresponds to the memory device shown in FIG. That is, the transistor M1 corresponds to the transistor 200, the capacitor CA corresponds to the capacitor 100, the wiring BIL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, and the wiring CAL corresponds to the wiring 1005.
  • the transistor 300 in FIG. 18 corresponds to the transistor provided in the peripheral circuit 1411 of the memory device 1400 illustrated in FIG.
  • the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed.
  • the memory cell MC may have a structure in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL as in the memory cell 1472 illustrated in FIG.
  • the memory cell MC may be a memory cell including a single-gate transistor, that is, a transistor M1 having no back gate, like the memory cell 1473 illustrated in FIG.
  • the transistor 200 can be used as the transistor M1
  • the capacitor 100 can be used as the capacitor CA.
  • an OS transistor as the transistor M1
  • the leakage current of the transistor M1 can be very low. That is, since the written data can be held for a long time by the transistor M1, the frequency of refreshing the memory cells can be reduced. Also, the refresh operation of the memory cell can be made unnecessary.
  • leakage current is extremely low, multi-value data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.
  • the bit line can be shortened. As a result, the bit line capacitance is reduced, and the storage capacity of the memory cell can be reduced.
  • FIGS. 25D to 25H show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor.
  • a memory cell 1474 illustrated in FIG. 25D includes a transistor M2, a transistor M3, and a capacitor CB.
  • the transistor M2 includes a front gate (sometimes simply referred to as a gate) and a back gate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • the first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 Is connected to the wiring BGL.
  • a second terminal of the capacitor CB is connected to the wiring CAL.
  • the first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. It is preferable to apply a low-level potential to the wiring CAL during data writing, during data holding, and during data reading.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
  • the memory cell 1474 illustrated in FIG. 25D corresponds to the memory device illustrated in FIG. That is, the transistor M2 is the transistor 200, the capacitor CB is the capacitor 100, the transistor M3 is the transistor 300, the wiring WBL is the wiring 2003, the wiring WOL is the wiring 2004, the wiring BGL is the wiring 2006, and the wiring CAL is the wiring CAL.
  • the wiring RBL corresponds to the wiring 2002, and the wiring SL corresponds to the wiring 2001.
  • the memory cell MC is not limited to the memory cell 1474, and the configuration of the circuit can be changed as appropriate.
  • the memory cell MC may have a structure in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL as in the memory cell 1475 illustrated in FIG.
  • the memory cell MC may be a single-gate transistor, that is, a memory cell including a transistor M2 having no back gate, as in the memory cell 1476 illustrated in FIG.
  • the memory cell MC may have a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL as in the memory cell 1477 illustrated in FIG.
  • the transistor 200 can be used as the transistor M2
  • the transistor 300 can be used as the transistor M3
  • the capacitor 100 can be used as the capacitor CB.
  • an OS transistor as the transistor M2
  • the leakage current of the transistor M2 can be very low.
  • the written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced.
  • the refresh operation of the memory cell can be made unnecessary.
  • the leakage current is very low, multi-value data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.
  • the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter sometimes referred to as a Si transistor).
  • the conductivity type of the Si transistor may be an n-channel type or a p-channel type.
  • the Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a reading transistor. Further, by using a Si transistor as the transistor M3, the transistor M2 can be provided over the transistor M3, so that the area occupied by the memory cells can be reduced and the storage device can be highly integrated.
  • the transistor M3 may be an OS transistor.
  • OS transistors are used as the transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.
  • FIG. 25H shows an example of a gain cell type memory cell having three transistors and one capacitor.
  • a memory cell 1478 illustrated in FIG. 25H includes transistors M4 to M6 and a capacitor CC.
  • the capacitor element CC is provided as appropriate.
  • the memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL.
  • the wiring GNDL is a wiring that applies a low level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.
  • the transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.
  • the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively.
  • the transistors M4 to M6 may be OS transistors.
  • the memory cell array 1470 can be configured using only n-type transistors.
  • the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC.
  • the leakage current of the transistor M4 can be very low.
  • peripheral circuit 1411 the memory cell array 1470, and the like described in this embodiment are not limited to the above.
  • the arrangement or function of these circuits, wirings connected to the circuits, circuit elements, and the like may be changed, deleted, or added as necessary.
  • FIG. 4 An example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown with reference to FIG.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system on chip
  • a chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
  • the chip 1200 is provided with a bump (not shown), and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in FIG.
  • a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and connected to the motherboard 1203.
  • the motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222.
  • storage devices such as a DRAM 1221 and a flash memory 1222.
  • the DOSRAM described in the above embodiment can be used as the DRAM 1221.
  • the NOSRAM described in the above embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores. Further, each of the CPU 1211 and the GPU 1212 may have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. As the memory, the above-described NOSRAM or DOSRAM can be used.
  • the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum operation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention or a product-sum operation circuit, image processing and product-sum operation can be executed with low power consumption.
  • the wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, After the calculation in the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog operation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum operation circuit may be provided in the analog operation unit 1213.
  • the memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.
  • the interface 1215 has an interface circuit with external devices such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface or the like can be used.
  • the network circuit 1216 has a network circuit such as a LAN (Local Area Network).
  • a network security circuit may be included.
  • the above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be referred to as a GPU module 1204.
  • the GPU module 1204 includes the chip 1200 using the SoC technology, the size of the GPU module 1204 can be reduced. In addition, since it is excellent in image processing, it is preferably used for portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (carry-out) game machines.
  • a product-sum operation circuit using the GPU 1212 allows a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network (
  • DNN deep neural network
  • CNN convolutional neural network
  • RNN recursive neural network
  • DBM deep Boltzmann machine
  • the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.
  • the semiconductor device described in the above embodiment is, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording / playback device, a navigation system, and the like).
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device described in any of the above embodiments is applied to various types of removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • FIG. 27 schematically shows some configuration examples of the removable storage device.
  • the semiconductor device described in any of the above embodiments is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG. 27A is a schematic diagram of a USB memory.
  • the USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104.
  • the substrate 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1105 or the like of the substrate 1104.
  • FIG. 27 (B) is a schematic diagram of the appearance of the SD card
  • FIG. 27 (C) is a schematic diagram of the internal structure of the SD card.
  • the SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113.
  • the substrate 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113.
  • a wireless chip having a wireless communication function may be provided on the substrate 1113.
  • data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110.
  • the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1114 of the substrate 1113 or the like.
  • FIG. 27D is a schematic diagram of the external appearance of the SSD
  • FIG. 27E is a schematic diagram of the internal structure of the SSD.
  • the SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153.
  • the substrate 1153 is housed in the housing 1151.
  • a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156.
  • a DOSRAM chip may be used.
  • the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1154 or the like of the substrate 1153.
  • the semiconductor device can be used for a processor such as a CPU or a GPU, or a chip.
  • FIG. 28 illustrates a specific example of an electronic device including a processor such as a CPU or a GPU or a chip according to one embodiment of the present invention.
  • the GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices.
  • electronic devices include relatively large screens such as monitors for television devices, desktop or notebook information terminals, digital signage (digital signage), large game machines such as pachinko machines, and the like.
  • electronic devices including digital cameras, digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, portable information terminals, sound reproduction devices, and the like.
  • artificial intelligence can be mounted on the electronic device.
  • the electronic device of one embodiment of the present invention may have an antenna. By receiving a signal with an antenna, video, information, and the like can be displayed on the display unit.
  • the antenna may be used for non-contact power transmission.
  • the electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared).
  • the electronic device of one embodiment of the present invention can have various functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for executing various software (programs), and wireless communication A function, a function of reading a program or data recorded on a recording medium, and the like can be provided.
  • FIG. 28 illustrates an example of an electronic device.
  • FIG. 28A illustrates a mobile phone (smart phone) which is a kind of information terminal.
  • the information terminal 5100 includes a housing 5101 and a display portion 5102. As an input interface, a touch panel is provided in the display portion 5102 and buttons are provided in the housing 5101.
  • the information terminal 5100 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • an application using artificial intelligence for example, an application for recognizing a conversation and displaying the content of the conversation on the display unit 5102, a character or a figure input by the user on the touch panel provided in the display unit 5102, Examples include an application displayed on the display unit 5102 and an application for performing biometric authentication such as a fingerprint or a voiceprint.
  • FIG. 28B shows a notebook information terminal 5200.
  • the notebook information terminal 5200 includes an information terminal main body 5201, a display portion 5202, and a keyboard 5203.
  • the notebook information terminal 5200 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention, similarly to the information terminal 5100 described above.
  • Examples of the application using artificial intelligence include design support software, sentence correction software, menu automatic generation software, and the like. Further, by using the notebook information terminal 5200, new artificial intelligence can be developed.
  • a smartphone and a notebook information terminal are illustrated as examples of electronic devices in FIGS. 28A and 28B, respectively, but an information terminal other than the smartphone and the notebook information terminal is applied. be able to.
  • Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.
  • FIG. 28C illustrates a portable game machine 5300 which is an example of a game machine.
  • a portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like.
  • the housing 5302 and the housing 5303 can be detached from the housing 5301.
  • the connection portion 5305 provided in the housing 5301 to another housing (not shown)
  • the video output to the display portion 5304 can be output to another video equipment (not shown). it can.
  • the housing 5302 and the housing 5303 can each function as an operation unit. Thereby, a plurality of players can play a game simultaneously.
  • the chip described in any of the above embodiments can be incorporated in the housing 5301, the housing 5302, and a chip provided on a substrate of the housing 5303 or the like.
  • FIG. 28D illustrates a stationary game machine 5400 which is an example of a game machine.
  • a controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.
  • the portable game machine 5300 having artificial intelligence can be realized.
  • expressions such as the progress of a game, the behavior of a creature appearing in the game, and the phenomenon that occurs in the game are determined by the program of the game, but by applying artificial intelligence to the portable game machine 5300
  • Expressions that are not limited to game programs are possible. For example, it is possible to express the content that the player asks, the progress of the game, the timing of the occurrence of an event in the game, the behavior of a person appearing on the game, etc. without being limited to the game program. .
  • a game player can be formed artificially by artificial intelligence. Therefore, even if one player is made a game player using artificial intelligence, Can play games.
  • 28C and 28D illustrate a portable game machine and a stationary game machine as examples of game machines, a game machine to which the GPU or the chip of one embodiment of the present invention is applied. It is not limited to. Examples of the game machine to which the GPU or the chip of one embodiment of the present invention is applied include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, and the like. Is mentioned.
  • the GPU or the chip of one embodiment of the present invention can be applied to a large computer.
  • FIG. 28E illustrates a supercomputer 5500, which is an example of a large computer.
  • FIG. 28F illustrates a rack-mounted computer 5502 included in the supercomputer 5500.
  • the super computer 5500 includes a rack 5501 and a plurality of rack mount computers 5502.
  • a plurality of computers 5502 are stored in a rack 5501.
  • the computer 5502 is provided with a plurality of substrates 5504, and the GPU or the chip described in the above embodiment can be mounted on the substrates.
  • the supercomputer 5500 is a large computer mainly used for scientific and technical calculations. In science and technology calculations, it is necessary to process a large number of operations at high speed, so that power consumption is high and chip heat is large. By applying the GPU or the chip of one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. In addition, since heat generation from the circuit can be reduced with low power consumption, the influence of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced.
  • FIGS. 28E and 28F illustrate a supercomputer as an example of a large computer
  • a large computer to which a GPU or a chip of one embodiment of the present invention is applied is not limited to this.
  • Examples of a large computer to which the GPU or the chip of one embodiment of the present invention is applied include a computer (server) that provides a service, a large general-purpose computer (mainframe), and the like.
  • the GPU or the chip of one embodiment of the present invention can be applied to an automobile that is a moving body and the vicinity of a driver's seat of the automobile.
  • FIG. 28 (G) is a view showing the periphery of the windshield in the interior of an automobile which is an example of a moving object.
  • FIG. 28G illustrates a display panel 5704 attached to a pillar in addition to the display panel 5701, the display panel 5702, and the display panel 5703 attached to the dashboard.
  • Display panels 5701 to 5703 can provide various information by displaying speedometers, tachometers, travel distances, fuel gauges, gear states, air conditioner settings, and the like.
  • the display items, layout, and the like displayed on the display panel can be changed as appropriate according to the user's preference, and the design can be improved.
  • the display panels 5701 to 5703 can also be used as lighting devices.
  • the display panel 5704 On the display panel 5704, an image from an imaging device (not shown) provided in the automobile is displayed, so that the view (dead angle) blocked by the pillar can be complemented. That is, by displaying an image from an imaging device provided outside the automobile, the blind spot can be compensated for and safety can be improved. Also, by displaying a video that complements the invisible part, it is possible to confirm the safety more naturally and without a sense of incongruity.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used in an automatic driving system of an automobile. Moreover, the chip can be used in a system for performing road guidance, risk prediction, and the like.
  • the display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.
  • the automobile is described as an example of the moving body, but the moving body is not limited to the automobile.
  • the moving object include a train, a monorail, a ship, and a flying object (helicopter, unmanned aerial vehicle (drone), airplane, rocket).
  • the chip of one embodiment of the present invention is applied to these moving objects.
  • a system using artificial intelligence can be provided.
  • FIG. 28H illustrates an electric refrigerator-freezer 5800 that is an example of an electrical appliance.
  • An electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator compartment door 5802, a refrigerator compartment door 5803, and the like.
  • an electric refrigerator-freezer 5800 having artificial intelligence can be realized.
  • the electric refrigerator-freezer 5800 is stored in the electric refrigerator-freezer 5800, a function for automatically generating menus based on the ingredients stored in the electric refrigerator-freezer 5800, the expiration date of the ingredients, and the like. It can have a function of automatically adjusting the temperature to the food material.
  • an electric refrigerator-freezer has been described as an example of an electrical appliance
  • other electrical appliances include, for example, a vacuum cleaner, a microwave oven, a microwave oven, a rice cooker, a water heater, an IH cooker, a water server, an air conditioner including an air conditioner, Examples include washing machines, dryers, and audiovisual equipment.
  • the electronic device described in this embodiment the function of the electronic device, the application example of artificial intelligence, the effect, and the like can be combined with the description of other electronic devices as appropriate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
PCT/IB2019/054361 2018-06-08 2019-05-27 半導体装置 Ceased WO2019234547A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US17/056,072 US11495691B2 (en) 2018-06-08 2019-05-27 Semiconductor device
JP2020523839A JP7161529B2 (ja) 2018-06-08 2019-05-27 半導体装置
US17/895,126 US11967649B2 (en) 2018-06-08 2022-08-25 Semiconductor device
JP2022165216A JP7371201B2 (ja) 2018-06-08 2022-10-14 半導体装置
US18/638,997 US12453134B2 (en) 2018-06-08 2024-04-18 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018110077 2018-06-08
JP2018-110077 2018-06-08

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/056,072 A-371-Of-International US11495691B2 (en) 2018-06-08 2019-05-27 Semiconductor device
US17/895,126 Continuation US11967649B2 (en) 2018-06-08 2022-08-25 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2019234547A1 true WO2019234547A1 (ja) 2019-12-12

Family

ID=68770161

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2019/054361 Ceased WO2019234547A1 (ja) 2018-06-08 2019-05-27 半導体装置

Country Status (3)

Country Link
US (3) US11495691B2 (https=)
JP (2) JP7161529B2 (https=)
WO (1) WO2019234547A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540249A (zh) * 2020-06-29 2021-10-22 台湾积体电路制造股份有限公司 半导体器件及其形成方法、半导体存储器器件
WO2025186691A1 (ja) * 2024-03-08 2025-09-12 株式会社半導体エネルギー研究所 半導体装置
WO2025224597A1 (ja) * 2024-04-26 2025-10-30 株式会社半導体エネルギー研究所 半導体装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013102149A (ja) * 2011-10-13 2013-05-23 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の作製方法
JP2015181162A (ja) * 2014-03-06 2015-10-15 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2015188070A (ja) * 2014-03-07 2015-10-29 株式会社半導体エネルギー研究所 半導体装置
US20160322388A1 (en) * 2015-04-28 2016-11-03 Boe Technology Group Co., Ltd. Array substrate, its manufacturing method and display device
WO2016203341A1 (ja) * 2015-06-18 2016-12-22 株式会社半導体エネルギー研究所 半導体装置
JP2017112374A (ja) * 2015-12-16 2017-06-22 株式会社半導体エネルギー研究所 トランジスタ、半導体装置、および電子機器

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070090456A1 (en) 2005-08-29 2007-04-26 Jin-Yuan Lee Soi device and method for fabricating the same
US7999335B2 (en) 2007-12-05 2011-08-16 Semiconductor Energy Laboratory Co., Ltd. Micromachine and method for manufacturing the same
KR101473684B1 (ko) 2009-12-25 2014-12-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR101809105B1 (ko) 2010-08-06 2017-12-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 집적 회로
WO2013042562A1 (en) 2011-09-22 2013-03-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8860022B2 (en) 2012-04-27 2014-10-14 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and semiconductor device
KR101957972B1 (ko) 2012-06-05 2019-07-04 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
KR102244460B1 (ko) 2013-10-22 2021-04-23 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US9929279B2 (en) * 2014-02-05 2018-03-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP2015188062A (ja) * 2014-02-07 2015-10-29 株式会社半導体エネルギー研究所 半導体装置
WO2016128859A1 (en) 2015-02-11 2016-08-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
TWI695513B (zh) * 2015-03-27 2020-06-01 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置
SG10201608814YA (en) 2015-10-29 2017-05-30 Semiconductor Energy Lab Co Ltd Semiconductor device and method for manufacturing the semiconductor device
JPWO2019048987A1 (ja) 2017-09-06 2020-10-15 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
WO2019197946A1 (ja) 2018-04-12 2019-10-17 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013102149A (ja) * 2011-10-13 2013-05-23 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の作製方法
JP2015181162A (ja) * 2014-03-06 2015-10-15 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2015188070A (ja) * 2014-03-07 2015-10-29 株式会社半導体エネルギー研究所 半導体装置
US20160322388A1 (en) * 2015-04-28 2016-11-03 Boe Technology Group Co., Ltd. Array substrate, its manufacturing method and display device
WO2016203341A1 (ja) * 2015-06-18 2016-12-22 株式会社半導体エネルギー研究所 半導体装置
JP2017112374A (ja) * 2015-12-16 2017-06-22 株式会社半導体エネルギー研究所 トランジスタ、半導体装置、および電子機器

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540249A (zh) * 2020-06-29 2021-10-22 台湾积体电路制造股份有限公司 半导体器件及其形成方法、半导体存储器器件
US12015065B2 (en) 2020-06-29 2024-06-18 Taiwan Semiconductor Manufacturing Company Limited Tri-gate orthogonal channel transistor and methods of forming the same
CN113540249B (zh) * 2020-06-29 2024-09-06 台湾积体电路制造股份有限公司 半导体器件及其形成方法、半导体存储器器件
WO2025186691A1 (ja) * 2024-03-08 2025-09-12 株式会社半導体エネルギー研究所 半導体装置
WO2025224597A1 (ja) * 2024-04-26 2025-10-30 株式会社半導体エネルギー研究所 半導体装置

Also Published As

Publication number Publication date
JPWO2019234547A1 (ja) 2021-06-24
US20210210640A1 (en) 2021-07-08
US11495691B2 (en) 2022-11-08
JP7161529B2 (ja) 2022-10-26
JP7371201B2 (ja) 2023-10-30
US11967649B2 (en) 2024-04-23
JP2022183244A (ja) 2022-12-08
US20240304728A1 (en) 2024-09-12
US20220416089A1 (en) 2022-12-29
US12453134B2 (en) 2025-10-21

Similar Documents

Publication Publication Date Title
CN112368846B (zh) 半导体装置及半导体装置的制造方法
JP7581215B2 (ja) 半導体装置
CN111788698B (zh) 半导体装置及半导体装置的制造方法
WO2019234561A1 (ja) 半導体装置、および半導体装置の作製方法
US12490475B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP2024052817A (ja) 半導体装置
JP7371201B2 (ja) 半導体装置
US12278291B2 (en) Thin film transistor array having a stacked multi-layer metal oxide channel formation region
JP7235418B2 (ja) 半導体装置の作製方法
JPWO2020049396A1 (ja) 半導体装置、および半導体装置の作製方法
WO2019197946A1 (ja) 半導体装置、および半導体装置の作製方法
WO2019224656A1 (ja) 半導体装置、および半導体装置の作製方法
WO2020075022A1 (ja) トランジスタ、半導体装置、および電子機器
JP2019201062A (ja) 半導体装置、および半導体装置の作製方法
US11929416B2 (en) Semiconductor device and method for manufacturing semiconductor device
WO2020109923A1 (ja) 半導体装置、および半導体装置の作製方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19814622

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020523839

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19814622

Country of ref document: EP

Kind code of ref document: A1