WO2019227939A1 - 移位寄存器单元、电路结构、栅极驱动电路、驱动电路及显示装置 - Google Patents

移位寄存器单元、电路结构、栅极驱动电路、驱动电路及显示装置 Download PDF

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Publication number
WO2019227939A1
WO2019227939A1 PCT/CN2019/070895 CN2019070895W WO2019227939A1 WO 2019227939 A1 WO2019227939 A1 WO 2019227939A1 CN 2019070895 W CN2019070895 W CN 2019070895W WO 2019227939 A1 WO2019227939 A1 WO 2019227939A1
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Prior art keywords
conductive portion
connection conductive
transistor
circuit
signal
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2019/070895
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English (en)
French (fr)
Chinese (zh)
Inventor
先建波
许晨
郝学光
乔勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
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Application filed by BOE Technology Group Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP19732243.1A priority Critical patent/EP3806078A4/en
Priority to KR1020197037441A priority patent/KR102314548B1/ko
Priority to JP2019570504A priority patent/JP7303127B2/ja
Priority to US16/475,513 priority patent/US11488513B2/en
Publication of WO2019227939A1 publication Critical patent/WO2019227939A1/zh
Anticipated expiration legal-status Critical
Priority to US17/807,908 priority patent/US11705048B2/en
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/007—Use of pixel shift techniques, e.g. by mechanical shift of the physical pixels or by optical shift of the perceived pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a circuit structure, a gate driving circuit, a driving circuit, and a display device.
  • a pixel array of a display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines interlaced therewith.
  • the gate line can be driven by an integrated driving circuit.
  • the gate driving circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate Driver On Array) to drive the gate lines.
  • GOA Gate Driver On Array
  • a GOA circuit composed of a plurality of cascaded shift register units may be used to provide switching state voltage signals to multiple rows of gate lines of a pixel array, thereby controlling the multiple rows of gate lines to sequentially turn on.
  • At least one embodiment of the present disclosure provides a shift register unit, which can flexibly select a position for connecting conductive parts according to the distance between the transistors, and avoids that the connecting conductive parts connected to each transistor are provided on the same layer, thereby simplifying the display panel. Routing design and improve the accuracy of signal transmission.
  • At least one embodiment of the present disclosure provides a shift register unit, which includes a base substrate and an input circuit, a reset circuit, and a first output circuit, a first output terminal, a first output terminal, and the input circuit disposed on the base substrate.
  • the input circuit is configured to control a level of a first node in response to an input signal; the reset circuit is configured to reset the first node in response to a reset signal; and the first output circuit is configured to Under the control of the level of the first node, outputting a first signal to the first output terminal; in the first connection conductive portion, the second connection conductive portion, and the third connection conductive portion Of any two or three different layers.
  • the shift register unit provided by an embodiment of the present disclosure further includes a first signal line input terminal and a fourth connection conductive portion.
  • the fourth connection conductive portion connects the first output circuit and the first signal line input terminal, and is configured to be connected to the first connection conductive portion, the second connection conductive portion, and the third connection. Any two or three different layers of the conductive portion are provided.
  • the shift register unit provided by an embodiment of the present disclosure further includes an output noise reduction circuit and a fifth connection conductive portion.
  • the output noise reduction circuit is configured to perform noise reduction on the first output terminal under the control of the level of the second node; the fifth connection conductive part connects the output noise reduction circuit and the first
  • the output circuit is configured to be disposed in a different layer from any two or three of the first connection conductive portion, the second connection conductive portion, and the third connection conductive portion.
  • the shift register unit provided by an embodiment of the present disclosure further includes a control circuit, a second signal line input terminal, and a sixth connection conductive portion.
  • the control circuit is configured to control the level of the second node under the control of the level of the first node and / or the second signal; the sixth connection conductive portion is configured to connect to the The control circuit and the second signal line input end are arranged in different layers from the fourth connection conductive portion.
  • a length of the first connection conductive portion is shorter than a length of the second connection conductive portion; or the first signal includes a clock signal, a voltage signal, At least one of a current signal; or the second signal includes at least one of a clock signal, a voltage signal, and a current signal.
  • At least one embodiment of the present disclosure further provides a circuit structure including a base substrate, a first transistor, a second transistor, a third transistor, and a storage capacitor, a first output terminal, and a first connection disposed on the base substrate.
  • the first connection conductive portion is configured to connect a first pole of the first transistor and a first electrode of the second transistor; and the second connection conductive portion is configured to connect a first pole of the second transistor.
  • the third connection conductive portion is configured to connect the first output terminal and the first electrode of the third transistor; the Any two or three of the first connection conductive portion, the second connection conductive portion, and the third connection conductive portion are disposed in different layers.
  • the circuit structure provided by an embodiment of the present disclosure further includes a fourth transistor, a first signal line input terminal, a fourth connection conductive portion, and a fifth connection conductive portion.
  • the fourth connection conductive portion is configured to connect the second pole of the third transistor and the first signal line input terminal, and is connected to the first connection conductive portion, the second connection conductive portion, and the first connection line. Any two or three different layers of the third connection conductive portion are provided; the fifth connection conductive portion is configured to connect the first pole of the third transistor and the first pole of the fourth transistor, and Any two or three of the first connection conductive portion, the second connection conductive portion, and the third connection conductive portion are disposed in different layers.
  • the circuit structure provided by an embodiment of the present disclosure further includes a fifth transistor, a sixth transistor, a second signal line input terminal, and a sixth connection conductive portion.
  • the first pole of the fifth transistor is connected to the first pole of the sixth transistor through the first connection conductive portion; the sixth connection conductive portion is configured to connect the gate of the sixth transistor and the gate of the sixth transistor.
  • the second signal line input terminal is disposed in a different layer from the fourth connection conductive portion.
  • the first pole of the third transistor is disposed on the same layer as the second connection conductive portion; or the first connection conductive portion and the first transistor
  • the semiconductor layer is made of the same material.
  • the circuit structure provided by an embodiment of the present disclosure further includes a seventh transistor, a third signal line input terminal, and a seventh connection conductive portion.
  • the gate of the seventh transistor is configured to be connected to the first output terminal to receive an output signal of the circuit structure, and the first pole of the seventh transistor is configured to be connected to the conductive portion through the seventh connection.
  • An input terminal of the third signal line is connected to receive a third signal, and a second pole of the seventh transistor is configured to be connected to a second output terminal.
  • all The seventh connection conductive portion is configured to be disposed at a different layer from the fourth connection conductive portion.
  • a circuit structure provided by an embodiment of the present disclosure further includes an eighth transistor; a gate of the eighth transistor is configured to be connected to a second node through the second connection conductive portion, and the first One pole is configured to be connected to the second output terminal, and the second pole of the eighth transistor is configured to be connected to a first voltage terminal to receive a first voltage.
  • At least one embodiment of the present disclosure provides a gate driving circuit including a plurality of cascaded shift register units provided by any one of the embodiments of the present disclosure.
  • the gate driving circuit further includes a second output circuit, a third signal line input terminal, and a seventh connection conductive portion.
  • the second output circuit is configured to output a third signal to the second output terminal under the control of the level output from the first output terminal; when the shift register unit includes a fourth connection conductive portion
  • the seventh connection conductive portion is configured to connect the third signal line input terminal and the second output circuit, and is disposed at a different layer from the fourth connection conductive portion.
  • At least one embodiment of the present disclosure also provides a driving circuit including a plurality of cascaded circuit structures provided by any one of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure provides a display device including a gate driving circuit or a driving circuit provided by any one of the embodiments of the present disclosure, and the gate driving circuit or the driving circuit is disposed on four sides of an array substrate.
  • a display device further includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer.
  • the first conductive layer Same material as the active layer
  • the second conductive layer is the same as the first gate line layer
  • the third conductive layer is the same as the second gate line layer
  • the fourth conductive layer is the same as the first data line layer
  • the fifth conductive layer is made of the same material as the second data line layer
  • the sixth conductive layer is made of the same material as the pixel electrode.
  • FIG. 1 is a schematic diagram of an example of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of another example of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 3 is a circuit diagram of an implementation example of the shift register unit shown in FIG. 1; FIG.
  • 4A is a schematic cross-sectional structure diagram of an example of an array substrate taken along line A1-A2 in FIG. 3;
  • 4B is a schematic cross-sectional structure view of the array substrate taken along the line C1-C2 in FIG. 3;
  • 4C is a schematic cross-sectional structure view of the array substrate taken along line D1-D2 in FIG. 3;
  • 4D is a schematic cross-sectional structure diagram of a conductive layer where each connection conductive portion is provided according to an embodiment of the present disclosure
  • FIG. 5 is a schematic circuit diagram of an implementation example of the shift register unit shown in FIG. 2; FIG.
  • FIG. 6 is a schematic diagram of still another example of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 7 is a circuit diagram of an implementation example of the shift register unit shown in FIG. 6; FIG.
  • FIG. 8 is a circuit diagram of another implementation example of the shift register unit shown in FIG. 6; FIG.
  • 9A is a schematic diagram of an example of a gate driving circuit according to an embodiment of the present disclosure.
  • 9B is a schematic diagram of another example of a gate driving circuit according to an embodiment of the present disclosure.
  • 9C is a schematic diagram of still another example of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 10A is a schematic block diagram of a gate driving circuit shown in FIG. 9B or 9C;
  • FIG. 10B is a circuit diagram of an implementation example of the gate driving circuit shown in FIG. 10A;
  • FIG. 11A is a signal timing chart corresponding to the operation of the gate driving circuit shown in FIG. 9B;
  • FIG. 11B is a signal timing chart corresponding to the operation of the gate driving circuit shown in FIG. 9C.
  • FIG. 12 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • GOA Gate Driver On Array
  • the gate drive circuit is integrated on the display panel through a thin film transistor process, so that narrow bezels and reduced assembly costs can be achieved.
  • At least one embodiment of the present disclosure provides a shift register unit including a base substrate and an input circuit, a reset circuit and a first output circuit, a first output terminal, a first output terminal, and a first circuit connected to the input circuit and the reset circuit.
  • the input circuit is configured to control the level of the first node in response to the input signal; the reset circuit is configured to reset the first node in response to the reset signal; the first output circuit is configured to be at the level of the first node Under control, the first signal is output to the first output terminal; any two or three of the first connection conductive portion, the second connection conductive portion, and the third connection conductive portion are arranged in different layers.
  • At least one embodiment of the present disclosure also provides a circuit structure, a gate driving circuit, and a display device.
  • the shift register unit provided in the embodiment of the present disclosure can flexibly select a position for connecting the conductive parts according to the distance between the transistors, thereby avoiding that multiple connection conductive parts connected to each transistor are provided on the same layer, thereby simplifying the wiring of the display panel Design and improve the accuracy of signal transmission.
  • FIG. 1 is a schematic block diagram of an example of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit 100 includes a base substrate (not shown in FIG. 1) and an input circuit 110, a reset circuit 120, a first output circuit 130, and a first output terminal provided on the base substrate. OUT1.
  • the shift register unit 100 is formed as a constituent unit of a gate driving circuit on an array substrate of a display device.
  • the array substrate includes the above-mentioned base substrate, and has an array region (display region) and a peripheral region.
  • the gate driving circuit is formed in a peripheral region of the array substrate, and the pixel circuit is formed in an array region of the array substrate.
  • the pixel circuit may include at least one transistor, such as a switching transistor, and may further include components such as a driving transistor.
  • the thin film transistor in the array region and the thin film transistor in the peripheral region can be obtained through a semiconductor fabrication process.
  • the shift register unit 100 further includes a first connection conductive portion 1 connecting the input circuit 110 and the reset circuit 120, a second connection conductive portion 2 connecting the reset circuit 120 and the first output circuit 130, and a first connection conductive portion 2.
  • An output circuit 130 is connected to the third conductive portion 3 of the first output terminal OUT1.
  • the third connection conductive portion 3 may be integrated with the gate line of the array substrate in the array area, or the third connection conductive portion 3 may be electrically connected to the gate line of the array substrate in the array area through a via, a connection line, or the like .
  • the first connection conductive portion 1, the second connection conductive portion 2, and the third connection conductive portion 3 are disposed on a base substrate, and any two or three of them are disposed in different layers.
  • the first connection conductive portion 1 and the second connection conductive portion 2 are disposed in different layers, and the third connection conductive portion 3 may be disposed in the same layer or a different layer from any of the first connection conductive portion 1 and the second connection conductive portion 2.
  • the first connection conductive portion 1, the second connection conductive portion 2, and the third connection conductive portion 3 are all disposed on different layers, which are not limited in the embodiments of the present disclosure.
  • the embodiments of the present disclosure are not limited to the number and connection manner of the first connection conductive portion 1, the second connection conductive portion 2, and the third connection conductive portion 3.
  • the first connection conductive portion 1 indicates that there is at least one first connection conductive portion 1 for electrical connection between the input circuit 110 and the reset circuit 120, and the number and manner of connection are not limited; that is, there is at least one input circuit
  • the connection conductive parts in the following embodiments are the same, and will not be described again.
  • the length of the first connection conductive portion is smaller than the length of the second connection conductive portion.
  • the length indicates the extension distance from the beginning to the end of the connection conductive portion, or the extension distance between the vias at the junction of the transistor elements in the circuit, so that the connection to the conductive portion can be flexibly selected according to the extension distance between the transistors. s position.
  • the extension distance depends on the shape (for example, line shape, S shape, etc.) of the connection conductive portion, rather than a straight line distance between the two ends.
  • the input circuit 110 is configured to control a level of a first node (not shown in FIG. 1, see FIG. 3) in response to an input signal, for example, to charge the first node.
  • the first node is a meeting point of the first connection conductive portion 1 and the second connection conductive portion 2, and belongs to both the first connection conductive portion 1 and the second connection conductive portion 2, and does not indicate an actually existing component.
  • the input circuit 110 may be respectively connected to the input terminal INPUT and the first connection conductive part 1 (ie, the first node), and is configured to transmit the voltage signal received by the input circuit 110 to the first node.
  • the reset circuit 120 is configured to reset the first node in response to a reset signal.
  • the reset circuit 120 may be configured to be connected to the reset terminal RST, the first connection conductive portion 1 (that is, the first node), and the second connection conductive portion 2 (that is, the first node), so that the reset terminal RST can be input.
  • the first node Under the control of the reset signal, the first node is applied with a low-level signal or is electrically connected to a low voltage terminal.
  • the low voltage terminal is, for example, the first voltage terminal VGL or a reference voltage terminal, so that the first node can be pulled down and reset. .
  • the embodiment of the present disclosure is described by taking an N-type transistor as an example. It should be noted that the embodiments of the present disclosure are not limited thereto, and a circuit structure of a P-type or mixed N-type and P-type transistor may also be adopted, and only the corresponding transistor needs to be Just turn on the low level.
  • controlling the level of a node includes charging the node to raise the level of the node, or Discharge the node to pull the node down.
  • Charging a node means, for example, electrically connecting the node with a high-level voltage signal, so that the high-level voltage signal is used to raise the level of the node;
  • discharging a node means, for example, connecting the node with A low-level voltage signal is electrically connected, so that the low-level voltage signal is used to pull down the level of the node.
  • a capacitor electrically connected to the node may be provided, and charging or discharging the node means charging or discharging the capacitor electrically connected to the node.
  • the high level and the low level are relative.
  • the high level indicates a higher voltage range (for example, the high level can be 5V, 10V, or other suitable voltages), and multiple high levels can be the same or different.
  • the low level indicates a lower voltage range (for example, the low level may adopt 0V, -5V, -10V, or other suitable voltages), and multiple low levels may be the same or different.
  • the minimum value of the high level is greater than the maximum value of the low level.
  • the first output circuit 130 is configured to output a first signal to the first output terminal OUT1 under the control of the level of the first node.
  • the first signal may include a first clock signal or other voltage signals (for example, High level signal).
  • the first output circuit 130 may be configured to be connected to the second connection conductive portion 2 (ie, the first node), the third connection conductive portion 3 (ie, the first output terminal OUT1), and the first signal line input terminal CLK1, respectively.
  • the first clock signal input from the first signal line input terminal CLK1 or other voltage signals input to the first output circuit 130 can be output to the first output terminal OUT1, so that As an output signal of the shift register unit 100, the output signal is input to other circuit structures connected to the first output circuit 130 (for example, a second output circuit, which will be described in detail later) .
  • the first output circuit 130 may be configured to be turned on under the control of the level of the first node, so that the first signal line input terminal CLK1 and the first output terminal OUT1 are electrically connected, so that the first signal line can be input.
  • the first signal input from the terminal CLK1 is output to the first output terminal OUT1 as an output signal of the shift register unit.
  • the first signal may include at least one of a clock signal, a voltage signal, or a current signal, which depends on specific situations, which is not limited in the embodiments of the present disclosure.
  • the clock signal may be a first clock signal
  • the voltage signal may be a first voltage (for example, a low voltage) or a second voltage (for example, a high voltage, for example, the first voltage is lower than the second voltage). ), Or other reference voltage.
  • FIG. 2 is a schematic diagram of another example of a shift register unit according to an embodiment of the present disclosure.
  • the shift register 100 may further include a fourth connection conductive portion 4.
  • the fourth connection conductive portion 4 is configured to connect the first output circuit 130 and the first signal line input terminal CLK1, and is connected to any two of the first connection conductive portion 1, the second connection conductive portion 2, and the third connection conductive portion 3.
  • the fourth connection conductive portion 4 is not provided on the same layer as the first connection conductive portion 1 and the second connection conductive portion 2.
  • the shift register 100 may further include an output noise reduction circuit 140 and a fifth connection conductive portion 5.
  • the fifth connection conductive portion 5 is configured to connect the output noise reduction circuit 140 and the first output circuit 130, and is connected to at least one of the first connection conductive portion 1, the second connection conductive portion 2, and the third connection conductive portion 3. Two different layers set.
  • the fifth connection conductive portion 5 is not provided on the same layer as the first connection conductive portion 1 and the second connection conductive portion 2.
  • the output noise reduction circuit 140 is configured to perform noise reduction on the first output terminal OUT1 under the control of the level of the second node PD.
  • the output noise reduction circuit 140 may be configured to electrically connect the first output terminal OUT1 and the first voltage terminal VGL under the control of the level of the second node PD, thereby performing pull-down noise reduction on the first output terminal OUT1.
  • the second node PD may be connected to a signal line input terminal or other circuits that can generate a level that controls the output noise reduction unit 140, which is not limited in the embodiments of the present disclosure.
  • the second node for example, the output noise reduction circuit 140 may be further configured to make at least two of the first output terminal OUT1 and the first voltage terminal VGL or other fixed voltage signals under the control of the level of the second node PD. Connected to pull down and reduce noise on the first output terminal OUT1.
  • FIG. 3 is a circuit diagram of an implementation example of the shift register unit shown in FIG. 1.
  • each transistor is described as an N-type transistor, but it does not constitute a limitation on the embodiment of the present disclosure.
  • Each transistor may also be a P-type transistor.
  • N-type transistors can use oxide as the active layer of the thin film transistor.
  • indium gallium zinc oxide (IGZO) is used as the active layer of the thin film transistor.
  • Polysilicon such as low temperature polysilicon LTPS or high temperature polysilicon HTPS
  • amorphous Silicon such as hydrogenated amorphous silicon
  • the active layer using indium gallium zinc oxide (IGZO) can effectively reduce the size of the transistor and prevent leakage current.
  • the shift register unit 100 includes first to third transistors T1 to T3 and a storage capacitor C.
  • the input circuit 110 may be implemented as a first transistor T1.
  • the gate and the first pole of the first transistor T1 are electrically connected to each other, and are configured to both be connected to the input terminal INPUT to receive an input signal, and the second pole is configured to connect the conductive portion 1 and the first node PU (that is, (The first pole of the second transistor) is connected so that when the first transistor T1 is turned on under the control of a turn-on signal (high-level signal) received at the input terminal INPUT, the turn-on signal is used to connect the first node PU Charging is performed so that the first node PU is at a high level.
  • the gate or the first pole of the first transistor T1 may be configured to be connected to at least one signal or a combination of a clock signal, a second voltage terminal VGH, or other fixed voltage signals, for example, the first transistor T1
  • the gate of is connected to the first signal terminal CLK1 to receive the clock signal
  • the first electrode of the first transistor T1 is connected to the second voltage terminal VGH to receive the second voltage.
  • connection conductive part can be used (it should be noted that these different parts are based on Need to be independent of each other or electrically connected to each other) for connection, for example, the first pole of the fifth transistor T5 and the first pole of the sixth transistor T6 shown in FIG. 7 can be connected using the first connection conductive part 1, and the remaining connections The conductive part can also do this.
  • the following embodiments are the same, and will not be described again.
  • the reset circuit 120 may be implemented as a second transistor T2.
  • the gate of the second transistor T2 is configured to be connected to the reset terminal RST to receive a reset signal
  • the first pole is configured to be connected to the first node PU through the first connection conductive portion 1
  • the second pole is configured to be connected to the first voltage
  • the terminal VGL is connected to receive a first voltage.
  • the output circuit 130 may be implemented as a third transistor T3.
  • the gate of the third transistor T3 is configured to be connected to the first node PU through the second connection conductive part 2, the first pole is configured to be connected to the first signal line input terminal CLK1 to receive the first signal, and the second pole is configured It is connected to the first output terminal OUT1 through the third connection conductive part 3.
  • the storage capacitor C may be part of the output circuit 130.
  • the storage capacitor C may also be an independent component of the shift register unit 100; or the storage capacitor C and other components form a component of the shift register unit 100.
  • the second pole of the storage capacitor C is configured to be connected to the first output terminal OUT1 through the third connection conductive portion 3, and the first pole is configured to be connected to the gate of the third transistor T3.
  • the first pole of the storage capacitor C is configured to be connected to the second connection conductive portion 2, and the second pole is connected to the clock signal terminal.
  • the first extremely transparent conductive layer and the second extremely first data line layer or gate line layer of the storage capacitor C are not limited in the embodiments of the present disclosure.
  • the first pole of the third transistor T3 is configured to be connected to the first signal line input terminal CLK1 through the fourth connection conductive portion 4 to receive the first signal.
  • different parts of the second connection conductive part 2 may be used (to be noted, these The different parts are independent of each other or electrically connected to each other as needed) for connection, for example, the second pole of the sixth transistor T6 and the gate of the fourth transistor T4 shown in FIG. 10B may be connected using the second connection conductive part 2, and the first The second electrode of the six transistor T6 and the gate of the eighth transistor T8 may be connected by the second connection conductive portion 2.
  • the first transistor T1 includes structures such as a first electrode 101, a second electrode 102, a gate 103, an active layer 111, and the like.
  • the second transistor T2 includes structures such as a first electrode 201, a second electrode 202, a gate electrode 203, and an active layer 111.
  • the first pole 101 of the first transistor T1 and the first pole 201 of the second transistor T2 are connected by the first connection conductive portion 1.
  • the start end of the first connection conductive portion 1 is a region corresponding to the first pole (for example, the drain) of the first transistor T1
  • the end end of the first connection conductive portion 1 is the first pole (for example, the source) of the second transistor T2. Pole) corresponding area. As shown in FIG.
  • the first connection conductive portion 1 includes a first electrode 101 (eg, a drain) of the first transistor T1 and a first electrode 201 (eg, a source) of the second transistor T2, that is, the first connection conductive portion 1 It is formed integrally with the first pole 101 of the first transistor T1 and the first pole 201 of the second transistor T2.
  • the first electrode 101 (for example, the drain) of the first transistor T1 and the first electrode 201 (for example, the source) of the second transistor T2 may be separately formed, and then pass through the first connection conductive part 1 respectively. Holes, laps, or integral formation are used for electrical connection, which are not limited in the embodiments of the present disclosure.
  • the first electrode 101 and the active layer of the first transistor T1 are connected to each other to establish an electrical connection; similarly, the first electrode 201 and the active layer of the second transistor T2 are connected to each other to establish an electrical connection.
  • the first connection conductive portion 1 includes an active layer conductive portion between the first transistor T1 and the second transistor T2.
  • the first connection conductive portion 1 and the second connection conductive portion 2 are disposed in different layers.
  • the first connection conductive portion 1 is in the same layer as the active layer 11 of the first transistor T1 and the second transistor T2, and the second connection conductive portion 2 is formed on the second passivation layer 1132 and passes through a second passivation layer.
  • the vias in the formation layer 1132, the first passivation layer 1131, and the gate insulating layer 112 are electrically connected to the first connection conductive portion 1.
  • the first connection conductive portion 1 is located on the first conductive layer 11 shown in FIG. 4D
  • the second connection conductive portion 2 is located on the fourth conductive layer 14 shown in FIG. 4D
  • the gate insulating layer 112 corresponds to FIG. 4D
  • the first insulating layer 21, the first passivation layer 1131 correspond to the second insulating layer 22 in FIG. 4D
  • the second passivation layer 1132 corresponds to the third insulating layer 23 in FIG. 4D.
  • one end (eg, the start end) of the second connection conductive portion 2 is formed between the gates of the first transistor T1 and the second transistor T2.
  • the gates of the second connection conductive part 2 and the third transistor T3 are electrically connected or formed integrally with each other, which is not limited in the embodiments of the present disclosure.
  • FIG. 4B is a schematic cross-sectional structure view of the array substrate taken along the line C1-C2 in FIG. 3.
  • the third transistor T3 includes structures such as a first electrode 301, a second electrode 302, a gate electrode 303, and an active layer 111.
  • the gate 303 of the third transistor, the gate 103 of the first transistor, and the gate 203 of the second transistor are provided in different layers.
  • the gate 303 of the third transistor is formed on the first passivation layer 1131.
  • the first pole 301 and the second pole 303 of the third transistor T3 are electrodes formed separately.
  • the first pole 301 and the second pole 302 of the third transistor T3 are formed on the second passivation layer 1132. And is connected to the active layer through vias on the second passivation layer 1132, the first passivation layer 1131, and the gate insulating layer 112.
  • the width-length ratio of the first transistor T1 is smaller than that of the third transistor T3.
  • the width-length ratio of the third transistor T3 is 3-50 times the width-length of the first transistor T1.
  • the width-length ratio of the first transistor T1 It is 0.6-1.2, and the aspect ratio of the third transistor T3 is 3-30.
  • the first electrode (for example, the drain) of the third transistor T3 and the second connection conductive part 2 are disposed on the same layer.
  • a third connection conductive portion 3 is further included.
  • the first electrode 301 of the third transistor T3 is electrically connected to the third connection conductive portion 3, and is connected to the first output terminal OUT1 through the third connection conductive portion 3.
  • the first electrode 301 of the third transistor T3 and the third connection conductive portion 3 may also be formed integrally, and thus both of them may be formed in the same layer, which is not limited in the embodiment of the present disclosure.
  • the third connection conductive portion 3 is formed on the third passivation layer 1133 and is connected to the first electrode 301 of the third transistor T3 through a via hole. Since the first electrode (for example, the drain) of the third transistor T3 is disposed on the same layer as the second connection conductive portion 2, the third connection conductive portion 3 and the second connection conductive portion 2 are disposed in different layers and connected to the first The conductive part 1 has a different layer, so that the connection conductive parts connected to each transistor can be prevented from being disposed on the same layer, thereby simplifying the wiring design of the display panel and improving the accuracy of signal transmission. It should be noted that, as long as any two or three different layers of the first connection conductive portion 1, the second connection conductive portion 2, and the third connection conductive portion 3 are satisfied, the embodiment of the present disclosure does not limit this. .
  • a fourth connection conductive portion 4 may be further included.
  • the fourth connection conductive portion 4 is formed on the third passivation layer 1133 and is connected to the second electrode 302 of the third transistor T3 through a via.
  • the fourth connection conductive portion 4 is connected to the first signal line input terminal CLK1. Connect to receive the first signal.
  • the second electrode 302 of the third transistor T3 and the fourth connection conductive portion 4 may also be formed integrally, which is not limited in the embodiments of the present disclosure.
  • the third connection conductive portion 3 and the fourth connection conductive portion 4 are provided on the same layer, and are provided at different layers from the first connection conductive portion 1 and the second connection conductive portion 2.
  • connection conductive portion 4 only needs to be provided in any two or three layers of the first connection conductive portion 1, the second connection conductive portion 2, and the third connection conductive portion 3.
  • the disclosed embodiments are not limited thereto.
  • a passivation layer may also be included between the second connection conductive part 2 and the gate 103 of the first transistor, for example, only the first passivation layer 1131 or the second passivation layer 1132 may be included.
  • FIG. 4C is a schematic cross-sectional structure view of the array substrate taken along line D1-D2 in FIG. 3.
  • the second connection conductive portion 2 and the third connection conductive portion 3 constitute a storage capacitor C.
  • a third passivation layer 1133 is formed on the second connection conductive portion 2, and a third connection conductive portion 3 is formed on the third passivation layer 1133.
  • the materials used for the first passivation layer 1131, the second passivation layer 1132, and the third passivation layer 1133 include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resin, or other suitable materials.
  • inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resin, or other suitable materials.
  • organic insulating materials such as organic resin, or other suitable materials.
  • the array substrate includes a plurality of layer structures in sequence from bottom to top, including but not limited to a first conductive layer 11, a first insulating layer 21, a second conductive layer 12, a second insulating layer 22, The third conductive layer 13, the third insulating layer 23, the fourth conductive layer 14, the fourth insulating layer 24, the fifth conductive layer 15, the fifth insulating layer 25, the sixth conductive layer 16, and the like.
  • the first conductive layer 11 is the same material as the active layer
  • the second conductive layer 12 is the same material as the first gate line layer
  • the third conductive layer 13 is the same material as the second gate line layer
  • the fourth conductive layer 14 is the same as the first
  • the material of the data line layer is the same
  • the material of the fifth conductive layer 15 is the same as that of the second data line layer
  • the material of the sixth conductive layer 16 is the same as that of the pixel electrode.
  • conductive layers located on different layers but connected to each other can be electrically connected through vias (not shown in the figure).
  • other structures may be included under the first conductive layer 11.
  • Each of the above-mentioned conductive layers may include at least a part of a conductive structure.
  • the first connection conductive portion 1 is located on the first conductive layer 11.
  • the first connection conductive portion 1 and the semiconductor layer of the first transistor are made of the same material.
  • a part of the structure of the semiconductor layer is conductorized to form the first connection conductive portion 1.
  • the semiconductor layer may be a conductive portion of an active layer.
  • the gate 103 of the first transistor T1 and the gate 203 of the second transistor T2 are located on the second conductive layer 12 or the third conductive layer 13, and the gate 303 of the third transistor T3 is located on the third conductive layer 13 or the second conductive layer 12.
  • the second connection conductive portion 2 is located on the fourth conductive layer 14, the third connection conductive portion 3 is located on the fifth conductive layer 15, and the fourth connection conductive portion 4 is also located on the fifth conductive layer 15.
  • the embodiments of the present disclosure include, but are not limited to, as long as any two or three of the first connection conductive portion 1, the second connection conductive portion 2, and the third connection conductive portion 3 are not in the same conductive layer.
  • any two or three of the fourth connection conductive portion 4 and the first connection conductive portion 1, the second connection conductive portion 2, and the third connection conductive portion 3 may be disposed on different conductive layers, and the implementation of the present disclosure The example does not limit this.
  • the materials of the first conductive layer 11 to the sixth conductive layer 16 include aluminum, aluminum alloy, copper, copper alloy, or any other suitable material, which is not limited in the embodiments of the present disclosure. It should be noted that the number of layers of the conductive layer and the insulating layer may depend on specific circumstances, which is not limited in the embodiments of the present disclosure.
  • the gate insulation layer 112 is located on the first insulation layer 21, the first passivation layer 1131 is located on the second insulation layer 22, and the second passivation layer 1132 is located on the third insulation layer. 23.
  • the third passivation layer 1133 is located on the fourth insulating layer 24.
  • the first conductive layer 11 may include a conductive active layer
  • the second conductive layer 12 may be a layer where the gates of the transistors are located
  • the third conductive layer 13 may be a first transparent conductive layer (for example, including a memory layer).
  • the first data line layer (for example, the fourth conductive layer) and the second data line layer (for example, the fifth conductive layer) may include a connection conductive portion connected to the signal line input end, which is not limited in the embodiments of the present disclosure.
  • the materials of the first transparent conductive layer and the second transparent conductive layer include transparent metal oxides such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the transparent conductive layer may be the same layer as the pixel electrode; for example, a conductor
  • the active layer includes polysilicon doped with conductive impurities, an oxide semiconductor (such as IGZO), and the like. It should be noted that the material of each conductive layer depends on the specific situation, which is not limited in the embodiments of the present disclosure.
  • the material of the active layer 111 included in the first transistor T1, the second transistor T2, and the third transistor T3 may include an oxide semiconductor, an organic semiconductor, or a polysilicon semiconductor, for example, an oxide
  • the semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polysilicon semiconductor includes a low-temperature polysilicon semiconductor or a high-temperature polysilicon semiconductor, which is not limited in the embodiments of the present disclosure.
  • IGZO indium gallium zinc oxide
  • the materials for the first, second, and second electrodes 101, 102, and 103 of the first transistor T1 and the first, second, and second electrodes 201, 202, and 203 of the second transistor T2 may include aluminum, aluminum alloy, Copper, copper alloy, or any other suitable material is not limited in the embodiments of the present disclosure.
  • the first connection conductive portion 1 to the fourth connection conductive portion 4 are formed on the base substrate 110.
  • the positions of the conductive parts can be flexibly selected according to the extension distance between the transistors, and the conductive parts connected to each transistor can be prevented from being set on the same layer, thereby simplifying the wiring design of the display panel and improving the signal transmission. accuracy.
  • the material of the base substrate 110 may be a glass substrate, a quartz substrate, a plastic substrate, or a substrate of other suitable materials.
  • the material of the gate insulating layer 112 includes inorganic insulating materials such as SiNx, SiOx, organic insulating materials such as organic resin, or other suitable materials, which are not limited in the embodiments of the present disclosure.
  • top-gate structure transistor As an example, and is not limited thereto.
  • a transistor of any other structure for example, a bottom-gate structure
  • the embodiments of the present disclosure are not limited thereto.
  • the following embodiments are the same and will not be described again.
  • FIG. 5 is a circuit diagram of an implementation example of the shift register unit shown in FIG. 2. As shown in FIG. 5, based on the example shown in FIG. 3, the shift register unit 100 further includes a fourth transistor.
  • the output noise reduction circuit 140 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the second node PD.
  • the first pole of the fourth transistor T4 is connected to the first output terminal OUT1 through the fifth connection conductive portion 5.
  • the second pole of the fourth transistor T4 is connected to the first voltage terminal.
  • VGL is connected to receive the first voltage.
  • the fourth transistor T4 is turned on when the second node PD is at an active level (for example, a high level), thereby electrically connecting the first output terminal OUT1 and the first voltage terminal VGL, so that the first voltage (for example, a low voltage) can be used. (Flat voltage) reduces noise at the first output terminal OUT1.
  • FIG. 6 is a schematic diagram of another example of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit 100 further includes a control circuit 150, a second signal line input terminal CLK2, and a sixth connection conductive portion 6.
  • the sixth connection conductive portion 6 is configured to connect the control circuit 150 and the second signal line input terminal CLK2, and is disposed at a different layer from the fourth connection conductive portion 4.
  • the fourth connection conductive portion 4 is provided on the fifth conductive layer 15 shown in FIG. 4D
  • the sixth connection conductive portion 6 may be provided on the first data line layer (fourth conductive layer 14) or on the first data line layer (fourth conductive layer 14).
  • the five conductive layers 15 are other layers, so that the connection conductive portions connecting the transistors can be prevented from being disposed on the same layer, thereby simplifying the wiring design of the display panel and improving the signal.
  • the accuracy of the transmission is not limited by the embodiments of the present disclosure.
  • the control circuit 150 is configured to control the level of the second node PD under the control of the level of the first node PU and the second signal, so as to control the output noise reduction circuit 140.
  • the control circuit 150 may be respectively connected to the first voltage terminal VGL, the second voltage terminal VGH, the first node PU, and the second node PD, so as to be controlled by the level of the first node PU and the level of the second signal,
  • the second node PD is electrically connected to the second voltage terminal VGH to control the level of the second node PD, for example, the second node PD is charged so that the second node PD is at a high potential.
  • FIG. 7 is a circuit diagram of an implementation example of the shift register unit shown in FIG. 6. As shown in FIG. 7, based on the example shown in FIG. 5, the shift register unit 100 further includes a fifth transistor T5 and a sixth transistor T6.
  • control circuit 150 may be implemented as a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 is configured to be connected to the first node PU
  • the first pole is configured to be connected to the second voltage terminal VGH to receive the second voltage
  • the second pole is configured to be connected to the conductive portion through the first 1 is connected to the first pole of the sixth transistor T6.
  • the gate of the sixth transistor T6 is configured to be connected to receive the second signal through the sixth connection conductive portion 6 and the second signal line input terminal CLK2, and the second electrode is configured to be connected to the second node PD.
  • FIG. 8 is a circuit diagram of another implementation example of the shift register unit shown in FIG. 6. As shown in FIG. 8, based on the example shown in FIG. 5, the shift register unit 100 further includes a fifth transistor T5 and a sixth transistor T6.
  • control circuit 150 may be implemented as a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 is configured to be connected through the sixth connection conductive portion 6 and the second signal line input terminal CLK2 to receive the second signal
  • the first electrode is configured to be connected to the second voltage terminal VGH to receive the first signal.
  • the two voltages and the second pole are configured to be connected through the first connection conductive portion 1 and the first pole of the sixth transistor T6.
  • the gate of the sixth transistor T6 is configured to be connected to the first node PU, and the second electrode is configured to be connected to the first voltage terminal VGL of the second node, so that the potential of the second node PD can be controlled, thereby controlling the output noise reduction circuit. 140 performs noise reduction on the first output terminal OUT1.
  • pull-down unit 150 may also be implemented as other circuit structures, which are not limited in the embodiments of the present disclosure.
  • the first voltage terminal VGL for example, maintains a DC low level signal, and this DC low level is referred to as a first voltage
  • the second voltage terminal VGH for example, maintains a DC high level input. Signal, this DC high level is called a second voltage.
  • the following embodiments are the same, and will not be described again.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the thin film transistors are used as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are described by taking N-type transistors as an example.
  • the first pole of the transistor may be a drain, and the second pole may be a source.
  • the embodiments of the present disclosure do not deal with this. limit.
  • one or more of the transistors in the shift register unit 100 provided by the embodiment of the present disclosure may also be a P-type transistor.
  • the first pole of the transistor may be a source and the second pole may be a drain.
  • the poles of the transistors of the selected type need to be connected with reference to the poles of the corresponding transistors in the embodiments of the present disclosure. For example, the on-level of the P-type transistor becomes a low level.
  • the embodiments of the present disclosure include, but are not limited to, the shift register unit 100 may also use a P-type transistor and an N-type transistor in a mixed manner.
  • the port polarities of the corresponding transistors in the embodiment may be correspondingly connected.
  • the shift register unit provided by the embodiment of the present disclosure can flexibly select the position of the connection conductive portion according to the extension distance between the transistors, avoiding that the connection conductive portions connected to the transistors are all disposed on the same layer, thereby simplifying the wiring design of the display panel. And improve the accuracy of signal transmission.
  • the circuit structure is, for example, a shift register unit or a partial constituent structure of a shift register unit.
  • the circuit structure includes a substrate (not shown) and a first transistor provided on the substrate T1, second transistor T2, third transistor T3 and storage capacitor C, first output terminal OUT1, first connection conductive portion 1, second connection conductive portion 2, and third connection conductive portion 3.
  • first connection conductive portion 1, the second connection conductive portion 2, and the third connection conductive portion 3 are provided in different layers.
  • the first connection conductive portion 1 is configured to connect a first pole of the first transistor T1 and a first pole of the second transistor T2.
  • the second connection conductive portion 2 is configured to connect the first electrode of the second transistor T2 and the gate of the third transistor T3 and the first electrode of the storage capacitor.
  • the third connection conductive portion 3 is configured to connect the first output terminal OUT1 and the first electrode of the third transistor T3.
  • connection relationship between the various transistors in this example is similar to the connection relationship between the individual transistors of the shift register unit shown in FIG. 3, and is not repeated here.
  • the circuit structure may further include a fourth transistor T4, a first signal line input terminal CLK1, a fourth connection conductive portion 4 and a first Five connected conductive parts 5.
  • the fourth connection conductive portion 4 is configured to connect the second pole of the third transistor T3 and the first signal line input terminal CLK1, and is connected to the first connection conductive portion 1, the second connection conductive portion 2 and the third connection conductive portion 3 In any two or three different layers.
  • the first signal line input terminal may also be the second voltage terminal VGH or the first voltage terminal VGL.
  • the fifth connection conductive portion 5 is configured to connect the first electrode of the third transistor T3 and the first electrode of the fourth transistor T4, and is connected to the first connection conductive portion 1, the second connection conductive portion 2, and the third connection conductive portion. Any two or three different layer settings in 3.
  • connection relationship between the transistors in this example is similar to the connection relationship between the transistors of the shift register unit shown in FIG. 5, which is not repeated here.
  • the circuit structure further includes a five transistor T5, a sixth transistor T6, a second signal line input terminal CLK2, and a sixth connection conductive portion 6.
  • the sixth connection conductive portion 6 is configured to connect the gate of the sixth transistor T6 and the second signal line input terminal CLK2, and is disposed at a different layer from the fourth connection conductive portion 4.
  • the first pole of the fifth transistor T5 is connected to the first pole of the sixth transistor T6 through the first connection conductive portion 1.
  • connection relationship between the transistors in this example is similar to the connection relationship between the transistors of the shift register unit shown in FIG. 7, which is not repeated here.
  • the circuit structure may further include a seventh transistor, a third signal line input terminal, and a seventh connection conductive portion 7.
  • the gate of the seventh transistor T7 is configured to be connected to the first output terminal OUT1 to receive the output signal of the first output terminal
  • the first electrode is configured to be connected to the third signal line input terminal CLK3 through the seventh connection conductive portion 7.
  • the second pole is configured to be connected to the second output terminal OUT2.
  • the seventh connection conductive portion 7 is configured to be provided in a different layer from the fourth connection conductive portion 4.
  • the circuit structure may further include an eighth transistor T8.
  • the gate of the eighth transistor T8 is configured to be connected to the second node PD in the circuit structure through the second connection conductive portion 2, the first pole is configured to be connected to the second output terminal OUT2, and the second pole is configured to Connected to the first voltage terminal VGL to receive the first voltage.
  • the first signal, the second signal, and the third signal mentioned in the embodiments of the present disclosure may all be at least one of a clock signal, a voltage signal, or a current signal, which depends on specific situations.
  • the clock signal may be a first clock signal
  • the voltage signal may be a first voltage (for example, a low voltage) or a second voltage (for example, a high voltage, for example, the first voltage is lower than the second voltage).
  • the first signal is a voltage signal
  • the second signal and the third signal are clock signals.
  • the circuit structure provided in the embodiment of the present disclosure can flexibly select the position of the connection conductive portion according to the extension distance between the transistors, avoiding that the connection conductive portions connected to each transistor are provided on the same layer, thereby simplifying the wiring design of the display panel and Improve the accuracy of signal transmission.
  • FIG. 9A is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit 10 includes a plurality of cascaded shift register units 100, a first signal line CLKA, and a second signal line CLKB.
  • each shift register unit 100 may adopt the circuit structure shown in FIG. 7 provided in an embodiment of the present disclosure.
  • the gate driving circuit 10 may further include four, six, or eight clock signal lines, and the number of clock signal lines depends on specific circumstances, which is not limited in the embodiments of the present disclosure.
  • each of the shift register units further includes a first signal line input terminal CLK1 and a second signal line input terminal CLK2, and is configured to communicate with the first signal line CLKA or the second signal line CLKB. Connect to receive the first or second signal.
  • the first signal line CLKA is connected to the first signal line input terminal CLK1 of the 2m-1 (m is an integer greater than 0) stage shift register unit
  • the second signal line CLKB is connected to the second signal line CLKB of the 2m-1 stage shift register unit.
  • the two signal line input terminals CLK2 are connected, the second signal line CLKB is connected to the first signal line input terminal CLK1 of the 2m-stage shift register unit, and the first signal line CLKA and the 2m (m is an integer greater than 0) stage are shifted
  • the second signal line input terminal CLK2 of the register unit is connected.
  • Embodiments of the present disclosure include but are not limited thereto.
  • OUT1_m shown in FIG. 9A represents the first output terminal of the m-th stage shift register unit
  • OUT1_m + 1 represents the first output terminal of the m + 1-stage shift register unit
  • OUT1_m + 2 represents the first The first output terminal of the m + 2 stage shift register unit.
  • the reference numerals in the following embodiments are similar to this and will not be described again.
  • the reset terminal RST of the shift register unit of the other stages is connected to the first output terminal OUT1 of the next-stage shift register unit.
  • the input terminals INPUT of the other stages of the shift register unit are connected to the first output terminal OUT1 of the previous-stage shift register unit.
  • the input terminal INPUT of the first stage shift register unit may be configured to receive the trigger signal STV
  • the reset terminal RST of the last stage shift register unit may be configured to receive the reset signal RESET, the trigger signal STV, and the reset signal. RESET is not shown in FIG. 9A.
  • the gate driving circuit 10 may further include a timing controller 300.
  • the timing controller 300 may be configured to be connected to the first signal line CLKA and the second signal line CLKB to provide the first signal or the second signal to each shift register unit 100.
  • the timing controller 300 may be further configured to provide a trigger signal STV and a reset signal RESET.
  • the signal timing provided on the first clock signal line CLKA and the second clock signal line CLKB may use the signal timing shown in FIG. 11A to implement the function of the gate driving circuit 10 outputting the gate scan signal line by line.
  • one shift register unit B is a shift register unit at the next stage of another shift register unit A.
  • the gate scan signal output by the shift register unit B is The gate scan signal is later than the output from the shift register unit A.
  • one shift register unit B is a shift register unit above the other shift register unit A.
  • the gate scan signal output by the shift register unit B is earlier in timing than the output of the shift register unit A. Gate scan signal.
  • An embodiment of the present disclosure further provides a gate driving circuit 10.
  • the gate driving circuit 10 further includes a second output circuit 200, a third signal line input terminal CLK3, and a seventh connection conductive portion (not shown in the figure).
  • a connection block diagram of the shift register unit 100 and the second output circuit 200 is shown in FIG. 10A.
  • the third signal line input terminal CLK3 may provide a third clock signal or a first voltage VGL or a second voltage VGH.
  • the second output circuit 200 is configured to output a third signal to the second output terminal OUT2 under the control of the level output from the first output terminal OUT1.
  • the second output circuit 200 is connected to the first output terminal OUT1, the second output terminal OUT2, and the third signal line input terminal CLK3, so as to be controlled at the second output terminal under the control of the effective level output from the first output terminal OUT1.
  • OUT2 outputs a third signal.
  • the shift register unit 100 includes a fourth connection conductive portion 4
  • the seventh connection conductive portion 7 connects the third signal line input terminal CLK3 and the second output circuit 200, and is configured to be connected to the fourth connection conductive portion. 4 different layer settings.
  • the seventh connection conductive portion 7 may be provided on the first data line layer (the fourth conductive layer 14) or in addition to the fifth conductive layer.
  • the layers other than the layer 15 can prevent the connecting conductive parts connecting the transistors from being disposed on the same layer, thereby simplifying the wiring design of the display panel and improving the accuracy of signal transmission. There are no restrictions.
  • the second output circuit 200 may also be connected to the second node of the shift register unit 100 through the second connection conductive portion 2.
  • FIG. 10B shows a circuit configuration diagram of an example of the gate driving circuit shown in FIG. 10A.
  • the gate driving circuit 10 further includes a seventh transistor, a third signal line input terminal, and a seventh Connected to the conductive portion 7.
  • the second output circuit 200 can be implemented as a seventh transistor T7.
  • the gate of the seventh transistor T7 is configured to be connected to the first output terminal OUT1 to receive the output signal of the shift register unit 100, and the first electrode is configured to connect the conductive portion 7 and the third signal line input terminal through a seventh connection CLK3 is connected to receive the third signal, and the second pole is configured to be connected to the second output terminal OUT2.
  • the second output circuit 200 may further include an eighth transistor T8.
  • the gate of the eighth transistor T8 is configured to be connected to the second node PD (ie, the second pole of the sixth transistor T6) in the shift register unit 100 through the second connection conductive portion 2, and the first pole is configured as Connected to the second output terminal OUT2, and the second pole is configured to be connected to the first voltage terminal VGL to receive the first voltage.
  • the gate driving circuit provided by the embodiment of the present disclosure is not limited to the cascade connection shown in FIG. 9B, and the gate driving circuit can also perform upper and lower stages through the second output terminal OUT2 of the second output circuit.
  • the following embodiments are the same, and will not be described again.
  • the second output circuit 200 may further include other circuits such as a gate line, a data line, or a pixel circuit connected to the gate driving circuit to implement different functions, and the other circuit structure may also be implemented by using the present disclosure.
  • the connection modes provided by the examples are not limited in the embodiments of the present disclosure.
  • the gate driving circuit 10 further includes a third signal line CLKC.
  • the third signal line CLKC is connected to a third signal line input terminal CLK3 of the second output circuit 200.
  • the timing controller 300 of the gate driving circuit 10 may be further configured to be connected to a third signal line CLKC to provide a third signal to the second output circuit 200.
  • the signals provided by the first signal line CLKA, the second signal line CLKB, and the third signal line CLKC may use the timing shown in FIG. 11A to implement the gate driving circuit 10 to output the gate scan line by line. The function of the signal.
  • OUT2_m shown in FIG. 9B represents the second output terminal of the m-th stage output control circuit
  • OUT2_m + 1 represents the second output terminal of the m + 1th stage output control circuit
  • OUT2_m + 2 represents the m + 2 stage output A second output of the control circuit.
  • An embodiment of the present disclosure further provides a gate driving circuit 10.
  • the gate driving circuit 10 is similar to the gate driving circuit shown in FIG. 9B, except that the first signal provided by the first signal line CLKA is a DC high level (e.g. Second voltage).
  • the first signal line input terminal CLK1 of the shift register unit 100 at each stage is connected to the first signal line CLKA.
  • the second signal line CLKB is connected to the second signal line input terminal CLK2 of the 2m-1 (m is an integer greater than 0) stage shift register unit, and the third signal line CLKC and the 2m-1 stage shift register unit
  • the third signal line input terminal CLKC is connected
  • the second signal line CLKB is connected to the third signal line input terminal CLKC of the 2m-stage shift register unit
  • the third signal line CLKC is connected to the 2m (m is an integer greater than 0) stage
  • the second signal line input terminal CLK2 of the shift register unit is connected, and the embodiments of the present disclosure include but are not limited thereto.
  • the signals provided by the first signal line CLKA, the second signal line CLKB, and the third signal line CLKC may use the timing shown in FIG. 11B to implement the gate driving circuit 10 to output the gate scan line by line.
  • the function of the signal may be used to implement the gate driving circuit 10 to output the gate scan line by line.
  • the working principle of the gate driving circuit 10 shown in FIG. 9B is described below with reference to the signal timing diagram shown in FIG. 11A.
  • the effective output level is high and the invalid output level is low. Level; and the first signal transmitted by the first signal line CLKA and the second signal transmitted by the second signal line CLKB are complementary to each other (for example, their phases are opposite to each other), and the third signal transmitted by the third signal line CLKC and the first signal line
  • the first signal transmitted by CLKA is the same in the first phase P1.
  • the gate driving circuit 10 can perform the following operations, respectively.
  • the first signal and the second signal may also overlap slightly in timing.
  • the first signal line CLKA provides a high-level signal and the third signal line CLKC provides a high-level signal. Since the first signal line input terminal CLK1 and the first signal line of the m-th shift register unit 100 CLKA is connected, so at this stage, the first signal line input terminal CLK1 of the m-th stage shift register unit 100 inputs a high-level signal; and because the first node PU of the m-th stage shift register unit 100 is high, Under the control of the high level of the first node PU, the high level input from the first signal line input terminal CLK1 is output to the first output terminal OUT1_m of the m-th shift register unit 100.
  • the second output circuit 200 is turned on under the control of the high level provided by the first output terminal OUT1_m, so that the second output terminal OUT2_m outputs the high level provided by the third signal line CLKC.
  • the level of the potential in the signal timing diagram shown in FIG. 11A is only schematic and does not represent the true potential value or relative proportion.
  • the high-level signal corresponds to the N-type.
  • the transistor is an on signal, and the low-level signal corresponds to the N-type transistor being an off signal.
  • the second signal line CLKB provides a high-level signal
  • the third signal line CLKC provides a high-level signal. Since the first signal line input terminal CLK1 and the second The signal line CLKB is connected, so at this stage, the first signal line input terminal CLK1 of the m + 1 stage shift register unit 100 inputs a high-level signal; and because the first node PU of the m + 1 stage shift register unit 100 Is high level, so under the control of the high level of the first node PU, the high level input from the first signal line input terminal CLK1 is output to the first output terminal OUT1_m + of the m + 1 stage shift register unit 100 1. At the same time, the second output circuit 200 is turned on under the control of the high level provided by the first output terminal OUT1_m + 1, so that the second output terminal OUT2_m + 2 outputs the high level provided by the third signal line CLKC.
  • the operating principle of the gate driving circuit 10 shown in FIG. 9C is similar to the operating principle of the gate driving circuit 10 shown in FIG. 9B, and is not repeated here.
  • Another embodiment of the present disclosure also provides a driving circuit including a plurality of cascaded circuit structures.
  • the circuit structure may adopt an example shown in FIG. 7 or FIG. 10B.
  • the circuit structure may further include a seventh transistor, a third signal line input terminal CLK3 and a seventh connection conductive portion 7.
  • the gate of the seventh transistor T7 is configured to be connected to the first output terminal OUT1 to receive the output signal of the first output terminal
  • the first electrode is configured to be connected to the third signal line input terminal CLK3 through the seventh connection conductive portion 7.
  • the second pole is configured to be connected to the second output terminal OUT2.
  • the seventh connection conductive portion 7 is configured to be provided in a different layer from the fourth connection conductive portion 4.
  • the circuit structure may further include an eighth transistor T8.
  • the gate of the eighth transistor T8 is configured to be connected to the second node PD in the circuit structure through the second connection conductive portion 2, the first pole is configured to be connected to the second output terminal OUT2, and the second pole is configured to Connected to the first voltage terminal VGL to receive the first voltage.
  • the driving circuit cascades between upper and lower stages through the first output terminal OUT1.
  • the driving circuit can pass the first The two output terminals OUT2 are cascaded between upper and lower stages.
  • the driving circuit is not limited to driving the shift register unit, and may also drive local area circuits other than the shift register unit.
  • the driving circuit is not limited to providing a voltage to the gate line.
  • at least one of the first light-emitting control line and the second light-emitting control line in the OLED pixel circuit may be driven to provide a first light-emitting control signal and / Or a second light emission control signal.
  • the pixel circuit is, for example, an 8T2C pixel circuit.
  • the driving circuit may also provide a light emission control signal to two adjacent rows of pixels through the second output terminal OUT2.
  • the display device 1000 includes a gate driving circuit 10 or a driving circuit provided by an embodiment of the present disclosure.
  • the display device 1000 includes a pixel array including a plurality of pixel units 30.
  • the display device 1000 may further include a data driving circuit 20.
  • the data driving circuit 20 is used to provide a data signal to the pixel array;
  • the gate driving circuit 10 is used to provide a gate scanning signal to the pixel array.
  • the data driving circuit 20 is electrically connected to the pixel unit 30 through a data line 21.
  • the gate driving circuit 10 may be specifically implemented as a GOA circuit, which is directly fabricated on the array substrate of the display device and is electrically connected to the pixel unit 30 through the gate line 11.
  • the gate driving circuit 10 or the driving circuit provided by the embodiment of the present disclosure included in the display device 1000 can be freely and flexibly arranged on the array substrate, for example, at least one side of the flexible array substrate, for example, both sides Side, or four sides.
  • the display device 1000 may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator And any other product or part with display capabilities.
  • the display device 1000 may further include other conventional components such as a display panel, which is not limited in the embodiments of the present disclosure.

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PCT/CN2019/070895 2018-05-28 2019-01-08 移位寄存器单元、电路结构、栅极驱动电路、驱动电路及显示装置 Ceased WO2019227939A1 (zh)

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EP19732243.1A EP3806078A4 (en) 2018-05-28 2019-01-08 SHIFT DAMPER UNIT, CIRCUIT STRUCTURE, GATE DRIVER CIRCUIT, CONTROL CIRCUIT AND DISPLAY DEVICE
KR1020197037441A KR102314548B1 (ko) 2018-05-28 2019-01-08 시프트 레지스터 유닛, 회로 구조체, 게이트 구동 회로, 구동 회로 및 디스플레이 디바이스
JP2019570504A JP7303127B2 (ja) 2018-05-28 2019-01-08 シフトレジスタユニット、回路構造、ゲート駆動回路、駆動回路及び表示装置
US16/475,513 US11488513B2 (en) 2018-05-28 2019-01-08 Shift register unit, circuit structure, gate drive circuit, drive circuit and display device
US17/807,908 US11705048B2 (en) 2018-05-28 2022-06-21 Shift register unit, circuit structure, gate drive circuit, drive circuit and display device

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CN201820809711.7 2018-05-28

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US17/807,908 Continuation US11705048B2 (en) 2018-05-28 2022-06-21 Shift register unit, circuit structure, gate drive circuit, drive circuit and display device

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US11705048B2 (en) 2023-07-18
US11488513B2 (en) 2022-11-01
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CN208141792U (zh) 2018-11-23
EP3806078A4 (en) 2022-03-02
JP2021524980A (ja) 2021-09-16
US20220319391A1 (en) 2022-10-06
US20210335195A1 (en) 2021-10-28
JP7303127B2 (ja) 2023-07-04
EP3806078A1 (en) 2021-04-14

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