WO2019227619A1 - 一种Nand设备的硬件控制器、控制方法及液晶显示器 - Google Patents

一种Nand设备的硬件控制器、控制方法及液晶显示器 Download PDF

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Publication number
WO2019227619A1
WO2019227619A1 PCT/CN2018/095807 CN2018095807W WO2019227619A1 WO 2019227619 A1 WO2019227619 A1 WO 2019227619A1 CN 2018095807 W CN2018095807 W CN 2018095807W WO 2019227619 A1 WO2019227619 A1 WO 2019227619A1
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Prior art keywords
read
nand device
bad block
module
write
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PCT/CN2018/095807
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English (en)
French (fr)
Inventor
周学兵
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深圳市华星光电技术有限公司
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Priority to US16/228,416 priority Critical patent/US10748462B2/en
Publication of WO2019227619A1 publication Critical patent/WO2019227619A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3618—Control of matrices with row and column drivers with automatic refresh of the display panel using sense/write circuits

Definitions

  • the present invention relates to the technical field of electronic circuits, and in particular, to a hardware controller, a control method, and a liquid crystal display of a Nand device.
  • bad blocks may occur due to hardware physical defects or abnormal shutdowns, power failures, and service termination due to abnormal processes.
  • a bad block is a block in a Nand device that does not support read / write operations due to a failure. Its characteristics are: when programming (Page Program) or Block (Erase) this block, an operation error will occur.
  • the prior art solution is to perform bad block management on the Nand device through the processor based on a software program.
  • this solution has the disadvantages of occupying large memory and low read / write speed.
  • Embodiments of the present invention provide a hardware controller, a control method, and a liquid crystal display of a Nand device.
  • the hardware method is used to perform bad block management on the Nand device.
  • the Nand device supports different data access methods, making the read / write operation of the Nand device more adaptable.
  • the present invention provides a hardware controller of a Nand device.
  • the hardware controller includes:
  • a bad block management module configured to manage bad block information of a Nand device, where the bad block information represents a set of bad blocks in the Nand device;
  • a main control module configured to receive an operation command of a terminal; the operation command is used to instruct a target block set of the Nand device to perform a read / write operation and a data transmission method used to perform the read / write operation;
  • the data transmission method includes at least one of parallel transmission and serial transmission;
  • the read-write module is configured to skip blocks in the Nand device that are simultaneously present in the bad block set and the target block set, and perform the read / write operation on the remaining blocks in the target block set.
  • the write operation includes at least one of an erase operation and a program operation; the bad block management module is further configured to: when the write operation fails to write data to the block Adding a block corresponding to the write operation as a bad block to the bad block set.
  • the hardware controller further includes an error checking module, and the error checking module is configured to perform error checking and correction on data corresponding to the read operation during the read operation.
  • the hardware controller further includes a speed test module, which is used to test the maximum access speed of the Nand device; the read-write module is specifically configured to, according to the maximum access The speed performs the read / write operation on the remaining blocks in the target block set.
  • the hardware controller further includes a power failure protection module, and the power failure protection module is configured to transmit bad block information of the Nand device and data corresponding to the Nand device. Manner, the maximum access speed corresponding to the Nand device is saved to a memory.
  • the present invention provides a control method, which includes: acquiring bad block information of a Nand device, where the bad block information represents a set of bad blocks in the Nand device;
  • the operation command is used to instruct a read / write operation on the target block set of the Nand device and a data transmission method used for performing the read / write operation, and the data transmission method includes parallel transmission And at least one of serial transmission;
  • the method further includes: when the write operation fails to write data to the block, adding a block corresponding to the write operation to the bad block as a bad block.
  • the write operation includes at least one of an erase operation and a program operation.
  • the method further includes: performing error checking and correction on data corresponding to the read operation during the read operation.
  • the method further includes: testing a maximum access speed of the Nand device; and performing the read / write on the remaining blocks in the target block set according to the maximum access speed. operating.
  • the method further includes: saving bad block information of the Nand device, a data transmission method corresponding to the Nand device, and a maximum access speed corresponding to the Nand device to a memory. .
  • the present invention provides a liquid crystal display including the hardware controller according to the first aspect.
  • the read / write module reads / removes the blocks from the bad block set in the target library set in the Nand device. Write operation. Therefore, the embodiments of the present invention are not only applicable to Nand devices with different data transmission methods, but also can perform fast read / write operations on the basis of managing bad blocks of Nand devices, without occupying a large operating memory of the terminal, and improving the applicability of Nand devices Sex.
  • FIG. 1 is a schematic diagram of a storage array and bad block information in a Nand device according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a storage array and bad block information in another Nand device according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a system architecture according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a hardware controller according to an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart of a control method according to an embodiment of the present invention.
  • FIG. 6 is a schematic flowchart of a write operation according to an embodiment of the present invention.
  • FIG. 7 is a schematic flowchart of a read operation according to an embodiment of the present invention.
  • FIG. 8 is a schematic flowchart of another control method according to an embodiment of the present invention.
  • FIG. 9 is a schematic flowchart of initialization according to an embodiment of the present invention.
  • FIG. 10 is a schematic interaction diagram of a hierarchical module according to an embodiment of the present invention.
  • a Nand device is composed of a block.
  • a block can be used to store / erase data and support read / write operations (such a block can also be called a good block).
  • the Nand device includes a storage array composed of block_0, bolt_1 ... block_i ... block_n, etc., and the basic unit of a block is a page.
  • a bad block is a block in a Nand device that does not support read / write operations due to a failure.
  • bad blocks are divided into inherent bad blocks and used bad blocks.
  • Inherent bad block refers to the bad block generated during the manufacturer's production process.
  • Using bad block refers to the block erase operation (Page Errase) or page write operation (Page Program) found during the use of the Nand device.
  • Bad block is not limited to the block erase operation (Page Errase) or page write operation (Page Program) found during the use of the Nand device.
  • Page Errase block erase operation
  • Page Program page write operation found during the use of the Nand device.
  • the bad block information includes a set of bad blocks in the Nand device.
  • the bad block information may be a bad block linked list in practical applications.
  • bits are used to indicate whether a block is a good block or a bad block, that is, a bit represents the good or bad condition of a block; for example, when a block is a bad block, the block corresponds to Is set to "1"; when the block is a good block, the bit corresponding to the block is set to "0".
  • the set of all bad blocks whose bits are set to "1" is the set of bad blocks.
  • a certain block in a storage array may be used to store the bad block information, for example, block_0 in the storage array is used in the figure to store a bad block linked list.
  • the hardware controller when data read / write operations are required on certain blocks, the hardware controller will first query the bad block set in the bad block information, and skip the bad blocks belonging to the bad block set among these blocks. Further, read / write operations are performed on other blocks among these blocks (understandably, the other blocks are good blocks).
  • the storage space of the Nand device can be divided into multiple storage areas, and each storage area includes a preset number of blocks. Each storage area can be individually simulated to operate in a circular queue to avoid the occurrence of bad blocks caused by repeated writing operations on the same block. In particular, for batch data that needs to be updated in real time, two circular queues can be allocated for reading and writing.
  • One circular queue is responsible for the current read and one circular queue is responsible for the real-time update and write.
  • Set the flag byte switch between read and write circular queues, the original read circular queue becomes a real-time update queue, and the original real-time update queue becomes a read circular queue; the set flag byte can be updated to non-volatile memory.
  • FIG. 3 shows a schematic diagram of a system architecture according to an embodiment of the present invention.
  • the architecture includes a user-side terminal (Host), a hardware controller, and a Nand device, where the hardware controller is connected to the user-side terminal (Host) and the Nand device, respectively.
  • the user-side terminal (Host) is used to generate read / write operation instructions. It can be a computer host, a mobile phone, a tablet, an IoT device, and other peripheral devices. It can also be a central processing unit, a graphics processor, and a neural network processor. Processor device.
  • a Nand device for example, Nand flash, etc.
  • the hardware controller is configured to implement operation on the Nand device based on the operation instruction of the user-side terminal (Host).
  • the hardware controller may be packaged with the Nand device as the same device, and the hardware controller may also be independent of the Nand device, which is not specifically limited herein.
  • the hardware controller in the embodiment of the present invention may include the following structures: a main control module 301, a bad block management module 302, and a read-write module 303. among them,
  • a main control module 301 is configured to connect to the user-side terminal and receive an operation command of the terminal; the operation command is used to instruct a target block set of the Nand device to perform a read / write operation and to perform the read / write operation.
  • the hardware controller after the hardware controller establishes a connection with the user-side terminal and the Nand device, the hardware controller will receive an operation command issued by the terminal based on the data transmission mode supported by the Nand device, and the operation command instructs the hardware controller to use a parallel At least one of transmission and serial transmission performs a read / write operation on the target fast set of the Nand device.
  • the bad block management module 302 is configured to manage bad block information of a Nand device, where the bad block information represents a set of bad blocks in the Nand device; for details, refer to the description of the bad block information in the embodiment of FIG. No longer.
  • the read-write module 303 is connected to the Nand device, and is configured to skip blocks in the Nand device that are simultaneously present in the bad block set and the target block set, and perform the rest of the blocks in the target block set. Read / write operation.
  • the hardware controller when the terminal issues a command to perform read / write operations on the Nand device, the hardware controller will first query the bad block set in the bad block information, skip the bad blocks included in the bad block set, and perform other good blocks. Perform read / write operations.
  • the read / write module reads / removes the blocks from the bad block set in the target library set in the Nand device. Write operation. Therefore, the embodiments of the present invention are not only applicable to Nand devices with different data transmission methods, but also can perform fast read / write operations on the basis of managing bad blocks of Nand devices, without occupying a large operating memory of the terminal, and improving the applicability of Nand devices. Sex.
  • FIG. 4 is a schematic structural diagram of another hardware controller according to an embodiment of the present invention.
  • the hardware controller provided in this embodiment has a finer structure and more functions.
  • the hardware controller in the embodiment of the present invention includes the following structure:
  • the main control module 401 is used for communication and data interaction with the user-side terminal, and analyzes the commands issued by the terminal to drive the next-level module to operate;
  • the main control module 401 is configured to receive an operation command of the terminal; the operation command is used to instruct a target block set of the Nand device to perform a read / write operation and a data transmission method used to perform the read / write operation,
  • the data transmission mode includes at least one of a parallel transmission and a serial transmission.
  • the bad block management module 402 is configured to store and manage bad block information of a Nand device; specifically, it is used to provide bad block information to a corresponding read / write module during a read / write operation.
  • the read control module 403 is configured to select a corresponding lower-level module to perform a read operation according to an instruction issued by the main control module 401.
  • the page data reading module 404 is configured to perform a reading operation on the page data in the Nand device. Specifically, the page data reading module 404 is configured to generate a page data reading instruction to the underlying module based on an instruction issued by the read control module 403.
  • the low-level module may include a low-level operation multiplexing selection module 413, a low-level command generating module 414, and a low-level driving signal generating module 415. Among them, during the read / write operation, the corresponding serial / parallel underlying command generation module 414 is selected by the underlying operation multiplexing selection module 413 for instruction transmission.
  • the fast cache read module 405 is configured to read multiple pages of data in the Nand device in a continuous and fast manner in the case of a parallel transmission mode; specifically, it is used to generate a fast cache read instruction to the bottom layer based on an instruction issued by the read control module 403 Module.
  • the device information reading module 406 is configured to read the device information of the Nand device. Specifically, the device information reading module 406 is configured to interact with the underlying module under the instruction of the main control module 401 to read the device information.
  • the write control module 407 is configured to select a corresponding lower-level module to perform a write operation according to a command issued by the main control module 401.
  • the page data writing module 408 is configured to perform a write operation on the page data in the Nand device; specifically, it is used to generate a page data writing instruction to the underlying module based on an instruction issued by the write control module 407.
  • the fast cache writing module 409 is configured to write multiple pages of data in a Nand device quickly and continuously in a parallel transmission mode; specifically, it is used to generate a fast cache writing instruction to the underlying module based on an instruction issued by the write control module 407.
  • the block data erasing module 410 is configured to perform an erasing operation on the block data in the Nand device. Specifically, the block data erasing module 410 is configured to generate a block erasure instruction to the underlying module based on an instruction issued by the write control module 407.
  • the page data cache management module 411 is responsible for managing the writing or reading of page data to the cache area 412. Specifically, the data sent from the terminal or the data of the read operation is written into the cache area 412, and the control of the cache area 412 is performed. The read data will be sent to the terminal or written to the Nand device.
  • the page data cache area 412 is used to cache page data.
  • the page data cache area may be implemented by using a volatile memory, such as an SRAM memory.
  • the cache area can implement cache of two pages, and the write operation or read operation of the Nand device can use the cache area in a time division multiplexing manner.
  • the low-level operation multiplexing selecting module 413 is configured to select a corresponding low-level command generating module 414 path according to a control command issued by a higher-level module.
  • the low-level command generating module 414 is divided into a low-level command generating module based on parallel transmission and a low-level command generating module based on serial transmission, and is specifically configured to generate a command sequence to the low-level driving signal generating module 415 according to a control command issued by a higher-level module.
  • the low-level driving signal generating module 415 is divided into a low-level driving signal generating module based on parallel transmission and a low-level driving signal generating module based on serial transmission, and is specifically configured to generate a driving sequence of a Nand device according to a command sequence issued by the low-level command generating module 414;
  • the main control module 401 selects a read / write operation on the target block set of the Nand device and a data transmission mode used for the read / write operation according to an operation command of the terminal.
  • the low-level operation multiplexing selection module 413 selects the control command issued by the upper level according to the data transmission mode to select a low-level drive module for parallel transmission or serial transmission, thereby performing corresponding read / write operations on the Nand device.
  • An error check module 416 configured to perform error checking and correction on data corresponding to the read operation during the read operation;
  • the error checking module is specifically configured to perform an error checking and correction function (ECC) on data in a hardware manner. Specifically, when a read operation is performed on the data in the Nand device, the data read in the buffer area 412 may be checked by the error checking module to ensure the correctness of the data.
  • ECC error checking and correction function
  • the speed test module 417 is used to test the maximum access speed of the Nand device; specifically, it is used to interact with the underlying module to test to obtain the maximum access speed.
  • the access control module 418 is used to control the access mode and access speed of the Nand device; specifically, it is used to send a control instruction to the underlying module to control the access mode and access speed of the Nand device.
  • the access speed between the hardware controller and the Nand device is the default speed.
  • the speed test module 417 starts to test the maximum access speed of the Nand device, and when the test passes, the access control module 418 adjusts the access speed to the maximum access speed.
  • the local setting management module 419 is configured to set configuration parameters of each module in the hardware controller.
  • the status management module 420 is configured to generate a corresponding working signal according to the working status of each module and feed it back to the user-side terminal.
  • the main control module 401 in the hardware controller enters an initialization process. After the initialization is completed, the state management module 420 feeds back the initialization completion signal to the terminal, and then waits for the terminal.
  • the main control module 401 receives the control command from the terminal, it first analyzes the control command and then performs the corresponding operation.
  • the main control module 401 sets a busy signal during the entire operation, and the status management module 420 feeds back the busy signal to the terminal, indicating that it no longer accepts control commands from the terminal during this period; after the main control module 401 operation is completed, the status management module 420 clears the busy Signal, and feedback the current operation status to the terminal, while waiting for the next control command from the terminal.
  • FIG. 5 is a schematic flowchart of the control method. This embodiment mainly uses the hardware controller of the foregoing embodiment as an example.
  • the control method includes but is not limited to the following steps:
  • Step 501 The hardware controller obtains bad block information of the Nand device, where the bad block information indicates a set of bad blocks in the Nand device.
  • Step 502 The hardware controller receives an operation command of the terminal.
  • the operation command is used to instruct a target block set of the Nand device to perform a read / write operation and a data transmission mode used for the read / write operation.
  • the data transmission method includes at least one of parallel transmission and serial transmission.
  • Step 503 The hardware controller skips the blocks in the Nand device that are present in both the bad block set and the target block set, and performs the read / write operation on the remaining blocks in the target block set.
  • the method further includes: when the write operation fails to write data to a block, adding a block corresponding to the write operation as a bad block to the bad block set; the write operation Including at least one of an erase operation and a program operation.
  • the method further includes: performing error checking and correction on data corresponding to the read operation during the read operation.
  • the method further includes: testing a maximum access speed of the Nand device; and performing the read / write operation on the remaining blocks in the target block set according to the maximum access speed.
  • the method further includes: storing the bad block information of the Nand device, a data transmission method corresponding to the Nand device, and a maximum access speed corresponding to the Nand device to a memory.
  • this embodiment can support Nand devices with different data access methods. During the operation of the Nand device, it can quickly skip bad blocks based on the bad block set and perform corresponding read / write operations on good blocks. Thus, the terminal is more adapted to the read / write operation of the Nand device.
  • the write operation is to write data to the target page in the target block. See FIG. 6, which is a schematic flowchart of the write operation of the hardware controller, including but not limited to the following steps:
  • the hardware controller queries the bad block set of the Nand device in the bad block management module to determine whether the target block is a bad block. When the target block is detected as a bad block or a written block, the current target block is skipped, and the next block is used as the target block to re-execute this step until a good block is found.
  • a block erase operation is performed on the target block first.
  • the block erase operation is to write all the data bits in the block as the same data information, for example, write the data bits as "1" to facilitate subsequent writing operations. Then, it is detected whether the erasing operation of the target block is successfully performed, if it is successful, step 63 is performed, and if it is failed, step 64 is performed.
  • step 64 is performed. Specifically, a data writing operation is performed on the target page, and it is detected whether the data writing operation for the target page is successful.
  • the hardware controller detects that the data writing operation fails, the number of writing failures of the target page is increased by 1, and the data writing operation is performed on the target page again; if the number of writing failures of the target page is detected to be higher than a preset number, The hardware controller determines that the page writing operation of the target page has failed, and executes step 64.
  • the preset number of times is three.
  • the hardware controller continues to write the next page as the target page. Similarly, if there is data to be written after the target block is written, the hardware controller takes the next block as the target block and executes step 61.
  • the hardware controller may use a volatile memory to store a bad block list of the Nand device described in the embodiment of FIG. 1.
  • the bad block management list of the Nand device may be stored in the bad block management module described above, and the same bad block list may be stored in a non-volatile memory.
  • the volatile memory may be a SRAM memory;
  • the non-volatile memory may be a memory in a hardware controller, or may be a memory independent of the hardware controller, a Nand device, or a Nand device Dedicated storage area (such as Block-0 area).
  • the bad block is not only added to the bad block list of the bad block management module, but also the bad block list Update to non-volatile memory.
  • the read operation is to read related data information from the Nand device, and includes a bad block scan operation and a data read operation.
  • the bad block scanning operation is specifically: detecting the bad block information bytes in each block, and when the bad block information bytes indicate that the block is a bad block, adding it to the bad block set to prevent the Nand device from Abnormally erased during operation.
  • the bad block information bytes are information bytes used for calibrating bad blocks before shipment.
  • the read operation is to read the data of the target page in the target block in the Nand device.
  • FIG. 7 is a schematic flowchart of the read operation of the hardware controller. The read operation flow includes but Not limited to the following steps:
  • the bad block set (bad block list) of the Nand device in the bad block management module is queried to determine whether the target block is a bad block.
  • the current target block is skipped, and this step is performed again as the target block until a good block is found.
  • step 73 is performed; if the hardware controller detects that the read operation of the target page of the target block has failed, the read operation is terminated and the read is deemed to have failed .
  • step 72 If the hardware controller detects that the target page is not the last page of the target block, the next page is used as the target page and step 72 is performed again; if the hardware controller detects that the target page is the last page of the target block, step 74 is performed.
  • the hardware controller detects that the target block is not the last block to read data, it takes the next block as the target block and performs step 71 again; if the hardware controller detects that the target block is the last block to read data, the data reading is completed .
  • the bad page can be skipped to read the target page in the target block, which improves the reading efficiency.
  • FIG. 8 is a schematic flowchart of another control method. This embodiment mainly uses the hardware controller of the foregoing embodiment as an example.
  • the control method includes but is not limited to the following steps:
  • Step 801 the hardware controller is powered on and initialized
  • initialization is performed when the hardware controller establishes a connection with the terminal and the Nand device.
  • the initialization is to set parameters of each module of the hardware controller to a default state or an adaptation state, so as to provide subsequent reading for the terminal.
  • the parameters involved in the initialization include data transmission mode, access speed, extraction of bad block information, etc.
  • FIG. 9 is a flowchart of the initialization after the connection is established, including but not limited to the following steps:
  • the device information of the Nand device read by the hardware controller through the device information reading module is the device device ID, so that it can determine the maximum access speed of the Nand device, the data transmission method, and the factory bad block identification.
  • device working attributes include bad block scan status, bad block information, and so on. It should be noted that after the Nand device completes the scan of the bad block, the hardware controller will set a scan identification byte to indicate that the scan state of the bad block of the Nand device is the scanned state.
  • the current access speed is the default access speed
  • the maximum access speed is the access speed obtained by reading device information. If the hardware controller detects that the current access speed is the maximum access speed, the current access speed is maintained; if the hardware controller detects that the current access speed is not the maximum access speed, step 95 is performed.
  • the hardware controller performs a read-write test according to the maximum access speed of the Nand device. If the test passes, step 95 is performed; if the test fails, the default access speed is maintained.
  • the hardware controller stores and updates the working attributes in a non-volatile memory. To ensure that the working attributes can be read after restarting to perform read / write operations quickly.
  • the initialization process of the hardware controller can obtain bad block information of the Nand device, and the access speed can be debugged to the maximum access speed, thereby facilitating the hardware controller to read / write the Nand device based on the terminal command.
  • Step 802 The hardware controller sends information indicating completion of initialization to the user-side terminal;
  • the main control module in the hardware controller enters an initialization process.
  • the state management module feedbacks the initialization completion signal to the terminal, and then waits for the control command from the terminal; when the main controller
  • the control module receives the control command from the terminal, it first analyzes the control command and then performs the corresponding operation.
  • the main control module sets a busy signal during the entire operation, and the status management module feeds back the busy signal to the terminal, indicating that it will no longer accept the control command of the terminal during this period; after the main control module operation is completed, the status management module clears the busy signal, and This operation status is fed back to the terminal while waiting for the next control command from the terminal.
  • Step 803 The user-side terminal (Host) generates an operation instruction.
  • the operation instruction may be a read / write instruction for the Nand device generated based on a user operation, or may be a read / write instruction for the Nand device automatically generated when the program of the Host runs, which is not limited herein.
  • Table 1 is an example of a command code set agreed between the hardware controller and the Host.
  • the main hardware controller in the hardware controller may respond to the command code set and make specific operations; the command code set may be Flexible extension or adding more control commands.
  • Command encoding Command operation 0001 Update bad block list 0010 Force initialization 0011 Write operation 1 0100 Write operation 2 ... ... 0111 Write operation 1000 Force bad block scan 1001 Read device information 1010 Read operation 1 1011 Read operation 2 ... ... 1111 Read operation n
  • Step 804 The user-side terminal sends an operation instruction to the hardware controller.
  • the operation command is used to instruct a read / write operation on the target block set of the Nand device and a data transmission mode used for the read / write operation.
  • the data transmission mode includes parallel transmission and serial operation. At least one of the transmissions.
  • Step 805 when the operation instruction indicates that the data transmission method used for performing the read / write operation is serial transmission, the hardware controller generates a serial Nand low-level command based on the operation instruction.
  • the hardware controller when the control instruction indicates that the data transmission method used for performing the read / write operation is serial transmission, the hardware controller generates a Serial Nand low-level command. For example, for a certain block and page programming operation, there are corresponding processes such as write enable, write load, write execution, and obtain features, and each process is broken down into a single or multiple operation cycles to complete each operation. The cycle consists of 8 operating times.
  • Step 806 Optionally, when the operation instruction indicates that the data transmission method used for performing the read / write operation is parallel transmission, the hardware controller generates a parallel Nand low-level command based on the operation instruction.
  • the hardware controller when the operation instruction indicates that the data transmission mode used for performing the read / write operation is parallel transmission, the hardware controller generates a Parallel Nand low-level command.
  • the low-level operations include write load, address send, write confirmation, read status, read status register, and other steps.
  • Parallel and Nand devices generally use asynchronous interface timing, with special address, command, and read / write control signals.
  • each operation process is decomposed into single or multiple sub-operations, and the sub-operations correspond to addresses and commands. , Read / write data, etc.
  • Step 807 optionally, when the operation instruction instructs a write operation to the nand device, the hardware controller skips blocks in the Nand device that are simultaneously present in the bad block set and the target block set, and performs a target operation on the target. The remaining blocks in the block set are written.
  • Step 808 optionally, when the operation instruction instructs the read operation of the nand device, the hardware controller skips the blocks in the Nand device that exist in the bad block set and the target block set at the same time, and The remaining blocks in the block set are read.
  • step 807 and step 808 may be an OR relationship, that is, only a write operation or a read operation is performed at the same time; step 807 and step 808 may also be an OR relationship, that is, the control instruction issued by the terminal instructs the hardware controller to Nand The device performs both a write operation and a read operation.
  • Step 809 Optionally, during the read operation, error checking and correction is performed on the data corresponding to the read operation.
  • Step 810 Optionally, save the bad block information of the Nand device, the data transmission method corresponding to the Nand device, and the maximum access speed corresponding to the Nand device to the memory.
  • the memory may be a memory in a hardware controller, or a memory that is independent of the hardware controller and the Nand device, or may be a dedicated storage area (such as a Block-0 area) in the Nand device.
  • the hardware controller tests the maximum access speed for transmission during the initialization process, skips bad blocks during read / write operations, and performs error checking and correction of data, etc. . It can be seen that the embodiments of the present invention can maximize the user experience, help the terminal to read / write data quickly, and reduce the operating memory occupied by the terminal.
  • each module of the hardware controller adopts a hierarchical design for internal command transmission and corresponding processing operations.
  • FIG. 10 shows a schematic diagram of an operation process performed by the hardware controller in cooperation with the terminal, which is described in detail as follows:
  • the terminal generates operation instructions
  • the terminal transmits the operation instruction to the main control module of the hardware controller
  • the main control module of the hardware controller generates a first control command based on the operation instruction and transmits it to the corresponding read / write control module;
  • the read / write control module of the hardware controller generates a second control command based on the first control command and transmits it to the corresponding fast cache / page data-read / write module;
  • the hardware controller's fast cache / page data-read / write module generates a third control command based on the second control command and transmits it to the corresponding serial / parallel underlying command generation module;
  • serial / parallel low-level command generating module of the hardware controller generates a command sequence based on the third control command and transmits it to the corresponding serial / parallel low-level driving signal generating module;
  • the serial / parallel underlying driving signal generation module of the hardware controller generates the driving timing based on the command sequence and transmits it to the Nand device;
  • the hardware controller controls the operation of each layer module through internal control commands, and each layer module sequentially responds to the operation request of the upper layer module from top to bottom; correspondingly, the operation of the lower layer module After the completion, the modules of each layer from the bottom to the top in order to feedback to the module on the signal about the completion of the operation.
  • the main control module feeds back the operation result to the terminal and waits for the next operation.
  • the present invention also provides a liquid crystal display.
  • the liquid crystal display includes the hardware controller provided in the foregoing embodiment.
  • the liquid crystal display can also execute the control method provided in the foregoing embodiment.
  • an embodiment herein means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they independent or alternative embodiments that are mutually exclusive with other embodiments. It is clearly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
  • the program can be stored in a computer-readable storage medium.
  • the program When executed, the processes of the embodiments of the methods described above may be included.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM), or a random access memory (Random, Access Memory, RAM).

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Abstract

本发明公开了一种Nand设备的硬件控制器、控制方法以及液晶显示器，其中，该硬件控制器包括：坏块管理模块，用于管理Nand设备的坏块信息，所述坏块信息表示所述Nand设备中的坏块集合；主控制模块，用于接收终端的操作命令；所述操作命令用于指示对所述Nand设备的目标块集合进行读/写操作以及进行所述读/写操作所采用的数据传输方式，所述数据传输方式包括并行传输和串行传输中的至少一种；读写模块，用于跳过所述Nand设备中同时存在于所述坏块集合和所述目标块集合的块，对所述目标块集合中的其余块进行所述读/写操作。本发明不仅适用于不同数据传输方式的Nand设备，且能够在对Nand设备坏块管理的基础上进行读/写操作，提高Nand设备的适用性。

Description

一种Nand设备的硬件控制器、控制方法及液晶显示器
本申请要求2018年5月29日提交中国专利局的，申请号为201810530147X，发明名称为“一种Nand设备的硬件控制器、控制方法及液晶显示器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电子电路技术领域，尤其涉及一种Nand设备的硬件控制器、控制方法及液晶显示器。
背景技术
随着电子科技的不断发展，在实际应用中经常会出现大批量、高密度的数据需要进行存储管理。例如在液晶显示器的屏驱动板(Timer Control Register，TCON)应用中，需要对配置参数、运行数据、补偿数据等进行存储，且随着面板解析率的增加，各种补偿数据的精细化，需要存储的数据量变得愈来愈大。所以，用于存储数据的存储器的各种参数要求也变得越来越高。现有技术中，Nand(not and)设备作为一种性能良好的非易失性存储设备(例如Nand Flash存储器)，由于具有容量大、成本低、寿命长等优点而被广泛使用。Nand设备通常由块(block)构成，在Nand设备的生产及使用过程，会由于硬件物理缺陷或者异常关机、掉电、终止服务使进程异常等原因而产生坏块。坏块为Nand设备中由于出现故障而不支持读/写操作的块，其特性是：当编程(Page Program)或擦除(Block Erase)这个块时，会出现操作错误。
为了降低坏块对Nand设备使用的影响，现有技术的方案是：基于软件程序通过处理器对Nand设备进行坏块管理，然而这种方案具有占用内存大、读/写速度低等缺陷。
发明内容
本发明实施例提供了一种Nand设备的硬件控制器、控制方法及液晶显示器，采用硬件的方式对Nand设备进行坏块管理，有利于解决占用内存大、读/写速度低等背景技术中提到的缺陷，且支持不同数据访问方式的Nand设备，使对Nand设备的读/写操作更加适配。
第一方面，本发明提供了一种Nand设备的硬件控制器，该硬件控制器包括：
坏块管理模块，用于管理Nand设备的坏块信息，所述坏块信息表示所述Nand设备中的 坏块集合；
主控制模块，用于接收终端的操作命令；所述操作命令用于指示对所述Nand设备的目标块集合进行读/写操作以及进行所述读/写操作所采用的数据传输方式，所述数据传输方式包括并行传输和串行传输中的至少一种；
读写模块，用于跳过所述Nand设备中同时存在于所述坏块集合和所述目标块集合的块，对所述目标块集合中的其余块进行所述读/写操作。
结合第一方面在一些可能的实现方式中，所述写操作包括擦除操作和编程操作中的至少一个；坏块管理模块还用于，当所述写操作未成功写入数据到块中时，将所述写操作对应的块作为坏块增加到所述坏块集合。
结合第一方面在一些可能的实现方式中，所述硬件控制器还包括错误校验模块，错误校验模块用于在读操作过程中对读操作对应的数据进行错误检查与纠正。
结合第一方面在一些可能的实现方式中，所述硬件控制器还包括速度测试模块，速度测试模块用于测试所述Nand设备的最大访问速度；读写模块具体用于，根据所述最大访问速度对所述目标块集合中的其余块进行所述读/写操作。
结合第一方面在一些可能的实现方式中，所述硬件控制器还包括掉电保护模块，所述掉电保护模块用于将所述Nand设备的坏块信息、所述Nand设备对应的数据传输方式、所述Nand设备对应的最大访问速度保存到存储器。
第二方面，本发明提供了一张控制方法，该方法包括：获取Nand设备的坏块信息，所述坏块信息表示所述Nand设备中的坏块集合；
接收终端的操作命令；所述操作命令用于指示对所述Nand设备的目标块集合进行读/写操作以及进行所述读/写操作所采用的数据传输方式，所述数据传输方式包括并行传输和串行传输中的至少一种；
跳过所述Nand设备中同时存在于所述坏块集合和所述目标块集合的块，对所述目标块集合中的其余块进行所述读/写操作。
结合第二方面在一些可能的实现方式中，所述方法还包括：当所述写操作未成功写入数据到块中时，将所述写操作对应的块作为坏块增加到所述坏块集合；所述写操作包括擦除操作和编程操作中的至少一个。
结合第二方面在一些可能的实现方式中，所述方法还包括：在读操作过程中对读操作对应的数据进行错误检查与纠正。
结合第二方面在一些可能的实现方式中，所述方法还包括：测试所述Nand设备的最大 访问速度；根据所述最大访问速度对所述目标块集合中的其余块进行所述读/写操作。
结合第二方面在一些可能的实现方式中，所述方法还包括：将所述Nand设备的坏块信息、所述Nand设备对应的数据传输方式、所述Nand设备对应的最大访问速度保存到存储器。
第三方面，本发明提供了一种液晶显示器，该液晶显示器包括如第一方面所述的硬件控制器。
通过实施本发明实施例，读写模块基于主控制模块确定的数据传输方式，结合坏块管理模块中的坏块信息，对Nand设备中的目标库集合中的除去坏块集合的块进行读/写操作。从而本发明实施例不仅适用于不同数据传输方式的Nand设备，且能够在对Nand设备坏块管理的基础上进行快速地读/写操作，无需占用终端较大的运行内存，提高Nand设备的适用性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种Nand设备中的存储阵列和坏块信息的示意图；
图2是本发明实施例提供的另一种Nand设备中的存储阵列和坏块信息的示意图；
图3是本发明实施例提供的一种系统架构的示意图；
图4是本发明实施例提供的一种硬件控制器的结构示意图；
图5是本发明实施例提供的一种控制方法的流程示意图；
图6是本发明实施例提供的一种写操作的流程示意图；
图7是本发明实施例提供的一种读操作的流程示意图；
图8是本发明实施例提供的另一种控制方法的流程示意图；
图9是本发明实施例提供的一种初始化的流程示意图；
图10是本发明实施例提供的一种层次化模块的交互示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
需要说明的是，下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。
为了便于理解本发明技术方案，首先描述本发明实施例中所涉及的坏块。参见图1，本发明实施例中，Nand设备由块(Block)构成，通常而言，块可用于存储/擦除数据，并支持读/写操作(这样的块又可称为好块)，如图示中Nand设备包括由block_0、bolck_1...block_i…block_n等构成的存储阵列，块的基本单元是页(Page)。相应的，坏块为Nand设备中由于故障不支持读/写操作的块。其中，坏块分为固有坏块与使用坏块。固有坏块指的是在厂家生产过程中产生的坏块，使用坏块指的是在对Nand设备使用过程中发现的块擦除操作(Block Erase)或页编写操作(Page Program)错误产生的坏块。
下面描述本发明实施例提供的坏块信息，以及基于坏块信息进行数据读/写操作的方案。坏块信息包括Nand设备中的坏块集合，具体地，坏块信息在实际应用中可以为坏块链表。如图1所示，在坏块链表中，采用比特位来指示块是好块还是坏块，即一个比特位表征一个块的好坏情况；例如：当块为坏块时，所述块对应的比特位设置为“1”；当块为好块时，所述块对应的比特位设置为“0”。那么，所有比特位设置为“1”的坏块的集合就是所述坏块集合。可以理解的是，上述例子仅为举例，不应理解为具体限定。
本发明具体实施例中，可以使用存储阵列中某个块来存储所述坏块信息，例如图示中使用存储阵列中block_0来存储坏块链表。
本发明具体实施例中，当需要对某些块进行数据的读/写操作时，硬件控制器将首先查询坏块信息中的坏块集合，跳过这些块中属于坏块集合的坏块，进而对这些块中的其它块(可以理解的，所述其他块即为好块)进行读/写操作。进一步地，如图2所示，针对不同数据类型的存储应用，可将Nand设备的存储空间划分为多个存储区，每个存储区包括预设个数的块。每个存储区都可单独模拟成循环队列方式进行操作，以避免对同一个块进行重复编写操作而导致坏块的发生。特别的是，对于需要实时更新的批量数据，可以分配读、写两个循环队列，一个循环队列负责当前的读取，一个循环队列负责实时更新写入；当确定实时更新写入完成后，可设置标志字节，读、写循环队列切换，原读循环队列变为实时更新队列，原实时更新队列变为读循环队列；设置的标志字节可以被更新至非易失性存储器中。
为了解决现有技术对坏块管理的缺陷，本发明实施例进一步提供了一种系统架构，请参阅图3，图3示出了本发明实施例所涉及的一种系统架构的示意图，该系统架构包括用户侧终端(Host)、硬件控制器以及Nand设备，其中，硬件控制器分别连接所述用户侧终端(Host) 和Nand设备。用户侧终端(Host)用于生成读/写操作指令，可以为电脑主机，手机，平板电脑，物联网设备等外设设备，进一步还可以是中央处理器、图形处理器、神经网络处理器等处理器设备。本发明实施例中，Nand设备(例如为Nand flash等)是一种非易失性存储设备，具有功耗更低、重量更轻和性能更佳等优势，同时还具有容量较大，改写速度快等优点，可用于大量数据的存储。硬件控制器用于实现基于所述用户侧终端(Host)的操作指令对Nand设备进行操作。本发明实施例中，所述硬件控制器可以与Nand设备封装在一起以作为同一设备，所述硬件控制器也可以独立于Nand设备，在此不作具体限定。
具体的，本发明实施例中的硬件控制器可包括以下结构：主控制模块301、坏块管理模块302、读写模块303。其中，
主控制模块301，用于连接所述用户侧终端，接收终端的操作命令；所述操作命令用于指示对所述Nand设备的目标块集合进行读/写操作以及进行所述读/写操作所采用的数据传输方式，所述数据传输方式包括并行传输和串行传输中的至少一种；
本发明实施例中，硬件控制器与用户侧的终端以及Nand设备建立连接后，硬件控制器将会接收终端基于Nand设备支持的数据传输方式发出的操作命令，该操作命令指示硬件控制器采用并行传输和串行传输中的至少一种对Nand设备的目标快集合进行读/写操作。
坏块管理模块302，用于管理Nand设备的坏块信息，所述坏块信息表示所述Nand设备中的坏块集合；具体可参考上文图1实施例中关于坏块信息的描述，这里不再赘述。
读写模块303，连接所述Nand设备，用于跳过所述Nand设备中同时存在于所述坏块集合和所述目标块集合的块，对所述目标块集合中的其余块进行所述读/写操作。
本发明实施例中，当终端发出命令对Nand设备进行读/写操作时，硬件控制器将首先查询坏块信息中的坏块集合，跳过坏块集合所包含的坏块进而对其它好块进行读/写操作。
通过实施本发明实施例，读写模块基于主控制模块确定的数据传输方式，结合坏块管理模块中的坏块信息，对Nand设备中的目标库集合中的除去坏块集合的块进行读/写操作。从而本发明实施例不仅适用于不同数据传输方式的Nand设备，且能够在对Nand设备坏块管理的基础上进行快速地读/写操作，无需占用终端较大的运行内存，提高Nand设备的适用性。
请参阅图4，图4是本发明实施例提供的另一种硬件控制器的结构示意图。与上一发明实施例相比，本实施例提供的硬件控制器结构划分更细，功能更多。如图4所示，本发明实施例中的硬件控制器包括以下结构：
主控制模块401，用于与用户侧终端进行通信及数据交互，并解析终端发出的命令，驱动下一层模块进行操作；
另外，主控制模块401用于接收终端的操作命令；所述操作命令用于指示对所述Nand设备的目标块集合进行读/写操作以及进行所述读/写操作所采用的数据传输方式，所述数据传 输方式包括并行传输和串行传输中的至少一种。
坏块管理模块402，用于对Nand设备的坏块信息进行存储管理；具体地，用于在读/写操作时提供坏块信息给对应的读/写模块。
读控制模块403，用于根据主控制模块401发出的指令选择对应的下一级模块进行读操作。
页数据读取模块404，用于对Nand设备中的页数据进行读取操作；具体地，用于基于读控制模块403发出的指令产生页数据读取指令给底层模块。
本发明实施例中，底层模块可包括：底层操作多路复用选择模块413、底层命令生成模块414、底层驱动信号生成模块415。其中，在读/写操作过程中，通过底层操作多路复用选择模块413选择对应的串/并行底层命令生成模块414进行指令发送。
快速缓存读取模块405，用于在并行传输方式的情况下，快速连续读取Nand设备中多个页数据；具体地，用于基于读控制模块403发出的指令产生快速缓存读取指令给底层模块。
设备信息读取模块406，用于读取Nand设备的设备信息；具体地，用于在主控制模块401的指令下与底层模块交互以读取设备信息。
写控制模块407，用于根据主控制模块401发出的命令选择对应的下一级模块进行写操作。
页数据编写模块408，用于对Nand设备中的页数据进行写入操作；具体地，用于基于写控制模块407发出的指令产生页数据编写指令给底层模块。
快速缓存编写模块409，用于在并行传输方式的情况下，快速连续写入Nand设备中多个页数据；具体地，用于基于写控制模块407发出的指令产生快速缓存编写指令给底层模块。
块数据擦除模块410，用于对Nand设备中的块数据进行擦除操作；具体地，用于基于写控制模块407发出的指令产生块擦除指令给底层模块。
页数据缓存管理模块411，用于负责页数据到缓存区412的写入或读取管理；具体地，控制终端发出的数据或者读取操作的数据写入缓存区412，以及控制缓存区412的读取数据将发送给终端或者写入Nand设备。
页数据缓存区412，用于对页数据进行缓存；具体地，页数据缓存区可采用易失性存储器实现，如SRAM存储器。优选地，缓存区可以实现两个页的缓存，且Nand设备的写操作或读操作可以采用时分复用的方式对缓存区进行使用。
底层操作多路复用选择模块413，用于根据上一级模块发出的控制命令选择对应的底层命令生成模块414通路。
底层命令生成模块414，分为基于并行传输的底层命令生成模块与基于串行传输的底层命令生成模块，具体用于根据上一级模块发出的控制命令产生命令序列给底层驱动信号生成模块415。
底层驱动信号生成模块415，分为基于并行传输的底层驱动信号生成模块与基于串行传输的底层驱动信号生成模块，具体用于根据底层命令生成模块414发出的命令序列生成Nand设备的驱动时序；
本发明实施例中，主控制模块401根据终端的操作命令选择对所述Nand设备的目标块集合进行读/写操作以及进行所述读/写操作所采用的数据传输方式。底层操作多路复用选择模块413根据所述数据传输方式将上一级发出的控制命令选择并行传输或串行传输的底层驱动模块，从而对Nand设备进行相应的读/写操作。
错误校验模块416，用于在读操作过程中对读操作对应的数据进行错误检查与纠正；
本发明实施例中，错误校验模块具体用于通过硬件的方式对数据进行错误检查与纠正功能(Error Correcting Code，ECC)。具体地，在从Nand设备中的数据进行读取操作时，可以通过所述错误校验模块对缓存区412中读取的数据进行校验，以保证数据的正确性。
速度测试模块417，用于测试所述Nand设备的最大访问速度；具体用于与底层模块进行交互进而测试得到最大访问速度。
访问控制模块418，用于控制Nand设备的访问方式以及访问速度；具体用于发出控制指令给底层模块，从而控制Nand设备的访问方式与访问速度。
本发明实施例中，在硬件控制器与Nand设备以及终端建立连接之后，硬件控制器与Nand设备之间的访问速度为默认速度。当硬件控制器没有对Nand设备进行最大访问速度测试的情况下，速度测试模块417开始测试所述Nand设备的最大访问速度，并在测试通过时访问控制模块418将访问速度调整为最大访问速度。
本地设置管理模块419，用于设置所述硬件控制器中各个模块的配置参数。
状态管理模块420，用于根据各模块的工作状态生成对应的工作信号并反馈于用户侧终端。
本发明实施例中，硬件控制器与终端以及Nand设备建立连接后，硬件控制器中的主控制模块401进入初始化过程，初始化完成后，状态管理模块420将初始化完成信号反馈给终端，然后等待终端的控制命令；当主控制模块401收到终端的控制命令时，首先解析控制命令，再进行相应操作。主控制模块401在整个操作期间设置忙碌信号，状态管理模块420将该忙碌信号反馈给终端，表示在此期间不再接受终端的控制命令；主控制模块401操作完成 后，状态管理模块420清除忙碌信号，并且将本次操作状态反馈给终端，同时等待终端的下一次控制命令。
基于同一发明构思，本发明实施例还提供了一种控制方法，参见图5，图5为该控制方法的流程示意图。本实施例主要以上述实施例的硬件控制器来举例说明。该控制方法包括但不限于以下步骤：
步骤501，硬件控制器获取Nand设备的坏块信息，所述坏块信息表示所述Nand设备中的坏块集合。
具体可参考前述图1实施例的描述，这里不再赘述。
步骤502，硬件控制器接收终端的操作命令；所述操作命令用于指示对所述Nand设备的目标块集合进行读/写操作以及进行所述读/写操作所采用的数据传输方式，所述数据传输方式包括并行传输和串行传输中的至少一种。
步骤503，硬件控制器跳过所述Nand设备中同时存在于所述坏块集合和所述目标块集合的块，对所述目标块集合中的其余块进行所述读/写操作。
在一实施例中，所述方法还包括：当所述写操作未成功写入数据到块中时，将所述写操作对应的块作为坏块增加到所述坏块集合；所述写操作包括擦除操作和编程操作中的至少一个。
在一实施例中，所述方法还包括：在读操作过程中对读操作对应的数据进行错误检查与纠正。
在一实施例中，所述方法还包括：测试所述Nand设备的最大访问速度；根据所述最大访问速度对所述目标块集合中的其余块进行所述读/写操作。
在一实施例中，所述方法还包括：将所述Nand设备的坏块信息、所述Nand设备对应的数据传输方式、所述Nand设备对应的最大访问速度保存到存储器。
可以看出，本实施例能够支持不同数据访问方式的Nand设备，在对所述Nand设备的操作过程中，能够基于坏块集合快速地跳过坏块对好块进行对应的读/写操作，从而使终端对Nand设备的读/写操作更加适配。
下面进一步描述本发明实施例中所涉及的写操作/读操作的实现过程。
本发明实施例中，写操作为将数据写入到目标块中的目标页中，可以参见图6，图6为硬件控制器的写操作的流程示意图，包括但不限于以下步骤：
61)判断目标块是否为坏块或者已写入的块。
具体地，硬件控制器查询坏块管理模块中的所述Nand设备的坏块集合，以确定目标块是否为坏块。当检测到目标块为坏块或者已写入的块的情况下，跳过当前目标块，将下一块作为目标块重新执行本步骤，直至找到好块。
62)对目标块进行块擦除操作，并判断是否操作成功；
具体地，首先对目标块进行块擦除操作，所述块擦除操作为将块中的数据位皆写为同一数据信息，例如将数据位写为“1”，以方便后续的编写操作。然后，检测是否将目标块的擦除操作执行成功，若成功则执行步骤63，若失败则执行步骤64。
63)对目标块中的页进行页编写操作，并判断是否操作成功；
本发明实施例中，根据终端发出的写入命令，将数据通过编写操作写入目标块的目标页中。当硬件控制器检测到页编写操作失败的情况下，则执行步骤64。具体地，对目标页进行数据编写操作，并检测针对于目标页的数据编写操作是否成功。当硬件控制器检测到所述数据编写操作失败时，将目标页的编写失败次数加1，并再次对目标页进行数据编写操作；若检测到目标页的编写失败次数高于预设次数时，硬件控制器判定目标页的页编写操作失败，执行步骤64。可选地，所述预设次数为3次。
需要说明的是，当目标页写入完成后若还有数据有待写入，则硬件控制器将下一页作为目标页继续编写操作。同理，当目标块写入完成后若还有数据有待写入，则硬件控制器将下一块作为目标块并执行步骤61。
64)将目标块加入Nand设备的坏块集合。
本发明实施例中，硬件控制器可采用易失性存储器存储图1实施例中描述的所述Nand设备的坏块链表。具体地，可采用上文中所述的坏块管理模块中存储所述Nand设备的坏块链表，另外在非易失性存储器中存储相同的坏块链表。具体地，所述易失性存储器可以为SRAM存储器；所述非易失性存储器可以是在硬件控制器内的存储器，也可以是独立于硬件控制器、Nand设备的存储器，还可以是Nand设备中的专用存储区域(如Block-0区)。进一步地，当Nand设备在运行过程中因块擦除操作或页编程操作产生坏块时，不仅将所述坏块添加至坏块管理模块的坏块链表中，同时还将所述坏块链表更新至非易失性存储器中。
本发明实施例中，读操作为从Nand设备中读取相关数据信息，包括：坏块扫描操作与数据读取操作。其中，坏块扫描操作具体为：检测每个块中的坏块信息字节，当所述坏块信息字节表明所述块为坏块时，将其加入坏块集合，以防止在Nand设备运行期间被异常擦除。所述坏块信息字节为出厂前用于标定坏块的信息字节。
可以看出，在硬件控制器对Nand设备进行写操作过程中，不仅能跳过坏块执行对应的写操作，而且能将发现的坏块加入坏块集合以便于后续读写。
本发明实施例中，读操作为将Nand设备中的目标块中目标页的数据进行读取，可以参见图7，图7为硬件控制器的读操作的流程示意图，所述读操作流程包括但不限于以下步骤：
71)查询坏块集合跳过坏块，以找到目标块；
具体地，查询坏块管理模块中的所述Nand设备的坏块集合(坏块链表)，以确定目标块是否为坏块。当检测到目标块为坏块的情况下，跳过当前目标块，将下一块作为目标块重新执行本步骤，直至找到好块。
72)对目标块的目标页进行读取操作，并判断是否操作成功；
若硬件控制器检测到对目标块的目标页的读取操作成功，则执行步骤73；若硬件控制器检测到对目标块的目标页的读取操作失败，则终止读取操作认定读取失败。
73)判断目标页是否为目标块的最后页；
若硬件控制器检测到目标页不是目标块的最后页，则将下一页作为目标页并重新执行步骤72；若硬件控制器检测到目标页是目标块的最后页，则执行步骤74。
74)判断目标块是否为数据读取的最后块；
若硬件控制器检测到目标块不是读取数据的最后块，则将下一块作为目标块并重新执行步骤71；若硬件控制器检测到目标块是读取数据的最后块，则数据读取完成。
可以看出，在硬件控制器对Nand设备进行读操作过程中，可以跳过坏块对目标块中的目标页进行读取，提高了读取效率。
基于同一发明构思，本发明实施例还提供了又一种控制方法，参见图8所示，图8为又一种控制方法的流程示意图。本实施例主要以上述实施例的硬件控制器来举例说明。该控制方法包括但不限于以下步骤：
步骤801，硬件控制器上电初始化；
本发明实施例中，当硬件控制器与终端、Nand设备建立连接时开始执行初始化，其中，初始化为将硬件控制器的各个模块参数设置为默认状态或适配状态，从而为终端提供后续的读/写操作，初始化涉及的参数包括数据传输方式、访问速度、坏块信息的提取等。
下面详细描述初始化过程，参见图9所示，图9是建立连接后的初始化流程图，包括但不限于以下步骤：
91)读取Nand设备的设备信息，以及读取设备工作属性；
本发明实施例中，硬件控制器通过设备信息读取模块读取的Nand设备的设备信息为设备器件ID，从而可以判定Nand设备的最大访问速度、数据传输方式、出厂坏块标识等。另外，设备工作属性包括坏块扫描状态、坏块信息等。需要说明的是，当Nand设备完成坏块扫描后，硬件控制器将设定一扫描标识字节，以表明所述Nand设备的坏块扫描状态为已扫描状态。
92)判断Nand设备是否进行出厂坏块扫描操作；
93)对Nand设备进行出厂坏块扫描操作，并更新坏块集合；
94)判断当前访问速度是否为最大访问速度；
本发明实施例中，当前访问速度为默认访问速度，最大访问速度为通过设备信息读取得到的访问速度。若硬件控制器检测到当前访问速度是为最大访问速度，则保持当前访问速度；若硬件控制器检测到当前访问速度不是为最大访问速度，则执行步骤95。
95)对Nand设备进行最大访问速度测试；
具体地，硬件控制器根据Nand设备的最大访问速度进行读写测试，若测试通过则执行步骤95；若测试不通过，则保持默认访问速度。
96)将访问速度调整为最大访问速度。
需要说明的是，当坏块信息、数据数据传输方式、最大访问速度、配置参数、坏块扫描状态等工作属性分析完成后或者更新后，硬件控制器将所述工作属性存储更新在非易失性存储器中，以保证重启后能读取所述工作属性从而快速进行读/写操作。
可以看出，硬件控制器的初始化流程能够获取Nand设备的坏块信息，且能够将访问速度调试为最大的访问速度，从而有利于硬件控制器基于终端命令对Nand设备的读/写操作。
步骤802，硬件控制器向用户侧终端发送用于指示初始化完成的信息；
具体的，硬件控制器与终端以及Nand设备建立连接后，硬件控制器中的主控制模块进入初始化过程，初始化完成后，状态管理模块将初始化完成信号反馈给终端，然后等待终端的控制命令；当主控制模块收到终端的控制命令时，首先解析控制命令，再进行相应操作。主控制模块在整个操作期间设置忙碌信号，状态管理模块将该忙碌信号反馈给终端，表示在此期间不再接受终端的控制命令；主控制模块操作完成后，状态管理模块清除忙碌信号，并且将本次操作状态反馈给终端，同时等待终端的下一次控制命令。
步骤803，用户侧终端(Host)生成操作指令；
具体的，所述操作指令可以是基于用户的操作生成的对Nand设备的读/写指令，还可以 是Host的程序运行时自动生成的对Nand设备的读/写指令，在此不作限定。
可选地，表1为硬件控制器与Host协定的一种命令编码集示例，硬件控制器中的主硬件控制器可响应于该命令编码集，并做出特定的操作；该命令编码集可灵活的扩展或者添加更加的控制命令。
表1
命令编码 命令操作
0001 更新坏块链表
0010 强制初始化
0011 写操作1
0100 写操作2
...... ......
0111 写操作n
1000 强制坏块扫描
1001 读取设备信息
1010 读操作1
1011 读操作2
...... ......
1111 读操作n
步骤804，用户侧终端向硬件控制器发送操作指令；
具体地，所述操作命令用于指示对所述Nand设备的目标块集合进行读/写操作以及进行所述读/写操作所采用的数据传输方式，所述数据传输方式包括并行传输和串行传输中的至少一种。
步骤805，可选的，当操作指令指示进行所述读/写操作所采用的数据传输方式为串行传输时，硬件控制器基于操作指令来生成串行(Serial)Nand底层命令。
具体地，当控制指令指示进行所述读/写操作所采用的数据传输方式为串行传输时，硬件控制器生成Serial Nand底层命令。举例来讲，对于某个块某个页编程操作，对应有写使能、编写加载、编写执行、获取特征等过程，而每个过程又分解为单个或多个操作周期来完成，每个操作周期由8个操作时间组成。
步骤806，可选的，当操作指令指示进行所述读/写操作所采用的数据传输方式为并行传输时，硬件控制器基于操作指令来生成并行(Parallel)Nand底层命令。
具体地，当操作指令指示进行所述读/写操作所采用的数据传输方式为并行传输时，硬件控制器生成Parallel Nand底层命令。举例来讲，底层操作包括编写加载、地址发送、编写确认、读状态、读状态寄存等步骤。另外，Parallel Nand设备一般采用异步接口时序，有特别的地址、命令、读/写控制信号；本申请中针对每个操作过程分解为单个或多个子操作来实现，子操作分别对应有地址、命令、读/写数据等。
步骤807，可选的，当操作指令指示对nand设备进行写操作时，硬件控制器跳过所述Nand设备中同时存在于所述坏块集合和所述目标块集合的块，对所述目标块集合中的其余块进行写操作。
具体可参考图6实施例中的相关描述，在此不再赘述。
步骤808，可选的，当操作指令指示对nand设备进行读操作时，硬件控制器跳过所述Nand设备中同时存在于所述坏块集合和所述目标块集合的块，对所述目标块集合中的其余块进行读操作。
具体可参考图7实施例中的相关描述，在此不再赘述。
需要说明的是，步骤807与步骤808可以是或关系，即在同一时间只执行写操作或读操作；步骤807与步骤808也可以是和关系，即终端发出的控制指令指示硬件控制器对Nand设备同时进行写操作与读操作。
步骤809，可选的，在读操作过程中对读操作对应的数据进行错误检查与纠正。
步骤810，可选的，将所述Nand设备的坏块信息、所述Nand设备对应的数据传输方式、所述Nand设备对应的最大访问速度保存到存储器。
具体地，当硬件控制器确定Nand设备中的坏块信息、数据传输方式、最大访问速度等参数后，可以将这些参数存储至存储器中，以防止掉电后数据丢失。具体实施例中，所述存储器可以是硬件控制器内的存储器，也可以是独立于硬件控制器、Nand设备的存储器，还可以是Nand设备中的专用存储区域(如Block-0区)。
通过本发明实施例提供的控制方法，硬件控制器在初始化的过程中测试最大访问速度进行传输，在读/写操作过程中能跳过坏块进行，且能对数据进行错误检查与纠错等等。可以看出，本发明实施例能够最大化用户体验，帮助终端快速地读/写数据，减少终端占用的运行内存等。
基于上述图4所描述的硬件控制器，下面具体说明硬件控制器中的相关模块执行本发明实施例的控制方法的过程。
本发明实施例中，硬件控制器的各个模块之间采用层次化设计进行内部的命令传递以及相应地处理操作。图10示出了硬件控制器配合终端进行一次操作过程的示意图，详细描述如下：
1、终端生成操作指令；
2、终端将操作指令传输至硬件控制器的主控制模块；
3、硬件控制器的主控制模块基于操作指令生成第一控制命令并传输至对应的读/写控制模块；
4、硬件控制器的读/写控制模块基于第一控制命令生成第二控制命令并传输至对应的快速缓存/页数据-读/写模块；
5、硬件控制器的快速缓存/页数据-读/写模块基于第二控制命令生成第三控制命令并传输至对应的串/并底层命令生成模块；
6、硬件控制器的串/并底层命令生成模块基于第三控制命令生成命令序列并传输至对应的串/并底层驱动信号生成模块；
7、硬件控制器的串/并底层驱动信号生成模块基于命令序列生成驱动时序并传输至Nand设备；
8-13、Nand设备以及硬件控制器各层模块依序向上一级反馈操作完成信号。
可以看出，终端发起控制操作后，硬件控制器通过内部控制命令控制各层模块进行操作，各层模块从上至下依序响应上一层模块的操作请求；对应地，在底层模块的操作完成后，各层模块从下至上依序反馈给上一层模块关于操作完成的信号。主控制模块接收到下一层的关于操作完成的信号后，向终端反馈操作结果，并等待下一次操作。
基于同一发明构思，本发明还提供了一种液晶显示器，该液晶显示器包括前述实施例中提供的硬件控制器，该液晶显示器还可以执行前述实施例中提供的控制方法。具体可参考前述实施例中的相关描述，在此不再赘述。
需要说明的是，在本发明实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
在本发明的描述中，需要说明的是，除非另有规定和限定，术语“安装”、“相连”、“连接”、“接”应做广义理解，例如，可以是机械连接或电连接，也可以是两个元件内部的连通，可以是直接相连，也可以通过中间媒介间接相连，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (15)

  1. 一种Nand设备的硬件控制器，其中，包括：
    坏块管理模块，用于管理Nand设备的坏块信息，所述坏块信息表示所述Nand设备中的坏块集合；
    主控制模块，用于接收终端的操作命令；所述操作命令用于指示对所述Nand设备的目标块集合进行读/写操作以及进行所述读/写操作所采用的数据传输方式，所述数据传输方式包括并行传输和串行传输中的至少一种；
    读写模块，用于跳过所述Nand设备中同时存在于所述坏块集合和所述目标块集合的块，对所述目标块集合中的其余块进行所述读/写操作。
  2. 根据权利要求1所述的硬件控制器，其中，所述写操作包括擦除操作和编程操作中的至少一个；坏块管理模块还用于，当所述写操作未成功写入数据到块中时，将所述写操作对应的块作为坏块增加到所述坏块集合。
  3. 根据权利要求1所述的硬件控制器，其中，所述硬件控制器还包括错误校验模块，所述错误校验模块用于在读操作过程中对读操作对应的数据进行错误检查与纠正。
  4. 根据权利要求1所述的硬件控制器，其中，所述硬件控制器还包括速度测试模块，速度测试模块用于测试所述Nand设备的最大访问速度；
    所述读写模块具体用于，根据所述最大访问速度对所述目标块集合中的其余块进行所述读/写操作。
  5. 根据权利要求4所述的硬件控制器，其中，所述硬件控制器还包括掉电保护模块，所述掉电保护模块用于将所述Nand设备的坏块信息、所述Nand设备对应的数据传输方式、所述Nand设备对应的最大访问速度保存到存储器。
  6. 一种Nand设备的控制方法，其中，包括：
    获取Nand设备的坏块信息，所述坏块信息表示所述Nand设备中的坏块集合；
    接收终端的操作命令；所述操作命令用于指示对所述Nand设备的目标块集合进行读/写操作以及进行所述读/写操作所采用的数据传输方式，所述数据传输方式包括并行传输和串行传输中的至少一种；
    跳过所述Nand设备中同时存在于所述坏块集合和所述目标块集合的块，对所述目标块集合中的其余块进行所述读/写操作。
  7. 根据权利要求6所述的方法，其中，所述方法还包括：当所述写操作未成功写入数据 到块中时，将所述写操作对应的块作为坏块增加到所述坏块集合；所述写操作包括擦除操作和编程操作中的至少一个。
  8. 根据权利要求6所述的方法，其中，所述方法还包括：在读操作过程中对读操作对应的数据进行错误检查与纠正。
  9. 根据权利要求6所述的方法，其中，所述方法还包括：测试所述Nand设备的最大访问速度；根据所述最大访问速度对所述目标块集合中的其余块进行所述读/写操作。
  10. 根据权利要求6所述的方法，其中，所述方法还包括：将所述Nand设备的坏块信息、所述Nand设备对应的数据传输方式、所述Nand设备对应的最大访问速度保存到存储器。
  11. 一种液晶显示器，其中，包括Nand设备的硬件控制器，所述Nand设备的硬件控制器包括：
    坏块管理模块，用于管理Nand设备的坏块信息，所述坏块信息表示所述Nand设备中的坏块集合；
    主控制模块，用于接收终端的操作命令；所述操作命令用于指示对所述Nand设备的目标块集合进行读/写操作以及进行所述读/写操作所采用的数据传输方式，所述数据传输方式包括并行传输和串行传输中的至少一种；
    读写模块，用于跳过所述Nand设备中同时存在于所述坏块集合和所述目标块集合的块，对所述目标块集合中的其余块进行所述读/写操作。
  12. 根据权利要求11所述的液晶显示器，其中，所述写操作包括擦除操作和编程操作中的至少一个；坏块管理模块还用于，当所述写操作未成功写入数据到块中时，将所述写操作对应的块作为坏块增加到所述坏块集合。
  13. 根据权利要求11所述的液晶显示器，其中，所述硬件控制器还包括错误校验模块，错误校验模块用于在读操作过程中对读操作对应的数据进行错误检查与纠正。
  14. 根据权利要求11所述的液晶显示器，其中，所述硬件控制器还包括速度测试模块，速度测试模块用于测试所述Nand设备的最大访问速度；
    读写模块具体用于，根据所述最大访问速度对所述目标块集合中的其余块进行所述读/写操作。
  15. 根据权利要求14所述的液晶显示器，其中，所述硬件控制器还包括掉电保护模块，所述掉电保护模块用于将所述Nand设备的坏块信息、所述Nand设备对应的数据传输方式、所述Nand设备对应的最大访问速度保存到存储器。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112000595A (zh) * 2020-07-06 2020-11-27 西安电子科技大学 一种阵列通道控制系统、方法、控制器、存储介质及应用

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109614044A (zh) * 2018-12-04 2019-04-12 浪潮电子信息产业股份有限公司 一种固态硬盘写错误的处理方法、装置及设备
CN109616036B (zh) * 2019-01-07 2022-01-18 重庆京东方显示技术有限公司 显示屏单体、显示屏单体不良位置定位系统及其定位方法
CN110471791A (zh) * 2019-07-15 2019-11-19 深圳市德名利电子有限公司 一种对闪存的坏块信息的存储方法和装置以及设备
CN111933199B (zh) * 2020-08-07 2021-03-30 深圳市纵维立方科技有限公司 基于存储器的数据读写方法、装置及存储介质
CN112068781B (zh) * 2020-09-10 2024-03-22 深圳芯邦科技股份有限公司 一种存储器的数据读写方法及相关设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105302474A (zh) * 2014-07-31 2016-02-03 华为技术有限公司 控制闪存的写操作的方法和闪存的控制器
CN107247563A (zh) * 2017-07-06 2017-10-13 济南浪潮高新科技投资发展有限公司 一种nand flash芯片的块信息标识实现方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102331911B (zh) * 2011-06-17 2014-07-16 杭州华三通信技术有限公司 用于文件系统向Nand Flash写数据的驱动装置及方法
CN105740163A (zh) * 2016-01-29 2016-07-06 山东鲁能智能技术有限公司 一种Nand Flash坏块管理方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105302474A (zh) * 2014-07-31 2016-02-03 华为技术有限公司 控制闪存的写操作的方法和闪存的控制器
CN107247563A (zh) * 2017-07-06 2017-10-13 济南浪潮高新科技投资发展有限公司 一种nand flash芯片的块信息标识实现方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112000595A (zh) * 2020-07-06 2020-11-27 西安电子科技大学 一种阵列通道控制系统、方法、控制器、存储介质及应用
CN112000595B (zh) * 2020-07-06 2022-02-01 西安电子科技大学 一种阵列通道控制系统、方法、控制器、存储介质及应用

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