WO2019227359A1 - 薄膜晶体管及其制作方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板和显示装置 Download PDF

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WO2019227359A1
WO2019227359A1 PCT/CN2018/089097 CN2018089097W WO2019227359A1 WO 2019227359 A1 WO2019227359 A1 WO 2019227359A1 CN 2018089097 W CN2018089097 W CN 2018089097W WO 2019227359 A1 WO2019227359 A1 WO 2019227359A1
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layer
substrate
contact
contact layer
interlayer dielectric
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French (fr)
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陈小明
赵晓辉
杨倩
施国龙
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to PCT/CN2018/089097 priority patent/WO2019227359A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

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  • the present invention relates to the field of display technology, and in particular, to a thin film transistor and a manufacturing method thereof, an array substrate, and a display device.
  • top-gate thin film transistors are used in active matrix organic light emitting display devices (OLEDs) due to their small parasitic capacitance and other advantages.
  • One method of making the source and drain regions into ohmic contact is to perform plasma treatment on the source and drain regions.
  • the plasma treatment may cause the channel region to be partially conductive.
  • the plasma treatment of hydrogen has a doping effect on indium gallium zinc oxide (IGZO) to make the source and drain regions conductive. Diffusion is isotropic, causing a part of the channel region to be conductorized, leading to an increase in parasitic capacitance.
  • IGZO indium gallium zinc oxide
  • an embodiment of the present invention discloses a thin film transistor and a manufacturing method thereof, an array substrate, and a display device.
  • a thin film transistor includes a substrate, an active layer, a first contact layer, a second contact layer, a gate insulating layer, a gate, a source, and a drain.
  • the active layer, the first contact layer, and The second contact layer is disposed on the substrate, and an overlap area between an orthographic projection of the gate on the substrate and an orthographic projection of the first contact layer on the substrate is Zero, the overlapping area between the orthographic projection of the gate on the substrate and the orthographic projection of the second contact layer on the substrate is zero.
  • first contact layer and the second contact layer are located on two sides of the active layer, respectively.
  • first contact layer is in contact with both the active layer and the source
  • second contact layer is in contact with both the active layer and the drain.
  • the substrate includes a substrate and a buffer layer which are disposed in a stacked manner, and the active layer is disposed on a side of the buffer layer away from the substrate.
  • the thin film transistor further includes a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer, and the first interlayer dielectric layer and the second interlayer dielectric layer are disposed on the substrate.
  • the first interlayer dielectric layer is disposed next to the first contact layer
  • the second interlayer dielectric layer is disposed next to the second contact layer
  • the third interlayer dielectric layer is disposed On the gate.
  • the active layer is a metal oxide semiconductor layer.
  • An array substrate includes the thin film transistor described above.
  • a display device includes the array substrate as described above.
  • a method for manufacturing a thin film transistor includes the following steps:
  • the prefabricated structure includes a prefabricated active layer, a gate insulating layer, and a gate electrode arranged in a stack;
  • An ion is implanted into a set region of the pre-formed active layer to form a first contact layer and a second contact layer, thereby forming a second pre-formed structure.
  • the remaining area of the pre-formed active layer is an active layer, and the gate electrode is The overlap area between the orthographic projection on the substrate and the orthographic projection of the first contact layer on the substrate is zero, and the orthographic projection of the gate on the substrate and the first The overlapping area between the two contact layers' orthographic projections on the substrate is zero.
  • the method includes:
  • a source electrode and a drain electrode are formed on the second prefabricated structure, the source electrode is in contact with both the first contact layer and the active layer, and the drain electrode is in contact with the second contact layer and the active layer.
  • the source layers are all in contact.
  • the step of “providing a substrate and forming a first prefabricated structure on the substrate” includes the following steps:
  • the substrate Providing the substrate, and forming the prefabricated active layer, the first prefabricated gate insulating layer, the first prefabricated gate, and the first photoresist layer that are stacked on the substrate;
  • the second photoresist layer is peeled off to form the first prefabricated structure.
  • the step of “implanting ions into a set region of the pre-formed active layer to form a first contact layer and a second contact layer” includes: performing a hydrogen plasma treatment on the set region of the pre-formed active layer. The first contact layer and the second contact layer.
  • the pre-made active layer includes a first region, a second region, and a third region, the third region is connected between the first region and the second region, and the setting region includes all The first area and the second area.
  • the "forming the source and drain on the second prefabricated structure” further includes: forming a first interlayer dielectric layer, a second interlayer dielectric layer, and a third layer on the second prefabricated structure. Interlayer dielectric layer, the first interlayer dielectric layer portion is disposed at an end of the first contact layer away from the active layer, and the second interlayer dielectric layer portion is disposed at the second contact layer away from the first contact layer One end of the active layer.
  • the "forming a source and a drain on the second prefabricated structure” further includes: forming a passivation layer on the second prefabricated structure, and the passivation layer is provided on the source and On the drain, the first interlayer dielectric layer, the second interlayer dielectric layer, and the third dielectric layer.
  • the orthogonal projection of the gate on the substrate and the orthogonal projection of the first contact layer on the substrate are different.
  • the area of overlap between the gates is zero, and the area of overlap between the orthographic projection of the gate on the substrate and the orthographic projection of the second contact layer on the substrate is zero.
  • the parasitic capacitance of the area where the active layer is located (channel region) due to the conductorization improves the performance of the thin film transistor.
  • FIG. 1 is a schematic cross-sectional view of a thin film transistor provided by an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram formed in step 201 shown in FIG. 2.
  • FIG. 4 is a schematic structural diagram formed in step 202 shown in FIG. 2.
  • FIG. 5 is a detailed flowchart of step 201 shown in FIG. 2.
  • FIG. 6 is a schematic structural diagram formed in step 2011 of FIG. 5.
  • FIG. 7 is a schematic structural diagram formed in step 2012 of FIG. 5.
  • FIG. 8 is a schematic structural diagram formed in step 2013 of FIG. 5.
  • FIG. 9 is a schematic structural diagram formed in step 2014 of FIG. 5.
  • FIG. 10 is a schematic structural diagram formed in step 2015 of FIG. 5.
  • FIG. 11 is a schematic diagram of an array substrate provided by an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a display device according to an embodiment of the present invention.
  • an embodiment of the present invention provides a thin film transistor 10.
  • the thin film transistor 10 includes a substrate 11, an active layer 12, a first contact layer 13, a second contact layer 14, a gate insulating layer 15, a gate 16, a source 17, and a drain 18.
  • the active layer 12, the first contact layer 13 and the second contact layer 14 are disposed on the substrate 11, and the first contact layer 13 and the second contact layer 14 are respectively located on the substrate 11. Both sides of the active layer 12.
  • the gate insulating layer 15 is formed on the active layer 12, and the gate 16 is formed on the gate insulating layer 15. In other words, the active layer 12, the gate insulating layer 15, and the gate 16 are sequentially stacked on the substrate 11.
  • the first contact layer 13 and the second contact layer 14 are formed by implanting ions into a pre-set active layer 31 (shown in FIG. 3 to FIG. 6), such as hydrogen ions.
  • the active layer 31 is subjected to a plasma treatment of hydrogen, and the pre-processed active layer 31 is the active layer 12 without being subjected to a plasma treatment of hydrogen.
  • the first contact layer 13 is in contact with both the source electrode 17 and the active layer 12, and the second contact layer 14 is in contact with both the drain electrode 18 and the active layer 12.
  • the first contact layer 13 and the second contact layer 14 are similar to an ohmic contact layer.
  • the overlapping area between the orthographic projection of the gate 16 on the substrate 11 and the orthographic projection of the first contact layer 13 on the substrate 11 is zero.
  • the overlapping area between the orthographic projection on the substrate 11 and the orthographic projection of the second contact layer 14 on the substrate 11 is zero, so as to avoid the region (channel region) where the gate 16 and the active layer 12 are located.
  • the parasitic capacitance caused in part by the conductorization improves the performance of the thin film transistor 10.
  • the first contact layer 13 and the second contact layer 14 are metal or alloy layers of the metal oxide semiconductor layer (active layer) after the action of hydrogen ions.
  • the contact resistance between the first contact layer 13 and the second contact layer 14 and the active layer 12 is small, and the adhesion with the active layer 12 is very good.
  • the first contact layer 13 is located directly below the source electrode 17, and the second contact layer 14 is located directly below the drain electrode 18, which can prevent the formation of a non-channel high-resistance region and the gate electrode 16.
  • the formation of parasitic capacitance with the source 17 or the gate 16 and the drain 18 further improves the performance of the thin film transistor 10.
  • the first contact layer 13 and the second contact layer 14 are disposed symmetrically in a mirror image.
  • the substrate 11 includes a base 113 and a buffer layer 115 that are stacked.
  • the active layer 12 is disposed on a side of the buffer layer 115 away from the base 113.
  • the thin film transistor 10 further includes a first interlayer dielectric layer 191, a second interlayer dielectric layer 193, and a third interlayer dielectric layer 195.
  • the first interlayer dielectric layer 191 and the second interlayer dielectric layer 193 are disposed on the buffer layer 115. An end of the first interlayer dielectric layer 191 and the first contact layer 13 away from the active layer 12 is disposed immediately. An end of the second interlayer dielectric layer 193 and the second contact layer 14 remote from the active layer 12 is disposed immediately.
  • the source electrode 17 is disposed on the first interlayer dielectric layer 191 and the first contact layer 13.
  • the drain electrode 18 is disposed on the second interlayer dielectric layer 193 and the second contact layer 14.
  • the third interlayer dielectric layer 195 is disposed on the gate 16 and partially disposed on the gate insulating layer 15.
  • the thin film transistor 10 further includes a passivation layer 20.
  • the passivation layer 20 is provided on the source electrode 17, the drain electrode 18, the first interlayer dielectric layer 191, the second interlayer dielectric layer 193, and the third interlayer dielectric layer. 195 on.
  • a method for manufacturing the above thin film transistor 10 is shown in FIG. 2 and includes the following steps:
  • Step 201 referring to FIG. 3, providing a substrate 11 on which a first prefabricated structure 101 is formed.
  • the prefabricated structure 101 includes a prefabricated active layer 31, a gate insulating layer 15 and a gate, which are arranged in a stack.
  • the electrode 16 is disposed adjacent to the substrate 11.
  • the prefabricated active layer 31 may be a metal oxide semiconductor layer, for example, it may be Indium Gallium Zinc Oxide (IGZO), Hafnium Indium Zinc Oxide (HIZO), Indium zinc oxide (IZO), amorphous indium zinc oxide a-InZnO, amorphous zinc oxide doped fluorine oxide ZnO: F, indium oxide doped tin oxide In2O3: Sn, amorphous indium oxide Doped molybdenum oxide In2O3: Mo, chromium tin oxide Cd2SnO4, amorphous zinc oxide doped aluminum oxide ZnO: Al, amorphous titanium oxide doped niobium oxide TiO2: Nb, chromium tin oxide Cd-Sn-O Or other metal oxides.
  • the pre-made active layer 31 is IGZO.
  • Step 202 implanting ions into a predetermined area of the pre-formed active layer 31 to form a first contact layer 13 and a second contact layer 14, thereby forming a second pre-formed structure 102.
  • the remaining area of the pre-formed active layer 31 is the active layer 12.
  • the orthographic projection of the gate 16 on the substrate 11 and the orthographic projection of the first contact layer 13 on the substrate 11 are different.
  • the overlap area between the two is zero, and the overlap area between the orthographic projection of the gate 16 on the substrate 11 and the orthographic projection of the second contact layer 14 on the substrate 11 is zero.
  • a first contact layer 13 and a second contact layer 14 are formed by performing a hydrogen plasma treatment on a set region of the pre-formed active layer 31.
  • the prefabricated active layer 31 includes a first region 601, a second region 602, and a third region 603.
  • the third region 603 is connected to the first region 601 and the second region 602.
  • the first region 601 corresponds to the region where the source electrode 17 is located
  • the second region 602 corresponds to the region where the drain electrode 18 is located.
  • Hydrogen plasma treatment is performed in the first region 601 and the second region 602.
  • the part of the pre-fabricated active layer 31 located in the third region 603 is the active layer 12, and the set region includes a first region 601 and a second region 602.
  • Step 203 referring to FIG. 1 again, a source electrode 17 and a drain electrode 18 are formed on the second prefabricated structure 102, and the first contact layer 13 is in contact with both the source electrode 17 and the active layer 12, The second contact layer 14 is in contact with both the drain electrode 18 and the active layer 12.
  • the step 203 further includes forming a first interlayer dielectric layer 191, a second interlayer dielectric layer 193, and a third interlayer dielectric layer 195 on the second prefabricated structure 102.
  • the first interlayer dielectric layer 191 is partially disposed on an end of the first contact layer 13 away from the active layer 12, and 193 is partially disposed on an end of the second contact layer 14 away from the active layer 12,
  • a third interlayer dielectric layer 195 is disposed on the gate 16.
  • the step 203 further includes forming a passivation layer 20 on the prefabricated structure 101.
  • the passivation layer 20 is disposed on the source electrode 17, the drain electrode 18, the first interlayer dielectric layer 191, and On the second interlayer dielectric layer 193 and the third interlayer dielectric layer 195.
  • the first region 601 and the second region 602 ie, the source and drain regions
  • the contact resistance between 14 and the drain electrode 18 further improves the performance of the thin film transistor 10.
  • the step 201 specifically includes the following steps:
  • Step 2012 referring to FIG. 7, the first pre-made gate insulating layer 32 is etched to form a second pre-made gate insulating layer 42, and the first pre-made gate 33 is etched to form a second pre-made gate 43.
  • the first pre-made gate insulating layer 32 is etched to be thinned.
  • step 2013, referring to FIG. 8, a portion of the first photoresist layer 36 is removed to form a second photoresist layer 56.
  • the pattern of the second photoresist layer 56 corresponds to the pattern of the gate 16, and the second pre-made gate 43 is partially exposed outside the second photoresist layer 56.
  • Step 2014 referring to FIG. 9, the second pre-made gate 43 is etched to form the gate 16.
  • the portion of the second pre-made gate 43 exposed outside the second photoresist layer 56 is etched away.
  • the second pre-fabricated gate insulating layer 42 is equivalent to the etch stop layer of the pre-fabricated active layer 31, which prevents the pre-fabricated active layer 31 from being eroded and polluted.
  • Step 2015 referring to FIG. 10, the second pre-made gate insulating layer 42 is etched to form a gate insulating layer 15.
  • Step 2016, referring to FIG. 3 again, peeling the second photoresist layer 56 to form the first prefabricated structure 101.
  • the stepwise etching to form the gate insulating layer 15 and the gate 16 is beneficial to accurately control the thickness and pattern of the gate insulating layer 15 and the gate 16, thereby improving the yield of the thin film transistor 10.
  • step 202 the second photoresist layer 56 is removed.
  • an array substrate 100 includes the thin film transistor 10 described above.
  • the array substrate 100 further includes other necessary or unnecessary structures, such as a pixel electrode 70.
  • a display device 200 includes the array substrate 100 described above.
  • the orthographic projection of the gate 16 on the substrate 11 and the first contact layer 13 are in the The overlapping area between the orthographic projections on the substrate 11 is zero.
  • the orthographic projection of the gate 16 on the substrate 11 and the orthographic projection of the second contact layer 14 on the substrate 11 are zero.
  • the overlapping area between the two electrodes is zero, which avoids the parasitic capacitance caused by the conductive part of the region where the gate 16 and the active layer 12 are located (channel region), which improves the performance of the thin film transistor 10 without increasing the mask.

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Abstract

本发明公开一种薄膜晶体管(10)，包括衬底(11)、有源层(12)、第一接触层(13)、第二接触层(14)、栅极绝缘层(15)、栅极(16)、源极(17)及漏极(18)，所述有源层(12)、所述第一接触层(13)及所述第二接触层(14)设于所述衬底(11)上，所述栅极(16)在所述衬底(11)上的正投影与所述第一接触层(13)在所述衬底(11)上的正投影之间的交叠面积为零，所述栅极(16)在所述衬底(11)上的正投影与所述第二接触层(14)在所述衬底(11)上的正投影之间的交叠面积为零。本发明还公开一种薄膜晶体管的制作方法、阵列基板和显示装置。

Description

薄膜晶体管及其制作方法、阵列基板和显示装置 技术领域
本发明涉及显示技术领域，特别涉及一种薄膜晶体管及其制作方法、阵列基板和显示装置。
背景技术
在显示技术领域，顶栅型薄膜晶体管由于寄生电容小等优点，被应用于有源矩阵式有机发光显示器件(Organic Light Emitting Device，OLED)。
使源漏极区域形成欧姆接触的其中一种方法是，对该源漏极区域进行等离子处理。然而，等离子处理可能会造成沟道区域部分被导体化，例如，氢的等离子处理对铟镓锌氧化物(indium gallium zinc oxide，IGZO)有掺杂作用使源漏极区域导体化，但由于氢的扩散是各向同性的，造成沟道区域也有一部分被导体化，导致寄生电容增加。
发明内容
为解决上述问题，本发明实施例公开一种薄膜晶体管及其制作方法、阵列基板和显示装置。
一种薄膜晶体管，包括衬底、有源层、第一接触层、第二接触层、栅极绝缘层、栅极、源极及漏极，所述有源层、所述第一接触层及所述第二接触层设于所述衬底上，所述栅极在所述衬底上的正投影与所述第一接触层在所述衬底上的正投影之间的交叠面积为零，所述栅极在所述衬底上的正投影与所述第二接触层在所述衬底上的正投影之间的交叠面积为零。
进一步地，所述第一接触层和所述第二接触层分别位于所述有源层的两侧。
进一步地，所述第一接触层与所述有源层及所述源极均接触，所述第二接触层与所述有源层及所述漏极均接触。
进一步地，所述衬底包括层叠设置的基底及缓冲层，所述有源层设于所述缓冲层远离所述基底的一侧。
进一步地，所述薄膜晶体管还包括第一层间介质层及第二层间介质层及第 三层间介质层，所述第一层间介质层与所述第二层间介质层设于所述缓冲层上，所述第一层间介质层与所述第一接触层紧邻设置，所述第二层间介质层与所述第二接触层紧邻设置，所述第三层间介质层设于所述栅极上。
进一步地，所述有源层为金属氧化物半导体层。
一种阵列基板，包括如上所述的薄膜晶体管。
一种显示装置，包括如上所述的阵列基板。
一种薄膜晶体管的制作方法，包括以下步骤：
提供一衬底，在所述衬底上形成第一预制结构，所述预制结构包括层叠设置的预制有源层、栅极绝缘层及栅极；
对所述预制有源层的设定区域注入离子形成第一接触层与第二接触层，从而形成第二预制结构，所述预制有源层的其余区域为有源层，所述栅极在所述衬底上的正投影与所述第一接触层在所述衬底上的正投影之间的交叠面积为零，所述栅极在所述衬底上的正投影与所述第二接触层在所述衬底上的正投影之间的交叠面积为零。
进一步地，所述“对所述预制有源层的设定区域注入离子形成第一接触层与第二接触层”之后包括：
在所述第二预制结构上形成源极及漏极，所述源极与所述第一接触层及所述有源层均接触，所述漏极与所述第二接触层及所述有源层均接触。
进一步地，所述“提供一衬底，在所述衬底上形成第一预制结构”，包括以下步骤：
提供所述衬底，在所述衬底上形成层叠设置的所述预制有源层、第一预制栅极绝缘层、第一预制栅极及第一光阻层；
蚀刻所述第一预制栅极绝缘层形成第二预制栅极绝缘层，蚀刻所述第一预制栅极形成第二预制栅极；
去除所述第一光阻层部分形成第二光阻层；
蚀刻所述第二预制栅极形成所述栅极；
蚀刻所述第二预制栅极绝缘层形成所述栅极绝缘层；
剥离所述第二光阻层，从而形成所述第一预制结构。
进一步地，所述“对所述预制有源层的设定区域注入离子形成第一接触层 与第二接触层”，包括：对所述预制有源层的设定区域进行氢的等离子处理形成所述第一接触层与所述第二接触层。
进一步地，所述预制有源层包括第一区域、第二区域及第三区域，所述第三区域连接于所述第一区域与所述第二区域之间，所述设定区域包括所述第一区域及所述第二区域。
进一步地，所述“在所述第二预制结构上形成源极及漏极”，还包括：在所述第二预制结构形成第一层间介质层、第二层间介质层及第三层间介质层，所述第一层间介质层部分设于所述第一接触层远离所述有源层的一端，所述第二层间介质层部分设于所述第二接触层远离所述有源层的一端。
进一步地，所述“在所述第二预制结构上形成源极及漏极”，还包括：在所述第二预制结构形成钝化层，所述钝化层设于所述源极、所述漏极、所述第一层间介质层、所述第二层间介质层及所述第三介质层上。
本发明提供的薄膜晶体管、阵列基板、显示装置及薄膜晶体管的制作方法，由于所述栅极在所述衬底上的正投影与所述第一接触层在所述衬底上的正投影之间的交叠面积为零，所述栅极在所述衬底上的正投影与所述第二接触层在所述衬底上的正投影之间的交叠面积为零，避免栅极与有源层所在区域(沟道区域)部分因导体化而产生的寄生电容，提高了薄膜晶体管的性能。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施方式提供的薄膜晶体管的剖面示意图。
图2为本发明实施方式提供的薄膜晶体管的制作方法的流程图。
图3为图2所示步骤201形成的结构示意图。
图4为图2所示步骤202形成的结构示意图。
图5为图2所示步骤201的具体流程图。
图6为图5的步骤2011形成的结构示意图。
图7为图5的步骤2012形成的结构示意图。
图8为图5的步骤2013形成的结构示意图。
图9为图5的步骤2014形成的结构示意图。
图10为图5的步骤2015形成的结构示意图。
图11为本发明实施方式提供的阵列基板的示意图。
图12为本发明实施方式提供的显示装置的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明实施方式提供一种薄膜晶体管10。薄膜晶体管10包括衬底11、有源层12、第一接触层13、第二接触层14、栅极绝缘层15、栅极16、源极17及漏极18。
所述有源层12、所述第一接触层13及所述第二接触层14设于所述衬底11上，所述第一接触层13和所述第二接触层14分别位于所述有源层12的两侧。
所述栅极绝缘层15形成于所述有源层12上，所述栅极16形成于所述栅极绝缘层15上。换而言之，所述有源层12、所述栅极绝缘层15、所述栅极16依次层叠于所述衬底11上。
本实施方式中，通过对预制有源层31(图3-图6所示)的设定区域注入离子形成第一接触层13和第二接触层14，例如氢的离子，即对所述预制有源层31进行氢的等离子处理，所述预制有源层31未经氢的等离子处理部分为有源层12。所述第一接触层13与所述源极17及所述有源层12均接触，所述第 二接触层14与所述漏极18及所述有源层12均接触。所述第一接触层13与所述第二接触层14类似于欧姆接触层。
所述栅极16在所述衬底11上的正投影与所述第一接触层13在所述衬底11上的正投影之间的交叠面积为零，所述栅极16在所述衬底11上的正投影与所述第二接触层14在所述衬底11上的正投影之间的交叠面积为零，避免栅极16与有源层12所在区域(沟道区域)部分因导体化而产生的寄生电容，提高了薄膜晶体管10的性能。
第一接触层13和第二接触层14为金属氧化物半导体层(有源层)经氢离子作用后的金属或合金层。第一接触层13和第二接触层14与有源层12的接触电阻较小，且与有源层12的附着性非常好。
所述第一接触层13位于所述源极17的正下方，所述第二接触层14位于所述漏极18的正下方，可以避免非沟道高阻区的形成，且避免栅极16与源极17或栅极16与漏极18之间寄生电容的形成，进一步提高了薄膜晶体管10的性能。
在一实施方式中，所述第一接触层13和所述第二接触层14呈镜像对称设置。
所述衬底11包括层叠设置的基底113及缓冲层115，所述有源层12设于所述缓冲层115远离所述基底113的一侧。
所述薄膜晶体管10还包括第一层间介质层191、第二层间介质层193及第三层间介质层195。所述第一层间介质层191与所述第二层间介质层193设于所述缓冲层115上。所述第一层间介质层191与所述第一接触层13远离所述有源层12的一端紧邻设置。所述第二层间介质层193与所述第二接触层14远离所述有源层12的一端紧邻设置。所述源极17设于所述第一层间介质层191与所述第一接触层13上。所述漏极18设于所述第二层间介质层193与所述第二接触层14上。所述第三层间介质层195设于所述栅极16上，并部分设于所述栅极绝缘层15。
所述薄膜晶体管10还包括钝化层20，钝化层20设于源极17、所述漏极18、第一层间介质层191、第二层间介质层193及第三层间介质层195上。
一种上述薄膜晶体管10的制作方法，请参阅图2，包括以下步骤：
步骤201，请参阅图3，提供一衬底11，在所述衬底11上形成第一预制结构101，所述预制结构101包括层叠设置的预制有源层31、栅极绝缘层15及栅极16，所述预制有源层31与所述衬底11相邻设置。
较佳地，所述预制有源层31可以是金属氧化物半导体层，例如可以是铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、铪铟锌氧化物(Hafnium Indium Zinc Oxide，HIZO)、铟锌氧化物(Indium Zinc Oxide，IZO)、非晶铟锌氧化物a-InZnO、非晶氧化锌掺杂氟氧化物ZnO：F、氧化铟掺杂锡氧化物In2O3：Sn、非晶氧化铟掺杂钼氧化物In2O3：Mo、铬锡氧化物Cd2SnO4、非晶氧化锌掺杂铝氧化物ZnO：Al、非晶氧化钛掺杂铌氧化物TiO2：Nb、铬锡氧化物Cd-Sn-O或其他金属氧化物。本实施方式中，所述预制有源层31为IGZO。
步骤202，请参阅图4，对所述预制有源层31的设定区域注入离子形成第一接触层13与第二接触层14，从而形成第二预制结构102。所述预制有源层31的其余区域为有源层12，所述栅极16在所述衬底11上的正投影与所述第一接触层13在所述衬底11上的正投影之间的交叠面积为零，所述栅极16在所述衬底11上的正投影与所述第二接触层14在所述衬底11上的正投影之间的交叠面积为零。
本实施方式中，对所述预制有源层31的设定区域进行氢的等离子处理形成第一接触层13与第二接触层14。
请再次参阅图3，所述预制有源层31包括第一区域601、第二区域602及第三区域603，所述第三区域603连接于所述第一区域601与所述第二区域602之间，所述第一区域601对应所述源极17所在区域，所述第二区域602对应所述漏极18所在区域，在第一区域601及第二区域602进行氢的等离子处理，所述预制有源层31位于第三区域603的部分为有源层12，所述设定区域包括第一区域601及第二区域602。
步骤203，请再次参阅图1，在所述第二预制结构102上形成源极17及漏极18，所述第一接触层13与所述源极17及所述有源层12均接触，所述第二接触层14与所述漏极18及所述有源层12均接触。
所述步骤203中，还包括：在所述第二预制结构102形成第一层间介质层191、第二层间介质层193及第三层间介质层195，所述第一层间介质层191 部分设于所述第一接触层13远离所述有源层12的一端，所述第二层间介质层193部分设于所述第二接触层14远离所述有源层12的一端，第三层间介质层195设于所述栅极16上。
所述步骤203中，还包括在所述预制结构101形成钝化层20，所述钝化层20设于所述源极17、所述漏极18、所述第一层间介质层191及所述第二层间介质层193及所述第三层间介质层195上。
在一实施方式中，通过延长对第一区域601、第二区域602(即源漏极区域)进行等离子处理的时间，有利于降低第一接触层13与源极17及/或第二接触层14与漏极18之间的接触电阻，进而提高薄膜晶体管10的性能。
进一步地，请参阅图5，所述步骤201具体包括以下步骤：
步骤2011，请参阅图6，提供所述衬底11，在所述衬底11上形成层叠设置的预制有源层31、第一预制栅极绝缘层32、第一预制栅极33及第一光阻层36。
步骤2012，请参阅图7，蚀刻所述第一预制栅极绝缘层32形成第二预制栅极绝缘层42，蚀刻所述第一预制栅极33形成第二预制栅极43。
本实施方式中，蚀刻所述第一预制栅极绝缘层32进行减薄。
步骤2013，请参阅图8，去除第一光阻层36部分形成第二光阻层56。
第二光阻层56的图形对应栅极16的图形，所述第二预制栅极43部分暴露在所述第二光阻层56外。
步骤2014，请参阅图9，蚀刻所述第二预制栅极43形成栅极16。蚀刻掉所述第二预制栅极43暴露在所述第二光阻层56外的部分。所述第二预制栅极绝缘层42相当于预制有源层31的刻蚀阻挡层，避免预制有源层31受到侵蚀及污染。
步骤2015，请参阅图10，蚀刻所述第二预制栅极绝缘层42形成栅极绝缘层15。
步骤2016，请再次参阅图3，剥离第二光阻层56，从而形成所述第一预制结构101。
通过逐步刻蚀形成栅极绝缘层15及栅极16，有利于精确控制栅极绝缘层15及栅极16的厚度及图形，进而提高薄膜晶体管10的良率。
可以理解，在一实施例中，在进行完步骤202后，再将第二光阻层56去除。
请参阅图11，一种阵列基板100包括如上所述的薄膜晶体管10，当然，所述阵列基板100还包括其他必要或非必要的结构，例如像素电极70。
请参阅图12，一种显示装置200，包括如上所述的阵列基板100。
本发明提供的薄膜晶体管10、阵列基板100、显示装置200及薄膜晶体管10的制作方法，由于所述栅极16在所述衬底11上的正投影与所述第一接触层13在所述衬底11上的正投影之间的交叠面积为零，所述栅极16在所述衬底11上的正投影与所述第二接触层14在所述衬底11上的正投影之间的交叠面积为零，避免栅极16与有源层12所在区域(沟道区域)部分因导体化而产生的寄生电容，提高了薄膜晶体管10的性能，且不需增加Mask。
以上所述是本发明的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (15)

  1. 一种薄膜晶体管，其特征在于，包括衬底、有源层、第一接触层、第二接触层、栅极绝缘层、栅极、源极及漏极，所述有源层、所述第一接触层及所述第二接触层设于所述衬底上，所述栅极在所述衬底上的正投影与所述第一接触层在所述衬底上的正投影之间的交叠面积为零，所述栅极在所述衬底上的正投影与所述第二接触层在所述衬底上的正投影之间的交叠面积为零。
  2. 如权利要求1所述的薄膜晶体管，其特征在于，所述第一接触层和所述第二接触层分别位于所述有源层的两侧。
  3. 如权利要求2所述的薄膜晶体管，其特征在于，所述第一接触层与所述有源层及所述源极均接触，所述第二接触层与所述有源层及所述漏极均接触。
  4. 如权利要求1所述的薄膜晶体管，其特征在于，所述衬底包括层叠设置的基底及缓冲层，所述有源层设于所述缓冲层远离所述基底的一侧。
  5. 如权利要求4所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括第一层间介质层及第二层间介质层及第三层间介质层，所述第一层间介质层与所述第二层间介质层设于所述缓冲层上，所述第一层间介质层与所述第一接触层紧邻设置，所述第二层间介质层与所述第二接触层紧邻设置，所述第三层间介质层设于所述栅极上。
  6. 如权利要求1所述的薄膜晶体管，其特征在于，所述有源层为金属氧化物半导体层。
  7. 一种阵列基板，其特征在于，包括如权利要求1-6任意一项所述的薄膜晶体管。
  8. 一种显示装置，其特征在于，包括如权利要求7所述的阵列基板。
  9. 一种薄膜晶体管的制作方法，其特征在于，包括以下步骤：
    提供一衬底，在所述衬底上形成第一预制结构，所述预制结构包括层叠设置的预制有源层、栅极绝缘层及栅极，所述预制有源层与所述衬底相邻设置；
    对所述预制有源层的设定区域注入离子形成第一接触层与第二接触层，从而形成第二预制结构，所述预制有源层的其余区域为有源层，所述栅极在所述衬底上的正投影与所述第一接触层在所述衬底上的正投影之间的交叠面积为 零，所述栅极在所述衬底上的正投影与所述第二接触层在所述衬底上的正投影之间的交叠面积为零。
  10. 如权利要求9所述的制作方法，其特征在于，所述“提供一衬底，在所述衬底上形成第一预制结构”，包括以下步骤：
    提供所述衬底，在所述衬底上形成层叠设置的所述预制有源层、第一预制栅极绝缘层、第一预制栅极及第一光阻层；
    蚀刻所述第一预制栅极绝缘层形成第二预制栅极绝缘层，蚀刻所述第一预制栅极形成第二预制栅极；
    去除所述第一光阻层部分形成第二光阻层；
    蚀刻所述第二预制栅极形成所述栅极；
    蚀刻所述第二预制栅极绝缘层形成所述栅极绝缘层。
  11. 如权利要求9所述的制作方法，其特征在于，所述“对所述预制有源层的设定区域注入离子形成第一接触层与第二接触层”，包括：对所述预制有源层的设定区域进行氢的等离子处理形成所述第一接触层与所述第二接触层。
  12. 如权利要求9所述的制作方法，其特征在于，所述预制有源层包括第一区域、第二区域及第三区域，所述第三区域连接于所述第一区域与所述第二区域之间，所述设定区域包括所述第一区域及所述第二区域。
  13. 如权利要求9所述的制作方法，其特征在于，所述“对所述预制有源层的设定区域注入离子形成第一接触层与第二接触层”之后包括：
    在所述第二预制结构上形成源极及漏极，所述源极与所述第一接触层及所述有源层均接触，所述漏极与所述第二接触层及所述有源层均接触。
  14. 如权利要求13所述的制作方法，其特征在于，所述“在所述第二预制结构上形成源极及漏极”，还包括：在所述第二预制结构形成第一层间介质层、第二层间介质层及第三层间介质层，所述第一层间介质层部分设于所述第一接触层远离所述有源层的一端，所述第二层间介质层部分设于所述第二接触层远离所述有源层的一端。
  15. 如权利要求13所述的制作方法，其特征在于，所述“在所述第二预制结构上形成源极及漏极”，还包括：在所述第二预制结构形成钝化层，所述钝化层设于所述源极、所述漏极、所述第一层间介质层、所述第二层间介质层及所 述第三介质层上。
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