WO2019218706A1 - 一种dc-dc变换器 - Google Patents

一种dc-dc变换器 Download PDF

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Publication number
WO2019218706A1
WO2019218706A1 PCT/CN2019/070645 CN2019070645W WO2019218706A1 WO 2019218706 A1 WO2019218706 A1 WO 2019218706A1 CN 2019070645 W CN2019070645 W CN 2019070645W WO 2019218706 A1 WO2019218706 A1 WO 2019218706A1
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WIPO (PCT)
Prior art keywords
power tube
driving signal
diode
high level
turned
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PCT/CN2019/070645
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English (en)
French (fr)
Inventor
李永昌
吴辉
李斌华
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广州金升阳科技有限公司
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Publication of WO2019218706A1 publication Critical patent/WO2019218706A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/3353—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having at least two simultaneously operating switches on the input side, e.g. "double forward" or "double (switched) flyback" converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a DC-DC converter, and more particularly to a DC-DC converter with energy bidirectional flow.
  • the DC-DC converter is an essential component of modern high-frequency switching power supplies. As its name implies, it converts the direct current (DC) input voltage Vin into a more desirable or more efficient direct current (DC) output voltage Vo.
  • a unidirectional DC-DC converter refers to a DC-DC converter that converts a DC voltage supplied at an input terminal into a DC voltage having a higher, lower or reverse voltage level.
  • a bidirectional DC-DC converter can realize bidirectional transmission of energy by forward or reverse operation of a bidirectional DC-DC converter, that is, allowing electric energy to flow from a defined input to an output.
  • the end, and vice versa is equivalent to two unidirectional DC converters.
  • It is a typical "one-machine dual-purpose" device, in the energy recovery system of uninterruptible power supply, battery charge and discharge, electric vehicles, high-power equipment, A wide range of applications are available in applications such as backup power for high-power equipment.
  • the flyback converter has the characteristics of few devices and high reliability, and is widely used in small and medium power DC-DC converters with a power of 50W or less.
  • the existing application number is 201410724447.3, and the invention patent application named "two-way non-destructive active equalization device", hereinafter referred to as background document 1, shows a bidirectional converter composed of a flyback converter.
  • the background document of this application Figure 1 of Figure 1 is presented in this application, see Figure 1 of the present application. It can be seen that the RCD absorbing circuit composed of the diode D1, the resistor R1 and the capacitor C2 is set on the single side, and the RCD absorbing circuit composed of the diode D4, the resistor R3 and the capacitor C4 is set on the whole side.
  • the working principle of the RCD absorbing circuit is a well-known technology, and can be referred to the section "4.3 RCD absorption flyback converter” on page 67 of "Switching Power Supply Converter Topology and Design” published by China Electric Power Press.
  • the author is Zhang Xingzhu, International The standard book number is ISBN 978-7-5083-9015-4.
  • the shortcoming of this document is that the RCD absorbing circuit originally only works when the power tube of the flyback converter changes from saturation conduction to cutoff. In the case of excitation on the primary side, the RCD absorption circuit of the secondary side participates in the whole process, and the energy consumed is relatively large, and the "non-destructive" absorption described in the background document 1 cannot be achieved.
  • the application patent No. 201610251403.2 entitled “A Bidirectional Converter", hereinafter referred to as Background Document 2
  • Background Document 2 overcomes the deficiencies of Background Document 1.
  • the present application corresponds to FIG. 4 of the technical solution of Background Document 2.
  • the advantage of this document is that the secondary side RCD absorbing circuit does not participate in the operation when the primary side is excited, and the primary side RCD absorbing circuit does not participate in the operation when the secondary side is excited;
  • the energy is very small, achieving "lossless” absorption; however, it still has shortcomings, as analyzed below.
  • the drain of MOS transistor Q2 should be reduced from a higher voltage to 0V at the same time, that is, dU/dt is larger.
  • the electromagnetic radiation will be larger, that is, the shortcomings of the background document 2 are: the MOS tube Q2 has a high withstand voltage, and the high withstand voltage MOS tube has the same on-state internal resistance, and the cost thereof is greatly increased; Poor; especially when the input voltage has a wide operating range, the disadvantages are more obvious. The same problem exists with MOS tube Q1.
  • the existing bidirectional converter composed of a flyback converter that is, a flyback type bidirectional converter, including the background document 2
  • a flyback type bidirectional converter including the background document 2
  • FIG. 3 Application No. 201710654256.8, an invention patent application entitled “A DC-DC Bidirectional Converter”, proposes a bidirectional DC-DC converter based on active clamp flyback and a control scheme thereof,
  • the schematic diagram of the bidirectional DC-DC converter is shown in FIG. 3.
  • the driving timing diagrams of the power tubes in the forward working and the reverse working according to the contents of the background document 3 are as shown in FIG. 4A and FIG. 4B, and Vgs1 and Vgs2 are shown.
  • Vgs3 and Vgs4 are driving levels corresponding to the control terminals of the corresponding power tubes Q1, Q2, Q3 and Q4.
  • the first switching transistor Q1 is the main power tube
  • the second switching tube Q2 is the rectifier tube.
  • the third switch tube Q3 is a clamp tube, and the fourth power tube Q4 is not working; when the background document 3 works in reverse, the first switch tube Q1 is a rectifier tube, the second switch tube Q2 is a main power tube, and the third power tube Q3 Not working, the fourth power tube Q4 is a clamp tube.
  • Background Document 3 can indeed realize the partial energy recovery of the leakage inductance of the transformer (B).
  • the main power tube Q1/Q2 and the clamp tube Q3 can be realized by the resonance of the clamp capacitor C1/C2 and the leakage inductance.
  • /Q4 zero voltage turn-on also referred to as ZVS
  • the main power tube and the clamp tube drive are complementary, that is, the driving of Q1 and Q3 is complementary, and the clamp capacitor C1 is clamped.
  • the whole process of tube opening participates in resonance, which will bring some unnecessary resonance loss.
  • the rectifier ie, power tube Q2
  • the power tube Q2 on the output side is at the moment of turn-off
  • the junction capacitance and leakage inductance of the power tube resonate, there is a leakage inductance spike voltage, and the drain of the transformer B The greater the sense, the greater the voltage spike.
  • the present invention is to solve the deficiencies of the existing flyback bidirectional converter, and provides a new converter such that the leakage inductance peak voltages of the first side and the second side power tube are clamped and lowered.
  • the voltage spikes at turn-off and the reduced turn-off losses allow for a more efficient bidirectional conversion of energy.
  • a DC-DC converter including a first side, a second side, a transformer, a first power tube, a second power tube, a third power tube, a fourth power tube, and a first a clamp capacitor, and a second clamp capacitor, the transformer includes at least a first winding and a second winding, the connection relationship is:
  • the conduction current outflow end of the first power tube is negative as the input of the first side; the conduction current inflow end of the first power tube is connected to the opposite end of the first winding of the transformer and the conduction current outflow end of the third power tube;
  • the in-current end of the third power tube is connected to one end of the first clamp capacitor, and the other end of the first clamp capacitor is connected to the same end of the first winding of the transformer and forms an input positive of the first side;
  • the conduction current outflow end of the second power tube forms an input negative of the second side;
  • the conduction current inflow end of the second power tube is connected to the same name end of the second winding of the transformer and the conduction current outflow end of the fourth power tube;
  • the on current inflow end of the four power tube is connected to one end of the second clamp capacitor, and the other end of the second clamp capacitor is connected to the opposite end of the second winding of the transformer and forms an input positive of the second side;
  • the control end of the first power tube is used to input the first driving signal
  • the control end of the second power tube is used to input the second driving signal
  • the control end of the third power tube is used to input the third driving signal
  • the fourth power tube The control terminal is configured to input a fourth driving signal, and the first driving signal to the fourth driving signal request are:
  • the four driving signals are pulse signals composed of a high level and a low level, and the frequencies are the same;
  • the first driving signal is inverted from a low level to a high level after the first driving signal is delayed by a high level from a high level to a low level, and the second driving signal is at a high level.
  • the first driving signal is delayed from a low level to a high level after a second set time; when the second driving signal is turned from a high level to a low level, the first driving is reversed. After the signal delays for the third set time, it is flipped from the low level to the high level.
  • the second driving signal is delayed by the fourth set time.
  • the third driving signal is turned to a high level after a delay of the fifth set time after the second driving signal is turned to a high level, and the third driving signal is turned to a low level after the sixth set time, and then the second The driving signal is flipped to a low level after the third driving signal is turned to a low level or simultaneously;
  • the fourth driving signal is turned to a high level after a delay of the seventh set time when the first driving signal is turned to a high level, and the fourth driving signal is turned to a low level after the eighth set time, and then the first The drive signal is flipped low after the fourth drive signal is flipped low.
  • the other end of the first clamp capacitor is negatively connected to the input of the first side
  • the other end of the second clamp capacitor is negatively connected to the input of the second side
  • the first power tube, the second power tube, the third power tube, and the fourth power tube are all N-channel enhancement type MOS tubes, and both are turned on when they are high level and turned off when they are low level.
  • the sixth set time and the eighth set time are narrow pulses of a fixed time, the time length of which is greater than 50 ns, which is smaller than the minimum on time of the MOS transistor Q1 or the MOS transistor Q2.
  • the first set time and the fourth set time, the second set time and the third set time, and the sixth set time and the eighth set time are selected or selected two or all equal.
  • the first diode is further included, the anode of the first diode is connected to the source of the first power tube, and the cathode of the first diode is connected to the drain of the first power tube.
  • the second diode is further included, the anode of the second diode is connected to the source of the second power tube, and the cathode of the second diode is connected to the drain of the second power tube.
  • the third diode is further included, the anode of the third diode is connected to the source of the third power tube, and the cathode of the third diode is connected to the drain of the third power tube.
  • the fourth diode is further included, the anode of the fourth diode is connected to the source of the fourth power tube, and the cathode of the fourth diode is connected to the drain of the fourth power tube.
  • the control end of the power tube the port that controls the switch to be turned on and off.
  • the MOS tube it refers to the gate of the MOS tube
  • the triode it refers to the base of the triode.
  • the conduction current of the power tube flows in: the port through which the current flows after the power tube is turned on, such as the MOS tube, refers to the drain of the MOS tube, regardless of the N-channel, P-channel, enhanced or depleted MOS When the tube is turned on, the current flows from the drain with a high voltage to the source with a low voltage.
  • the triode it refers to the collector of the triode. When turned on, the current flows from the collector with a high voltage to a low voltage. The emitter.
  • the conduction current flowing out of the power tube After the power tube is turned on, the current flowing out of the port, for the MOS tube, refers to the source of the MOS tube; for the triode, the emitter of the triode.
  • FIG. 2 is a schematic diagram of a bidirectional converter in the background document 2;
  • FIG. 3 is a schematic diagram of a bidirectional converter in the background document 3;
  • 4A is a timing chart of driving of each power tube when the background document 3 is working in the forward direction;
  • 4B is a timing chart of driving of each power tube when the background document 3 is reversely operated
  • Figure 5 is a circuit schematic diagram of a first embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a body diode inside a power tube
  • Figure 7 is a circuit schematic diagram of the transformer of Figure 3 after equivalent
  • FIG. 8 is a timing chart of driving of each power tube according to the first embodiment of the present invention.
  • Figure 9 is a circuit diagram of the fifth embodiment.
  • the technical idea of the present invention is to still adopt the hardware structure of the schematic diagram of the background document 3, and the adjustment and control strategies are adjusted so that the turn-on and turn-off timings of the power tubes are completely different, and the forward working and the reverse working are all provided to the clamp tube. (third power tube, fourth power tube), so that the steady state characteristics of the circuit are completely different from those of the background document 3.
  • the driving signals of the first power tube and the second power tube are complementary driven, and when the energy is transferred from the first side to the second side (forward operation, the driving timing is shown in FIG. 4A), the second power tube and the The driving signal of the three power tubes is isolated and synchronized, then the first clamping capacitor is always resonating when the first power tube is turned off, causing unnecessary loss, and because the fourth power tube is in the off state, such that
  • the two power tubes act as rectifiers, and their turn-off voltages are not clamped and have high voltage spikes, and together with the turn-off current, have large turn-off losses.
  • the driving timing is shown in FIG. 4B
  • the driving signals of the first power tube and the fourth power tube are isolated and synchronized, then
  • the second clamp capacitor is always resonating when the second power tube is turned off, and also causes unnecessary resonance loss, and because the third power tube is in the off state, the first power tube acts as a rectifier tube, and the turn-off voltage is not It is clamped to have a high voltage spike and, together with the off current, has a large turn-off loss.
  • the present invention provides driving for the third power tube and the fourth power tube in one cycle, and the driving of the first power tube and the third power tube are no longer complementary, the second power tube and the fourth
  • the drive of the power tube is no longer complementary, but provides a fixed high level of high power to the third power tube after the first power tube is turned off, and a fixed short time after the second power tube is turned off.
  • the level is given to the fourth power tube to be turned on, so that the first clamp capacitor and the second clamp capacitor are discharged to the outside to achieve charge and discharge equalization; when the first clamp capacitor takes a large value, both ends thereof
  • the voltage change amount can be neglected, and the voltage across it is stable at the turn-on ratio multiplied by the voltage between the second side input positive and the negative input end.
  • the turn-off voltage of the first power transistor at the turn-off is clamped at about the first The voltage between the side input positive and the negative input plus the voltage across the first clamp capacitor; similarly, when the second clamp capacitor takes a large value, the voltage change across the two is negligible, and the voltage across the capacitor Stable on the first side of the input positive and negative input ends
  • the voltage is divided by the turn-to-turn ratio, and the turn-off voltage of the second power transistor at the turn-off is clamped to the voltage across the second clamp capacitor and the voltage input to the second side of the input and the negative input is implemented. While retaining the technical advantages of the background document 3, the shortage of the voltage spike and the large turn-off loss when the first power tube and the second power tube are turned off as the rectifier tube are also solved.
  • the third power tube can provide a high level at any time after the first power tube is turned off, and the best condition is to turn off simultaneously with the second power tube; the fourth power tube can be at any time after the second power tube is turned off.
  • the high level is provided, and the best case is to turn off simultaneously with the first power tube.
  • the invention must require that the first drive signal be flipped to a low level after the fourth drive signal is flipped low or simultaneously because the first drive signal is flipped low before the fourth drive signal is flipped low.
  • the best implementation method is that the first driving signal is turned over at the fourth driving signal.
  • the low level is flipped to a low level at the same time, so that the turn-off voltage of the first power tube and the second power tube is clamped, the turn-off loss is reduced, and because the inductor current cannot be abruptly changed, the fourth power tube is turned off.
  • the leakage inductance of the second winding, the second side winding, and the junction capacitance between the source and the drain of the second power tube form a loop, maintaining the continuity of the current, that is, extracting the second power
  • the energy of the junction capacitor causes the voltage between the source and the drain of the second power tube to drop, which reduces the turn-on loss of the tube to some extent, and even more easily realizes the ZVS of the second power tube under certain conditions; likewise,
  • the second driving signal must be required to be flipped to a low level after the third driving signal is turned to a low level or simultaneously, for the same reason, and the best implementation manner is that the second driving signal is flipped while the third driving signal is turned to a low level. Is low.
  • the first set time and the fourth set time, the second set time and the third set time, and the sixth set time and the eighth set time are alternatively selected to be the second or all equal, thus, The difficulty of control can be reduced to some extent due to the consistency of time settings.
  • FIGS. 2 and 3 Vo on the second side, FIGS. 2 and 3, and Vs in FIGS. 5, 7, and 9 are the same.
  • the first side or the second side of the present invention may be either a single side or a general side because the circuit is bilaterally symmetrical, but in the specific embodiment 1-5 of the present application, the first side is set.
  • the second side is set to the monomer side;
  • the monomer side of the background document 1 corresponds to the second side Vs of the specific embodiment 1-5 of the present invention, and the overall side corresponds to the first side Vp of the specific embodiment 1 of the present invention.
  • FIG. 5 is a circuit schematic diagram of a first embodiment of the present invention, which is consistent with FIG. 3, and includes a first side Vp, a second side Vs, a transformer B, a first power tube Q1, and a second power tube.
  • Q2 third power tube Q3, fourth power tube Q4, first clamp capacitor C1, second clamp capacitor C2, first filter capacitor Cp, second filter capacitor Cs, and the transformer includes at least a first winding Np and a second Winding Ns, the connection relationship is:
  • the input of the first power tube Q1 is extremely negative on the first side, and is represented by a - sign corresponding to the first side Vp; the drain of the first power tube Q1 is connected to the different end of the first winding Np of the transformer B and a source of the third power tube Q3; a drain of the third power tube Q3 is connected to one end of the first clamp capacitor C1, and the other end of the first clamp capacitor C1 is connected to the same end of the first winding Np of the transformer B and forms a first
  • the input of one side Vp is positive, and the figure is represented by the + sign corresponding to the first side Vp, and the voltage of the first side is Vp;
  • the input of the second power tube Q2 is extremely negative on the second side, and is represented by a - sign corresponding to the second side Vs; the drain of the second power tube Q2 is connected to the same end of the second winding Ns of the transformer B and the fourth The source of the power tube Q4; the drain of the fourth power tube Q4 is connected to one end of the second clamp capacitor C2, and the other end of the second clamp capacitor C2 is connected to the different end of the second winding Ns of the transformer B and form a first
  • the input of the two-side Vs is positive, and the figure is represented by the + sign corresponding to the second side Vs, and the second side voltage is Vs.
  • the power tube generally refers to a field effect transistor, that is, a MOS tube.
  • the first power tube Q1, the second power tube Q2, the third power tube Q3, and the fourth power tube Q4 are all N-channel enhancement type MOS tubes;
  • the body diodes are not reflected in the general power tube schematic.
  • Figure 6 shows The corresponding relationship between the field effect transistor of the body diode and the electrical symbol of the field effect tube of the general simple drawing; see FIG.
  • the body diode of the power tube Q4 is drawn, which is a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4, respectively.
  • the actual transformer will have leakage inductance.
  • the equivalent model of the transformer will be introduced for analysis.
  • the principle diagram is as follows. 7, the first leakage inductance Lr1, the second leakage inductance Lr2, and the magnetizing inductance Lm are defined.
  • the driving timing diagram of driving the four power tubes in the forward working mode in this embodiment is shown in FIG. 8.
  • the first driving signal Vgs1 is applied between the gate and the source of the power tube Q1, that is, the P1 end;
  • the driving signal Vgs2 is applied between the gate and the source of the power transistor Q2, that is, the P2 terminal;
  • the third driving signal Vgs3 is applied between the gate and the source of the power transistor Q3, that is, the P3 terminal;
  • the fourth driving signal Vgs4 is applied between the gate and the source of the power transistor Q4, that is, the P4 terminal; since the driving timing diagrams of the four power transistors in the reverse operation are symmetrical with the forward operation, no drawing is performed.
  • the driving signals Vgs1, Vgs2, Vgs3, and Vgs4 of this embodiment are required as follows:
  • the driving signals of the four-way driving power tube are driving signals of fixed frequency with the same frequency, and when the high level is high, the corresponding power tube is turned on, and when the level is low, the corresponding power tube is turned off;
  • the relationship between the driving signal Vgs1 and the driving signal Vgs2 is a complementary pulse signal with a fixed time dead time and adjustable duty ratio, that is, when the driving signal Vgs1 is at a high level, Vgs2 is a low level in one working period.
  • the driving signal Vgs1 When the driving signal Vgs1 is turned from a high level to a low level, the driving signal Vgs2 is flipped from a low level to a high level after a dead time (t2-t3); then the two signals are maintained for a period of time (t3-t5) When the driving signal Vgs2 is turned from a high level to a low level, the driving signal Vgs1 is flipped from a low level to a high level after a dead time (t5-t6); then the two are maintained for a while (t6-t8) When the drive signal Vgs1 is turned from high level to low level again, it enters the next duty cycle.
  • the driving signal Vgs3 has a high level pulse in one working cycle, and the rest is low level, and its high level time is fixed ⁇ t3; the driving signal Vgs3 is high after the driving signal Vgs2 is at a high level for some time.
  • the level, the driving signal Vgs2 has a period of time at the same time, and becomes a low level simultaneously with the driving signal Vgs2 to turn off the corresponding power tube;
  • the driving signal Vgs4 has a high level pulse in one working cycle, and the rest is low level, and its high level time is a fixed ⁇ t1; the driving signal Vgs4 is high after the driving signal Vgs1 is at a high level for a certain time.
  • the level which is at a high level for a while with the driving signal Vgs1, and becomes a low level simultaneously with the driving signal Vgs1 to turn off the corresponding power tube;
  • the present application defines energy transfer from the first side Vp to the second side Vs, and by increasing the high-level duty ratio of the driving signal Vgs1, that is, the duty ratio of the driving signal Vgs2 is synchronously reduced.
  • this paper defines energy transfer from the second side Vs to the first side Vp, by reducing the high-level duty cycle of the drive signal Vgs1, that is, increasing the duty cycle of the drive signal Vgs2. Controlling a power level converted from the second side Vs to the first side Vp;
  • the MOS transistors Q2, Q3, and Q4 are all in the off state due to the respective driving low levels, the driving signal Vgs1 is at the high level, the MOS transistor Q1 is turned on, and the polarity of the first winding Np is up. Lower, the excitation inductance Lm of the first winding Np is positively excited and stored, and the current of the excitation inductor Lm rises linearly, while the polarity of the second winding Ns is positive and negative, and the body diode D2 of the MOS transistor Q2 is reversed.
  • the voltage of the second winding Ns plus the voltage of the second winding Ns leakage inductance Lr2 is charged by the body diode D4 of the MOS transistor Q4 for the capacitor C2, the voltage on the capacitor C2 is up and down, and the second winding leakage inductance Lr2 The energy is transferred to capacitor C2 to charge capacitor C2, so the voltage between the drain-source of MOS transistor Q2 is clamped at approximately Vp/N+Vs;
  • the MOS transistors Q2 and Q3 are in the off state due to the respective driving signals being low level, the driving signal Vgs1 is at the high level, the MOS transistor Q1 is still turned on, the excitation and energy storage are continued, and the driving signal Vgs4 is simultaneously driven.
  • the MOS transistor Q4 is turned on, which is equivalent to a straight line.
  • the voltage on the capacitor C2 is higher than the voltage refracted by the first winding Np to the second winding Ns, and the energy is released.
  • the MOS transistors Q1 and Q4 are simultaneously in the t2 stage. cutoff;
  • the MOS transistors Q2 and Q3 are still in the off state because the corresponding driving signals are low level, and the driving signals of the MOS transistors Q1 and Q4 are turned to the low level at the time t2, and the exciting inductance Lm is turned off.
  • the excitation current on the excitation current and the leakage inductance Lr1 are first charged to the junction capacitance of the MOS transistor Q1, and after about Vp+NVs, the first leakage inductance Lr1 energy flows into the clamp capacitor through the body diode D3 of the MOS transistor Q3.
  • the leakage inductance Lr1 energy of the first winding Np is absorbed by the capacitor C1, and the drain-source voltage of the MOS transistor Q1 is clamped at about Vp+NVs; meanwhile, the leakage inductance Lr2 of the second winding Ns is due to the inductance. The current cannot be abruptly changed.
  • the MOS transistor Q4 is turned off, the leakage inductance Lr2 of the second winding Ns, the second winding Ns, and the junction capacitance between the source and the drain of the MOS transistor Q2 form a loop, and the current is continuously maintained, that is, the MOS transistor is extracted.
  • the energy of the Q2 junction capacitor causes the voltage between the source and the drain of the MOS transistor Q2 to drop, which reduces the turn-on loss of the tube to some extent, and even realizes the ZVS of the MOS transistor Q2 under certain conditions, and at the same time, the transformer polarity On the contrary, the polarity of the second winding Ns of the transformer becomes upper and lower negative, and the magnetizing inductance Lm is at t1-t2. Segment stored energy is released through the coupled output is rectified by the body diode of the MOS transistor Q2 to the terminal Vs, Vs to provide power to the load side.
  • the MOS transistors Q1, Q3, and Q4 are still in the off state because the corresponding driving signals are all at the low level, and the MOS transistor Q2 is turned on due to the driving signal Vgs2 being at the high level, and the conduction voltage drop is turned on. Approximately zero provides a lower loss rectification path that provides synchronous rectification for the converter operating in the forward direction.
  • the MOS transistors Q1 and Q4 are still in the off state because the corresponding driving signals are all at the low level, and the MOS transistor Q2 is still turned on because its driving signal Vgs2 is still at the high level, at time t4
  • the drive signal Vgs3 changes from a low level to a high level
  • the MOS transistor Q3 starts to conduct
  • the capacitor C2 discharges (t2-t3 phase leakage inductance Lr2 energy is transferred to C2, t4-t5 phase is released), to t5 time
  • the MOS tubes Q3 and Q2 are simultaneously turned off.
  • the MOS transistors Q1 and Q4 are still in the off state due to the corresponding driving signals being low level, and the MOS transistors Q2 and Q3 are turned off due to the corresponding driving signals being turned to the low level at the time t5.
  • the body diode of the MOS transistor Q2 provides a rectification path, and continues to provide rectification for the converter.
  • the MOS transistor Q3 is turned off, because the inductor current cannot be abruptly changed, and the leakage inductance Lr1 of the first winding Np is turned off after the MOS transistor Q3 is turned off.
  • the first winding Np inductor and the junction capacitance between the source and the drain of the MOS transistor Q1 form a loop, maintaining the continuity of the current, that is, extracting the energy of the junction capacitance of the MOS transistor Q1, so that the source and the drain of the MOS transistor Q1 are
  • the voltage drop reduces the turn-on loss of the tube to a certain extent, and even realizes the ZVS of the MOS transistor Q1 under certain conditions.
  • [t6-t7] stage enter the work of the next cycle, that is, the above t0-t1 phase, and then (ie t7-t8, t8-t9, t9-t10, t10-t11, t11-t12) work principle and front The same, no longer repeat them here;
  • t2-t3 is the first set time
  • t5-t6 is the second set time
  • t5-t6 is the third set time
  • t2-t3 is the fourth set time
  • t3-t4 is the fifth setting Time
  • t4-t5 is the sixth set time
  • t0-t1 is the seventh set time
  • t1-t2 is the eighth set time.
  • the sixth set time and the eighth set time length are generally greater than 50 ns, but less than the minimum on time of the MOS transistor Q1 or the MOS transistor Q2, because the MOS transistor Q1 and the MOS transistor Q3 or the MOS transistor Q2 and the MOS transistor Q4 are simultaneously prevented. Turning on, causing the clamp capacitor to over discharge, releasing more power through the transformer to the other side and returning the network, the energy is transferred back and forth between the primary and secondary sides of the transformer, which will cause unnecessary power loss.
  • the first set time and the fourth set time, and the second set time and the third set time are equal.
  • both sides of the circuit and control have a high degree of symmetry, although the operating voltage on both sides may be different, such as the first side Vp connected to the entire battery pack, the second side Vs connected to a single battery pack Body, but because MOS transistors Q1 and Q2 use complementary control, the current direction between the source and the drain of the turned-on MOS transistor can vary depending on the source-drain voltage, so Adjusting the duty ratio of the MOS transistor Q1 can control the output current in the forward operation, and can also realize the reverse operation of the energy transfer from the second side Vs to the first side Vp by adjusting the duty ratio of the MOS transistor Q1.
  • the reverse working principle is the same as the forward working principle, and the reverse working principle is not described again.
  • adjusting the duty ratio of the driving signal of the MOS transistor Q1 or Q2 that is, adjusting the duty ratio of Vgs1 or Vgs2
  • energy bidirectional can be realized.
  • the MOS transistors Q3 and Q4 are simultaneously driven to provide signals, so that the clamp capacitors C1 and C2 absorb the leakage inductance energy, so that the leakage inductance energy is recovered and utilized by charging and discharging the capacitors C1 and C2, and at the same time, the MOS transistor Q1 is realized. And Q2's ZVS.
  • the above embodiment achieves bidirectional transmission of energy, leakage inductance recovery, and ZVS of part of the power tube.
  • the rectifier tube ie MOS tube Q1 or Q2
  • the specific analysis is as follows:
  • the present invention provides driving for the third power tube and the fourth power tube in one cycle, and the driving of the first power tube and the third power tube are no longer complementary, the second power tube and the fourth power
  • the drive of the tube is no longer complementary, but by providing a fixed low-time high level to the third power tube after the first power tube is turned off, and providing a fixed short-time high power after the second power tube is turned off.
  • the fourth power tube is turned on and turned on respectively, so that the first clamp capacitor and the second clamp capacitor are discharged to the outside to achieve charge and discharge equalization.
  • the first clamp capacitor has a large value, both ends thereof are The voltage change is small and negligible.
  • the voltage at both ends is stable at the turn-on ratio multiplied by the voltage between the positive input and the negative input of the second input.
  • the turn-off voltage of the first power transistor at the turn-off is clamped on the first side. Input the voltage between the positive and negative terminals and the voltage across the first clamp capacitor; when the value of the second clamp capacitor is large, the voltage change between the two ends can be neglected, and the voltage at both ends is stable at the first
  • the voltage between the side input positive and the negative input is divided by Near the turns ratio, the turn-off voltage of the second power transistor at the turn-off is clamped at the voltage across the second clamp capacitor plus the voltage at the second side of the input positive and negative input, thereby achieving the preservation of the background literature.
  • 3 technical advantages also solve the problem that the first power tube and the second power tube are large as the voltage peak and the turn-off loss are large when the rectifier tube is turned off.
  • the power circuit used in the experiment is shown in Figure 5. It is applied between the battery pack and the battery cell, and equalizes the voltage of one cell in the battery pack and the voltage of other cells in the group:
  • the Vs working voltage is 3.3V, which is the voltage of one battery cell.
  • the power tubes Q2 and Q4 are two CMOS tubes of Infineon model BSC034N06NS used in parallel, which is a 60V 100A MOS tube with RDS(ON) of 3.4. M ⁇ , package is PG-TDSON-8, capacitor C2 is 1uF;
  • Vp working voltage is 24V, which is the voltage of one battery pack. It is obtained by connecting ten battery cells in series.
  • Power tube Q1 and Q3 are both MOS tubes of Infineon model BSC123N08NS3 G, which is 80V 55A, and its RDS (ON) ) is 12.3m ⁇ , packaged as MOS tube of PG-TSDSON-8, capacitor C1 is 1uF;
  • the core is the universal core of EIR18, the core material is P61 material of Yuefeng Company (ACME); the winding is a plane winding based on 12-layer PCB, the copper thickness is 3 ounces, and the first winding Np is 12 ⁇ ; the second winding Ns is 2 ⁇ ; the design power is 40W;
  • the technical scheme of PWM control uses the microcontroller to generate the control signal.
  • the control signal is formed by SILICON LABORATORIES and is modeled after the Si8235 driver to form Vgs1, Vgs2, Vgs3, and Vgs4.
  • the same sample is modified, the power circuit remains unchanged, the same transformer and power transistors Q1, Q2, Q3 and Q4 are retained, and the same capacitors C1, C2 are used only for the control signal.
  • Change that is, the drive signals Vgs1 and Vgs2 are complementary, the drive signal Vgs4 is removed in the forward operation, and the drive signals Vgs1 and Vgs3 are complementary; when the reverse operation is performed, the drive signal Vgs3 is removed or set to 0, and the drive signals Vgs2 and Vgs4 are complementary;
  • the conversion efficiency from the first side Vp to the second side Vs is 91.12%, which is 1.64% lower than that of the present invention.
  • the drain-source voltage Vds1 ⁇ 50V of the MOS transistor Q1 is measured at a bandwidth of 20 MHz, and the maximum drain-source voltage Vds2 of the MOS transistor Q2 is 15 V, which is increased by more than 7 V compared with the present invention (Vds2 peak voltage is compared Big);
  • the conversion efficiency from the second side Vs to the first side Vp 90.86%; compared to the present invention, a decrease of 3%.
  • the maximum drain-source voltage Vds1 of the MOS transistor Q1 is 82V measured at a bandwidth of 20MHz, and the maximum drain-source voltage Vds2 of the MOS transistor Q2 is 8V.
  • the Vds of the MOS transistor Q1 is increased by 30V. (Vds1 has a large peak voltage);
  • the solution of the present invention realizes the power by storing and releasing the energy of the equivalent leakage inductance of the first winding and the capacitor C1, and storing and releasing the energy of the equivalent leakage inductance of the second winding and the capacitor C2.
  • the voltage clamping of the tubes Q1 and Q2 achieves a smaller turn-off loss and spike voltage than the prior art; by limiting the on-time of the clamp tubes Q3 and Q4, the loss of the clamp capacitors C1 and C2 and the transformer resonance is reduced.
  • the invention achieves the purpose of the invention by implementing the isolated bidirectional transformation with higher efficiency.
  • a first diode is connected in parallel between the source and the drain of Q1, the anode of the first diode is connected to the source of the MOS transistor Q1, and the cathode of the first diode is connected.
  • the first diode may be a Schottky diode. When the first diode is forward-conducting, the first diode conduction loss is smaller than the body diode conduction loss of the MOS transistor Q1, which can further improve the conversion efficiency.
  • a second diode is connected in parallel between the source and the drain of the MOS transistor Q2, the anode of the D2 is connected to the source of the MOS transistor Q2, and the cathode of the second diode is connected to the MOS.
  • the second diode may be a Schottky diode. When the second diode is forward-conducting, the second diode conduction loss is smaller than the body diode conduction loss of the MOS transistor Q2, which can further improve the conversion efficiency.
  • a third diode is connected in parallel between the source and the drain of the MOS transistor Q3, and the anode of the third diode is connected to the source of the MOS transistor Q3, and the third diode
  • the cathode is connected to the drain of the MOS transistor Q3; the fourth diode is connected in parallel between the source and the drain of the MOS transistor Q4, and the anode of the fourth diode is connected to the source of the MOS transistor Q4, and the fourth diode
  • the cathode is connected to the drain of the MOS transistor Q4.
  • the third diode and the fourth diode may be Schottky diodes, and when the third diode or the fourth diode is forward-conducting, its conduction loss is turned on than the body diode of the power tube connected in parallel thereto The loss is smaller and the conversion efficiency can be further improved.
  • a schematic diagram of a circuit according to a fifth embodiment of the present invention is different from the first embodiment in that the other end of the first clamp capacitor C1 is connected to the input of the first side Vp, and the second clamp capacitor is connected.
  • the other end of C2 is connected to the input of the second side Vs negatively; the control strategy and working principle of each power tube are the same, and will not be described here.
  • the above is only a preferred embodiment of the present invention, and it should be noted that the above preferred embodiments are not to be construed as limiting the invention.

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Abstract

一种DC‑DC变换器，包括第一侧、第二侧、变压器B，功率管Q1、Q2、Q3、Q4，电容C1、C2，变压器B至少包括第一绕组Np与第二绕组Ns；第一侧连接关系为Q1与Np串联，Q3与C1串联后与Np并联；第二侧与第一侧对称，Vgs1、Vgs2、Vgs3、Vgs4为依次施加在Q1、Q2、Q3及Q4的栅极和源极之间的驱动信号；功率管Q1至Q4采用的驱动时序克服了Q1和Q2的电压因漏感与其结电容进行谐振而存在较高关断电压尖峰的问题；并通过限制Q3和Q4的导通时间，降低了Q1和Q2关断时C1和C2谐振产生的损耗；具有电路简单，转换功率高的特点。

Description

一种DC-DC变换器 技术领域
本发明涉及DC-DC变换器，特别涉及能量双向流动的DC-DC变换器。
现有技术
DC-DC变换器是现代高频开关电源的基本组成部分，顾名思义，它把直流(DC)输入电压Vin变换成更满足要求的或者更有效的直流(DC)输出电压Vo。
一般情况下，单向DC-DC变换器是指将在输入端供给的直流电压转换成具有较高、较低或反向电压电平的直流电压的DC-DC变换器。
和单向DC-DC变换器相比，双向DC-DC变换器通过双向DC-DC变换器的正向或者反向工作，可实现能量的双向传输，即允许电能从定义的输入端流到输出端，反之亦然，在功能上相当于两个单向直流变换器，是典型的“一机两用”设备，在不间断电源、蓄电池充放电、电动汽车、大功率设备的能量回收系统、大功率设备的备用电源等场合中有着非常广泛的应用。
反激变换器具有器件少，可靠性高的特点，广泛应用于功率为50W以下的中小功率的DC-DC变换器中。
现有申请号为201410724447.3，名为《双向无损主动均衡装置》的发明专利申请，以下称为背景文献1，示出了利用反激变换器组成的双向变换器，为了方便，本申请把背景文献1的图1呈现在本申请中，参见本申请的图1。可以看到，其单体侧设立了由二极管D1、电阻R1、电容C2组成的RCD吸收电路，其总体侧设立了由二极管D4、电阻R3、电容C4组成的RCD吸收电路。RCD吸收电路的工作原理为公知技术，可参考中国电力出版社出版的《开关电源功率变换器拓扑与设计》第67页“4.3RCD吸收反激变换器”一节，该文献作者为张兴柱、国际标准书号为ISBN 978-7-5083-9015-4，该文献的不足之处：RCD吸收电路原来只是工作在反激变换器的功率管由饱和导通变为截止的瞬间，而在背景文献1中，在原边激磁时，副边的RCD吸收电路全程参与了工作，消耗的能量比较大，无法实现背景文献1所述的“无损”吸收。
申请号为201610251403.2，名为《一种双向变换器》的发明专利申请，以下称为背景文献2，克服了背景文献1的不足，为了方便，本申请把背景文献2的技术方案对应的图4呈现在本申请中，参见本申请的图2，该文献的优势在于在原边激磁时，副边的RCD吸收电路不参与工作，在副边激磁时，原边的RCD吸收电路不参与工作；消耗的能量非常小，实 现了“无损”吸收；然而，其仍然存在不足之处，分析如下。
背景文献2漏感能量还是通过消耗的方式来吸收掉，且第二绕组Ns感应电压等于：(Ns/Np)Vs，即匝比乘上第一侧的工作电压，第一侧的工作电压的变化范围较大，如用于锂电的均衡充电中，Vs的工作电压范围为3.0V至4.20V，变化达40％，若匝比为10，那么背景文献2中，为了正常工作，稳压二极管W2的稳压值大于第二绕组Ns感应电压的最大值4.2V*10＝42V，才能保证良好工作，当第二侧Vo需要工作时，MOS管Q2处于PWM的开关状态，这时二极管D4、电容C2、电阻R2，以及稳压二极管W2组成的RCD吸收电路，其吸收电压过高，MOS管Q2的漏极在同样的时间，要从更高的电压降为0V，即dU/dt更大了，电磁辐射也会更大，即背景文献2存在的不足为：MOS管Q2的耐压要高，高耐压的MOS管做成同样的通态内阻，其成本大幅升高；EMI较差；特别在输入电压工作范围较宽时，缺点更明显。同样MOS管Q1也存在这个问题。
因此，现有利用反激变换器组成的双向变换器，即反激式双向变换器，包括背景文献2，目前仍不够理想。
背景文献3：申请号为201710654256.8，名为《一种DC-DC双向变换器》的发明专利申请，提出了一种基于有源钳位反激的双向DC-DC变换器及其控制方案，其双向DC-DC变换器的原理图如图3所示，依据背景文献3的内容绘制的正向工作和反向工作时各功率管的驱动时序图如图4A和图4B所示，Vgs1、Vgs2、Vgs3和Vgs4为依次施加对应功率管Q1、Q2、Q3和Q4控制端的驱动电平，背景文献3正向工作时，第一开关管Q1是主功率管，第二开关管Q2是整流管，第三开关管Q3是钳位管，第四功率管Q4不工作；背景文献3反向工作时，第一开关管Q1是整流管,第二开关管Q2是主功率管，第三功率管Q3不工作，第四功率管Q4是钳位管。
背景文献3确实可以实现把变压器(B)漏感的部分能量回收利用，一定参数条件下，可通过钳位电容C1/C2和漏感的谐振，实现主功率管Q1/Q2和钳位管Q3/Q4的零电压开通(也可以简称之为ZVS)，但是，正向工作时，主功率管与钳位管的驱动为互补驱动，即Q1与Q3的驱动互补，钳位电容C1在钳位管开通的整个过程均参与谐振，将带来一些不必要的谐振损耗，随钳位电容C1的电压越高，对应的谐振能量越大，即谐振损耗越大；另外，正向工作只有功率管Q1被钳位，整流管(即功率管Q2)没有被钳位，输出侧的功率管Q2在关断时刻，功率管的结电容和漏感进行谐振，存在漏感尖峰电压，变压器B的漏感越大，其电压尖峰越大，为了使该功率管安全可靠工作，需要选取更高电压规格的功率管，从而 带来一些成本上的不利，且该功率管的电压规格越高，其导通压降会越大，若采用MOS管的话，一般情况下，电压规格越大的MOS管，其导通电阻越大，因此，同等电流规格下，损耗将更大；再者，在变换器工作于连续模式(即CCM模式)下，其整流管，即功率管Q2的关断损耗将更大，从而导致一些不可接受的转换效率下降、产品温升升高；反向工作时问题亦是如此，因此该方案仍然不够理想。
发明内容
有鉴于此，本发明要解决现有反激式双向变换器所存在的不足，提供一种新的变换器，使得第一侧和第二侧功率管的漏感尖峰电压都被钳位，降低关断时的电压尖峰和减小关断损耗，使其能更高效率地实现能量的双向变换。
本发明的目的是这样实现的，一种DC-DC变换器，包括第一侧、第二侧、一个变压器、第一功率管、第二功率管、第三功率管、第四功率管、第一钳位电容，以及第二钳位电容，变压器至少包括第一绕组与第二绕组，连接关系为：
第一功率管的导通电流流出端作为第一侧的输入负；第一功率管的导通电流流入端连接变压器的第一绕组的异名端以及第三功率管的导通电流流出端；第三功率管的导通电流流入端连接第一钳位电容的一端，第一钳位电容的另一端与变压器的第一绕组的同名端相连并形成第一侧的输入正；
第二功率管的导通电流流出端形成第二侧的输入负；第二功率管的导通电流流入端连接变压器的第二绕组的同名端以及第四功率管的导通电流流出端；第四功率管的导通电流流入端连接第二钳位电容的一端，第二钳位电容的另一端与变压器的第二绕组的异名端相连并形成第二侧的输入正；
第一功率管的控制端用于输入第一驱动信号，第二功率管的控制端用于输入第二驱动信号，第三功率管的控制端用于输入第三驱动信号，第四功率管的控制端用于输入第四驱动信号，第一驱动信号至第四驱动信号要求为：
四路驱动信号均为由高电平和低电平组成的脉冲信号，频率相同；
正向工作时，第一驱动信号在由高电平翻转为低电平时第二驱动信号延迟第一设定时间后才由低电平翻转为高电平，第二驱动信号在由高电平翻转为低电平时第一驱动信号延时第二设定时间后才由低电平翻转为高电平；反向工作时，第二驱动信号在由高电平翻转为低电平时第一驱动信号延迟第三设定时间后才由低电平翻转为高电平，第一驱动信号在由高电平翻转为低电平时第二驱动信号延时第四设定时间后才由低电平翻转为高电平；
第三驱动信号在第二驱动信号翻转为高电平时延时第五设定时间后才翻转为高电平，并经过第六设定时间后第三驱动信号翻转为低电平，然后第二驱动信号在第三驱动信号翻转为低电平之后或同时翻转为低电平；
第四驱动信号在第一驱动信号翻转为高电平时延时第七设定时间后才翻转为高电平，并经过第八设定时间后第四驱动信号翻转为低电平，然后第一驱动信号在第四驱动信号翻转为低电平之后或同时翻转为低电平。
作为上述技术方案的等同替换，将第一钳位电容的另一端与第一侧的输入负相连，第二钳位电容的另一端与第二侧的输入负相连。优选的，第一功率管、第二功率管、第三功率管，以及第四功率管均为N沟道增强型MOS管，且均为高电平时导通，低电平时关断。
优选地，第六设定时间和第八设定时间为一个固定时间的窄脉冲，其时间长度大于50ns，小于MOS管Q1或者MOS管Q2的最小导通时间。
作为上述技术方案的改进，第一设定时间与第四设定时间、第二设定时间与第三设定时间，以及第六设定时间与第八设定时间择一或者择二或者全部相等。
作为上述技术方案的改进，还包括第一二极管，第一二极管的阳极与第一功率管的源极连接，第一二极管的阴极与第一功率管的漏极连接。
作为上述技术方案的改进，还包括第二二极管，第二二极管的阳极与第二功率管的源极连接，第二二极管的阴极与第二功率管的漏极连接。
作为上述技术方案的改进，还包括第三二极管，第三二极管的阳极与第三功率管的源极连接，第三二极管的阴极与第三功率管的漏极连接。
作为上述技术方案的改进，还包括第四二极管，第四二极管的阳极与第四功率管的源极连接，第四二极管的阴极与第四功率管的漏极连接。
术语解释：
功率管的控制端：控制开关导通与截止的端口，如对于MOS管，指的是MOS管的栅极；对于三极管，指的是三极管的基极。
功率管的导通电流流入端：功率管导通后，电流流入的端口，如对于MOS管，指的是MOS管的漏极，无论N沟道、P沟道、增强型还是耗尽型MOS管，在导通时，电流都是由电压高的漏极流向电压低的源极；对于三极管，指的是三极管的集电极，在导通时，电流是由电压高的集电极流向电压低的发射极。
功率管的导通电流流出端：功率管导通后，电流流出的端口，如对于MOS管，指的是 MOS管的源极；对于三极管，指的是三极管的发射极。
详细的工作原理将结合实施案例深入描述。
与现有技术相比较，本发明的一种双向变换器的有益效果为：
(1)转换效率更高，元器件温升更小；
(2)功率管的电压应力更小，可以选取更小电压规格的功率管，成本有优势；
(3)第一和第二功率管关断瞬间的电压尖峰被钳位电容吸收，高频噪声和EMI更好；
(4)输入电压工作范围较宽时，仍保持上述三个有益效果；
(5)变压器漏感较大时，依然能保持上述四个有益效果。
附图说明
图1为背景文献1中双向无损主动均衡装置；
图2为背景文献2中一种双向变换器的原理图；
图3为背景文献3中一种双向变换器的原理图；
图4A为背景文献3正向工作时各功率管的驱动时序图；
图4B为背景文献3反向工作时各功率管的驱动时序图；
图5为本发明第一实施例电路原理图；
图6为功率管内部的体二极管示意图；
图7为图3变压器等效后的电路原理图；
图8为本发明第一实施例各功率管的驱动时序图；
图9为第五实施例电路原理图。
具体实施方式
本发明的技术构思为依然采用背景文献3原理图的硬件结构，通过控制策略的调整，使得各功率管的导通和关闭时序完全不同，正向工作和反向工作均提供驱动给钳位管(第三功率管、第四功率管)，从而使得电路的稳态特性与背景文献3完全不同。
背景文献3第一功率管和第二功率管的驱动信号是互补驱动的，当能量从第一侧向第二侧转移时(正向工作，驱动时序见图4A)，第二功率管和第三功率管的驱动信号是隔离且同步的，那么第一钳位电容在第一功率管关断时一直在谐振，带来不必要的损耗，又因为第四功率管处于关断状态，这样第二功率管作为整流管，其关断电压没有被钳位而具有较高的电压尖峰，与关断电流一起，具有较大的关断损耗。
同样地，背景文献3当能量从第二侧向第一侧转移时(反向工作，驱动时序见图4B)， 第一功率管和第四功率管的驱动信号是隔离且同步的，那么第二钳位电容在第二功率管关断时一直在谐振，也带来不必要的谐振损耗，又因为第三功率管处于关断状态，这样第一功率管作为整流管，其关断电压没有被钳位而具有较高的电压尖峰，与关断电流一起，具有较大的关断损耗。
本发明在背景文献3的基础上，一个周期内分别给第三功率管和第四功率管提供驱动，且第一功率管和第三功率管的驱动不再互补，第二功率管和第四功率管的驱动不再互补，而是通过在第一功率管关断后提供一个固定短时间的高电平给第三功率管，又在第二功率管关断后提供一个固定短时间的高电平给第四功率管，分别使其导通，从而使第一钳位电容和第二钳位电容对外放电，达到充放电均衡；当第一钳位电容取值较大时，其两端电压变化量较小可以忽略，其两端电压稳定在匝比乘以第二侧输入正与输入负两端的电压附近，第一功率管在关断时的关断电压被钳位在约第一侧输入正与输入负两端的电压加上第一钳位电容两端的电压；同样地，当第二钳位电容取值较大时，其两端电压变化量较小可以忽略，其两端电压稳定在第一侧输入正与输入负两端的电压除以匝比附近，第二功率管在关断时的关断电压被钳位在约第二钳位电容两端电压再加第二侧输入正与输入负两端的电压，从而实现了在保留背景文献3技术优势的同时还解决了其第一功率管和第二功率管作为整流管关断时电压尖峰大和关断损耗大的不足。
第三功率管可以在第一功率管关断后的任意时刻提供高电平，最佳情况是与第二功率管同时关断；第四功率管可以在第二功率管关断后的任意时刻提供高电平，最佳情况是与第一功率管同时关断。
本发明必须要求第一驱动信号在第四驱动信号翻转为低电平之后或同时翻转为低电平，原因在于，如果第一驱动信号在第四驱动信号翻转为低电平之前就翻转为低电平，则在第一功率管关断后变压器绕组同名端翻转，即绕组两端电压极性翻转，第二谐振电容两端电压不能突变，会释放过多的能量通过变压器传递回原边，之后再传回来，而变压器传递能量是有损耗的，能量在变压器原边和副边之间来回传递将造成不必要的功率损失，最佳实施方式是第一驱动信号在第四驱动信号翻转为低电平的同时翻转为低电平，如此实现了第一功率管和第二功率管的关断电压被钳位，降低了关断损耗，且又因为电感电流不能突变，第四功率管关断后，第二绕组的漏感、第二侧绕组以及第二功率管源极和漏极之间的结电容形成回路，维持电流的连续，即抽取第二功率管结电容的能量，使得第二功率管的源极和漏极之间的电压下降，一定程度上降低该管子的开通损耗，甚至一定条件下更容 易实现第二功率管的ZVS；同样地，还必须要求第二驱动信号在第三驱动信号翻转为低电平之后或同时翻转为低电平，原因相同，最佳实施方式是第二驱动信号在第三驱动信号翻转为低电平的同时翻转为低电平。
本发明如果第一设定时间与第四设定时间、第二设定时间与第三设定时间，以及第六设定时间与第八设定时间择一获得择二或者全部相等，如此，可以在一定程度上因时间设定上的一致而降低控制的难度。
由于本发明引用的背景文献以及本申请对相关技术术语的标号有所不同，对此特作以下说明：
(1)第一侧、图2和图3中的Vs，以及图5、图7和图9中的Vp所指对象相同；
(2)第二侧、图2和图3中的Vo，以及图5、图7和图9中的Vs所指对象相同。
(3)本发明的第一侧或者第二侧由于电路是左右对称的，既可以为单体侧，也可以为总体侧，但在本申请的具体实施例1-5，第一侧设定为总体侧，第二侧设定为单体侧；
(4)背景文件1的单体侧，相当于本发明的具体实施例1-5的第二侧Vs，总体侧相当于本发明的具体实施例1的第一侧Vp。
第一实施例
请参见图5，为本发明的第一实施例的电路原理图，与图3是一致的，包括第一侧Vp、第二侧Vs，一个变压器B，第一功率管Q1、第二功率管Q2、第三功率管Q3、第四功率管Q4，第一钳位电容C1、第二钳位电容C2，第一滤波电容Cp、第二滤波电容Cs，变压器至少包括第一绕组Np与第二绕组Ns，连接关系为：
第一功率管Q1的源极为第一侧的输入负，图中以第一侧Vp对应的-号表示；第一功率管Q1的漏极连接变压器B的第一绕组Np的异名端以及第三功率管Q3的源极；第三功率管Q3的漏极连接第一钳位电容C1的一端，第一钳位电容C1的另一端与变压器B的第一绕组Np的同名端相连并形成第一侧Vp的输入正，图中以第一侧Vp对应的+号表示，记第一侧电压为Vp；
第二功率管Q2的源极为第二侧的输入负，图中以第二侧Vs对应的-号表示；第二功率管Q2的漏极连接变压器B的第二绕组Ns的同名端以及第四功率管Q4的源极；第四功率管Q4的漏极连接第二钳位电容C2的一端，第二钳位电容C2的另一端与变压器B的第二绕组Ns的异名端相连并形成第二侧Vs的输入正，图中以第二侧Vs对应的+号表示，记第二侧电压为Vs。
功率管一般指场效应管，即MOS管，本实施例第一功率管Q1，第二功率管Q2，第三功率管Q3，第四功率管Q4均为N沟道增强型MOS管；由于其体内一般都有寄生二极管，又叫体二极管，体二极管在一般的功率管原理图中不体现，为了方便描述工作原理，提供了功率管内部结构图，见图6，图6示出了带有体二极管的场效应管与一般简易画法的场效应管电气符号的对应关系；参见图5，本图中将第一功率管Q1、第二功率管Q2、第三功率管Q3，以及第四功率管Q4的体二极管进行了绘制，分别为第一二极管D1、第二二极管D2、第三二极管D3，以及第四二极管D4。
实际的变压器都会存在漏感，当原边和副边的漏感均不可忽视时，为了方便描述工作原理，将引入变压器的等效模型进行分析，变压器换成等效模型后，其原理图如图7所示，包括第一漏感Lr1、第二漏感Lr2以及励磁电感Lm，定义匝比为N，第一绕组Np的匝数为Np，第二绕组Ns的匝数为Ns，那么N＝Np/Ns；
本实施案例正向工作时分别驱动四个功率管的驱动时序图请详见图8，包括第一驱动信号Vgs1，施加在功率管Q1的栅极与源极之间，即P1端；第二驱动信号Vgs2，施加在功率管Q2的栅极与源极之间，即P2端；第三驱动信号Vgs3，施加在功率管Q3的栅极与源极之间，即P3端；第四驱动信号Vgs4，施加在功率管Q4的栅极与源极之间，即P4端；由于反向工作时四个功率管的驱动时序图与正向工作时对称，因此未进行绘制。
本实施例的驱动信号Vgs1、Vgs2、Vgs3、Vgs4要求如下：
四路驱动功率管的驱动信号均为频率相同的固定频率的驱动信号，且均为高电平时使对应的功率管导通，低电平时使对应的功率管关断；
驱动信号Vgs1与驱动信号Vgs2的关系为有一个固定时间的死区时间、占空比可调节的互补的脉冲信号，即在一个工作周期内，驱动信号Vgs1为高电平时，Vgs2为低电平，当驱动信号Vgs1由高电平翻转为低电平时，驱动信号Vgs2经过一死区时间(t2-t3)后由低电平翻转为高电平；接着两个信号维持一段时间(t3-t5)，当驱动信号Vgs2由高电平翻转为低电平时，驱动信号Vgs1经一死区时间(t5-t6)后由低电平翻转为高电平；接着两者再维持一段时间(t6-t8)；当驱动信号Vgs1再次由高电平翻转为低电平时，即进入下一个工作周期。
驱动信号Vgs3在一个工作周期内，有一个高电平脉冲，其余为低电平，其高电平时间是固定的△t3；驱动信号Vgs3在驱动信号Vgs2处于高电平若干时间后才为高电平，与驱动信号Vgs2存在一段同时处于高电平的时间，并与驱动信号Vgs2同时变成低电平使对应 的功率管关断；
驱动信号Vgs4在一个工作周期内，有一个高电平脉冲，其余为低电平，其高电平时间是固定的△t1；驱动信号Vgs4在驱动信号Vgs1处于高电平若干时间后才为高电平，与驱动信号Vgs1存在一段同时处于高电平的时间，并与驱动信号Vgs1同时变成低电平使对应的功率管关断；
正向工作时，本申请定义为能量从第一侧Vp传递到第二侧Vs，通过增大驱动信号Vgs1的高电平占空比，即同步减小了驱动信号Vgs2的占空比，来实现控制从第一侧Vp转换到第二侧Vs的功率大小；
反向工作时，本文定义为能量从第二侧Vs传递到第一侧Vp，通过减小驱动信号Vgs1的高电平占空比，即同步增大了驱动信号Vgs2的占空比，来实现控制从第二侧Vs转换到第一侧Vp的功率大小；
工作原理介绍：
以稳态的正向工作的一个周期(t0-t6)为例，结合图7和图8进行本实施案例的原理介绍：
[t0-t1]阶段，MOS管Q2、Q3和Q4因各自的驱动为低电平均处于截止状态，驱动信号Vgs1为高电平，MOS管Q1导通，第一绕组Np的极性为上正下负，第一绕组Np的励磁电感Lm正向激磁和储能，通过励磁电感Lm电流线性上升，同时第二绕组Ns的极性为上负下正，MOS管Q2的体二极管D2反偏不导通，第二绕组Ns的电压加上第二绕组Ns漏感Lr2的电压通过MOS管Q4的体二极管D4为电容C2充电，电容C2上的电压为上负下正，第二绕组漏感Lr2的能量被转移到电容C2上，为电容C2充电，因此MOS管Q2的漏极-源极之间的电压被钳位在约为Vp/N+Vs处；
[t1-t2]阶段，MOS管Q2和Q3因各自的驱动信号为低电平均处于截止状态，驱动信号Vgs1为高电平，MOS管Q1依然导通，继续激磁和储能，同时驱动信号Vgs4为高电平，MOS管Q4导通，相当于一条直线，电容C2上的电压高于第一绕组Np折射到第二绕组Ns上的电压，能量释放出来，至t2阶段MOS管Q1和Q4同时截止；
[t2-t3]阶段，MOS管Q2和Q3因对应的驱动信号均为低电平而依旧处于截止状态，在t2时刻开始MOS管Q1和Q4驱动信号转为低电平而截止，励磁电感Lm上的励磁电流和漏感Lr1上的漏感电流依次先为MOS管Q1的结电容充电，至约Vp+NVs后，第一漏感Lr1能量通过MOS管Q3的体二极管D3流进钳位电容C1上，第一绕组Np的漏感Lr1能量被电容C1吸 收，MOS管Q1的漏极-源极的电压被钳位在约Vp+NVs处；同时，第二绕组Ns的漏感Lr2因为电感电流不能突变，MOS管Q4关断后，第二绕组Ns的漏感Lr2、第二绕组Ns以及MOS管Q2源极和漏极之间的结电容形成回路，维持电流的连续，即抽取MOS管Q2结电容的能量，使得MOS管Q2的源极和漏极之间的电压下降，一定程度上降低该管子的开通损耗，甚至一定条件下实现MOS管Q2的ZVS，与此同时，变压器极性相反，变压器第二绕组Ns的极性变成了上正下负，励磁电感Lm在t1-t2阶段所储能量通过耦合的方式释放出来，通过MOS管Q2的体二极管进行整流后输出到Vs端，为Vs端的负载提供供电。
[t3-t4]阶段，MOS管Q1、Q3和Q4依然因对应的驱动信号均为低电平而处于截止状态，MOS管Q2因其驱动信号Vgs2处于高电平而导通，导通压降近似为零，提供一个更低损耗的整流通路，即为处于正向工作的变换器提供同步整流。
[t4-t5]阶段，MOS管Q1和Q4依然因对应的驱动信号均为低电平而处于截止状态，MOS管Q2的因其驱动信号Vgs2依然为高电平而依然导通，在t4时刻开始，驱动信号Vgs3由低电平转为高电平，MOS管Q3开始导通，电容C2放电(t2-t3阶段漏感Lr2能量转移到C2上，t4-t5阶段释放出来)，至t5时刻，MOS管Q3和Q2同时截止。
[t5-t6]阶段，MOS管Q1和Q4依然因对应的驱动信号均为低电平而处于截止状态，t5时刻开始，MOS管Q2和Q3因其对应的驱动信号转为低电平而截止状态，其中MOS管Q2的体二极管提供整流路径，继续为变换器提供整流，t5时刻MOS管Q3关断，因为电感电流不能突变，MOS管Q3关断后，第一绕组Np的漏感Lr1、第一绕组Np电感以及MOS管Q1源极和漏极之间的结电容形成回路，维持电流的连续，即抽取MOS管Q1结电容的能量，使得MOS管Q1的源极和漏极之间的电压下降，一定程度上降低该管子的开通损耗，甚至一定条件下实现MOS管Q1的ZVS。
[t6-t7]阶段，进入下一个周期的工作，即上述的t0-t1阶段，之后(即t7-t8、t8-t9、t9-t10、t10-t11、t11-t12)的工作原理与前面相同，此处不再赘述；
其中：t2-t3为第一设定时间，t5-t6为第二设定时间，t5-t6为第三设定时间，t2-t3为第四设定时间，t3-t4为第五设定时间，t4-t5为第六设定时间，t0-t1为第七设定时间，t1-t2为第八设定时间。
第六设定时间和第八设定时间长度一般大于50ns，但是小于MOS管Q1或者MOS管Q2的最小导通时间，原因在于防止MOS管Q1和MOS管Q3或者MOS管Q2和MOS管Q4同时导通，使得钳位电容过度放电，通过变压器释放更多的电能到另外一侧再网回传，能量在变 压器原边和副边之间来回传递将造成不必要的功率损耗。
本实施例第一设定时间与第四设定时间，以及第二设定时间与第三设定时间相等。
以上为变换器正向的工作原理，能量从第一侧Vp经过变换转移至第二侧Vs。从图5可以看出，两侧的电路和控制均具有高度的对称性，尽管两侧的工作电压可能不同，比如第一侧Vp接整个电池组，第二侧Vs接电池组的某一个单体，但因为MOS管Q1和Q2使用的是互补控制，导通的MOS管其源极和漏极之间的电流方向是随着源极-漏极的电压不同而方向可以变化的，因此通过调节MOS管Q1的占空比既可以控制正向工作时的输出电流，也可以通过调节MOS管Q1的占空比实现能量由第二侧Vs传输到第一侧Vp的反向工作。
反向工作与正向工作原理是相同的，反向工作原理不再赘述，这样，通过调节MOS管Q1或者Q2的驱动信号占空比，即调节Vgs1或Vgs2的占空比能实现能量的双向传输和双向传输的功率大小。
本实施例同时通过提供信号驱动MOS管Q3和Q4，使钳位电容C1和C2吸收漏感能量，使得漏感能量通过对电容C1和C2进行充放电得到回收利用，同时有利于实现MOS管Q1和Q2的ZVS。
上述实施例实现能量的双向传输、漏感回收利用及部分功率管的ZVS虽然现有技术(特别是背景技术3，即申请号为201710654256.8)均能实现，但是本方案还克服了现有技术的整流管(即MOS管Q1或者Q2)关断损耗较大及电压应力较大的不足，具体分析如下：
本发明在背景文献3基础上，一个周期内分别给第三功率管和第四功率管提供驱动，且第一功率管和第三功率管的驱动不再互补，第二功率管和第四功率管的驱动不再互补，而是通过在第一功率管关断后提供一个固定短时间的高电平给第三功率管，又在第二功率管关断后提供一个固定短时间的高电平给第四功率管，分别使其导通，从而使第一钳位电容和第二钳位电容对外放电，达到充放电均衡，其当第一钳位电容取值较大时，其两端电压变化量较小可以忽略，两端电压稳定在匝比乘以第二侧输入正与输入负两端的电压附近，第一功率管在关断时的关断电压被钳位在约第一侧输入正与输入负两端的电压加上第一钳位电容两端的电压；其当第二钳位电容取值较大时，其两端电压变化量较小可以忽略，两端电压稳定在第一侧输入正与输入负两端的电压除以匝比附近，第二功率管在关断时的关断电压被钳位在约第二钳位电容两端电压再加第二侧输入正与输入负两端的电压，从而实现了在保留背景文献3技术优势的同时还解决了其第一功率管和第二功率管作为整流管关断时电压尖峰大和关断损耗大的不足。
以下为实验数据：
实验采用的功率电路见图5，应用于电池组与电池单体与之间，均衡电池组中的一个单体电压与组内的其他单体的电压：
其中Vs工作电压为3.3V，为一个电池单体的电压，功率管Q2和Q4均为两个Infineon公司型号为BSC034N06NS的MOS管并联使用，为60V 100A的MOS管，其RDS(ON)为3.4mΩ，封装为PG-TDSON-8，电容C2为1uF；
Vp工作电压为24V，为一个电池组的电压，为十个电池单体串联后所得，功率管Q1和Q3均为1个Infineon公司型号为BSC123N08NS3 G的MOS管，为80V 55A，其RDS(ON)为12.3mΩ，封装为PG-TSDSON-8的MOS管，电容C1为1uF；
变压器B的参数：磁芯为EIR18的通用磁芯，磁芯材质为越峰公司(ACME)的P61材质；绕组为基于12层PCB的平面绕组，铜厚为3盎司，第一绕组Np为12匝；第二绕组Ns为2匝；设计功率为40W；
没有设置会降低变换效率的电流检测电阻，PWM控制方面的技术方案采用微控制器编程产生控制信号，控制信号经SILICON LABORATORIES公司生产的型号为Si8235驱动器后形成Vgs1、Vgs2、Vgs3，以及Vgs4四路驱动信号，四路驱动信号的高电平电压为12V，低电平电压约为0V，工作频率为350KHz，其中死区时间(t2-t3和t5-t6)为60ns，即△t2＝△t4＝60ns，驱动信号Vgs3和Vgs4固定的脉冲时间(t1-t2，t4-t5)为100ns，即△t1＝△t3＝100ns，示意图如图8所示，通过控制驱动信号Vgs1的占空比来控制工作电流的大小和方向。
正向工作，能量从第一侧Vp至第二侧Vs(即输入电压为24V，输出电压为3.3V，通过调整驱动信号Vgs1的占空比，使其输出电流为10A，即输出功率为33W)的变换效率为：92.76％,；20MHz带宽下测得MOS管Q1的漏极-源极电压Vds1≤50V，MOS管Q2的漏极-源极电压Vds2≤8V；
反向工作，能量从第二侧Vs至第一侧Vp(即输入电压为3.3V，输出电压为24V，通过调整驱动信号Vgs1的占空比，使其输入电流为10A，即输入功率为33W)的变换效率：93.86％；20MHz带宽下测得MOS管Q1的漏极-源极电压Vds1≤52V，MOS管Q2的漏极-源极电压Vds2≤8V；
对比现有技术：
参见图5的电路，在同一个样品上进行修改，功率电路保持不变，保留使用同一个变 压器和功率管Q1、Q2、Q3和Q4，以及同样的电容C1、C2，只做控制信号上的改变，即驱动信号Vgs1和Vgs2为互补，正向工作时去掉驱动信号Vgs4，同时驱动信号Vgs1和Vgs3互补；反向工作时去掉驱动信号Vgs3或者置0，同时驱动信号Vgs2和Vgs4互补；
同等输出功率条件下，效率下降为：
正向工作，从第一侧Vp至第二侧Vs的变换效率：91.12％，与本发明的相比，下降了1.64％。20MHz带宽下测得MOS管Q1的漏极-源极电压Vds1≤50V，MOS管Q2的漏极-源极电压Vds2最大值为15V，与本发明相比上升了7V以上(Vds2的尖峰电压较大)；
反向工作，从第二侧Vs至第一侧Vp的变换效率：90.86％；与本发明的相比，下降了3％。20MHz带宽下测得MOS管Q1的漏极-源极电压Vds1最大值为82V，MOS管Q2的漏极-源极电压Vds2最大值为8V，与本发明相比MOS管Q1的Vds上升了30V(Vds1的尖峰电压较大)；
可见，本发明的方案每个周期通过将第一绕组等效漏感的能量与电容C1储存并释放，又将第二绕组的等效漏感的能量与电容C2储存并释放，来实现对功率管Q1和Q2的电压钳位，实现了比现有技术更小的关断损耗和尖峰电压；通过限制钳位管Q3和Q4的导通时间，降低钳位电容C1和C2与变压器谐振的损耗；较高效率地实现隔离式双向变换，实现了发明目的。
第二实施例
与第一实施例不同的是，在Q1的源极和漏极之间并联第一二极管，第一二极管的阳极连接在MOS管Q1的源极，第一二极管的阴极连接在MOS管Q1的漏极。第一二极管可以是肖特基二极管，在第一二极管正向导通时，第一二极管导通损耗比MOS管Q1的体二极管导通损耗更小，可以进一步提高转换效率。
第三实施例
与第二实施例不同的是，在MOS管Q2的源极和漏极之间并联第二二极管，D2的阳极连接在MOS管Q2的源极，第二二极管的阴极连接在MOS管Q2的漏极。第二二极管可以是肖特基二极管，在第二二极管正向导通时，第二二极管导通损耗比MOS管Q2的体二极管导通损耗更小，可以进一步提高转换效率。
第四实施例
与第三实施例不同的是，在MOS管Q3的源极和漏极之间并联第三二极管，第三二极管的阳极连接在MOS管Q3的源极，第三二极管的阴极连接在MOS管Q3的漏极；在MOS管Q4 的源极和漏极之间并联第四二极管，第四二极管的阳极连接在MOS管Q4的源极，第四二极管的阴极连接在MOS管Q4的漏极。第三二极管和第四二极管可以是肖特基二极管，在第三二极管或者第四二极管正向导通时，其导通损耗比与其并联的功率管的体二极管导通损耗更小，可以进一步提高转换效率。
第五实施例
请参见图9，为本发明的第五实施例的电路原理图，与第一实施例不同的是第一钳位电容C1的另一端与第一侧Vp的输入负相连，第二钳位电容C2的另一端与第二侧Vs的输入负相连；各功率管的控制策略及工作原理相同，在此不赘述。以上仅是本发明的优选实施方式，应当指出的是，上述优选实施方式不应视为对本发明的限制。
对于本技术领域的普通技术人员来说，在不脱离本发明的精神和范围内，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围，这里不再用实施例赘述，本发明的保护范围应当以权利要求所限定的范围为准。

Claims (9)

  1. 一种DC-DC变换器，包括第一侧、第二侧、一个变压器、第一功率管、第二功率管、第三功率管、第四功率管、第一钳位电容，以及第二钳位电容，变压器至少包括第一绕组与第二绕组，连接关系为：
    第一功率管的导通电流流出端作为第一侧的输入负；第一功率管的导通电流流入端连接变压器的第一绕组的异名端以及第三功率管的导通电流流出端；第三功率管的导通电流流入端连接第一钳位电容的一端，第一钳位电容的另一端与变压器的第一绕组的同名端相连并形成第一侧的输入正；
    第二功率管的导通电流流出端形成第二侧的输入负；第二功率管的导通电流流入端连接变压器的第二绕组的同名端以及第四功率管的导通电流流出端；第四功率管的导通电流流入端连接第二钳位电容的一端，第二钳位电容的另一端与变压器的第二绕组的异名端相连并形成第二侧的输入正；
    第一功率管的控制端用于输入第一驱动信号，第二功率管的控制端用于输入第二驱动信号，第三功率管的控制端用于输入第三驱动信号，第四功率管的控制端用于输入第四驱动信号；
    其特征在于：第一驱动信号至第四驱动信号要求如下：
    四路驱动信号均为由高电平和低电平组成的脉冲信号，频率相同；
    正向工作时，第一驱动信号在由高电平翻转为低电平时第二驱动信号延迟第一设定时间后才由低电平翻转为高电平，第二驱动信号在由高电平翻转为低电平时第一驱动信号延时第二设定时间后才由低电平翻转为高电平；反向工作时，第二驱动信号在由高电平翻转为低电平时第一驱动信号延迟第三设定时间后才由低电平翻转为高电平，第一驱动信号在由高电平翻转为低电平时第二驱动信号延时第四设定时间后才由低电平翻转为高电平；
    第三驱动信号在第二驱动信号翻转为高电平时延时第五设定时间后才翻转为高电平，并经过第六设定时间后第三驱动信号翻转为低电平，然后第二驱动信号在第三驱动信号翻转为低电平之后或同时翻转为低电平；
    第四驱动信号在第一驱动信号翻转为高电平时延时第七设定时间后才翻转为高电平，并经过第八设定时间后第四驱动信号翻转为低电平，然后第一驱动信号在第四驱动信号翻转为低电平之后或同时翻转为低电平。
  2. 根据权利要求1所述的DC-DC变换器，其特征在于：将第一钳位电容的另一端与第 一侧的输入负相连，第二钳位电容的另一端与第二侧的输入负相连。
  3. 根据权利要求1或2所述的DC-DC变换器，其特征在于：第六设定时间和第八设定时间长度大于50ns，小于第一功率管或者第二功率管的最小导通时间。
  4. 根据权利要求1或2所述的DC-DC变换器，其特征在于：第一设定时间与第四设定时间、第二设定时间与第三设定时间，以及第六设定时间与第八设定时间择一或者择二或者全部相等。
  5. 根据权利要求1或2所述的DC-DC变换器，其特征在于：第一功率管、第二功率管、第三功率管，以及第四功率管均为N沟道增强型MOS管，且均为高电平时导通，低电平时关断。
  6. 根据权利要求1或2所述的DC-DC变换器，其特征在于：还包括第一二极管，第一二极管的阳极与第一功率管的源极连接，第一二极管的阴极与第一功率管的漏极连接。
  7. 根据权利要求1或2所述的DC-DC变换器，其特征在于：还包括第二二极管，第二二极管的阳极与第二功率管的源极连接，第二二极管的阴极与第二功率管的漏极连接。
  8. 根据权利要求1或2所述的DC-DC变换器，其特征在于：还包括第三二极管，第三二极管的阳极与第三功率管的源极连接，第三二极管的阴极与第三功率管的漏极连接。
  9. 根据权利要求1或2所述的DC-DC变换器，其特征在于：还包括第四二极管，第四二极管的阳极与第四功率管的源极连接，第四二极管的阴极与第四功率管的漏极连接。
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CN104300795A (zh) * 2014-10-11 2015-01-21 广州金升阳科技有限公司 一种反激变换器及其控制方法
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CN107482921A (zh) * 2017-08-03 2017-12-15 广州金升阳科技有限公司 一种双向dc‑dc变换器
CN108418438A (zh) * 2018-05-18 2018-08-17 广州金升阳科技有限公司 一种dc-dc变换器
CN208424210U (zh) * 2018-05-18 2019-01-22 广州金升阳科技有限公司 一种dc-dc变换器

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