WO2019218557A1 - 阵列基板和显示屏 - Google Patents

阵列基板和显示屏 Download PDF

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Publication number
WO2019218557A1
WO2019218557A1 PCT/CN2018/106317 CN2018106317W WO2019218557A1 WO 2019218557 A1 WO2019218557 A1 WO 2019218557A1 CN 2018106317 W CN2018106317 W CN 2018106317W WO 2019218557 A1 WO2019218557 A1 WO 2019218557A1
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WIPO (PCT)
Prior art keywords
display area
shaped display
pixels
output transistor
array substrate
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PCT/CN2018/106317
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English (en)
French (fr)
Inventor
范龙飞
王龙彦
马占洁
胡思明
韩珍珍
朱晖
Original Assignee
昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to KR1020207006739A priority Critical patent/KR102307440B1/ko
Priority to JP2020501449A priority patent/JP6932234B2/ja
Priority to EP18919025.9A priority patent/EP3640927A4/en
Priority to US16/540,041 priority patent/US11011119B2/en
Publication of WO2019218557A1 publication Critical patent/WO2019218557A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate and a display screen.
  • a non-rectangular display is called a shaped display.
  • the shaped display includes a shaped display area and a non-shaped display area.
  • the number of pixels per line in the heterogeneous display area is different from the number of pixels per line in the non-aliased display area.
  • a driving circuit in a display panel controls pixels on a corresponding row through different scanning lines.
  • the scan line provides the same scan signal for the pixels on the corresponding row, since the number of pixels in each row of the alien display region and the non-profile display region is different, the load on the scan line is different, resulting in uneven brightness of the displayed image. , affecting the display effect.
  • the present application provides an array substrate and a display screen, which can solve the technical problem that the brightness of the display image is uneven due to the difference in the number of pixels in each row of the alien display region and the non-profile display region.
  • the application provides an array substrate, the array substrate comprising:
  • the display area includes pixels arranged in an array, and the display area includes a special-shaped display area and a non-shaped display area;
  • At least one first gate driving unit located in the non-display area and connected to pixels on corresponding rows in the shaped display area by a first lead line, wherein the first gate driving unit is configured to drive pixels on the corresponding row ;as well as
  • At least one second gate driving unit located in the non-display area and connected to pixels on a corresponding row in the non-profile display area by a second lead line, wherein the second gate driving unit is configured to drive the corresponding row Pixel
  • the first gate driving unit includes at least one first output transistor
  • the second gate driving unit includes at least one second output transistor, the first output transistor having a width to length ratio smaller than the second output a width-to-length ratio of the transistor; and a width of the first lead line corresponding to the shaped display area and a width of the second lead line corresponding to the non-profile display area are respectively adaptively configured to make the profile The illuminating currents of the display area and the non-profile display area are equal.
  • the number of pixels per row of the shaped display area is smaller than the number of pixels of any row of the non-shaped display area.
  • the first gate driving unit includes a scan driving circuit and/or a transmission driving circuit.
  • the second gate driving unit includes a scan driving circuit and/or a transmission driving circuit.
  • the number of pixels of at least two rows of pixels in the shaped display area is different, and the width-to-length ratio of the first output transistor corresponding to each row of pixels in the shaped display area follows The number of pixels is reduced by a decrease.
  • the shaped display area comprises at least one sub-shaped display area, each of the sub-shaped display areas comprising at least two rows of pixels.
  • the number of pixels of each row in the sub-shaped display area is the same, and the width-to-length ratio of the first output transistors corresponding to any row of pixels in the sub-shaped display area is equal.
  • the aspect ratio of the first output transistor corresponding to each row of pixels in each of the sub-shaped display regions is positively correlated with the number of pixels in each row in each of the sub-identical display regions.
  • the gate area of the first output transistor is greater than the gate area of the second output transistor.
  • the shaped display area includes a plurality of sub-shaped display areas, each of the sub-shaped display areas includes at least two rows of pixels, and the width of the first output transistor corresponding to each row of pixels in the different sub-shaped display areas The length ratio is positively correlated with the number of pixels in each row of the different sub-profile display regions.
  • the array substrate further includes signal lines respectively located in the shaped display area and the non-profiled display area, and the signal line is attached to the edge of the shaped display area in the shaped display area. Concentrating a curved trace; the signal line located in the shaped display area is for connecting the first output transistor and transmitting a driving signal to a pixel on a corresponding row in the shaped display area, and compensating for the shaped display area The difference in resistance between the resistance of the signal line and the resistance of the signal line in the non-profile display area.
  • the width of the signal line of the shaped display area and the width of the signal line of the non-profiled display area are not equal.
  • the signal line in the shaped display area includes a plurality of sub-signal lines, and at least one of the plurality of sub-signal lines has a width of the sub-signal line and a signal line of the non-shaped display area. The width varies.
  • the signal line includes a scan signal line and a transmit control signal line, wherein the scan signal line is used to connect a scan driving circuit and corresponding pixels and transmit a scan signal, and the transmit control signal line is used for The transmit drive circuit and the corresponding pixels are connected and the transmit control signal is transmitted.
  • the array substrate is provided with a mounting slot in the non-display area, and the signal line of the shaped display area is attached to the edge of the mounting slot to concentrate the curved trace.
  • a gate insulating layer of the first output transistor has a dielectric constant smaller than a dielectric constant of a gate insulating layer of the second output transistor.
  • the thickness of the gate insulating layer of the first output transistor is greater than the thickness of the gate insulating layer of the second output transistor.
  • a first mask layer is formed on a surface of the gate insulating layer of the first output transistor, the first mask layer exposing a gate insulating layer of the first output transistor,
  • the first mask layer is a mask
  • the gate insulating layer of the first output transistor is microetched such that a thickness of the gate insulating layer of the first output transistor is smaller than a gate insulating layer of the second output transistor thickness of.
  • the first output transistor has a semiconductor layer, a first gate insulating layer formed on the semiconductor layer, a second gate insulating layer formed on the first gate insulating layer, and formed a second mask layer on a surface of the second gate insulating layer, the second mask layer exposing a second gate insulating layer of the first output transistor, by using the second mask layer as a mask Removing the second gate insulating layer of the first output transistor to expose the first gate insulating layer of the first output transistor to make the first gate insulating layer and the second gate insulating layer of the first output transistor
  • the thickness is smaller than the thickness of the gate insulating layer of the second output transistor.
  • the application also provides a display screen comprising any of the above array substrates.
  • the present application provides an array substrate and a display screen.
  • the corresponding display area on the array substrate includes a special-shaped display area and a non-profile display area, and the first gate driving unit corresponding to the pixel in the non-display area and the special-shaped display area is located at the non-display area.
  • the aspect ratio of the first output transistor of the first gate driving unit is smaller than the aspect ratio of the second output transistor of the second gate driving unit
  • the width of the first lead line corresponding to the shaped display area and the width of the second lead line corresponding to the non-shaped display area accurately compensating for the difference between the shaped display area and the non-shaped display area, so that the shaped display area and The illuminating currents of the non-profile display area are equal, which solves the technical problem that the display image brightness is uneven due to different loads between the abnormal display area and the non-profile display area, and improves the display effect.
  • 1a is a schematic structural view of an array substrate in an embodiment of the present application.
  • 1b is a schematic structural view of a first lead line and a second lead line in an embodiment of the present application
  • FIG. 2 is a schematic structural view of an array substrate according to another embodiment of the present application.
  • FIG. 3 is a circuit diagram of a 6T2C circuit in an embodiment of the present application.
  • FIG. 4 is a circuit diagram of a 13T3C pixel circuit in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a plurality of sub-shaped display areas in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a first output transistor in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a scanning signal line in a shaped display area in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a display device in an embodiment of the present application.
  • the present application provides an array substrate including a substrate on which a display area and a non-display area 110 are disposed.
  • the display area includes a shaped display area 120 and a non-shaped display area 130.
  • the corresponding display area on the substrate includes the pixels 140 arranged in an array, and the number of pixels in each row of the shaped display area 120 is smaller than the number of pixels in any row of the non-shaped display area 130.
  • the driver drives the pixels on each line of the alien display area and the pixels on each line of the non-shaped display area, since the number of pixels on each line of the shaped display area and the non-shaped display area is different, that is, the load is different, which may result in The display effect of the irregular display area and the non-shaped display area is uneven.
  • the number of pixels in each row in the non-profile display area is equal, and the non-profile display area is generally a regular area.
  • the shape of the non-profile display area is a rectangle.
  • the number of pixels on each line of the non-profile display area is generally equal, and the luminescence characteristics of each line of pixels in the non-profile display area remain the same.
  • the array substrate further includes at least one first gate driving unit 150 and at least one second gate driving unit 160 .
  • the first gate driving unit 150 is located in the non-display area 110.
  • the first gate driving unit 150 connects the pixels 140 on the corresponding rows in the shaped display region 120 through the first lead line 170.
  • the first gate driving unit 150 is for driving the pixels 140 on the corresponding row.
  • the second gate driving unit 160 is located in the non-display area 110.
  • the second gate driving unit 160 connects the pixels 140 on the corresponding rows in the non-profile display area 130 through the second lead line 180.
  • the second gate driving unit 160 is for driving the pixels 140 on the corresponding row.
  • the first gate driving unit 150 includes at least one first output transistor
  • the second gate driving unit 160 includes at least one second output transistor.
  • the first output transistor and the second output transistor each include a gate, a source and a drain, and the voltage of the gate can control the turn-off or turn-on of the first/second output transistor.
  • the aspect ratio of the first output transistor is smaller than the aspect ratio of the second output transistor.
  • the width of the first lead line 170 corresponding to the shaped display area 120 and the width of the second lead line 180 corresponding to the non-profiled display area 130 are respectively adaptively arranged so that the illuminating currents of the shaped display area and the non-shaped display area are equal.
  • the aspect ratio of the transistor refers to the ratio of the width to the length of the conductive channel of the transistor, that is, W/L, where W is the width of the conductive channel of the transistor, and L is the length of the conductive channel of the transistor.
  • W the width of the conductive channel of the transistor
  • L the length of the conductive channel of the transistor.
  • the larger the aspect ratio of a transistor the greater its driving capability, that is, the load carrying capability, and the larger the driving current flowing through the transistor.
  • the scan signal line extends in a second direction.
  • the first lead line 170 is connected to the scanning signal line of the shaped display area 120.
  • the second lead line 180 is connected to the scanning signal line of the non-profile display area 130.
  • the width of the first lead line 170 refers to the dimension W1 of the first lead line 170 in the first direction
  • the width of the second lead line 180 refers to the dimension W2 of the second lead line 180 in the first direction.
  • the first direction and the second direction are perpendicular to each other.
  • the scanning signal line also has a certain size in the first direction, which is recorded as the width of the scanning signal line, and the scanning signal line may include a plurality of sub-scanning signal lines, and each of the sub-scanning signal lines also has the first direction.
  • a certain size is recorded as the width of the sub-scanning signal line, and will not be described here.
  • the width of the first lead line 170 and the width of the second lead line 180 may be further adaptively configured on the basis of changing the aspect ratio of the first output transistor, such as by adaptively configuring the width of the first lead line 170
  • the width of the first lead line 170 may be smaller than the width of the second lead line 180, or the width of the first lead line 170 may be greater than the width of the second lead line 180 to achieve accurate compensation.
  • the driving capability of the first gate driving unit in the shaped display region 120 can be reduced by reducing the aspect ratio of the first output transistor in the shaped display region 120
  • the adaptive display region 120 can be configured by adaptively.
  • the width of the lead wire 170 is varied to vary the capacitive load accordingly.
  • the dissimilar display area 120 can be solved from the driving capability and the capacitive load of the first gate driving unit.
  • the display effect between the non-shaped display area 130 and the non-aliased display area 130 is uneven.
  • the width of the first lead line 170 corresponding to the shaped display area may be increased, such that the width of the first lead line 170 corresponding to the shaped display area is increased.
  • the width of the first lead line 170 is greater than the width of the second lead line 180 corresponding to the non-profile display area to correspondingly increase the capacitive load of the shaped display area 120.
  • the width of the first lead-out line 170 corresponding to the shaped display region may be reduced, so that the first lead-out The width of the line 170 is smaller than the width of the second lead line 180 corresponding to the non-profiled display area to correspondingly reduce the capacitive load of the shaped display area 120.
  • the simulation results are as shown in the following table.
  • the current difference between the shaped display region and the non-profiled display region is 0.27 nA.
  • the current difference between the shaped display area and the non-profiled display area is 5 nA, and the brightness of the shaped display area and the non-shaped display area differ by at least 5 gray scales, especially when the gray scale is low.
  • the uneven brightness between the shaped display area and the non-shaped display area is more obvious.
  • the simulation results are shown in the following table, by adjusting the aspect ratio of the first output transistor and adaptively adjusting The width of the first lead line, the current difference between the shaped display area and the non-shaped display area is 0.08 nA. Therefore, the difference in current after compensation in combination with the two methods is smaller than the difference in current after compensation by one mode, and the brightness between the shaped display area and the non-shaped display area can be made more uniform.
  • the driving capability of the first gate driving unit in the shaped display area can be reduced.
  • the capacitor compensation is appropriately performed to make the illuminating currents of the abnormal display area and the non-shaped display area equal, thereby solving the technical problem that the brightness of the displayed image is uneven due to the load difference between the shaped display area and the non-shaped display area. , the brightness uniformity between the shaped display area and the non-shaped display area is improved.
  • the first gate driving unit and the second gate driving unit are both gate driving units, and the gate driving unit includes a scan driving circuit and/or a transmitting driving circuit.
  • the gate driving unit may include only the scan driving circuit, or only the transmitting driving circuit, and may also include the scan driving circuit and the transmitting driving circuit.
  • a scan driving circuit for sequentially applying scan signals to pixels.
  • a transmit driver circuit for applying a transmit control signal to the pixel.
  • the gate driving unit includes a scan driving circuit 210 and a transmitting driving circuit 220.
  • the scan driving circuit 210 connects the plurality of pixels PX11 to PXnm arranged in a matrix form through the scanning signal lines S1 to Sn, and the pixels PX11 to PXnm are also connected to the emission control signal lines E1 to Em, and are connected to the emission driving through the emission control signal lines E1 to Em. Circuit.
  • the emission control signal lines E1 to Em are substantially parallel to the scanning signal lines S1 to Sn.
  • the scan driving circuit 210 is a 6T2C circuit, including a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a capacitor C1, and a capacitor C2.
  • the transistor M5 and the transistor M6 are output transistors of the scan driving circuit 210.
  • the transistor M5 and the transistor M6 are turned on or off according to the voltage of their gates.
  • the transistor M5 is turned on, the input signal of the clock signal input terminal SCK2 is transmitted to the output terminal of the scan driving circuit 210.
  • the transistor M6 is turned on, the input signal of the power supply voltage signal input terminal VGH is transmitted to the output terminal of the scan driving circuit 210.
  • the aspect ratio of the first output transistor corresponding to the pixel of the shaped display area 120 is smaller than the aspect ratio of the second output transistor corresponding to the pixel of the non-shaped display area 130.
  • the aspect ratio of the transistor M5 corresponding to the pixel of the shaped display area 120 is smaller than the aspect ratio of the transistor M5 corresponding to the pixel of the non-shaped display area 130.
  • the width-to-length ratio of the transistor M6 corresponding to the pixel of the dissimilar display area 120 is smaller than the aspect ratio of the transistor M6 corresponding to the pixel of the non-profile display area 130.
  • the emission driving circuit 220 is a 13T3C circuit, including a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9, a transistor M10, and a transistor M11.
  • the transistor M9 and the transistor M10 are output transistors of the emission driving circuit 220.
  • the transistor M9 and the transistor M10 are turned on or off according to the voltage of their gates.
  • the aspect ratio of the first output transistor corresponding to the pixel of the shaped display area 120 is smaller than the aspect ratio of the second output transistor corresponding to the pixel of the non-shaped display area 130 .
  • the width-to-length ratio of the transistor M9 corresponding to the pixel of the shaped display area 120 is smaller than the aspect ratio of the transistor M9 corresponding to the pixel of the non-shaped display area 130.
  • the width-to-length ratio of the transistor M10 corresponding to the pixel of the dissimilar display area 120 is smaller than the aspect ratio of the transistor M10 corresponding to the pixel of the non-profile display area 130.
  • the gate driving unit in the array substrate includes a scan driving circuit 210 and a transmitting driving circuit 220, and the scanning driving circuit 210 and the transmitting driving circuit 220 can be changed.
  • the aspect ratio of the first output transistor of one or both of them may, for example, only reduce the aspect ratio of the transistor M5 and the transistor M6 in the scan driving circuit 210, or may only reduce the transistor M9 in the emission driving circuit 220.
  • the aspect ratio of the transistor M10 it is also possible to simultaneously reduce the aspect ratio of the transistor M5 and the transistor M6 in the scan driving circuit 210 and the aspect ratio of the transistor M9 and the transistor M10 in the emission driving circuit 220.
  • the gate driving unit may include one of the scan driving circuit or the emission driving circuit or both the scan driving circuit and the emission driving circuit.
  • the gate driving unit may include only the scan driving circuit, and may also include the scan driving circuit and the light emitting driving circuit. The designer can design the difference between the width-to-length ratio parameter of the first output transistor corresponding to the shaped display area and the second output transistor corresponding to the non-shaped display area according to actual conditions.
  • the driving capability solves the problem of unbalanced load between the heterogeneous display area and the non-aliased display area, so that the display effect of both the abnormal shaped display area and the non-shaped display area is uniform, and the display effect is improved.
  • the number of pixels on at least two rows of the shaped display area is different, and the width to length ratio of the first output transistor corresponding to each row of pixels decreases as the number of pixels in the row decreases.
  • There are a plurality of rows of pixels in the shaped display area and the number of pixels on at least two lines is different.
  • the driving ability of the gate driving unit corresponding to the shaped display area should be weakened, so that the shaped display area is The width to length ratio of the first output transistor corresponding to each row of pixels decreases as the number of pixels in the row decreases.
  • the drive drives the pixels of the display area line by line.
  • the driver can drive the pixels of the display area column by column.
  • the load of the driver is related to the number of pixels on each column of the profiled display area.
  • the aspect ratio of the first output transistor corresponding to the shaped display area may decrease in the column direction.
  • the first output transistors of different aspect ratios can be accurately designed according to the number of pixels on each row in the shaped display area, and the technical problem of uneven display effect between the heterogeneous display area and the non-shaped display area can be solved. .
  • the shaped display area includes at least one sub-shaped display area, each sub-shaped display area includes at least two rows of pixels, and each row has the same number of pixels.
  • the width-to-length ratio of the first output transistors in each sub-profile display area is equal.
  • the shaped display area may include a sub-shaped display area, and the heterogeneous display area may also include a plurality of sub-shaped display areas, each of the sub-shaped display areas includes at least two rows of pixels, and each row has the same number of pixels.
  • the shaped display area includes a first sub-shaped display area 510, a second sub-shaped display area 520, a third sub-shaped display area 530, and a fourth sub-shaped display area 540.
  • the first sub-shaped display area 510 includes at least two rows of pixels, and the number of pixels per row corresponding to the first sub-shaped display area 510 is approximately equal, and the first sub- The width-to-length ratio of the first output transistors of the shaped display area 510 is substantially equal, and the width-to-length ratio of the first output transistors corresponding to any one of the pixels in the first sub-shaped display area 510 is equal.
  • the aspect ratio of the first output transistor of the second sub-shaped display area 520, the third sub-shaped display area 530, and the fourth sub-shaped display area 540 is not described herein.
  • the number of pixels in each of the different sub-shaped display areas may be unequal.
  • the aspect ratio of the first output transistor corresponding to each row of pixels in the different sub-shaped display regions is positively correlated with the number of pixels in each row of the different sub-shaped display regions.
  • the number of pixels of each row in the first sub-shaped display area 510 is smaller than the number of pixels in each row of the third sub-shaped display area 530
  • the width-to-length ratio of the first output transistor corresponding to the first sub-shaped display area 510 is smaller than The width and length ratio of the first output transistor corresponding to the three sub-shaped display area 530.
  • the number of pixels of each row in each sub-shaped display area may be equal or not equal.
  • the width-to-length ratio of the first output transistors corresponding to each row of pixels in the number of pixels in each sub-shaped display area is also unequal, and the width-to-length ratio of the first output transistors corresponding to each row of pixels and each of the sub-shaped display areas.
  • the number of pixels in a row is positively correlated, that is, the aspect ratio of the first output transistor decreases as the number of pixels in each row in each sub-shaped display region decreases, and the number of pixels in each row in each sub-shaped display region increases. And increase.
  • the number of pixels in each row of the sub-shaped display area is regarded as approximately equal, and the first output transistor is designed for the sub-shaped display area, and the sub-shaped display area is designed.
  • the first output transistors corresponding to each row of pixels have the same aspect ratio, which can make the layout of the array substrate simple and reduce the complexity of the process.
  • the gate area of the first output transistor is greater than the gate area of the second output transistor.
  • the gate area of the transistor is equal to the product of the gate length and the gate width, which is approximately equal to the product of the width and length of the conductive channel of the transistor, ie, W*L.
  • the larger the product of the width and length of the conductive channel of the transistor the larger the parasitic capacitance of the transistor itself.
  • the aspect ratio of the first output transistor is smaller than the aspect ratio of the second output transistor
  • the width and length of the first output transistor are approximately proportionally increased to keep the aspect ratio of the first output transistor unchanged.
  • the gate area of the first output transistor is larger than the gate area of the second output transistor.
  • the first output transistor is maintained by approximately proportionally increasing the gate length and the gate width of the first output transistor.
  • the width-to-length ratio is constant, increasing the overlap area between the gate and the channel layer of the first output transistor, correspondingly increasing the capacitive load, compensating for the load reduction caused by the decrease in the number of pixels in the single-shaped display area, and solving the problem
  • the technical problem that the display is uneven due to the difference in the number of pixels per row of the heterogeneous display area and the non-shaped display area.
  • the array substrate further includes signal lines respectively located in the shaped display area and the non-profiled display area.
  • the signal line is bent at the edge of the shaped display area in the shaped display area.
  • the signal line located in the shaped display area is used for connecting the first output transistor and transmitting the driving signal to the pixels on the corresponding row in the shaped display area, and compensating for the resistance of the signal line in the shaped display area and the resistance of the signal line in the non-shaped display area. The difference in resistance between.
  • the signal line includes a scanning signal line and an emission control signal line.
  • the scan signal line is connected to the scan driving circuit and the corresponding pixel and transmits the scan signal
  • the emission control signal line is connected to the emission driving circuit and the corresponding pixel and transmits the emission control signal.
  • the non-display area of the array substrate is provided with a mounting groove.
  • the opening direction of the mounting groove may be in the row direction or in the column direction. The application does not limit the opening direction and specific position of the mounting groove.
  • the mounting slot can be used to place sensors such as cameras, earpieces, fingerprint recognition components, and iris recognition components. The mounting slot results in the creation of a profiled display area with less load in the profiled display area.
  • the gate area of the first output transistor is increased proportionally.
  • the gate area of the first output transistor is larger than the gate area of the second output transistor, which causes the gate line resistance of the first output transistor to decrease relative to the gate line resistance of the second output transistor.
  • the scanning signal line transmitting the scanning signal is attached to the edge of the shaped display area to concentrate the curved line.
  • the scanning signal line located in the shaped display area increases the length of the scanning signal line along the edge of the shaped display area, correspondingly increases the resistance of the scanning signal line of the shaped display area, thereby compensating for the resistance of the scanning signal line of the shaped display area The difference in resistance between the scanning signal lines and the non-profile display area.
  • the shape of the mounting groove may be U-shaped, curved, or circular.
  • the mounting groove extends through the array substrate and includes a bottom surface and sides on both sides of the bottom surface.
  • the vertical projection area of the mounting groove on the array substrate is a slotted area, and the slotted area includes a bottom edge and side edges on both sides of the bottom edge.
  • the bottom edge of the grooved area may extend along the row direction of the pixel arrangement, and the bottom edge of the grooved area may also extend along the column direction of the pixel arrangement.
  • the scanning signal line is taken as an example.
  • the mounting slot 710 is a U-shaped slot, and the mounting slot 710 is located in the non-display area.
  • the area corresponding to the vertical projection of the mounting groove on the array substrate is a slotted area.
  • the slotted area includes a bottom edge 713 and side edges 711 and sides 712 distributed on both sides of the bottom edge 713.
  • the scanning signal lines corresponding to the different-shaped display areas are routed along the bottom side 713, the side 711, and the side 712.
  • the scanning signal line in the shaped display area includes a first sub-scanning signal line 721, a second sub-scanning signal line 722 along the side 711, a third sub-scanning signal line 723 along the bottom side 713, along The fourth sub-scanning signal line 724 and the fifth sub-scanning signal line 725 of the side 712.
  • the signal line of the shaped display area includes a plurality of sub-signal lines, and the width of at least one of the plurality of sub-signal lines and the width of the signal lines of the non-shaped display area are not equal.
  • the width of the signal line is related to the resistance on the signal line.
  • the scanning signal line is taken as an example.
  • the widths of the first sub-scanning signal line 721 and the fifth sub-scanning signal line 725 may be equal to the width of the gate of the first output transistor. Since the gate area of the first output transistor is large, the widths of the first sub-scanning signal line 721 and the fifth sub-scanning signal line 725 are large, which reduces the resistance on the scanning signal line, but can be adjusted by adjusting the second sub- The widths of the scan signal line 722, the third sub-scanning signal line 723, and the fourth sub-scanning signal line 724 achieve accurate compensation of the resistance, such as reducing the second sub-scanning signal line 722, the third sub-scanning signal line 723, and the fourth sub- The width of the signal line 724 is scanned to correspondingly increase the resistance on the scan signal line of the profiled display area.
  • the width of the partial section of the first sub-scanning signal line 721 and the fifth sub-scanning signal line 725 may not be equal to the width of the gate of the first output transistor, and the first sub-scanning signal line 721 and the second sub-field may be adjusted.
  • the widths of the scan signal line 722, the third sub-scanning signal line 723, the fourth sub-scanning signal line 724, and the fifth sub-scanning signal line 725, for example, the first sub-scanning signal line 721 and the second sub-scanning signal line 722 are reduced.
  • the scanning signal line in the shaped display area is routed along the edge of the mounting slot, which increases the length of the scanning signal line in the shaped display area, increases the resistance of the scanning signal line, and solves the number of pixels due to the shaped display area.
  • the problem of uneven resistance caused by less is achieved, and accurate compensation of the resistance in the shaped display area is realized.
  • the first output transistor includes a buffer layer 610, a semiconductor layer (not shown) on the buffer layer 610, a gate insulating layer 630 on the semiconductor layer, and a gate insulating layer 630 away from the semiconductor.
  • the source and drain metal layers include a source metal lead 661 and a drain metal lead 662.
  • the parasitic capacitance of the first output transistor is related to the thickness of the gate insulating layer and its dielectric constant, and the parasitic capacitance of the first output transistor can be increased in the following two ways.
  • the first way is to change the parasitic capacitance of the first output transistor by changing the dielectric constant of the gate insulating layer 630 of the first output transistor.
  • the dielectric constant of the gate insulating layer of the first output transistor is made larger than the dielectric constant of the gate insulating layer of the second output transistor.
  • the parasitic capacitance of the transistor is proportional to the dielectric constant of the transistor, and the dielectric constant of the gate insulating layer of the first output transistor corresponding to the shaped display region can be changed by changing the material of the gate insulating layer corresponding to the first driving transistor in the shaped display region.
  • the dielectric constant of the gate insulating layer of the second output transistor corresponding to the non-profile display area.
  • the second way is to increase the parasitic capacitance of the first output transistor corresponding to the shaped display region by reducing the thickness of the gate insulating layer 630 corresponding to the shaped display region.
  • the thickness of the gate insulating layer of the first output transistor is made smaller than the thickness of the gate insulating layer of the second output transistor.
  • a first mask layer is formed on the surface of the gate insulating layer, and the first mask layer exposes the gate insulating layer of the shaped display region.
  • the gate insulating layer of the shaped display region is microetched by using the first mask layer as a mask to reduce the thickness of the gate insulating layer of the shaped display region.
  • a first gate insulating layer is formed on the semiconductor layer.
  • a second gate insulating layer is formed on the first gate insulating layer.
  • a second mask layer is formed on the surface of the second gate insulating layer.
  • the second mask layer exposes the second gate insulating layer of the shaped display region.
  • the second gate insulating layer is removed by using the second mask layer as a mask to expose the first gate insulating layer of the shaped display region.
  • the thickness of the gate insulating layer corresponding to the shaped display region is made smaller than the thickness of the gate insulating layer corresponding to the non-profile display region. It should be noted that, in the embodiment, the designer needs to ensure the characteristics of the first output transistor and the second output transistor when increasing the dielectric constant of the gate insulating layer of the shaped display region or thinning the thickness of the gate insulating layer. constant.
  • the present application provides a display screen comprising the array substrate of any of the above embodiments.
  • the shape of the display screen may be a closed figure including at least one of a circle, an ellipse, a polygon, and a graphic including a circular arc.
  • a display with an R angle, a slot or a notch or a circle may be a closed figure including at least one of a circle, an ellipse, a polygon, and a graphic including a circular arc.
  • a display with an R angle, a slot or a notch or a circle may be a display with an R angle, a slot or a notch or a circle.
  • the present application provides a display device 800.
  • the display device 800 includes a display screen 810 as in the above embodiment.
  • the number of pixels in the heterogeneous display area is different from the number of pixels distributed in the non-shaped display area, for example, the number of pixels in each row in the heterogeneous display area is different from the number of pixels in each line in the non-shaped display area. It can be understood that the distinction between the alien display area and the non-profile display area is relative.
  • a partial area having a small number of pixels in the display area is referred to as a "alien shaped display area”; and a partial area having a large number of pixels in the display area is referred to as a "non-aliased display area".
  • first, second and the like used in the embodiments of the present application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.
  • a first output transistor can be referred to as a second output transistor without departing from the scope of the present application, and similarly, a second output transistor can be referred to as a first output transistor. Both the first output transistor and the second output transistor are output transistors, but they are not the same output transistor.

Abstract

一种阵列基板和显示屏，阵列基板上对应的显示区包括异形显示区和非异形显示区，阵列基板上包括位于非显示区与异形显示区中的像素对应的第一栅极驱动单元，位于非显示区与非异形显示区中的像素对应的第二栅极驱动单元，第一栅极驱动单元的第一输出晶体管的宽长比小于第二栅极驱动单元的第二输出晶体管的宽长比，并适应性地配置异形显示区对应的第一引出线的宽度与非异形显示区对应的第二引出线的宽度，精确补偿了异形显示区和非异形显示区之间的差异，解决了异形显示区与非异形显示区中因负载不同所导致的显示的图像亮度不均的技术问题。

Description

阵列基板和显示屏 技术领域
本申请涉及显示技术领域，特别是涉及一种阵列基板和显示屏。
背景技术
目前，常见的显示装置，例如显示器、电视机、手机、平板电脑等，其显示屏通常为规则的矩形。随着显示技术的发展，矩形的显示屏已经不能满足用户多样化的使用需求。因而，显示屏的形状越来越多样化。
通常，非矩形的显示屏称为异形显示屏。异形显示屏包括异形显示区与非异形显示区。异形显示区中每行的像素个数与非异形显示区中每行的像素个数不同。
在传统技术中，显示面板中的驱动电路通过不同的扫描线控制对应行上的像素。然而，扫描线为对应行上的像素提供相同的扫描信号时，由于异形显示区与非异形显示区每行的像素个数不同会导致扫描线上的负载不同，从而导致显示的图像亮度不均，影响显示效果。
发明内容
基于此，本申请提供一种阵列基板和显示屏，能够解决由于异形显示区与非异形显示区每行的像素数量不同而导致显示图像亮度不均的技术问题。
本申请提供一种阵列基板，该阵列基板包括：
基板，所述基板上设置有显示区和非显示区，所述显示区包括阵列排布的像素，所述显示区包括异形显示区和非异形显示区；
至少一个第一栅极驱动单元，位于所述非显示区且通过第一引出线连接所述异形显示区中对应行上的像素，所述第一栅极驱动单元用于驱动对应行上的像素；以及
至少一个第二栅极驱动单元，位于所述非显示区且通过第二引出线连接所述非异形显示区中的对应行上的像素，所述第二栅极驱动单元用于驱动对应行上的像素；
其中，所述第一栅极驱动单元包括至少一个第一输出晶体管，所述第二栅极驱动单元包括至少一个第二输出晶体管，所述第一输出晶体管的宽长比小于所述第二输出晶体管的宽长比；且所述异形显示区对应的所述第一引出线的宽度和所述非异形显示区对应的所述第二引出线的宽度分别适应性地配置，以使所述异形显示区和所述非异形显示区的发光电流相等。
在其中一个实施例中，所述异形显示区每一行的像素数量均小于所述非异形显示区任一行的像素数量。
在其中一个实施例中，所述第一栅极驱动单元包括扫描驱动电路和/或发射驱动电路。
在其中一个实施例中，所述第二栅极驱动单元包括扫描驱动电路和/或发射驱动电路。
在其中一个实施例中，在所述异形显示区的至少两行像素的像素数量不同，且所述异形显示区中每一行像素所对应的所述第一输出晶体管的宽长比随着所在行的像素数量的减少而减小。
在其中一个实施例中，所述异形显示区包括至少一个子异形显示区，每个所述子异形显示区包括至少两行像素。
在其中一个实施例中，所述子异形显示区中每一行的像素数量均相同，所述子异形显示区中任一行像素对应的所述第一输出晶体管的宽长比相等。
在其中一个实施例中，所述每个子异形显示区中每一行像素对应的所述第一输出晶体管的宽长比与所述每个子异性显示区中每一行的像素数量呈正相关。
在其中一个实施例中，所述第一输出晶体管的栅极面积大于所述第二输出晶体管的栅极面积。
在其中一个实施例中，所述异形显示区包括多个子异形显示区，每个所述子异形显示区包括至少两行像素，不同子异形显示区中每一行像素对应的第一输出晶体管的宽长比与所述不同子异形显示区每一行的像素数量呈正相关。
在其中一个实施例中，所述阵列基板还包括分别位于所述异形显示区和所述非异形显示区的信号线，所述信号线在所述异形显示区贴合所述异形显示区的边缘集中弯曲走线；位于所述异形显示区的所述信号线用于连接所述第一输出晶体管并向所述异形显示区中对应行上的像素传递驱动信号，并补偿所述异形显示区中信号线的电阻与所述非异形显示区中信号线的电阻之间的电阻差异。
在其中一个实施例中，所述异形显示区的所述信号线的宽度与所述非异形显示区的所述信号线的宽度不等。
在其中一个实施例中，在所述异形显示区的所述信号线包括多段子信号线，所述多段子信号线中至少一段所述子信号线的宽度与所述非异形显示区的信号线的宽度不等。
在其中一个实施例中，所述信号线包括扫描信号线和发射控制信号线，其中所述扫描信号线用于连接扫描驱动电路和对应的像素并传递扫描信号，所述发射控制信号线用于连接发射驱动电路和对应的像素并传递发射控制信号。
在其中一个实施例中，所述阵列基板在所述非显示区设置有安装槽，所述异形显示区的所述信号线贴合所述安装槽的边缘集中弯曲走线。
在其中一个实施例中，所述第一输出晶体管的栅绝缘层的介电常数小于所述第二输出晶 体管的栅绝缘层的介电常数。
在其中一个实施例中，所述第一输出晶体管的栅绝缘层的厚度大于所述第二输出晶体管的栅绝缘层的厚度。
在其中一个实施例中，在所述第一输出晶体管的栅绝缘层表面形成第一掩膜层，所述第一掩膜层暴露出所述第一输出晶体管的栅绝缘层，通过以所述第一掩膜层为掩膜，对所述第一输出晶体管的栅绝缘层进行微刻蚀，以使所述第一输出晶体管的栅绝缘层的厚度小于所述第二输出晶体管的栅绝缘层的厚度。
在其中一个实施例中，所述第一输出晶体管具有半导体层、形成于所述半导体层上的第一栅绝缘层、形成在所述第一栅绝缘层上的第二栅绝缘层、及形成在所述第二栅绝缘层表面的第二掩膜层，所述第二掩膜层暴露出所述第一输出晶体管的第二栅绝缘层，通过以所述第二掩膜层为掩膜，去除所述第一输出晶体管的第二栅绝缘层，暴露出所述第一输出晶体管的第一栅绝缘层，以使所述第一输出晶体管的第一栅绝缘层和第二栅绝缘层的厚度和小于所述第二输出晶体管的栅绝缘层的厚度。
本申请还提供了一种显示屏，包括上述任一阵列基板。
本申请提供了阵列基板和显示屏，该阵列基板上对应的显示区包括异形显示区和非异形显示区，位于非显示区与异形显示区中的像素对应的第一栅极驱动单元，位于非显示区与非异形显示区中的像素对应的第二栅极驱动单元，第一栅极驱动单元的第一输出晶体管的宽长比小于第二栅极驱动单元的第二输出晶体管的宽长比，且通过配置异形显示区对应的第一引出线的宽度与非异形显示区对应的第二引出线的宽度，精确补偿了异形显示区和非异形显示区之间的差异，使得异形显示区和非异形显示区的发光电流相等，解决了异形显示区与非异形显示区二者因负载不同所导致的显示图像亮度不均的技术问题，改善了显示效果。
附图说明
图1a为本申请一个实施例中阵列基板的结构示意图；
图1b为本申请一个实施例中第一引出线与第二引出线的结构示意图；
图2为本申请另一个实施例中阵列基板的结构示意图；
图3为本申请一个实施例中的6T2C电路的电路图；
图4为本申请一个实施例中的13T3C像素电路的电路图；
图5为本申请一个实施例中的多个子异形显示区的结构示意图；
图6为本申请一个实施例中的第一输出晶体管的结构示意图；
图7为本申请一个实施例中的异形显示区中扫描信号线的示意图；
图8为本申请一个实施例中显示装置的示意图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施例的限制。
在一个实施例中，请参见图1a，本申请提供一种阵列基板，该阵列基板包括基板，基板上设置有显示区和非显示区110，显示区包括异形显示区120和非异形显示区130，该基板上对应的显示区包括阵列排布的像素140，异形显示区120每一行的像素数量均小于非异形显示区130任一行的像素数量。其中，驱动器在驱动异形显示区每行上的像素及非异形显示区每行上的像素时，由于异形显示区与非异形显示区每行上的像素数量不等，即负载不同，这会导致异形显示区和非异形显示区的显示效果不均匀。
可以理解的是，非异形显示区中的各行像素数量相等，非异形显示区一般是规则区域，例如，非异形显示区的形状为矩形。非异形显示区每行上的像素数量一般相等，则非异形显示区中的每行像素的发光特性保持一致。
请参见图1a，该阵列基板还包括至少一个第一栅极驱动单元150和至少一个第二栅极驱动单元160。第一栅极驱动单元150位于非显示区110。第一栅极驱动单元150通过第一引出线170连接异形显示区120中对应行上的像素140。第一栅极驱动单元150用于驱动所对应行上的像素140。第二栅极驱动单元160位于非显示区110。第二栅极驱动单元160通过第二引出线180连接非异形显示区130中对应行上的像素140。第二栅极驱动单元160用于驱动所对应行上的像素140。其中，第一栅极驱动单元150包括至少一个第一输出晶体管，第二栅极驱动单元160包括至少一个第二输出晶体管。第一输出晶体管和第二输出晶体管均包括栅极、源极和漏极，通过栅极的电压可以控制第一/第二输出晶体管的关断或者导通。第一输出晶体管的宽长比小于第二输出晶体管的宽长比。异形显示区120对应的第一引出线170的宽度与非异形显示区130对应的第二引出线180的宽度分别进行适应性的配置，以使异形显示区和非异形显示区的发光电流相等。其中，晶体管的宽长比指的是晶体管的导电沟道的宽与长的比值即W/L，其中W为晶体管的导电沟道的宽，L为晶体管的导电沟道的长。一般情况下，晶体管的宽长比越大，其驱动能力即带负载的能力越大，流经晶体管的驱动电流越大。
示例性地，请参见图1b，扫描信号线沿着第二方向延伸。第一引出线170与异形显示区120的扫描信号线连接。第二引出线180与非异形显示区130的扫描信号线连接。第一引出 线170的宽度指的是第一引出线170在第一方向上的尺寸W1，第二引出线180的宽度指的是第二引出线180在第一方向上的尺寸W2。其中，第一方向与第二方向相互垂直。可以理解的是，扫描信号线在第一方向上也具有一定的尺寸，记为扫描信号线的宽度，扫描信号线可以包括多段子扫描信号线，每段子扫描信号线在第一方向上同样具有一定的尺寸，记为子扫描信号线的宽度，在此不再赘述。
具体地，通过改变第一输出晶体管的宽长比不能精准地补偿异形显示区与非异形显示区之间的差异，所以，在减小第一输出晶体管的宽长比之后，第一栅极驱动单元的驱动能力依旧不能完全改善异形显示区120与非异形显示区130之间的显示效果不均匀的问题。可以在改变第一输出晶体管的宽长比的基础上进一步地适应性地配置第一引出线170的宽度与第二引出线180的宽度，比如通过适应性地配置使得第一引出线170的宽度可以等于第二引出线180的宽度，第一引出线170的宽度可以小于第二引出线180的宽度，或者第一引出线170的宽度可以大于第二引出线180的宽度，以实现精准补偿。那么，首先可以通过减小异形显示区120中第一输出晶体管的宽长比以降低异形显示区120中第一栅极驱动单元的驱动能力，其次可以通过适应性地配置异形显示区120中第一引出线170的宽度以相应地改变电容负载。结合使用减小第一输出晶体管的宽长比和适应性地调整第一引出线170的宽度两种方式，可以从第一栅极驱动单元的驱动能力及电容负载两个方面解决异形显示区120和非异形显示区130之间的显示效果不均匀的问题。
比如，当宽长比减小后的第一栅极驱动单元的驱动能力相对于异形显示区120的像素数量依旧较强时，可以增大异形显示区对应的第一引出线170的宽度，使得第一引出线170的宽度大于非异形显示区对应的第二引出线180的宽度以相应地增大异形显示区120的电容负载。当宽长比减小后的第一栅极驱动单元的驱动能力相对于异形显示区120的像素数量较弱时，可以减小异形显示区对应的第一引出线170的宽度，使得第一引出线170的宽度小于非异形显示区对应的第二引出线180的宽度，以相应地减小异形显示区120的电容负载。
对于仅通过减小第一输出晶体管的宽长比的方式，仿真结果如下表所示，通过降低第一输出晶体管的宽长比，使得异形显示区与非异形显示区的电流差异为0.27nA。在第一输出晶体管的宽长比改变前，异形显示区与非异形显示区的电流差异为5nA，则异形显示区与非异形显示区的亮度相差至少5个灰阶，特别是低灰阶时，异形显示区与非异形显示区之间的亮度不均会更加明显。
  改变前的电流(nA) 改变后的电流(nA)
异形显示区 181.84 177.49
非异形显示区 176.28 177.22
对于结合使用减小第一输出晶体管的宽长比和适应性地调整第一引出线的宽度两种方式，仿真结果如下表所示，通过降低第一输出晶体管的宽长比且适应性地调整第一引出线的宽度，异形显示区与非异形显示区的电流差异为0.08nA。因此，结合两种方式进行补偿后的电流差异比通过一种方式进行补偿后的电流差异更小，可以使得异形显示区与非异形显示区之间的亮度更均匀。
  改变前的电流(nA) 改变后的电流(nA)
异形显示区 181.84 177.30
非异形显示区 176.28 177.22
在本实施例中，通过减小异形显示区中第一输出晶体管的宽长比并合理配置异形显示区中第一引出线的宽度，可以降低异形显示区中第一栅极驱动单元的驱动能力并适当地进行电容补偿，使异形显示区和非异形显示区的发光电流相等，从而解决了异形显示区与非异形显示区之间因负载不同导致二者的显示的图像亮度不均的技术问题，提升了异形显示区与非异形显示区之间的亮度均一性。
在一个实施例中，第一栅极驱动单元和第二栅极驱动单元均为栅极驱动单元，栅极驱动单元包括扫描驱动电路和/或发射驱动电路。其中，栅极驱动单元可以仅包括扫描驱动电路，也可以仅包括发射驱动电路，还可以同时包括扫描驱动电路和发射驱动电路。扫描驱动电路，用于将扫描信号顺序地施加到像素。发射驱动电路，用于将发射控制信号施加到像素。
示例性地，请参见图2，栅极驱动单元包括扫描驱动电路210和发射驱动电路220。扫描驱动电路210通过扫描信号线S1至Sn连接矩阵形式排列的多个像素PX11至PXnm，像素PX11至PXnm也连接到发射控制信号线E1至Em，并通过发射控制信号线E1至Em连接发射驱动电路。其中，发射控制信号线E1至Em大致平行于扫描信号线S1至Sn。
示例性地，请参见图3,扫描驱动电路210为6T2C电路，包括晶体管M1、晶体管M2、晶体管M3、晶体管M4、晶体管M5、晶体管M6、电容C1及电容C2。其中，晶体管M5、晶体管M6为扫描驱动电路210的输出晶体管。晶体管M5、晶体管M6根据其栅极的电压导通或者关断。晶体管M5导通时，将时钟信号输入端SCK2的输入信号传输至扫描驱动电路210的输出端。晶体管M6导通时，将电源电压信号输入端VGH的输入信号传输至扫描驱动电路210的输出端。进一步地，请参见图1a及图3，异形显示区120的像素对应的第一输出 晶体管的宽长比小于非异形显示区130的像素对应的第二输出晶体管的宽长比。具体地，异形显示区120的像素对应的晶体管M5的宽长比小于非异形显示区130的像素对应的晶体管M5的宽长比。异形显示区120的像素对应的晶体管M6的宽长比小于非异形显示区130的像素对应的晶体管M6的宽长比。
示例性地，请参见图4，发射驱动电路220为13T3C电路，包括晶体管M1、晶体管M2、晶体管M3、晶体管M4、晶体管M5、晶体管M6、晶体管M7、晶体管M8、晶体管M9、晶体管M10、晶体管M11、晶体管M12、晶体管M13、电容C1、电容C2及电容C3。其中，晶体管M9、晶体管M10为发射驱动电路220的输出晶体管。晶体管M9、晶体管M10根据其栅极的电压导通或者关断。晶体管M9导通时，将电源电压信号输入端VGH的输入信号传输至发射驱动电路220的输出端，晶体管M10导通时，将电源电压信号输入端VGL的输入信号传输至发射驱动电路220的输出端。进一步地，请参见图1a及图4，异形显示区120的像素对应的第一输出晶体管的宽长比小于非异形显示区130的像素对应的第二输出晶体管的宽长比。具体地，异形显示区120的像素对应的晶体管M9的宽长比小于非异形显示区130的像素对应的晶体管M9的宽长比。异形显示区120的像素对应的晶体管M10的宽长比小于非异形显示区130的像素对应的晶体管M10的宽长比。
示例性的，请参见图1a、图2、图3及图4，阵列基板中的栅极驱动单元包括扫描驱动电路210和发射驱动电路220，可以改变扫描驱动电路210、发射驱动电路220中任一者或者两者对应的第一输出晶体管的宽长比，比如可以仅减小扫描驱动电路210中的晶体管M5及晶体管M6的宽长比，也可以仅减小发射驱动电路220中的晶体管M9及晶体管M10的宽长比，还可以同时减小扫描驱动电路210中的晶体管M5及晶体管M6的宽长比和发射驱动电路220中的晶体管M9及晶体管M10的宽长比。
可以理解的是，栅极驱动单元可以包括扫描驱动电路或发射驱动电路中的一者或同时包括扫描驱动电路和发射驱动电路。比如，栅极驱动单元可以仅包括扫描驱动电路，也可以同时包括扫描驱动电路和发光驱动电路。设计者可以根据实际情况对异形显示区对应的第一输出晶体管和非异形显示区对应的第二输出晶体管进行宽长比参数的差异化设计。
在本实施例中，通过减小扫描驱动电路、发射驱动电路中任一者或者两者对应的第一输出晶体管的宽长比，降低了扫描驱动电路或者发射驱动电路中任一者或者两者的驱动能力，解决了异形显示区和非异形显示区之间负载不均衡的问题，使得异形显示区和非异形显示区二者的显示效果均匀，改善了显示效果。
在一个实施例中，在异形显示区至少两行上的像素数量不同，且每一行像素所对应的第一输出晶体管的宽长比随着所在行的像素数量的减少而减小。其中，在异形显示区具有多行 像素，且至少两行上的像素数量不同。当异形显示区的每行上的像素数量减少时，为了使得异形显示区与非异形显示区的显示效果一致，异形显示区对应的栅极驱动单元的驱动能力应该减弱，则使异形显示区中每一行像素对应的第一输出晶体管的宽长比随着所在行的像素数量的减少而减小。通常情况下，驱动器逐行地驱动显示区的像素。然而，根据实际情况，驱动器可以逐列地驱动显示区的像素。驱动器在驱动异形显示区每列上的像素时，驱动器的负载与异形显示区每列上的像素数量相关。当异形显示区的每列上像素数量减少时，异形显示区对应的第一输出晶体管的宽长比可以在列方向上随着减小。在本实施例中，可以根据异形显示区中每行上的像素数量精确地设计不同宽长比的第一输出晶体管，解决异形显示区与非异形显示区二者的显示效果不均匀的技术问题。
在一个实施例中，异形显示区包括至少一个子异形显示区，每个子异形显示区包括至少两行像素，且每一行的像素数量均相同。每个子异形显示区内的第一输出晶体管的宽长比相等。
其中，异形显示区可以包括一个子异形显示区，异形显示区也可以包括多个子异形显示区，每个子异形显示区包括至少两行像素，且每一行的像素数量均相同。请参见图5，异形显示区包括第一子异形显示区510、第二子异形显示区520、第三子异形显示区530、和第四子异形显示区540。以第一子异形显示区510为例进行说明，第一子异形显示区510包括至少两行像素，且第一子异形显示区510对应的每行像素的数量是近似相等的，则第一子异形显示区510的第一输出晶体管的宽长比基本相等，且第一子异形显示区510中的任一行像素对应的第一输出晶体管的宽长比是相等的。同理可知第二子异形显示区520、第三子异形显示区530、第四子异形显示区540的第一输出晶体管的宽长比的情况，在此不再赘述。
此外，不同子异形显示区中的每一行的像素数量可以是不相等的。不同子异形显示区中每一行像素对应的第一输出晶体管的宽长比与所述不同子异形显示区每一行的像素数量呈正相关。例如，第一子异形显示区510中每一行的像素数量小于第三子异形显示区530中每一行的像素数量，则第一子异形显示区510对应的第一输出晶体管的宽长比小于第三子异形显示区530对应的第一输出晶体管的宽长比。
具体地，每个子异形显示区中的每一行的像素数量可以相等，也可以不相等。每个子异形显示区中像素数量不等的每一行像素对应的第一输出晶体管的宽长比也是不相等的，每一行像素对应的第一输出晶体管的宽长比与每个子异形显示区中每一行的像素数量呈正相关，即第一输出晶体管的宽长比随所在的每个子异形显示区中每一行的像素数量的减少而减小，随每个子异形显示区中每一行的像素数量的增加而增加。
本实施例中，通过将异形显示区划分为不同的子异形显示区，子异形显示区中每行的像 素数量看作近似相等，针对该子异形显示区设计第一输出晶体管，子异形显示区中每行像素对应的第一输出晶体管是相同的宽长比，这样可以使得阵列基板的版图布局简洁，并减少工艺的复杂性。
在一个实施例中，第一输出晶体管的栅极面积大于第二输出晶体管的栅极面积。其中，晶体管的栅极面积等于栅长和栅宽的乘积，近似等于是晶体管的导电沟道的宽与长的乘积即W*L。一般情况下，晶体管的导电沟道的宽与长的乘积越大，晶体管自身的寄生电容越大。具体地，在第一输出晶体管的宽长比小于第二输出晶体管的宽长比的前提条件下，近似等比例增加第一输出晶体管的宽和长以保持第一输出晶体管的宽长比不变，且同时增大第一输出晶体管的栅极面积，则第一输出晶体管的栅极面积大于第二输出晶体管的栅极面积。
在本实施例中，在第一输出晶体管的宽长比小于第二输出晶体管的宽长比的前提条件下,通过近似等比例增加第一输出晶体管的栅长和栅宽，保持第一输出晶体管的宽长比不变，增大第一输出晶体管的栅极与沟道层的交叠面积，相应地增大了电容负载，补偿了异形显示区因单行像素数目减少而导致的负载降低，解决了由于异形显示区和非异形显示区每行像素数量不同导致二者显示不均匀的技术问题。
在一个实施例中，阵列基板还包括分别位于异形显示区和非异形显示区的信号线。信号线在异形显示区贴合异形显示区的边缘集中弯曲走线。位于异形显示区的信号线用于连接第一输出晶体管并向异形显示区中对应行上的像素传递驱动信号，并补偿异形显示区中信号线的电阻与非异形显示区中信号线的电阻之间的电阻差异。
信号线包括扫描信号线和发射控制信号线。扫描信号线连接扫描驱动电路和对应的像素并传递扫描信号，发射控制信号线连接发射驱动电路和对应的像素并传递发射控制信号。阵列基板的非显示区设置有安装槽。安装槽的开口方向可以位于行方向上，也可以位于列方向上。本申请对安装槽的开口方向及具体位置不作限定。安装槽可以用于放置摄像头、听筒、指纹识别元件、虹膜识别元件等传感器。安装槽导致了异形显示区的产生，且异形显示区内的负载较少。为了保持异形显示区与非异形显示区的亮度均匀，等比例的增大第一输出晶体管的栅极面积。但是第一输出晶体管的栅极面积大于第二输出晶体管的栅极面积会导致第一输出晶体管的栅线电阻相对于第二输出晶体管的栅线电阻减小。在本实施例中，在异形显示区内，传递扫描信号的扫描信号线贴合异形显示区的边缘集中弯曲走线。位于异形显示区内的扫描信号线沿着异形显示区的边缘增加了扫描信号线的长度，相应地增大了异形显示区的扫描信号线的电阻，从而补偿异形显示区的扫描信号线的电阻与非异形显示区的扫描信号线的电阻的差异。
具体地，安装槽的形状可以是U型，也可以是弧形，还可以是圆形等。安装槽贯穿阵列 基板，且包括底面和位于底面两侧的侧面。安装槽在阵列基板上的垂直投影区域为开槽区，则开槽区包括底边和位于底边两侧的侧边。开槽区的底边可以沿着像素排列的行方向延伸，开槽区的底边也可以沿着像素排列的列方向延伸。比如，以扫描信号线为例进行说明，请参见图7，安装槽710是U型槽，安装槽710位于非显示区。安装槽在阵列基板上的垂直投影对应的区域为开槽区。开槽区包括底边713和分布于底边713两侧的侧边711及侧边712。异形显示区对应的扫描信号线沿着底边713、侧边711及侧边712布线。具体地，异形显示区中的扫描信号线包括第一子扫描信号线721、沿着侧边711的第二子扫描信号线722、沿着底边713的第三子扫描信号线723、沿着侧边712的第四子扫描信号线724及第五子扫描信号线725。
进一步地，异形显示区的信号线包括多段子信号线，多段子信号线中至少一段子信号线的宽度与非异形显示区的信号线的宽度不等。其中，信号线的宽度与信号线上的电阻有关。通过改变异形显示区的信号线的宽度，可以相应地改变信号线上的电阻，从而更加准确地对异形显示区的信号线上的电阻与非异形显示区的信号线上的电阻之间的电阻差异进行补偿。
在本实施例中，以扫描信号线为例进行说明，请参见图7，第一子扫描信号线721和第五子扫描信号线725的宽度可以等于第一输出晶体管的栅极的宽度。由于第一输出晶体管的栅极面积较大，则第一子扫描信号线721和第五子扫描信号线725的宽度较大，减小了扫描信号线上的电阻，但是可以通过调节第二子扫描信号线722、第三子扫描信号线723、第四子扫描信号线724的宽度实现电阻的精确补偿，比如减小第二子扫描信号线722、第三子扫描信号线723、第四子扫描信号线724的宽度，以相应地增大异形显示区的扫描信号线上的电阻。另外，第一子扫描信号线721和第五子扫描信号线725的部分区段的宽度可以不等于第一输出晶体管的栅极的宽度，则可以调节第一子扫描信号线721、第二子扫描信号线722、第三子扫描信号线723、第四子扫描信号线724及第五子扫描信号线725的宽度，比如，减小第一子扫描信号线721、第二子扫描信号线722、第三子扫描信号线723、第四子扫描信号线724及第五子扫描信号线725中至少一条扫描信号线的宽度。
在本实施例中，异形显示区中的扫描信号线沿着安装槽边沿布线，增大了异形显示区中扫描信号线的长度，增大了扫描信号线电阻，解决了由于异形显示区像素数量少引起的电阻不均衡的问题，实现对异形显示区中电阻的准确补偿。
在一个实施例中，请参见6，第一输出晶体管包括缓冲层610、位于缓冲层610上的半导体层(未标出)、位于半导体层上的栅绝缘层630、位于栅绝缘层630远离半导体层一侧的栅极640、位于栅极640上的间绝缘层650、位于间绝缘层650远离半导体层一侧的源漏金属层，半导体层包括源极621、漏极622和沟道623。源漏金属层包括源极金属引线661和漏极金属 引线662。第一输出晶体管的寄生电容与栅绝缘层的厚度及其介电常数有关，可以通过以下两种方式增大第一输出晶体管的寄生电容。
第一种方式：通过改变第一输出晶体管的栅绝缘层630的介电常数以改变第一输出晶体管的寄生电容。具体地，使第一输出晶体管的栅绝缘层的介电常数大于第二输出晶体管的栅绝缘层的介电常数。晶体管的寄生电容与晶体管的介电常数成正比，可以通过改变异形显示区对应第一驱动晶体管的栅绝缘层的材料，以使异形显示区对应的第一输出晶体管的栅绝缘层的介电常数大于非异形显示区对应的第二输出晶体管的栅绝缘层的介电常数。
第二种方式：通过减小异形显示区对应的栅绝缘层630的厚度以增加异形显示区对应的第一输出晶体管的寄生电容。具体地，使第一输出晶体管的栅绝缘层的厚度小于第二输出晶体管的栅绝缘层的厚度。在形成栅绝缘层时，可以通过以下两种方法改变栅绝缘层的厚度。
第一种，在栅绝缘层表面形成第一掩膜层，第一掩膜层暴露出异形显示区的栅绝缘层。以第一掩膜层为掩膜，对异形显示区的栅绝缘层进行微刻蚀，以减小异形显示区的栅绝缘层的厚度。
第二种，在半导体层上，形成第一栅绝缘层。在第一栅绝缘层上，形成第二栅绝缘层。在第二栅绝缘层表面形成第二掩膜层。第二掩膜层暴露出异形显示区的第二栅绝缘层。以第二掩膜层为掩膜，去除异形显示区的第二栅绝缘层，暴露出异形显示区的第一栅绝缘层。使得异形显示区对应的栅绝缘层的厚度小于非异形显示区对应的栅绝缘层的厚度。需要说明的是，在本实施例中，在增大异形显示区的栅绝缘层的介电常数或减薄栅绝缘层的厚度时，设计者要保证第一输出晶体管和第二输出晶体管的特性不变。
在一个实施例中，本申请提供一种显示屏，该显示屏包括上述任一实施例中的阵列基板。在本申请实施例中，显示屏的形状可以为包括圆形、椭圆形、多边形以及包括圆弧的图形中的至少一种的封闭图形。例如带R角、开槽或切口(notch)或圆形的显示屏。
在一个实施例中，本申请提供一种显示装置800，请参见图8，显示装置800包括如上述实施例中的显示屏810。
需要说明的是，异形显示区中的像素数量与非异形显示区中分布的像素数量不同，例如异形显示区中每一行的像素的数量，与非异形显示区中每一行的像素数量不同。可以理解，异形显示区与非异形显示区的区分是相对而言的。本申请中，将显示区中像素数量较少的部分区域，作为“异形显示区”；将显示区中像素数量较多的部分区域，作为“非异形显示区”。
另外，本申请实施例中所使用的术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将第一个元件与另一个元件区分。举例来说，在不脱离本申请范围的情况下，可以将第一输出晶体管称为第二输出晶体管，且类似地，可 将第二输出晶体管称为第一输出晶体管。第一输出晶体管和第二输出晶体管两者都是输出晶体管，但其不是同一输出晶体管。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括：
    基板，所述基板上设置有显示区和非显示区，所述显示区包括阵列排布的像素，所述显示区包括异形显示区和非异形显示区；
    至少一个第一栅极驱动单元，位于所述非显示区且通过第一引出线连接所述异形显示区中对应行上的像素，所述第一栅极驱动单元用于驱动所述对应行上的像素；以及
    至少一个第二栅极驱动单元，位于所述非显示区且通过第二引出线连接所述非异形显示区中的对应行上的像素，所述第二栅极驱动单元用于驱动所述对应行上的像素；
    其中，所述第一栅极驱动单元包括至少一个第一输出晶体管，所述第二栅极驱动单元包括至少一个第二输出晶体管，所述第一输出晶体管的宽长比小于所述第二输出晶体管的宽长比，且所述异形显示区对应的所述第一引出线的宽度和所述非异形显示区对应的所述第二引出线的宽度分别适应性地配置，以使所述异形显示区和所述非异形显示区的发光电流相等。
  2. 根据权利要求1所述的阵列基板，其中，所述异形显示区每一行的像素数量均小于所述非异形显示区任一行的像素数量。
  3. 根据权利要求1所述的阵列基板，其中，所述第一栅极驱动单元包括扫描驱动电路和/或发射驱动电路。
  4. 根据权利要求1所述的阵列基板，其中，所述第二栅极驱动单元包括扫描驱动电路和/或发射驱动电路。
  5. 根据权利要求1所述的阵列基板，其中，在所述异形显示区的至少两行像素的像素数量不同，且所述异形显示区中每一行像素所对应的所述第一输出晶体管的宽长比随着所在行的像素数量的减少而减小。
  6. 根据权利要求1所述的阵列基板，其中，所述异形显示区包括至少一个子异形显示区，每个所述子异形显示区包括至少两行像素。
  7. 根据权利要求6所述的阵列基板，所述子异形显示区中每一行的像素数量均相同，所述子异形显示区中任一行像素对应的所述第一输出晶体管的宽长比相等。
  8. 根据权利要求6所述的阵列基板，所述每个子异形显示区中每一行像素对应的所述第一输出晶体管的宽长比与所述每个子异性显示区中每一行的像素数量呈正相关。
  9. 根据权利要求1所述的阵列基板，其中，所述第一输出晶体管的栅极面积大于所述第二输出晶体管的栅极面积。
  10. 根据权利要求7所述的阵列基板，其中，所述异形显示区包括多个子异形显示区，每个所述子异形显示区包括至少两行像素，不同子异形显示区中每一行像素对应的第一输出 晶体管的宽长比与所述不同子异形显示区每一行的像素数量呈正相关。
  11. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括分别位于所述异形显示区和所述非异形显示区的信号线，所述信号线在所述异形显示区贴合所述异形显示区的边缘集中弯曲走线；
    位于所述异形显示区的所述信号线用于连接所述第一输出晶体管并向所述异形显示区中对应行上的像素传递驱动信号，并补偿所述异形显示区中所述信号线的电阻与所述非异形显示区中所述信号线的电阻之间的电阻差异。
  12. 根据权利要求11所述的阵列基板，其中，所述异形显示区的所述信号线的宽度与所述非异形显示区的所述信号线的宽度不等。
  13. 根据权利要求11所述的阵列基板，其中，在所述异形显示区的所述信号线包括多段子信号线，所述多段子信号线中至少一段所述子信号线的宽度与所述非异形显示区的所述信号线的宽度不等。
  14. 根据权利要求11所述的阵列基板，其中，所述信号线包括扫描信号线和发射控制信号线，其中所述扫描信号线用于连接扫描驱动电路和对应的像素并传递扫描信号，所述发射控制信号线用于连接发射驱动电路和对应的像素并传递发射控制信号。
  15. 根据权利要求11所述的阵列基板，其中，所述阵列基板在所述非显示区设置有安装槽，所述异形显示区的所述信号线贴合所述安装槽的边缘集中弯曲走线。
  16. 根据权利要求1所述的阵列基板，其中，所述第一输出晶体管的栅绝缘层的介电常数大于所述第二输出晶体管的栅绝缘层的介电常数。
  17. 根据权利要求1所述的阵列基板，其中，所述第一输出晶体管的栅绝缘层的厚度小于所述第二输出晶体管的栅绝缘层的厚度。
  18. 根据权利要求17所述的阵列基板，其中，在所述第一输出晶体管的栅绝缘层表面形成第一掩膜层，所述第一掩膜层暴露出所述第一输出晶体管的栅绝缘层，通过以所述第一掩膜层为掩膜，对所述第一输出晶体管的栅绝缘层进行微刻蚀，以使所述第一输出晶体管的栅绝缘层的厚度小于所述第二输出晶体管的栅绝缘层的厚度。
  19. 根据权利要求17所述的阵列基板，其中，所述第一输出晶体管具有半导体层、形成于所述半导体层上的第一栅绝缘层、形成在所述第一栅绝缘层上的第二栅绝缘层、及形成在所述第二栅绝缘层表面的第二掩膜层，所述第二掩膜层暴露出所述第一输出晶体管的第二栅绝缘层，通过以所述第二掩膜层为掩膜，去除所述第一输出晶体管的第二栅绝缘层，暴露出所述第一输出晶体管的第一栅绝缘层，以使所述第一输出晶体管的第一栅绝缘层和第二栅绝缘层的厚度和小于所述第二输出晶体管的栅绝缘层的厚度。
  20. 一种显示屏，其中，包括如权利要求1-19中任一项所述的阵列基板。
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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190213939A1 (en) * 2018-01-19 2019-07-11 Kunshan Go-Visionox Opto-Electronics Co., Ltd. Emission control circuit, emission control driver and display device
CN108447439B (zh) * 2018-05-14 2019-07-02 昆山国显光电有限公司 阵列基板、显示屏及显示装置
TWI674571B (zh) * 2018-08-28 2019-10-11 友達光電股份有限公司 顯示裝置及補償電容的操作方法
TWI673551B (zh) * 2018-09-20 2019-10-01 友達光電股份有限公司 陣列基板
CN109188751B (zh) * 2018-09-29 2021-11-05 武汉天马微电子有限公司 显示面板、显示装置以及显示面板的制作方法
CN109410761B (zh) * 2018-10-30 2021-04-30 武汉天马微电子有限公司 显示面板和显示装置
CN109410771B (zh) * 2018-10-31 2021-06-25 武汉天马微电子有限公司 显示面板和显示装置
CN109272955B (zh) * 2018-11-06 2021-02-12 信利半导体有限公司 Gip走线图处理方法和gip走线图处理装置
TWI703550B (zh) * 2018-11-07 2020-09-01 友達光電股份有限公司 顯示裝置及閘極驅動裝置
CN110599937B (zh) * 2018-11-07 2023-03-17 友达光电股份有限公司 显示装置及栅极驱动装置
CN111179792B (zh) * 2018-11-12 2021-05-07 重庆先进光电显示技术研究院 一种显示面板、检测方法及显示装置
CN109459900A (zh) * 2018-12-24 2019-03-12 信利半导体有限公司 像素阵列基板及显示设备
CN109637421A (zh) 2019-01-14 2019-04-16 京东方科技集团股份有限公司 栅极驱动电路以及显示基板
CN109637374B (zh) * 2019-01-29 2021-07-23 上海天马有机发光显示技术有限公司 显示面板和显示装置
CN109686243A (zh) * 2019-01-31 2019-04-26 上海天马有机发光显示技术有限公司 显示面板和显示装置
CN109935193B (zh) * 2019-04-25 2022-06-03 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、阵列基板、显示面板和装置
CN110989255A (zh) * 2019-12-11 2020-04-10 武汉天马微电子有限公司 一种显示面板及显示装置
CN111261640A (zh) * 2020-01-21 2020-06-09 京东方科技集团股份有限公司 一种显示面板及显示装置
CN111583865B (zh) * 2020-06-12 2021-11-26 京东方科技集团股份有限公司 显示面板、显示装置及开关器件的沟道宽长比的确定方法
CN111816112B (zh) * 2020-07-24 2022-04-08 昆山国显光电有限公司 显示面板的补偿参数确定方法及装置
CN112634807A (zh) * 2020-12-22 2021-04-09 昆山国显光电有限公司 栅极驱动电路、阵列基板和显示面板
CN114038423B (zh) * 2021-12-09 2023-03-21 京东方科技集团股份有限公司 显示面板及显示装置
CN114155814B (zh) * 2021-12-09 2022-12-06 武汉天马微电子有限公司 像素驱动电路及显示面板、显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060261752A1 (en) * 2005-05-18 2006-11-23 Samsung Electro-Mechanics Co., Ltd. DC-DC converter having protective function of over-voltage and over-current and led driving circuit using the same
US7411354B2 (en) * 2006-12-20 2008-08-12 Niko Semiconductor Co., Ltd. Feedback and protection circuit of liquid crystal display panel backlight apparatus
CN104715719A (zh) * 2013-12-16 2015-06-17 双叶电子工业株式会社 显示驱动装置、显示驱动方法及显示设备
CN106711180A (zh) * 2016-12-29 2017-05-24 上海天马有机发光显示技术有限公司 显示面板、显示装置及显示面板制作方法
CN108447439A (zh) * 2018-05-14 2018-08-24 昆山国显光电有限公司 阵列基板、显示屏及显示装置
CN108492775A (zh) * 2018-05-14 2018-09-04 昆山国显光电有限公司 阵列基板、显示屏及显示装置
CN208271541U (zh) * 2018-05-14 2018-12-21 昆山国显光电有限公司 阵列基板、显示屏及显示装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101779227B (zh) * 2007-10-24 2012-03-28 夏普株式会社 显示面板和显示装置
KR101975581B1 (ko) 2012-08-21 2019-09-11 삼성디스플레이 주식회사 발광 제어 구동부 및 그것을 포함하는 유기발광 표시장치
KR101962432B1 (ko) 2012-09-20 2019-03-27 삼성디스플레이 주식회사 스테이지 회로 및 이를 이용한 유기전계발광 표시장치
JP2015087474A (ja) * 2013-10-29 2015-05-07 パナソニック株式会社 表示パネル装置および電子機器
US9450581B2 (en) * 2014-09-30 2016-09-20 Semiconductor Energy Laboratory Co., Ltd. Logic circuit, semiconductor device, electronic component, and electronic device
JP6568755B2 (ja) * 2015-09-11 2019-08-28 株式会社ジャパンディスプレイ 表示装置
WO2018030207A1 (ja) * 2016-08-08 2018-02-15 シャープ株式会社 表示装置
CN107004392B (zh) * 2016-11-28 2019-11-05 上海云英谷科技有限公司 显示面板的分布式驱动
CN106710525B (zh) * 2017-01-06 2019-02-05 上海天马有机发光显示技术有限公司 有机发光显示面板及其驱动方法、有机发光显示装置
CN107611142B (zh) * 2017-09-11 2020-06-09 上海天马有机发光显示技术有限公司 显示面板及显示装置
CN107564452B (zh) * 2017-09-21 2020-08-18 信利（惠州）智能显示有限公司 显示面板
CN107887418B (zh) * 2017-10-19 2021-10-22 武汉天马微电子有限公司 一种显示面板及显示装置
CN107610645B (zh) * 2017-10-26 2020-04-28 上海天马有机发光显示技术有限公司 一种oled显示面板、其驱动方法及显示装置
CN107610636B (zh) * 2017-10-30 2021-02-02 武汉天马微电子有限公司 一种显示面板及显示装置
CN107784939A (zh) * 2017-10-31 2018-03-09 昆山国显光电有限公司 异形显示屏和集成异形显示屏的显示装置
CN107749247B (zh) * 2017-11-03 2019-09-27 武汉天马微电子有限公司 一种显示面板及显示装置
CN107742499B (zh) * 2017-11-30 2021-02-19 武汉天马微电子有限公司 一种异形显示面板及显示装置
CN107731153A (zh) * 2017-11-30 2018-02-23 武汉天马微电子有限公司 异形显示面板和异形显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060261752A1 (en) * 2005-05-18 2006-11-23 Samsung Electro-Mechanics Co., Ltd. DC-DC converter having protective function of over-voltage and over-current and led driving circuit using the same
US7411354B2 (en) * 2006-12-20 2008-08-12 Niko Semiconductor Co., Ltd. Feedback and protection circuit of liquid crystal display panel backlight apparatus
CN104715719A (zh) * 2013-12-16 2015-06-17 双叶电子工业株式会社 显示驱动装置、显示驱动方法及显示设备
CN106711180A (zh) * 2016-12-29 2017-05-24 上海天马有机发光显示技术有限公司 显示面板、显示装置及显示面板制作方法
CN108447439A (zh) * 2018-05-14 2018-08-24 昆山国显光电有限公司 阵列基板、显示屏及显示装置
CN108492775A (zh) * 2018-05-14 2018-09-04 昆山国显光电有限公司 阵列基板、显示屏及显示装置
CN208271541U (zh) * 2018-05-14 2018-12-21 昆山国显光电有限公司 阵列基板、显示屏及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3640927A4 *

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