WO2019218371A1 - 一种振荡器的集成电路 - Google Patents

一种振荡器的集成电路 Download PDF

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Publication number
WO2019218371A1
WO2019218371A1 PCT/CN2018/087578 CN2018087578W WO2019218371A1 WO 2019218371 A1 WO2019218371 A1 WO 2019218371A1 CN 2018087578 W CN2018087578 W CN 2018087578W WO 2019218371 A1 WO2019218371 A1 WO 2019218371A1
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Prior art keywords
integrated circuit
coil
oscillator
mos transistor
tail
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PCT/CN2018/087578
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English (en)
French (fr)
Inventor
胡诣哲
黄寿
斯里布莱隆·提拉硕特
斯塔谢夫斯基•罗伯特•博格丹
周盛华
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201880078141.1A priority Critical patent/CN111434030B/zh
Priority to PCT/CN2018/087578 priority patent/WO2019218371A1/zh
Publication of WO2019218371A1 publication Critical patent/WO2019218371A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
    • H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
    • H03B5/1215—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors

Definitions

  • the embodiments of the present application relate to the field of electronic technologies, and in particular, to an integrated circuit of an oscillator.
  • the oscillator has a wide range of applications.
  • the phase noise (PN) of the oscillator includes flicker phase noise (flicker PN) and thermal phase noise (thermal PN).
  • flicker phase noise and thermal phase noise are the main parameters for measuring the performance of the oscillator.
  • Oscillator with low phase noise has been the subject of long-term research.
  • the class B oscillator includes a main resonance composed of an inductor L0 and a capacitor C0. Cavity, a cross-coupling pair consisting of MOS transistors M1 and M2, consisting of a tail resonator L tail and a MOS transistor parasitic capacitance (represented by C M1 and C M2 in Figure 1), and a plurality of parallel capacitors.
  • a decoupling capacitor array located between the oscillator's power supply VDD and ground VSS.
  • the optimum phase noise of the above oscillator only occurs when the resonant frequency of the tail resonator is twice the free resonant frequency, and a slight change in the free resonant frequency will quickly deteriorate the phase noise.
  • the above oscillator often uses a single-turn inductor L0, but the actual common-mode loop includes a decoupling capacitor array. There is a large parasitic inductance in the decoupling capacitor array and the common mode current direction is difficult to determine, which leads to The phase noise of the oscillator is seriously degraded.
  • Embodiments of the present application provide an integrated circuit of an oscillator capable of achieving low phase noise requirements.
  • an integrated circuit for an oscillator comprising a transformer, a cross-coupling unit and a tail inductor unit; wherein the transformer comprises first and second coils intertwined with each other, the first coil and the second coil
  • the voltage terminals are each coupled to a power supply terminal (VDD)
  • the first coil includes a pair of first output terminals
  • the second coil includes a pair of second output terminals
  • the cross-coupling unit includes a first metal oxide semiconductor MOS transistor and a second MOS transistor
  • the gates of the first MOS transistor and the second MOS transistor are respectively connected to the pair of second output terminals, and the drains of the first MOS transistor and the second MOS transistor are respectively connected to the pair of first output terminals
  • the source of the tube and the second MOS transistor are each coupled to a ground terminal (VSS) by a tail inductor unit, wherein the tail inductor unit extends from the cross-coupled unit across the transformer toward a side on which the voltage terminal is
  • the tail inductor unit since the tail inductor unit is coupled to VSS, and the voltage terminal is coupled to VDD, the tail inductor unit extends from the cross-coupling unit to the voltage terminal, which is equivalent to pulling the oscillator circuit in the wiring.
  • the distance between the VDD terminal and the VSS terminal thereby reducing the parasitic inductance of the decoupling capacitance between the VDD and the VSS, avoiding the flicker phase noise up-regulation of the integrated circuit due to the uncertainty of the parasitic inductance
  • the problem makes the integrated circuit have lower phase noise.
  • the integrated circuit is disposed on the multilayer wiring layer, wherein the first coil and the second coil of the transformer may be disposed on one or more wiring layers, in order to zoom in
  • the distance between the VDD terminal and the VSS terminal of the circuit the tail inductance unit needs to pass through the projection of the other wiring layer through the first coil and the second coil, which is called "crossing the transformer".
  • crossing the transformer In order to reduce the parasitic inductance of the oscillator, the end of the tail inductor unit coupled to the ground end is naturally closer to the VDD end, and therefore, the "extending toward the side where the voltage terminal is located is extended. "only the direction of extension of the tail inductor unit is illustrated, and the extension distance of the tail inductor unit should not stop at the position of the voltage terminal.
  • the integrated circuit is provided with a plurality of parallel wiring layers, and a circuit path between a voltage end of the first coil and a VDD of the integrated circuit is a first path, and a second The circuit path between the voltage terminal of the coil and the VDD of the integrated circuit is a second path, at least a portion of the first path being in line with the projection of the tail inductor unit on the same wiring layer; at least a portion and the tail of the second path The projection of the inductive unit on the same wiring layer is in a straight line.
  • the transformer employs a top three-layer metal layout with low resistivity in the integrated circuit process to achieve a higher quality factor.
  • the tail inductor consists of a linear inductor consisting of a bottom metal stack that passes through the center of the transformer to ensure that the center of the oscillator is symmetrical without additional footprint.
  • the parasitic inductance between VDD and VSS of the integrated circuit can be reduced as much as possible.
  • the integrated circuit is provided with a plurality of parallel wiring layers, wherein a circuit path between a voltage terminal of the first coil and VDD is a first path, and a voltage end of the second coil
  • the circuit path between the VDD and the VDD is a second path.
  • a portion of the first path that is in contact with the first coil is in line with the projection of the tail inductor unit on the same wiring layer, and the second path is connected to the second coil.
  • a portion of the projection is in line with the projection of the tail inductor unit on the same wiring layer.
  • the first coil and the second coil are symmetrical about the tail inductance unit. Specifically, when the first coil, the second coil, and the tail inductor unit are all projected on a same plane, the first coil and the second coil are symmetric about the tail inductor unit on the plane of the projection. In the above possible implementation manner, the problem that the surrounding magnetic field excited by the tail inductance unit has inconsistent influence on both sides of the first coil and the second coil can be avoided.
  • the integrated circuit further includes a first capacitor and a second capacitor, wherein the pair of first outputs are further connected to the two ends of the first capacitor, and the pair of second outputs are further They are respectively connected to both ends of the second capacitor.
  • the ratio of the second capacitor to the first capacitor is greater than or equal to 2.
  • the first capacitor and the second capacitor may both be capacitor arrays.
  • a ratio of the second capacitor to the first capacitor is further less than or equal to 4.
  • the integrated circuit of the oscillator can have lower phase noise and a wider tuning range.
  • the integrated circuit comprises a dual core oscillator comprising two oscillators of identical structure and symmetrically arranged, the first of the two oscillators being combined.
  • the area of the integrated capacitor can be reduced, and at least half of the thermal noise of the passive device can be effectively reduced, thereby further reducing the phase of the integrated circuit. noise.
  • the integrated circuit is provided with a plurality of mutually parallel wiring layers, and the transformer, the cross-coupling unit and the tail inductor unit are respectively arranged on one or more wiring layers, and the plurality of wirings Vias are provided between the layers to connect the signal paths on the different wiring layers.
  • a terminal comprising at least a radio frequency device and an integrated circuit of the oscillator provided by the first aspect or any one of the possible implementations of the first aspect, the integrated circuit of the oscillator is used for
  • the radio frequency device provides a local carrier signal.
  • a base station comprising at least a transceiver and a phase locked loop circuit, the phase locked loop circuit comprising the integrated circuit of the oscillator provided by the first aspect or any one of the possible implementation manners of the first aspect
  • the integrated circuit of the oscillator is used to provide a local carrier signal to the transceiver.
  • Figure 1 is an integrated circuit of a Class B oscillator using tail cavity technology
  • FIG. 2 is a schematic structural diagram of an oscillator according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another oscillator according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another oscillator according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an integrated circuit of an oscillator according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of an integrated circuit of another oscillator according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of an oscillator according to an embodiment of the present disclosure.
  • the oscillator has a power terminal (VDD) and a ground terminal (VSS).
  • the oscillator includes: a transformer-based resonant unit 201, and a crossover.
  • the coupling unit 202 and the tail inductance unit 203 are connected to the oscillator.
  • the transformer-based resonant unit 201 is configured to generate an oscillating signal having a certain frequency; the cross-coupling unit 202 is configured to compensate the energy consumption of the transformer-based resonant unit 201 to cause the resonant unit 201 to output a stable oscillating signal; 203 is for reducing parasitic inductance between the VDD and the VSS.
  • the transformer-based resonance unit 201 includes: a transformer, a first capacitor C D and a second capacitor XC D ; the transformer includes a first coil and a second coil that are intertwined with each other, the first coil and the first coil The voltage ends of the two coils are connected to the power terminal VDD, the first coil includes a pair of first output ends, the pair of first output ends are respectively connected to the two ends of the first capacitor C D , and the second coil includes a pair The second output end is connected to the two ends of the second capacitor XC D respectively.
  • the ratio of the number of turns of the first coil to the second coil in the transformer is 1:2 as an example.
  • the cross-coupling unit 202 includes a first metal oxide semiconductor (MOS) transistor M3 and a second MOS transistor M4; the gates (gate, G) of the first MOS transistor M3 and the second MOS transistor M4 are respectively A pair of second output terminals are connected, and drains (drain, D) of the first MOS transistor M3 and the second MOS transistor M4 are respectively connected to the pair of first output terminals, the first MOS transistor M3 and the second MOS
  • the source (S) of the tube M4 is connected to the ground terminal (VSS) through the tail inductor unit.
  • the first MOS transistor M3 and the second MOS transistor M4 are both N-channel metal oxide semiconductor (NMOS) transistors.
  • the tail inductance unit 203 may be a coil or a metal wire, which only needs to have low resistance and overcurrent capability.
  • the tail inductor unit in the transformer-based oscillator can achieve secondary resonance without forming a tail cavity, thus saving tail resonance.
  • the space occupied by the cavity reduces the area of the integrated circuit corresponding to the oscillator.
  • the tail inductor unit 203 is a line inductor L tail , and in the wiring design, the line inductor L tail extends from the cross coupling unit across the transformer toward a side where the voltage terminal is located, thereby
  • the physical distance between the via provided in the wiring layer of the integrated circuit of the oscillator and the via of the VDD in the wiring layer is shortened at the end of the tail inductor unit. In this way, the physical distance between the via corresponding to the VDD and the via corresponding to the VSS in the integrated circuit of the oscillator can be made less than or equal to 10 um.
  • a decoupling capacitor 204 may be included between the VSS and the VDD.
  • the decoupling capacitor 204 is a capacitor C1.
  • the decoupling capacitor 204 may be a capacitor specially provided for the oscillator, or may be a capacitor in the other circuit of the VDD and the VSS together with the oscillator, that is, in the circuit structure of the oscillator.
  • the decoupling capacitor 204 may be included or may not be included in the embodiment of the present application.
  • the decoupling capacitor 204 is included in the circuit structure of the oscillator as an example.
  • the transformer-based resonant unit 201 adjusts the capacitance values of the first capacitor C D and the second capacitor XC D to cause the resonance unit 201 to resonate to generate an oscillating signal having a certain frequency.
  • the resonant unit 201 consumes a certain amount of energy during the resonance process, and the cross-coupling unit 202 is used to compensate the energy consumption of the resonant unit 201 so that the resonant unit 201 outputs a stable oscillating signal.
  • the transformer, the first capacitor C D and the second capacitor XC D constitute a resonance frequency of the resonance unit 201. It can be equivalent to a conventional RLC resonant network, which consumes energy during the oscillation process due to the presence of parasitic resistance.
  • the cross-coupling unit 202 can be equivalent to a "negative resistance" to provide energy to the network.
  • the oscillators in the embodiments of the present application all use the first capacitor C D and the second capacitor XC D as examples of the resonance unit 201, but in the prior art, there are many resonance units 201 that match the transformer output resonance frequency.
  • the implementation of the first capacitor C D and the second capacitor XC D should not constitute a limitation of the scope of the present application.
  • the flicker noise mainly causes the phase shift of the waveform at the rising and falling edges of V DS (the voltage difference between the drain and the source), and the direction of the phase shift is opposite to the rising edge and the falling edge, and the phase shift is the same.
  • V DS the voltage difference between the drain and the source
  • the flicker noise may cancel the phase shifts in one cycle and do not contribute phase noise.
  • the secondary resonance technique mainly makes the waveform symmetrical.
  • the VSS of the oscillator is sufficiently close to the VDD by the tail inductance unit 203 to reduce the physical distance between the VDD and the VSS, for example, to be less than or equal to 10 um, thereby
  • the parasitic inductance of the decoupling capacitor between the VDD and the VSS can be sufficiently reduced to be neglected, thereby avoiding the problem that the rising edge and the falling edge of the oscillation waveform are asymmetrical due to the uncertainty of the parasitic inductance. , in turn, avoids the problem of flicker phase noise up-regulation due to the asymmetry of its rising and falling edges, so that the oscillator has lower phase noise.
  • V SOURCE is connected to VSS through the tail inductor unit 203, which is equivalent to connecting a resistor between V SOURCE and VSS, so that the voltage of V SOURCE is not zero. According to the operating characteristics of the MOS transistor, when the voltage of V SOURCE is not zero.
  • the V SOURCE voltage follows the gate voltage change, which is equivalent to introducing a voltage following the gate at the source V SOURCE of the two MOS transistors, so that the turn-on size and the turn-on time of the MOS transistor are reduced, thereby reducing the MOS transistor. Thermal noise, which in turn reduces the phase noise of the oscillator.
  • the ratio of the second capacitor XC D to the first capacitor C D is greater than or equal to 2, that is, the capacitance value of the first capacitor C D is C D , and the capacitance value of the second capacitor XC D is X*C D , where Then X is a positive number greater than or equal to 2.
  • the ratio of the second capacitor XC D and the first capacitor C D is still less than or equal to 4, that is, 2 ⁇ X ⁇ 4.
  • the first capacitor and the second capacitor may each be a single capacitor or a capacitor array composed of multiple capacitors.
  • the oscillator can be operated in the passive gain saturation region, thereby suppressing the thermal noise 4kTg m of the MOS transistor from being converted into phase noise, and further The phase noise of the oscillator is reduced while ensuring that the oscillator has a wide tuning range.
  • the embodiment of the present application provides a transformer-based dual-core oscillator.
  • the transformer-based dual-core oscillator provided by the embodiment of the present application includes two oscillators of the same structure and symmetrically arranged (two oscillators are represented by 410 and 420 respectively in FIG. 4), and each oscillator is
  • the structure can be as shown in the structure of the oscillator shown in FIG. 3.
  • the first capacitor C D of the two oscillators can be combined, that is, the first capacitor C D of the two oscillators is realized by a capacitor of 2C D.
  • the combined capacitors can be generated using existing CMOS processes. For example, the combined capacitors can be implemented directly using the smallest MOM capacitor in the TSMC-16nm process.
  • the area of the integrated capacitor can be reduced by combining the first capacitors of the two resonating units of the dual-core oscillator into one capacitor, and in the dual-core oscillator, the two transformer-based resonating units are The parallel connection can effectively reduce half of the thermal noise of the passive device, thereby further reducing the phase noise of the oscillator.
  • the power consumption of the dual-core oscillator is doubled, so it can be applied to oscillators with strict phase noise requirements, in exchange for power consumption in exchange for oscillators with lower phase noise.
  • FIG. 5 is a schematic structural diagram of an integrated circuit of an oscillator according to an embodiment of the present disclosure.
  • the integrated circuit includes a transformer, a cross-coupling unit, and a tail inductor unit.
  • the transformer includes a first coil and a second coil wound with each other, the voltage ends of the first coil and the second coil are both coupled to the power supply terminal (VDD), the first coil includes a pair of first output ends, and the second coil includes a first coil a second output terminal;
  • the cross-coupling unit includes a first MOS transistor and a second MOS transistor, and the gates of the first MOS transistor and the second MOS transistor (V G+ and V G- in FIG. 5) and the pair respectively The second output terminal is connected, and the drains of the first MOS transistor and the second MOS transistor (V D+ and V D- in FIG. 5 ) are respectively connected to the pair of first output terminals, the first MOS transistor and the second MOS
  • the source of the tube (V SOURCE in Figure 5) is coupled to ground (VSS) through the tail inductor unit.
  • the integrated circuit When designing the wiring, the integrated circuit is provided with a plurality of mutually parallel wiring layers, and the transformer, the cross-coupling unit and the tail inductor unit are respectively arranged on one or more wiring layers, and a plurality of wiring layers are provided with via holes to connect Signal paths on different wiring layers.
  • the integrated circuit integrates the tail inductor unit and the partial structure of the transformer on different wiring layers by means of via holes, so that the tail inductor unit can pass over the transformer through other wiring layers, facing the voltage terminal. Extending on one side, where the tail inductance unit passes over the transformer, it can be a barrier of the circuit component (such as a coil) of the tail inductance unit bypassing the transformer on other wiring layers.
  • the tail inductance unit may be a coil or a metal wire, which only needs to have low resistance and overcurrent capability.
  • the flicker noise mainly causes the phase shift of the waveform at the rising edge and the falling edge of V DS (the voltage difference between the drain and the source), and the direction of the phase shift is opposite to the rising edge and the falling edge, and the phase shift is the same.
  • V DS the voltage difference between the drain and the source
  • the flicker noise may cancel the phase shifts in one cycle and do not contribute phase noise.
  • the secondary resonance technique mainly makes the waveform symmetrical.
  • the tail inductance unit extends from the cross-coupling unit across the transformer toward the side where the voltage terminal is located, so that the power supply terminal (VDD) can be narrowed on the plurality of wiring layers of the integrated circuit.
  • VDD power supply terminal
  • a physical distance from the ground (VSS) via vias on the plurality of wiring layers thereby reducing the parasitic inductance of the decoupling capacitance between VDD and VSS, so that it is negligible, solving the decoupling capacitor array
  • the transformer-designed oscillator saves the secondary resonance by eliminating the need for a tail cavity in the transformer-designed oscillator compared to the prior art single-turn inductor-based oscillator.
  • the space occupied by the tail cavity reduces the area of the integrated circuit.
  • the integrated circuit may be provided with a plurality of parallel wiring layers, the circuit path between the voltage terminal of the first coil and VDD is the first path, and the circuit path between the voltage terminal of the second coil and VDD is Two paths.
  • the first path is projected on the wiring layer where the tail inductor unit is located, in line with the tail inductor unit, and at least a portion of the second path is projected on the wiring layer where the tail inductor unit is located, and
  • the tail inductor units are in a straight line.
  • a portion of the first path that is in contact with the first coil and a projection of the tail inductor unit on the same wiring layer are in a straight line
  • a portion of the second path that is in contact with the second coil is in the same wiring layer as the tail inductor unit.
  • the projections on the line are in a straight line, that is, the starting portion in the first path and the starting portion in the second path are both in line with the projection of the tail inductor unit on the same wiring layer.
  • the integrated circuit includes a plurality of wiring layers in which the first and second coils and the tail inductance unit included in the transformer can be disposed in different wiring layers.
  • the first coil and the second coil are realized by a three-layer high-rise metal of low resistivity, and when the tail inductor unit is a metal line, the underlying metal stack is used.
  • the inductor unit is in a straight line
  • the physical distance between the via corresponding to VDD and the via corresponding to VSS can be reduced.
  • the starting part of the first path and the starting part of the second path are in line with the projection of the tail inductor unit on the same wiring layer, the corresponding via of VDD corresponding to VSS can be minimized. The physical distance between the holes.
  • a plurality of metal layers may be generally included, each metal layer corresponding to one wiring layer, and a metal layer close to the substrate of the integrated circuit may be referred to as an underlying metal layer, and the metal layer away from the substrate may be It is called a high-rise metal layer.
  • the metal layer in the integrated circuit may include 9 layers of metal and an aluminum layer (AP), and the 9 layers of metal may be M1 to M9 from low to high, and the three layers of high-rise metal may refer to M8, M9, and AP, the underlying metal stack may refer to M4 to M7 stacked to implement a tail inductor unit.
  • the transformer adopts a top three-layer metal layout with low resistivity in the integrated circuit process to obtain a higher quality factor.
  • the tail inductor unit is a linear inductor composed of a bottom metal stack, which extends along the central axis of the projection of the transformer on its wiring layer, and on the one hand ensures that the integrated circuit of the oscillator is projected with the tail inductor unit as axisymmetric. On the other hand, the tail inductor unit does not occupy an additional area.
  • the physical distance of VSS in the plurality of wiring layers in the integrated circuit and the via of VDD in the plurality of wiring layers is less than or equal to 10 um.
  • the physical distance between the via corresponding to VSS and the via corresponding to VDD is less than or equal to 10 um.
  • both the first coil and the second coil are symmetrical about the tail inductance unit.
  • the first coil and the second coil are both symmetric with respect to the tail inductance unit, and may mean that when the first coil, the second coil and the tail inductance unit are all projected on a same plane, on the plane of the projection, the first Both the coil and the second coil are symmetrical about the tail inductance unit.
  • both the first coil and the second coil are projected on the wiring layer where the tail inductance unit is located, the projection of the first coil on the wiring layer where the tail inductance unit is located, and the second coil in the tail inductance unit
  • the projections on the wiring layer are symmetric about the tail inductance unit.
  • both the second coil and the tail inductor unit are projected on the wiring layer where the first coil is located, the projections of the first coil and the second coil on the wiring layer where the first coil is located are all related to the tail inductance.
  • the projection of the unit on the wiring layer on which the first coil is located is symmetrical.
  • both the first coil and the tail inductor unit are projected on the wiring layer where the second coil is located, the projection of the first coil on the wiring layer where the second coil is located, and the second coil are all related to the tail inductance
  • the projection of the unit on the wiring layer on which the second coil is located is symmetrical.
  • the problem that the surrounding magnetic field excited by the tail inductor unit is inconsistent with respect to the two sides of the first coil and the two sides of the second coil can be avoided, thereby causing the tail inductor unit to be excited.
  • the influence of the surrounding magnetic field on both sides of the first coil and the two sides of the second coil can cancel each other, ensuring that the phase noise of the integrated circuit is not affected by the surrounding magnetic field excited by the tail inductor unit.
  • the integrated circuit further includes a first capacitor and a second capacitor, wherein the pair of first outputs are also respectively connected to two ends of the first capacitor, and the pair of second outputs are further respectively connected to the second capacitor The two ends are connected, and the ratio of the second capacitor to the first capacitor is greater than or equal to 2.
  • the ratio of the second capacitor to the first capacitor is further less than or equal to 4.
  • the first capacitor and the first coil, the second capacitor and the second coil may form a resonance for outputting an oscillating signal having a certain frequency.
  • the integrated circuit can work in the passive oscillator gain saturation region, thereby suppressing the thermal noise of the MOS transistor is converted into phase noise 4kTg m
  • the integrated circuit of the oscillator has low phase noise and a wide tuning range.
  • the VSS in the integrated circuit of the oscillator is sufficiently close to VDD through the tail inductance unit to reduce the physical distance between the VDD and the VSS, so that the VDD and the VDD can be sufficiently reduced.
  • the parasitic inductance of the decoupling capacitor between VSS is negligible to avoid the asymmetry of the rising and falling edges of the oscillating waveform due to the uncertainty of the parasitic inductance, thereby avoiding the rising edge and falling of the waveform.
  • the problem of flicker phase noise up-regulation along the asymmetry is such that the oscillator has lower phase noise.
  • the MOS transistor is fully turned on, which is equivalent to a resistor connected to the resonance unit, which contributes noise to the oscillator.
  • the tail inductor unit can introduce a voltage following the gate at the source V SOURCE of the MOS transistor, so that The turn-on size and turn-on time of the MOS transistor are reduced, thereby reducing the thermal noise of the MOS transistor, thereby reducing the phase noise of the oscillator.
  • the integrated circuit of the oscillator includes a dual core oscillator including two oscillators of the same structure and symmetrically arranged, and the first of the two oscillators is combined. That is, the structure of the integrated circuit of each oscillator in the dual-core oscillator is as shown in FIG. 5, and the first capacitor C D of the two oscillators is realized by a capacitance of 2C D.
  • the first capacitor C D is a passive device.
  • the existing CMOS process may not be able to be produced, or the capacitor component produced by the existing CMOS process has a poor quality factor, thereby affecting the oscillator. performance.
  • the combined capacitors can be generated using the existing CMOS process.
  • the combined capacitors can be directly implemented using the smallest MOM capacitor in the TSMC-16nm process. Thereby, the area of the integrated capacitor can be reduced, and the thermal noise of half of the passive device can be effectively reduced, thereby further reducing the phase noise of the integrated circuit of the oscillator.
  • a decoupling capacitor C1 may be connected between VSS and VDD of each oscillator, and the decoupling capacitor C1 may be specialized.
  • the capacitance set for the oscillator may also be the capacitance in the other circuit of the VDD and the VSS together with the oscillator, which is not shown in FIG. 5 and FIG. 6, and may be specifically referred to in FIG. 3 and FIG. description.
  • each MOS transistor in any embodiment or the accompanying drawings may be a single MOS transistor that satisfies the required startup gain or the required on-current. Or a MOS tube combination that needs to meet a required starting gain or a required on-current according to a plurality of MOS tubes connected in parallel, that is, a sum of starting gains corresponding to each of the plurality of MOS tubes is greater than or It is equal to the required starting gain; each capacitor in the embodiment of the present application may be a capacitor that satisfies a required capacitance value, or a capacitor combination that is composed of multiple capacitors in parallel or in series to satisfy a required capacitance value, that is, The capacitance value of the plurality of capacitors in series or in parallel is equal to the required capacitance value; each inductor in the embodiment of the present application may be an inductor that satisfies the required inductance value, or may be connected by multiple inductors in series or
  • the embodiment of the present application further provides a terminal, where the terminal includes at least a radio frequency device and an integrated circuit of an oscillator provided by the embodiment of the present application, and the integrated circuit of the oscillator is used to provide a local carrier signal for the radio frequency device.
  • the radio frequency device is used in any one or combination of the following: a cellular mobile communication module in a terminal, a Bluetooth module, a Wireless Fidelity (WIFI) module, or any device that requires a local carrier signal.
  • the radio frequency device in the terminal may be a Bluetooth module and a WIFI module, or may be a Bluetooth module or a WIFI module.
  • the embodiment of the present application further provides a base station, where the base station includes at least a transceiver and a phase-locked loop circuit, where the phase-locked loop circuit includes an integrated circuit of an oscillator provided by an embodiment of the present application, and an integrated circuit of the oscillator is used for the
  • the transceiver of the base station provides a local carrier signal.
  • the foregoing terminal and the base station are only the products of the integrated circuit to which the oscillator provided by the embodiment of the present application is applied, and the configuration of the integrated circuit of the oscillator provided by the embodiment of the present application is not limited.
  • the integrated circuit of the provided oscillator can be used in any low noise performance requirements scenario, as well as in any product with low noise performance requirements.

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  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

本申请实施例提供一种振荡器的集成电路，涉及电子技术领域，用于降低振荡器的集成电路的相位噪声。该集成电路包括变压器、交叉耦合单元和尾电感单元；其中，变压器包括互相缠绕的第一线圈和第二线圈，第一线圈和第二线圈的电压端均耦合至电源端（VDD），第一线圈包括一对第一输出端，第二线圈包括一对第二输出端，交叉耦合单元包括第一MOS管和第二MOS管，第一MOS管和第二MOS管的栅极分别与一对第二输出端相接，第一MOS管和第二MOS管的漏极分别与一对第一输出端相接，第一MOS管和第二MOS管的源极均通过尾电感单元耦合至地端（VSS），其中，尾电感单元自交叉耦合单元越过变压器，朝向电压端所处的一侧延伸。

Description

一种振荡器的集成电路 技术领域
本申请实施例涉及电子技术领域，尤其涉及一种振荡器的集成电路。
背景技术
振荡器作为电子系统的重要单元之一，其应用范围非常广泛。通常振荡器的相位噪声(phase noise，PN)包括闪烁相位噪声(flicker PN)和热相位噪声(thermal PN)。闪烁相位噪声和热相位噪声是衡量振荡器性能的主要参数，具有低相位噪声的振荡器一直是被长期研究的课题。
现有技术中，如图1所示，提供一种采用尾谐振腔技术的B类(class-B)振荡器的集成电路，该B类振荡器包括：由电感L0和电容C0组成的主谐振腔，由MOS管M1和M2组成的交叉耦合对，由尾电感L tail和MOS管寄生电容(图1中以C M1和C M2表示)组成的尾谐振腔，以及由多个并联的电容组成的位于振荡器的电源VDD和地VSS之间的去耦合电容阵列。上述B类振荡器只要将尾谐振调谐到两倍的振荡器的自由振荡频率，则该振荡器的闪烁相位噪声和热相位噪声都会大幅度降低。
上述振荡器最佳的相噪点仅仅发生在尾部谐振腔的谐振频率是自由谐振频率的两倍，自由谐振频率稍微的变化将很快恶化相位噪声。另外，上述振荡器常采用的是单圈电感L0，但是其实际共模回路中包含了去耦合电容阵列，去耦合电容阵列中存在较大的寄生电感且共模电流方向难以确定，这些会导致振荡器的相位噪声严重恶化。
发明内容
本申请实施例提供一种振荡器的集成电路，能够达到低相位噪声的要求。
第一方面，提供一种振荡器的集成电路，该集成电路包括变压器、交叉耦合单元和尾电感单元；其中，变压器包括互相缠绕的第一线圈和第二线圈，第一线圈和第二线圈的电压端均耦合至电源端(VDD)，第一线圈包括一对第一输出端，第二线圈包括一对第二输出端，交叉耦合单元包括第一金属氧化物半导体MOS管和第二MOS管，第一MOS管和第二MOS管的栅极分别与一对第二输出端相接，第一MOS管和第二MOS管的漏极分别与一对第一输出端相接，第一MOS管和第二MOS管的源极均通过尾电感单元耦合至地端(VSS)，其中，尾电感单元自交叉耦合单元越过所述变压器，朝向所述电压端所处的一侧延伸。上述技术方案中，由于尾电感单元与VSS相耦合，而电压端与VDD相耦合，尾电感单元从所述交叉耦合单元向所述电压端延伸，这相当于在布线中拉近了振荡器电路的VDD端和VSS端之间的距离，从而减小所述VDD与所述VSS间的去耦合电容的寄生电感，避免因为寄生电感的不确定性，而导致该集成电路的闪烁相位噪声上调的问题，进而使该集成电路具有较低的相位噪声。在可能的实现方式中，所述集成电路设置在多层布线层上，其中，所述变压器的第一线圈和第二线圈，可以设置在一个或多个布线层上，为了拉近所述振荡器电路的VDD端和VSS端的距离，尾电感单元需要通过其他布线层穿过所述第一线圈和第二线圈的投影，这就是所谓的“越过所述变压器”。而为了减小所述振荡器的寄生电感，所述 尾电感单元的与地端耦合的一端自然越靠近所述VDD端越好，因此，所述“朝向所述电压端所处的一侧延伸”仅仅是说明了尾电感单元的延伸方向，而尾电感单元的延伸距离不应止于所述电压端的位置。
在第一方面的一种可能的实现方式中，该集成电路设置有相互平行的多层布线层，第一线圈的电压端与该集成电路的VDD之间的电路路径为第一路径，第二线圈的电压端与该集成电路的VDD之间的电路路径为第二路径，第一路径的至少一部分与尾电感单元在同一布线层上的投影处于一条直线上；第二路径的至少一部分与尾电感单元在同一布线层上的投影处于一条直线上。可选地，变压器采用集成电路工艺中具有低电阻率的顶三层金属布局，以获得较高的品质因数。尾电感由底层金属叠层构成的线型电感，它从变压器的中心穿过，保证振荡器的中心对称，而不额外占用面积。上述可能的实现方式中，可以尽可能地缩小该集成电路的VDD与VSS间的寄生电感。
在第一方面的一种可能的实现方式中，该集成电路设置有相互平行的多层布线层，第一线圈的电压端与VDD之间的电路路径为第一路径，第二线圈的电压端与VDD之间的电路路径为第二路径，第一路径中与第一线圈相接的一部分与尾电感单元在同一布线层上的投影处于一条直线上，第二路径中与第二线圈相接的一部分与尾电感单元在同一布线层上的投影处于一条直线上。
在第一方面的一种可能的实现方式中，第一线圈和第二线圈关于尾电感单元对称。具体可以是指将第一线圈、第二线圈和尾电感单元均投影在一个相同的平面上时，在该投影的平面上，第一线圈和第二线圈均关于尾电感单元对称。上述可能的实现方式中，可以避免尾电感单元激发的周围磁场对于第一线圈和第二线圈两侧影响不一致的问题。
在第一方面的一种可能的实现方式中，该集成电路还包括第一电容和第二电容，一对第一输出端还分别与第一电容的两端连接，一对第二输出端还分别与第二电容的两端连接。
在可能的实现方式中，所述使得第二电容与第一电容的比值大于或等于2。在实际应用中，第一电容和第二电容可以为均为电容阵列。上述可能的实现方式中，通过设置第二电容和第一电容的比值，可以使该振荡器的集成电路工作在被动增益饱和区，从而抑制MOS管的热噪声转换为相位噪声，进一步减小该集成电路的相位噪声，同时具有较宽的调谐范围。
在第一方面的一种可能的实现方式中，第二电容与第一电容的比值还小于或等于4。上述可能的实现方式中，通过设置第二电容和第一电容的比值，可以使该振荡器的集成的电路具有较低的相位噪声、以及较宽的调谐范围。
在第一方面的一种可能的实现方式中，该集成电路包括双核振荡器，双核振荡器包括结构相同且对称设置的两个振荡器，两个振荡器中的第一电容合并设置。上述可能的实现方式中，通过将双核振荡器的中的第一电容合并为一个电容，可以减小集成电容的面积，同时可以有效降低被动器件的一半热噪声，进而进一步降低该集成电路的相位噪声。
在第一方面的一种可能的实现方式中，该集成电路设置有多个相互平行的布线层，变压器，交叉耦合单元和尾电感单元分别排布在一个或多个布线层上，多个布线层间 设有过孔以连接不同布线层上的信号路径。
第二方面，提供一种终端，该终端至少包括射频装置以及如第一方面或第一方面的任意一种可能的实现方式所提供的振荡器的集成电路，该振荡器的集成电路用于为所述射频装置提供本地载波信号。
第三方面，提供一种基站，该基站至少包括收发机及锁相环电路，锁相环电路包括如第一方面或第一方面的任意一种可能的实现方式所提供的振荡器的集成电路，该振荡器的集成电路用于为收发机提供本地载波信号。
附图说明
图1为一种采用尾谐振腔技术的B类振荡器的集成电路；
图2为本申请实施例提供的一种振荡器的结构示意图；
图3为本申请实施例提供的另一种振荡器的结构示意图；
图4为本申请实施例提供的又一种振荡器的结构示意图；
图5为本申请实施例提供的一种振荡器的集成电路的结构示意图；
图6为本申请实施例提供的另一种振荡器的集成电路的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。其中，在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和次序进行限定。
图2为本申请实施例提供的一种振荡器的结构示意图，参见图2，该振荡器具有电源端(VDD)和地端(VSS)，该振荡器包括：基于变压器的谐振单元201、交叉耦合单元202和尾电感单元203。
其中，基于变压器的谐振单元201用于产生具有一定频率的振荡信号；交叉耦合单元202，用于补偿基于变压器的谐振单元201的能量消耗，以使谐振单元201输出稳定的振荡信号；尾电感单元203用于降低所述VDD与所述VSS间的寄生电感。
具体地，如图3所示，基于变压器的谐振单元201包括：变压器、第一电容C D和第二电容XC D；该变压器包括相互缠绕的第一线圈和第二线圈，第一线圈和第二线圈的电压端均接所述电源端VDD，第一线圈包括一对第一输出端，所述一对第一输出端分别与第一电容C D的两端连接，第二线圈包括一对第二输出端，所述一对第二输出端分别与第二电容XC D的两端连接。图3中以变压器中第一线圈与第二线圈的圈数比值为1：2为例进行说明。
交叉耦合单元202包括第一金属氧化物半导体(metal oxide semiconductor，MOS)管M3和第二MOS管M4；第一MOS管M3和第二MOS管M4的栅极(gate，G)分别与所述一对第二输出端相接，第一MOS管M3和第二MOS管M4的漏极(drain，D)分别与所述一对第一输出端相接，第一MOS管M3和第二MOS管M4的源极(source，S)均通过所述尾电感单元接所述地端(VSS)。可选地，第一MOS管M3和第二MOS管M4均为N型沟道金属氧化物半导体(negative channel metal oxide semiconductor，NMOS)管。可选地，尾电感单元203可以是一个线圈，也可以是一 根金属线，其只需具有低电阻和过电流能力即可。
基于变压器设计的振荡器与现有技术中基于单圈电感的振荡器相比，基于变压器设计的振荡器中的尾电感单元无需形成尾部谐振腔，即可实现二次谐振，从而节省了尾部谐振腔占用的空间，减小了振荡器对应的集成电路的面积。
在可选择的实施例中，尾电感单元203为线型电感L tail，在布线设计中，该线型电感L tail自交叉耦合单元越过变压器，朝向所述电压端所处的一侧延伸，从而缩短设置于所述尾电感单元末端的所述VSS在振荡器的集成电路的布线层中的过孔与所述VDD在所述布线层中的过孔之间的物理距离。通过这种方式，可以使得所述振荡器的集成电路中所述VDD对应的过孔与所述VSS对应的过孔之间的物理距离小于或等于10um。
在图3所示的振荡器中，在所述VSS和所述VDD之间还可以包括一个去耦合电容204，比如，去耦合电容204为电容C1。需要说明的是，去耦合电容204可以是专门为该振荡器设置的电容，也可以是与该振荡器共同所述VDD和所述VSS的其他电路中的电容，即该振荡器的电路结构中可以包括去耦合电容204，也可以不包括去耦合电容204，本申请实施例对此不做具体限定，图3中仅以该振荡器的电路结构中包括去耦合电容204为例进行说明。
其中，振荡器在产生振荡信号的过程中，基于变压器的谐振单元201通过调节第一电容C D和第二电容XC D的电容值，以使谐振单元201发生谐振，产生具有一定频率的振荡信号，谐振单元201在谐振过程中会消耗一定的能量，交叉耦合单元202用于补偿谐振单元201的能量消耗，以使谐振单元201输出稳定的振荡信号。
具体地，变压器、第一电容C D及第二电容XC D构成谐振单元201输出谐振频率。它可以等效为传统的RLC谐振网络，由于有寄生电阻的存在，该谐振单元201在振荡过程消耗能量。为了形成稳定的谐振，交叉耦合单元202可以等效为“负电阻”，为该网络提供能量。需要注意的是，本申请实施例中的振荡器均以第一电容C D和第二电容XC D作为谐振单元201的示例，但在现有技术中配合变压器输出谐振频率的谐振单元201有多种实现方案，第一电容C D和第二电容XC D的设计不应构成了本申请保护范围的限定。
另外，闪烁噪声主要在V DS(漏极与源极的电压差)的上升沿和下降沿造成波形的相位偏移，相位偏移的方向在上升沿和下降沿相反，而相位偏移的大小取决于上升沿和下降沿期间，闪烁噪声的强度和波形的斜率。如果，振荡器波形上升沿和下降沿对称，则闪烁噪声有可能在一个周期内造成的相位偏移相互抵消，不贡献相位噪声。二次谐振技术，主要是使得波形对称。
假设V DS的上升沿的斜率大于下降沿的斜率，即：同样大小的闪烁噪声，在上升沿引入的相移大于下降沿造成的相反的相移(净相位移不为0)，那么，闪烁噪声在一个周期内转化为相位噪声。然而，闪烁噪声的强度在一个周期内的幅度变化，主要取决于V GS(栅极与源极的电压差)。通过引入V GS和V DS相位偏移，可以使得上升沿闪烁噪声强度小，而下降沿闪烁噪声强度大。最终使得，一个周期净相移为0，闪烁噪声不能转换相位噪声。
在本申请实施例中，通过尾电感单元203将该振荡器的所述VSS充分接近所述 VDD，以缩小所述VDD与所述VSS间的物理距离，比如，使其小于或等于10um，从而可以充分减小所述VDD与所述VSS间的去耦合电容的寄生电感，以使其忽略不计，从而避免因为寄生电感的不确定性，而导致振荡波形的上升沿和下降沿不对称的问题，进而避免因为其波形上升沿和下降沿不对称而造成的闪烁相位噪声上调的问题，以使该振荡器具有较低的相位噪声。
另外，在振荡过程中，交叉耦合单元202中的第一MOS管M3和第二MOS管M4会完全开启，相当于电阻接入谐振单元，对振荡器贡献噪声，由于两个MOS管的源极V SOURCE通过所述尾电感单元203接VSS，即相当于在V SOURCE与VSS间接入一个电阻，使得V SOURCE的电压不为零，根据MOS管的工作特性，当V SOURCE的电压不为零时，其V SOURCE电压跟随栅极电压变化，即相当于在两个MOS管的源极V SOURCE引入一个追随栅极的电压，使得MOS管的开启大小和开启时间都减小，从而减小MOS管的热噪声，进而减小该振荡器的相位噪声。
进一步地，第二电容XC D和第一电容C D的比值大于或者等于2，即第一电容C D的电容值为C D，第二电容XC D的电容值为X*C D，其中，则X为大于或等于2的正数。可选地，第二电容XC D和第一电容C D的比值还小于或者等于4，即2≤X≤4。
在实际应用中，第一电容和第二电容可以均为单电容，或者由多电容组成的电容阵列。
在本申请实施例中，通过设置第二电容XC D和第一电容C D的比值，可以使该振荡器工作在被动增益饱和区，从而抑制MOS管的热噪声4kTg m转换为相位噪声，进一步减小该振荡器的相位噪声，同时保证该振荡器具有较宽的调谐范围。
进一步地，在标准CMOS工艺中，一般没有极厚金属(ultra-thick metal)，这将进一步限制被动器件(也可以称为无源器件)的品质因数。比如，图3所示的振荡器中第一电容C D为被动器件，当其电容值较小时，现有CMOS工艺可能无法生产，或者以现有CMOS工艺生产的电容器件其品质因数较差，从而影响振荡器的性能。为解决这一问题，本申请实施例提供了一种基于变压器的双核振荡器。
如图4所示，本申请实施例提供的基于变压器的双核振荡器包括两个结构相同且对称设置的振荡器(图4中以410和420分别表示两个振荡器)，每个振荡器的结构可以如图3所示的振荡器的结构，两个振荡器中的第一电容C D可以合并设置，即将两个振荡器中的第一电容C D通过一个电容为2C D来实现。合并设置后的电容可以采用现有的CMOS工艺来生成，比如，合并后的电容可以直接采用TSMC-16nm工艺中最小的MOM电容来实现。
在本申请实施例中，通过将双核振荡器的两个谐振单元中的第一电容合并为一个电容，可以减小集成电容的面积，同时在双核振荡器中，通过两个基于变压器的谐振单元的并联，可以有效降低被动器件的一半热噪声，进而进一步降低振荡器的相位噪声。此时，该双核振荡器的功耗会加倍，因此，可以将其应用在对相位噪声要求比较严格的振荡器中，以牺牲功耗来换取具有更低相位噪声的振荡器。
图5为本申请实施例提供的一种振荡器的集成电路的结构示意图，参见图5，该集成电路包括变压器、交叉耦合单元和尾电感单元。
其中，变压器包括相互缠绕的第一线圈和第二线圈，第一线圈和第二线圈的电压 端均耦合至电源端(VDD)，第一线圈包括一对第一输出端，第二线圈包括一对第二输出端；交叉耦合单元包括第一MOS管和第二MOS管，第一MOS管和第二MOS管的栅极(图5中的V G+和V G-)分别与所述一对第二输出端连接，第一MOS管和第二MOS管的漏极(图5中的V D+和V D-)分别与所述一对第一输出端连接，第一MOS管和第二MOS管的源极(图5中的V SOURCE)均通过尾电感单元耦合至地端(VSS)。
在设计布线时，该集成电路设置有多个相互平行的布线层，变压器，交叉耦合单元和尾电感单元分别排布在一个或多个布线层上，多个布线层间设有过孔以连接不同布线层上的信号路径。通过过孔的方式在集成电路将尾电感单元与变压器的部分结构设计在不同的布线层上，从而使得所述尾电感单元能够通过其他布线层越过所述变压器，朝向所述电压端所处的一侧延伸，这里的尾电感单元越过变压器，可以是指尾电感单元在其他布线层上绕过变压器的电路器件(比如线圈)的阻挡。
可选地，尾电感单元可以是一个线圈，也可以是一根金属线，其只需具有低电阻和过电流能力即可。
其中，闪烁噪声主要在V DS(漏极与源极的电压差)的上升沿和下降沿造成波形的相位偏移，相位偏移的方向在上升沿和下降沿相反，而相位偏移的大小取决于上升沿和下降沿期间，闪烁噪声的强度和波形的斜率。如果，振荡器波形上升沿和下降沿对称，则闪烁噪声有可能在一个周期内造成的相位偏移相互抵消，不贡献相位噪声。二次谐振技术，主要是使得波形对称。
假设V DS的上升沿的斜率大于下降沿的斜率，即：同样大小的闪烁噪声，在上升沿引入的相移大于下降沿造成的相反的相移(净相位移不为0)，那么，闪烁噪声在一个周期内转化为相位噪声。然而，闪烁噪声的强度在一个周期内的幅度变化，主要取决于V GS(栅极与源极的电压差)。通过引入V GS和V DS相位偏移，可以使得上升沿闪烁噪声强度小，而下降沿闪烁噪声强度大。最终使得，一个周期净相移为0，闪烁噪声不能转换相位噪声。
在本申请实施例中，尾电感单元自交叉耦合单元越过变压器，朝向所述电压端所处的一侧延伸，可以缩小电源端(VDD)在该集成电路的多个布线层上的过孔，与地端(VSS)在所述多个布线层上的过孔之间的物理距离，从而减小VDD与VSS间的去耦合电容的寄生电感，以使其忽略不计，解决去耦合电容阵列中难以准确仿真的分布式寄生电感导致的振荡器闪烁噪声上调问题，以使该集成电路具有较低的相位噪声。
此外，基于变压器设计的振荡器与现有技术中基于单圈电感的振荡器相比，基于变压器设计的振荡器中的尾电感单元无需形成尾部谐振腔，即可实现二次谐振，从而节省了尾部谐振腔占用的空间，减小了该集成电路的面积。
进一步地，该集成电路可以设置有相互平行的多层布线层，第一线圈的电压端与VDD之间的电路路径为第一路径，第二线圈的电压端与VDD之间的电路路径为第二路径。
其中，第一路径的至少一部分在尾电感单元所处的布线层上的投影，与尾电感单元处于一条直线上，第二路径的至少一部分在尾电感单元所处的布线层上的投影，与尾电感单元处于一条直线上。或者，第一路径中与第一线圈相接的一部分与尾电感单元在同一布线层上的投影处于一条直线上，第二路径中与第二线圈相接的一部分与尾 电感单元在同一布线层上的投影处于一条直线上，即保证第一路径中的起始部分和第二路径中起始部分均与尾电感单元在同一布线层上的投影处于一条直线上。
在实际应用中，该集成电路包括多层布线层，该集成电路中变压器包括的第一线圈和第二线圈、以及尾电感单元可以部署在不同的布线层中。比如，第一线圈和第二线圈采用低电阻率的三层高层金属来实现，当尾电感单元为金属线时采用底层金属叠层来实现。当第一路径的至少一部分在尾电感单元所处的布线层上的投影与尾电感单元处于一条直线上，以及使第二路径的至少一部分在尾电感单元所处的布线层上的投影与尾电感单元处于一条直线上时，可以缩小VDD对应的过孔与VSS对应的过孔之间的物理距离。当第一路径中的起始部分和第二路径中起始部分均与尾电感单元在同一布线层上的投影处于一条直线上，可以最大限度的减小VDD对应的过孔与VSS对应的过孔之间的物理距离。
需要说明的是，在集成电路中通常可以包括多层金属层，每层金属层对应一层布线层，靠近集成电路的衬底的金属层可以称为底层金属层，远离衬底的金属层可以称为高层金属层。比如，集成电路中的金属层可以包括9层金属和一层铝层(AP)，9层金属从低到高可以依次为M1至M9，则所述三层高层金属可以是指M8、M9和AP，所述底层金属叠层可以是指M4至M7叠在一起用来实现尾电感单元。
在本申请实施例中，变压器采用集成电路工艺中具有低电阻率的顶三层金属布局，以获得较高的品质因数。尾电感单元由底层金属叠层构成的线型电感，它沿着变压器在其布线层上的投影的中轴延伸，一方面可以保证振荡器的集成电路得投影以该尾电感单元为轴对称，另一方面尾电感单元不额外占用面积。
可选地，该集成电路中VSS在多个布线层中的过孔，与VDD在多个布线层中的过孔之间的物理距离小于或等于10um。比如，在尾电感单元所处的布线层上，VSS对应的过孔与VDD对应的过孔之间的物理距离小于或等于10um。
进一步地，第一线圈和第二线圈均关于尾电感单元对称。其中，第一线圈和第二线圈均关于尾电感单元对称，可以是指将第一线圈、第二线圈和尾电感单元均投影在一个相同的平面上时，在该投影的平面上，第一线圈和第二线圈均关于尾电感单元对称。
具体地，若将第一线圈和第二线圈均投影在尾电感单元所处的布线层上，则第一线圈在尾电感单元所处的布线层上的投影、以及第二线圈在尾电感单元所处的布线层上的投影，均关于尾电感单元对称。或者，若将第二线圈和尾电感单元均投影在第一线圈所处的布线层上，则第一线圈、以及第二线圈在第一线圈所处的布线层上的投影，均关于尾电感单元在第一线圈所处的布线层上的投影对称。或者，若将第一线圈和尾电感单元均投影在第二线圈所处的布线层上，则第一线圈在第二线圈所处的布线层上的投影、以及第二线圈，均关于尾电感单元在第二线圈所处的布线层上的投影对称。
通过设置第一线圈和第二线圈均关于尾电感单元对称，可以避免尾电感单元激发的周围磁场对于第一线圈两侧和第二线圈两侧的影响不一致的问题，从而使得尾电感单元激发的周围磁场对于第一线圈两侧和第二线圈两侧的影响可以相互抵消，保证该集成电路的相位噪声不受尾电感单元激发的周围磁场的影响。
进一步地，该集成电路还包括第一电容和第二电容，所述一对第一输出端还分别 与第一电容的两端连接，所述一对第二输出端还分别与第二电容的两端连接，第二电容与第一电容的比值大于或等于2。可选地，第二电容与第一电容的比值还小于或等于4。
其中，第一电容与第一线圈、第二电容与第二线圈可以形成谐振，用于输出具有一定频率的振荡信号。当第二电容与第一电容的比值大于或等于2、且小于或等于4时，可以使该振荡器的集成电路工作在被动增益饱和区，从而抑制MOS管的热噪声4kTg m转换为相位噪声，使得该振荡器的集成电路具有较低的相位噪声，且具有较宽的调谐范围。
在本申请实施例中，通过尾电感单元将该振荡器的集成电路中的VSS充分接近VDD，以缩小所述VDD与所述VSS间的物理距离，从而可以充分减小所述VDD与所述VSS间的去耦合电容的寄生电感，以使其忽略不计，从而避免因为寄生电感的不确定性，而导致振荡波形的上升沿和下降沿不对称的问题，进而避免因为其波形上升沿和下降沿不对称而造成的闪烁相位噪声上调的问题，以使该振荡器具有较低的相位噪声。
另外，在振荡过程中，MOS管会完全开启，相当于一个电阻接入谐振单元，对振荡器贡献噪声，通过尾电感单元可以在MOS管的源极V SOURCE引入一个追随栅极的电压，使得MOS管的开启大小和开启时间都减小，从而减小MOS管的热噪声，进而减小该振荡器的相位噪声。
进一步地，如图6所示，该振荡器的集成电路包括双核振荡器，双核振荡器包括结构相同且对称设置的两个振荡器，两个振荡器中的第一电容合并设置。即双核振荡器中每个振荡器的集成电路的结构如图5所示，且将两个振荡器中的第一电容C D通过一个电容为2C D来实现。
由于在标准CMOS工艺中，一般没有极厚金属，这将进一步限制被动器件的品质因数。比如，图5中第一电容C D为被动器件，当其电容值较小时，现有CMOS工艺可能无法生产，或者以现有CMOS工艺生产的电容器件其品质因数较差，从而影响振荡器的性能。通过合并设置两个振荡器中的第一电容，可以使合并设置后的电容采用现有的CMOS工艺来生成，比如，合并后的电容可以直接采用TSMC-16nm工艺中最小的MOM电容来实现，从而可以减小集成电容的面积，有效降低一半被动器件的热噪声，进而进一步降低振荡器的集成电路的相位噪声。
需要说明的是，在上述图5和图6所示的振荡器的集成电路中，每个振荡器的VSS和VDD之间还可以连接有一个去耦合电容C1，该去耦合电容C1可以是专门为该振荡器设置的电容，也可以是与该振荡器共同所述VDD和所述VSS的其他电路中的电容，图5和图6中未画出，具体可以参见图3和图4中的描述。
需要说明的是，本申请实施例和附图仅仅是一种示例，任一实施例或附图中的每个MOS管可以为一个单独的满足所需要启动增益或者所需要导通电流的MOS管，也可以为通过多个MOS管并联组合成的需要满足所需要启动增益或者所需要导通电流的MOS管组合，也即该多个MOS管中每个MOS管对应的启动增益之和大于或等于所需要启动增益；本申请实施例中的每个电容可以为满足所需电容值的一个电容，也可以是由多个电容通过并联或者串联组成的满足所需电容值的电容组合，也即该多个 电容串联或并联后对应的电容值等于所需要的电容值；本申请实施例中的每个电感可以为满足所需要电感值的一个电感，也可以是由多个电感通过串联或者并联方式组成的满足所需要电感值的电感组合。
本申请实施例还提供一种终端，该终端至少包括射频装置以及本申请实施例提供的振荡器的集成电路，该振荡器的集成电路用于为上述射频装置提供本地载波信号。该射频装置用于以下任意一项或组合：终端中的蜂窝移动通信模块、蓝牙模块、无线保真(WIFI)模块或任何需要本地载波信号的装置。例如，该终端中的射频装置可以为蓝牙模块以及WIFI模块,也可以为蓝牙模块或者WIFI模块。
本申请实施例还提供一种基站，该基站至少包括收发机以及锁相环电路，该锁相环电路包括本申请实施例提供的振荡器的集成电路，该振荡器的集成电路用于为该基站的收发机提供本地载波信号。
需要说明的是，上述终端和基站只是举例说明应用本申请实施例提供的振荡器的集成电路的产品，并不能构成对本申请实施例提供的振荡器的集成电路的应用的限制，本申请实施例提供的振荡器的集成电路可以应用在任何低噪声性能要求的场景，以及任何低噪声性能要求的产品中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种振荡器的集成电路，其特征在于，所述集成电路包括变压器、交叉耦合单元和尾电感单元；其中，
    所述变压器包括互相缠绕的第一线圈和第二线圈，所述第一线圈和第二线圈的电压端均耦合至电源端(VDD)，所述第一线圈包括一对第一输出端，所述第二线圈包括一对第二输出端，
    所述交叉耦合单元包括第一金属氧化物半导体MOS管和第二MOS管，所述第一MOS管和第二MOS管的栅极分别与所述一对第二输出端相接，所述第一MOS管和第二MOS管的漏极分别与所述一对第一输出端相接，所述第一MOS管和第二MOS管的源极均通过所述尾电感单元耦合至地端(VSS)，
    其中，所述尾电感单元自所述交叉耦合单元越过所述变压器，朝向所述电压端所处的一侧延伸。
  2. 根据权利要求1所述的集成电路，其特征在于，所述集成电路设置有相互平行的多层布线层，所述第一线圈的电压端与所述VDD之间的电路路径为第一路径，所述第二线圈的电压端与所述VDD之间的电路路径为第二路径，
    所述第一路径的至少一部分与所述尾电感单元在同一布线层上的投影处于一条直线上，
    所述第二路径的至少一部分与所述尾电感单元在同一布线层上的投影处于一条直线上。
  3. 根据权利要求1所述的集成电路，其特征在于，所述集成电路设置有相互平行的多层布线层，所述第一线圈的电压端与所述VDD之间的电路路径为第一路径，所述第二线圈的电压端与所述VDD之间的电路路径为第二路径，
    所述第一路径中与所述第一线圈相接的一部分与所述尾电感单元在同一布线层上的投影处于一条直线上，
    所述第二路径中与所述第二线圈相接的一部分与所述尾电感单元在同一布线层上的投影处于一条直线上。
  4. 根据权利要求1-3任一项所述的集成电路，其特征在于，所述第一线圈和所述第二线圈均关于所述尾电感单元对称。
  5. 根据权利要求1-4任一项所述的集成电路，其特征在于，所述集成电路还包括第一电容和第二电容，所述一对第一输出端还分别与所述第一电容的两端连接，所述一对第二输出端还分别与所述第二电容的两端连接。
  6. 根据权利要求5所述的集成电路，其特征在于，所述第二电容与所述第一电容的比值大于或等于2。
  7. 根据权利要求6所述的集成电路，其特征在于，所述第二电容与所述第一电容的比值还小于或等于4。
  8. 根据权利要求1-7任一项所述的集成电路，其特征在于，所述集成电路设置有多个相互平行的布线层，所述变压器，所述交叉耦合单元和所述尾电感单元分别排布在一个或多个所述布线层上，所述多个布线层间设有过孔以连接不同布线层上的信号 路径。
  9. 一种振荡器的集成电路，其特征在于，包括两个如权利要求1-5任一项所述的振荡器的集成电路，两个所述振荡器的集成电路共享所述第一电容。
  10. 根据权利要求8所述的集成电路，其特征在于，所述第二电容与所述第一电容的比值等于1，或者大于1。
  11. 一种终端，其特征在于，所述终端至少包括射频装置以及如权利要求1-10任意一项所述的振荡器的集成电路，所述振荡器的集成电路用于为所述射频装置提供本地载波信号。
  12. 一种基站，其特征在于，所述基站至少包括收发机及锁相环电路，所述锁相环电路包括如权利要求1-10任意一项所述的振荡器的集成电路，所述振荡器的集成电路用于为所述收发机提供本地载波信号。
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