WO2023169038A1 - 一种变压器型分布式多核振荡器及其集成电路与终端 - Google Patents

一种变压器型分布式多核振荡器及其集成电路与终端 Download PDF

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WO2023169038A1
WO2023169038A1 PCT/CN2022/139165 CN2022139165W WO2023169038A1 WO 2023169038 A1 WO2023169038 A1 WO 2023169038A1 CN 2022139165 W CN2022139165 W CN 2022139165W WO 2023169038 A1 WO2023169038 A1 WO 2023169038A1
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Prior art keywords
transformer
tuning capacitor
cross
capacitor array
distributed multi
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PCT/CN2022/139165
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English (en)
French (fr)
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胡诣哲
林福江
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安徽传矽微电子有限公司
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Publication of WO2023169038A1 publication Critical patent/WO2023169038A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
    • H03B5/1218—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the generator being of the balanced type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B1/00—Details
    • H03B1/04—Reducing undesired oscillations, e.g. harmonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006—Functional aspects of oscillators
    • H03B2200/0088—Reduction of noise
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the invention belongs to the technical field of radio frequency integrated circuits, and specifically relates to a transformer-type distributed multi-core oscillator, its integrated circuit and terminal.
  • Millimeter wave oscillators are the core components of 5G/6G communication chips. Millimeter wave oscillators with low phase noise (PN) are currently a hot research topic. Designing millimeter wave oscillators as distributed multi-core oscillator structures is an effective means to reduce thermal phase noise (thermal PN), but the low-frequency flicker phase noise (flicker PN) in such oscillator products is still very high. In millimeter-wave phase-locked loops using distributed multi-core oscillators, low-frequency flicker phase noise is difficult to filter out by the loop, which worsens the jitter of the local oscillator signal in the circuit and ultimately limits the signal transmission rate of the communication chip.
  • PN phase noise
  • Figure 1 shows the integrated circuit of a traditional inductive distributed multi-core oscillator: the capacitor C and the distributed inductor form a resonant cavity; two cross-coupled pairs (M1/M2 and M3/M4) are equidistantly distributed in the single-turn inductor. on, providing the required "negative resistance" for the oscillator's oscillation. In particular, they are further cross-connected to ensure that the resonant first harmonic current forms a loop along the single-turn inductance.
  • this distributed multi-core oscillator can halve the inductance value of the resonant cavity in the circuit and double the capacitance value at the same frequency and the same resonant cavity quality factor.
  • the present invention provides a transformer-type distributed multi-core oscillator, its integrated circuit and terminal.
  • a transformer-type distributed multi-core oscillator is used to generate required AC signals under DC power supply conditions.
  • the transformer-type distributed multi-core oscillator includes: four MOS tube units M1, M2, M3 and M4; two symmetrically arranged transformer units T1 and T2, and two sets of coarse-tuning capacitor arrays C G1 and symmetrically arranged with the same structure.
  • C G2 two sets of fine-tuning capacitor arrays C D1 and CD2 with the same structure and symmetrical arrangement; two sets of tail inductance units L tail1 and L tail2 .
  • MOS transistors M1 and M2 form a first cross-coupling pair
  • MOS transistors M3 and M4 form a second cross-coupling pair.
  • the inner side is the inner coil L d
  • the outer side is the outer coil L g .
  • Two sets of fine-tuning capacitor arrays C D1 and C D2 are connected in series at both ends of the inner coils L d of the two transformer units T1 and T2 to form a loop; two sets of coarse-tuning capacitor arrays C G1 and C G2 are connected in series on two transformer units T1 and T2 respectively.
  • the two ends of the inner coils L g of the transformer units T1 and T2 form another loop; and the two ends of the two inner coils L d of the two transformer units T1 and T2 are cross-connected.
  • the drains of MOS transistors M1 and M2 are respectively connected to both ends of the fine-tuning capacitor array CD1
  • the drains of MOS transistors M3 and M4 are respectively connected to both ends of the fine-tuning capacitor array CD2 .
  • the gate electrodes of MOS transistors M1 and M2 are respectively connected to both ends of the coarse adjustment capacitor array C G1
  • the gate electrodes of MOS transistors M3 and M4 are respectively connected to both ends of the coarse adjustment capacitor array C G2 .
  • the sources of MOS tubes M1 and M3 are directly connected and connected to the ground terminal Vss through one set of tail inductor units L tail1 .
  • the sources of MOS tubes M2 and M4 are directly connected and connected to the ground terminal Vss through another set of tail inductor units L tail2 .
  • the tap ends of the coils in the transformer units T1 and T2 are both electrically connected to the power supply terminal Vdd.
  • the drains of the two MOS transistors of the cross-coupling pair are respectively led out as signal output ports.
  • the transformer units T1 and T2 have identical transformer structures, and in the transformer units T1 and T2, the turns ratio of the inner coil and the outer coil is both 1:1.
  • the coarse-adjusting capacitor arrays C G1 and CG2 and the fine-adjusting capacitor arrays CD1 and CD2 are composed of multiple turn-off capacitor units connected in parallel.
  • the capacitance values of the coarse-tuning capacitor array and the fine-tuning capacitor array are adjustable.
  • the specifications and parameters of the two sets of coarse-tuning capacitor arrays C G1 and C G2 are exactly the same; the specifications and parameters of the two sets of fine-tuning capacitor arrays C D1 and C D2 are also exactly the same. .
  • the frequency of the output AC signal is adjusted.
  • the coarse-tuning capacitor array serves as the gate resonant cavity capacitor
  • the fine-tuning capacitor array serves as the source-level resonant cavity capacitor.
  • the ratio of the capacitance values of the gate resonant cavity capacitance and the source resonant cavity capacitance is 2 to 4.
  • a capacitor is also connected between the ground terminal Vss and the power terminal Vdd as a decoupling capacitor.
  • the present invention also includes an integrated circuit of a transformer-type distributed multi-core oscillator, which includes the aforementioned transformer-type distributed multi-core oscillator circuit structure.
  • transformer-type distributed multi-core oscillators also adopt the following layout:
  • the NT_N layer is only provided in the annular area where the two transformer units T1 and T2 are distributed; the cross-coupling unit is located inside the annular area that does not contain the NT_N layer; the coarse-tuning capacitor array and the fine-tuning capacitor array are located in the annular area that does not contain the NT_N layer. Outside the annular area of the NT_N layer.
  • the NT_N layer is an undoped N-type active region and is often used for isolation in radio frequency layouts.
  • the coarse-tuned capacitor array and the fine-tuned capacitor array form a fully differential capacitor array
  • a tail inductor unit is connected between the source electrode and the ground terminal Vss in the MOS tube.
  • the tail inductor unit passes from the inside of the annular area without the NT_N layer to below the power terminal Vdd.
  • a capacitor is connected between the power terminal Vdd and the ground terminal Vss as a decoupling capacitor.
  • the invention also includes a terminal, which at least includes a radio frequency device and an integrated circuit of a transformer-type distributed multi-core oscillator as described above.
  • the integrated circuit of the transformer-type distributed multi-core oscillator is used to provide a local carrier for the radio frequency device. Signal.
  • the present invention adopts a new transformer-type distributed multi-core oscillator circuit and component connection method; adopts an appropriately sized tail inductor and a fully differential capacitor array; thereby solving the problem of uncertain common-mode return paths in traditional circuits. This not only ensures lower thermal phase noise, but also avoids the flicker noise up-regulation problem in traditional circuits caused by the uncertainty of parasitic inductance.
  • the present invention proposes a method for improving the circuit manufacturing process.
  • four MOS are laid out in the center of the layout using a special "cross-coupling" connection method, and the transformer and capacitor array are laid out outside the MOS tube.
  • a special Native layer layout design is used to reduce the impact of circuit connection relationships on the Q value of the transformer.
  • the present invention effectively suppresses low-frequency flicker phase noise in the "negative phase shift saturation interval" of the circuit through the proposed 1:1 distributed transformer structure.
  • the transformer gain further suppresses thermal phase noise. Achieve simultaneous improvement in circuit thermal phase noise and low-frequency flicker phase noise performance.
  • the output signal of the transformer-type distributed multi-core oscillator provided by the present invention has a wider frequency range and can output higher frequency signals; and the output signal can be accurately adjusted through a coarse-tuning capacitor array and a fine-tuning capacitor array.
  • a single full-function circuit unit can output two outputs with exactly the same characteristics without causing any interference to each other, which can be applied to more diverse scenarios.
  • FIG. 1 is a circuit diagram of a transformer-type distributed multi-core oscillator provided in Embodiment 1 of the present invention.
  • FIG. 2 is a layout of an integrated circuit of a transformer-type distributed multi-core oscillator provided in Embodiment 2 of the present invention.
  • FIG. 3 is an integrated circuit layout of a typical inductive distributed multi-core oscillator mentioned in Embodiment 2 of the present invention.
  • the transformer-type distributed multi-core oscillator includes: four MOS tube units M1, M2, M3 and M4; two symmetrically arranged transformer units T1 and T2, and two sets of coarse-grained oscillators with the same structure and symmetrical arrangement. Adjusting capacitor arrays C G1 and C G2 ; two sets of fine-tuning capacitor arrays C D1 and CD2 with the same structure and symmetrical arrangement; two sets of tail inductance units L tail1 and L tail2 .
  • MOS transistors M1 and M2 form a first cross-coupling pair
  • MOS transistors M3 and M4 form a second cross-coupling pair.
  • the inner side is the inner coil L d
  • the outer side is the outer coil L g .
  • Two sets of fine-tuning capacitor arrays C D1 and C D2 are connected in series at both ends of the inner coils L d of the two transformer units T1 and T2 to form a loop; two sets of coarse-tuning capacitor arrays C G1 and C G2 are connected in series on two transformer units T1 and T2 respectively.
  • the two ends of the inner coils L g of the transformer units T1 and T2 form another loop; and the two ends of the two inner coils L d of the two transformer units T1 and T2 are cross-connected.
  • the drains of MOS transistors M1 and M2 are respectively connected to both ends of the fine-tuning capacitor array CD1
  • the drains of MOS transistors M3 and M4 are respectively connected to both ends of the fine-tuning capacitor array CD2 .
  • the gate electrodes of MOS transistors M1 and M2 are respectively connected to both ends of the coarse adjustment capacitor array C G1
  • the gate electrodes of MOS transistors M3 and M4 are respectively connected to both ends of the coarse adjustment capacitor array C G2 .
  • the sources of MOS tubes M1 and M3 are directly connected and connected to the ground terminal Vss through one set of tail inductor units L tail1 .
  • the sources of MOS tubes M2 and M4 are directly connected and connected to the ground terminal Vss through another set of tail inductor units L tail2 .
  • the tap ends of the coils in the transformer units T1 and T2 are both electrically connected to the power supply terminal Vdd.
  • the distributed transformer structure and the capacitor array connected to it constitute a distributed multi-core resonant cavity, which is used to generate the AC output signal of the oscillation circuit; two cross-coupled pairs (M1/M2 and M3/M4) are used for oscillation.
  • the oscillation of the inductor provides the required energy; the tail inductor unit provides high common mode impedance to suppress the second harmonic component of the output signal.
  • the three work together to convert the DC energy provided by the power supply into clean AC energy output.
  • the drains of the two MOS transistors of the cross-coupling pair are respectively led out as signal output ports; in the circuit of this embodiment, up to two identical signals can be output.
  • the solution of the present invention arranges the power supply terminal V DD and the ground terminal V SS on the left and right sides of the circuit, so that the physical distance between the power supply terminal and the ground terminal on the chip is the shortest, and the decoupling capacitance is greatly reduced. parasitic inductance in. This makes the rising and falling edges of the generated oscillation waveform more symmetrical, solves the problem of uncertain common-mode return paths in the circuit, and eliminates the influence of low-frequency flicker phase noise.
  • the coarse-adjusting capacitor arrays C G1 and CG2 and the fine-adjusting capacitor arrays CD1 and CD2 are composed of multiple turn-off capacitor units connected in parallel.
  • the capacitance values of the coarse-tuning capacitor array and the fine-tuning capacitor array are adjustable.
  • the specifications and parameters of the two sets of coarse-tuning capacitor arrays C G1 and C G2 are exactly the same; the two sets of fine-tuning capacitor arrays have the same specifications.
  • the specifications and parameters of arrays CD1 and CD2 are also exactly the same.
  • the coarse-tuned capacitor array serves as the gate resonant cavity capacitor
  • the fine-tuned capacitor array serves as the source-level resonant cavity capacitor.
  • the ratio of the capacitance values of the gate resonant cavity capacitance and the source resonant cavity capacitance is set to 2 to 4.
  • both the fine-tuning capacitor array and the coarse-tuning capacitor array adopt the form of a fully differential capacitor array, and a capacitor is connected between the ground terminal Vss and the power terminal Vdd as a decoupling capacitor.
  • a capacitor is connected between the ground terminal Vss and the power terminal Vdd as a decoupling capacitor.
  • the main impact of the cross-coupled flicker current noise is that it is injected into the resonant cavity at the rising and falling edges of V DS (the voltage difference between the drain and the source), thereby causing a phase shift in the waveform.
  • the direction of the resulting phase shift is opposite between rising and falling edges.
  • the size of the phase shift depends on the intensity of the flicker noise during the rising and falling edges, as well as the slope of the rising or falling edge of the voltage. Steeper edges are more resistant to current noise. If the rising and falling edges of the oscillator waveform are symmetrical, the phase shifts caused by the flicker current noise may cancel each other out within one cycle and not be converted into phase noise.
  • the common mode return path can be controlled to enter the inductive impedance.
  • V DS steeper than the falling edge, that is: for the same size of flicker noise, the phase shift introduced on the rising edge is smaller than the opposite phase shift caused by the falling edge (the net phase shift is not 0). Therefore, flicker noise is converted into phase noise within one cycle.
  • the intensity of the flicker noise of a cross-coupled pair changes in amplitude within a cycle, mainly depending on V GS (the voltage difference between the gate and the source).
  • the negative phase offset of V GS to V DS is introduced through the transformer structure (making the top of V GS close to the steep rising edge of V DS ), which can increase the noise current injection intensity during the rising edge and increase the phase shift introduction of the rising edge. , ultimately causing the net phase shift of the circuit to be 0 within one signal period, and the flicker current noise cannot convert phase noise.
  • Transformer units T1 and T2 have identical transformer structures, and in transformer units T1 and T2, the turns ratio of the inner coil and the outer coil is 1:1.
  • the 1:1 distributed transformer is more suitable for millimeter wave oscillators.
  • its equivalent voltage gain is greater than 1, which further improves the circuit's suppression effect on thermal phase noise.
  • the equivalent gain ratio of a planar transformer with a turns ratio of 1:1 on the chip is (greater than 1), so it still has the required transformer gain.
  • the oscillator can be made to operate in the "transformer passive gain saturation region"". This achieves the purpose of suppressing the conversion of thermal noise of the MOS tube into thermal phase noise and achieving a wide tuning range at the same time.
  • the transformer with a turns ratio of 1:1 used in this embodiment can significantly reduce the overall inductance value of the transformer while keeping the inner diameter of the transformer unchanged, compared to the previous transformer with a turns ratio of 2:1.
  • the output frequency of the oscillator is further increased, allowing the output signal to reach a higher frequency range, making it more suitable for use as a millimeter wave oscillator and improving the practical value of the product.
  • the new transformer-type distributed multi-core oscillator provided in this embodiment can further improve the generated low-frequency flicker phase noise effect while improving the thermal phase noise suppression effect. Therefore, it is very suitable for use in new communication chips such as 5G/6G to improve the signal transmission rate of communication chips.
  • this embodiment further provides an integrated circuit for a transformer-type distributed multi-core oscillator.
  • integrated circuits makes it easier to manufacture and apply transformer-type distributed multi-core oscillator units.
  • the integrated circuit provided in this embodiment includes the circuit structure of the transformer-type distributed multi-core oscillator in Embodiment 1.
  • the following layout method is also adopted in the layout of the integrated circuit:
  • FIG. 2 the specific layout of the transformer-type distributed multi-core oscillator is shown in Figure 2. It can be seen from Figure 2 that: this embodiment only sets the NT_N layer in the annular area where the two transformer units T1 and T2 are distributed; the cross-coupling unit is located inside the annular area that does not contain the NT_N layer; the coarse-tuning capacitor array and the fine-tuning capacitor array Located outside the annular area that does not contain the NT_N layer.
  • the NT_N layer is an undoped N-type active region and is often used for isolation in radio frequency layouts.
  • This embodiment uses a hollow NT_N layer to completely cover the substrate under the coil, thereby reducing substrate doping and effectively improving the resistivity of the substrate and the quality factor of the coil.
  • this process also places the cross-coupled pairs composed of MOS tubes in the hollow area in the center of the NT_N layer. The MOS tubes are not covered by the NT_N layer, thus avoiding the latch-up effect in the transistors.
  • the coarse adjustment capacitor array and the fine adjustment capacitor array form a fully differential capacitor array
  • a tail inductor unit is connected between the source electrode and the ground terminal Vss in the MOS tube.
  • the tail inductor unit passes from the inside of the annular area without the NT_N layer to below the power terminal Vdd.
  • a capacitor is connected between the power terminal Vdd and the ground terminal Vss as a decoupling capacitor.
  • this embodiment places the cross-coupled pairs (M1, M2 and M3, M4) as "negative resistance” inside the transformer, and then adds a "linear" tail inductor through layout wiring to further shorten the distance.
  • the distance between the power supply terminal V DD and the ground terminal V SS of the oscillator circuit is reduced, thereby reducing the parasitic inductance of the decoupling capacitor between V DD and V SS , and avoiding the traditional inductance type caused by the uncertainty of parasitic inductance.
  • Figure 3 reflects the layout of a typical inductive distributed multi-core oscillator (that is, the multi-core oscillator mentioned in the background art), and the common mode return path (arrow part) in the decoupling capacitor in the circuit.
  • Figure 2 is a layout of the transformer-type distributed multi-core oscillator in this embodiment, in which the common-mode return path (arrow part) in the circuit is also marked. It can be found by comparing Figure 2 and Figure 3.
  • Figure 3 uses a complex decoupling capacitor array containing a large number of parasitic inductors and parasitic resistors, but the common-mode return path in this circuit is still non-directional. In the circuit of this embodiment, only a simple capacitor is needed to be connected between V DD and V SS as a decoupling capacitor to achieve completely certain common mode backflow.
  • this embodiment further provides a terminal, which at least includes a radio frequency device and an integrated circuit of a transformer-type distributed multi-core oscillator as described in Embodiment 2.
  • the transformer-type distributed multi-core oscillator The integrated circuit of the receiver is used to provide the local carrier signal to the radio frequency device.
  • the type of radio frequency device is not limited to any form.
  • it may be a cellular mobile communication module, a Bluetooth module, a wifi module in the terminal, or other devices that require local carrier signals.
  • the terminal referred to in this embodiment only provides an application scenario of the integrated circuit of the transformer-type distributed multi-core oscillator in Embodiment 2.
  • the practical application of the transformer-type distributed multi-core oscillator integrated circuit is very wide. It even includes phase-locked loop products, communication base stations, mobile phones, computers and other terminal equipment that need to implement communication functions, etc.
  • the core function of the distributed multi-core oscillator mentioned in this embodiment is to generate a frequency source of AC signals that meets the design target under power supply conditions. Therefore, any device that directly or indirectly uses the integrated circuit of the transformer-type distributed multi-core oscillator designed in the solution provided in this embodiment to generate the required frequency signal with low thermal phase noise and low-frequency flicker phase noise characteristics or systems all belong to the terminals mentioned in this embodiment.

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Abstract

本发明属于射频集成电路技术领域，具体涉及一种变压器型分布式多核振荡器及其集成电路与终端。变压器型分布式多核振荡器包括：四个MOS管单元M1、M2、M3和M4；两个对称设置的变压器单元T1和T2、两组具有相同结构且对称设置的粗调电容阵列CG1和CG2；两组具有相同结构且对称设置的细调电容阵列CD1和CD2；两组尾电感单元Ltail1和Ltail2。其中，M1和M2构成第一交叉耦合对，M3和M4构成第二交叉耦合对；两组交叉耦合对位于电路中央。MOS管的源极和漏极分别接地端和电源端，第一交叉耦合对和/或所述第二交叉耦合对中的两个MOS管的漏极分别引出作为信号输出端口。本发明同步解决了现有分布式多核振荡器中，热相位噪声和低频闪烁相位噪声较高的问题。

Description

一种变压器型分布式多核振荡器及其集成电路与终端 技术领域
本发明属于射频集成电路技术领域，具体涉及一种变压器型分布式多核振荡器及其集成电路与终端。
背景技术
毫米波振荡器是5G/6G通信芯片的核心组成部分，具有低相位噪声(phasenoise，PN)的毫米波振荡器是当前的热点研究课题。将毫米波振荡器设计为分布式多核振荡器结构，是一种降低热相位噪声(thermal PN)的有效手段，但这类振荡器产品中的低频闪烁相位噪声(flicker PN)依然很高。在使用分布式多核振荡器的毫米波锁相环中，低频闪烁相位噪声难以被环路滤除，这会恶化电路中本振信号的抖动，最终限制了通信芯片的信号传输速率。
图1展示了一种传统的电感型分布式多核振荡器的集成电路：电容C和分布式电感构成谐振腔；两个交叉耦合对(M1/M2和M3/M4)等距分布在单圈电感上，为振荡器的振荡提供所需的“负阻”。特别地，它们进一步交叉连接，确保谐振一次谐波电流沿单圈电感构成环路。相比于传统电感振荡器，这种分布式多核振荡器可以在相同频率，相同谐振腔品质因数下，使得电路中的谐振腔电感值减半，并使得电容值翻倍。进而有效抑制电流噪声注入谐振腔的电容导致的输出波形相位扰动，并将热相位噪声的抑制效果提升一倍。特别地，在实现性能提升的同时，分布式多核振荡器和传统多核振荡器相比，电路的结构尺寸并不会出现明显地增大。
然而，在现有的分布式多核振荡器中，电路的电源VDD和地VSS往往相距位置遥远，这导致电路中的二次谐波电流(IH2)必然经过VDD和VSS之间的去耦合电容，这会在去耦合电容中产生很大的寄生电感，进而导致振荡波形上升沿、下降沿不对称，引入很高的低频闪烁相位噪声。
发明内容
为了解决现有分布式多核振荡器仅仅可以改善热相位噪声，电路中的闪烁相位噪声依然很大的问题，本发明提供一种变压器型分布式多核振荡器及其集成电路与终端。
本发明采用以下技术方案实现：
一种变压器型分布式多核振荡器，其用于在直流供电条件下产生所需的交流信号。变压器型分布式多核振荡器中包括：四个MOS管单元M1、M2、M3和M4；两个对称设置的变 压器单元T1和T2，两组具有相同结构且对称设置的粗调电容阵列C G1和C G2；两组具有相同结构且对称设置的细调电容阵列C D1和C D2；两组尾电感单元L tail1和L tail2。
其中，MOS管M1和M2构成第一交叉耦合对，MOS管M3和M4构成第二交叉耦合对。变压器单元T1和T2中，靠内一侧的为内侧线圈L d，靠外一侧的为外侧线圈L g。两组细调电容阵列C D1和C D2分别串联在两个变压器单元T1和T2的内侧线圈L d的两端构成一个环路；两组粗调电容阵列C G1和C G2分别串联在两个变压器单元T1和T2的内侧线圈L g的两端构成另一个环路；且两个变压器单元T1和T2中的两个内侧线圈L d的两端交叉相连。MOS管M1和M2的漏极分别连接在细调电容阵列C D1的两端，MOS管M3和M4的漏极分别连接在细调电容阵列C D2的两端。MOS管M1和M2的栅极分别连接在粗调电容阵列C G1的两端，MOS管M3和M4的栅极分别连接在粗调电容阵列C G2的两端。MOS管M1和M3的源极直接连接并通过其中一组尾电感单元L tail1连接地端Vss，MOS管M2和M4的源极直接连接并通过另外一组尾电感单元L tail2连接地端Vss。变压器单元T1和T2中线圈的抽头端均与电源端Vdd电连接。
在第一交叉耦合对和/或第二交叉耦合对中，交叉耦合对两个MOS管的漏极分别引出作为信号输出端口。
作为本发明进一步的改进，变压器单元T1和T2为全同的变压器结构，且在变压器单元T1和T2中，内侧线圈和外侧线圈的匝数比均为1:1。
作为本发明进一步的改进，粗调电容阵列C G1和C G2，以及细调电容阵列C D1和C D2均由多个可关断的电容单元相互并联构成。粗调电容阵列和细调电容阵列的电容值可调。
作为本发明进一步的改进，在变压器型分布式多核振荡器中，两组粗调电容阵列C G1和C G2的规格参数完全相同；两组细调电容阵列C D1和C D2规格参数也完全相同。通过同步调节粗调电容阵列C G1和C G2，以及细调电容阵列C D1和C D2的电容值，进而调整输出的交流信号的频率。
作为本发明进一步的改进，在变压器型分布式多核振荡器中，粗调电容阵列作为栅极谐振腔电容，细调电容阵列作为源级谐振腔电容。栅极谐振腔电容和源级谐振腔电容的电容值之比为2～4。
作为本发明进一步的改进，地端Vss和电源端Vdd之间还连接一个电容器作为去耦合电容。
本发明还包括一种变压器型分布式多核振荡器的集成电路，该集成电路中包含如前述变压器型分布式多核振荡器电路结构。在集成电路的版图中，变压器型分布式多核振荡器还采用如下的布局方式：
(1)将第一交叉耦合对和第二交叉耦合对相邻设置构成交叉耦合单元，并将交叉耦合单元设置于电路的中央。交叉耦合单元中，四个MOS管按照M1、M2、M4、M3的循环顺序排列在一个矩形区域的四角；任意两个相邻的MOS管结构对称。
(2)将两个变压器单元设置在交叉耦合单元的外周，保持两个变压器单元结构对称。并将两个变压器单元T1和T2中的内侧线圈L d的两端交叉相连。
(3)将粗调电容阵列和细调电容阵列设置在交叉耦合单元的外周，并保持粗调电容阵列靠外，细调电容阵列靠内。将其中一组细调电容阵列C D1和粗调电容阵列C G1设置在靠近第一交叉耦合的位置。另外一组细调电容阵列C D2和粗调电容阵列C G2设置在靠近第二交叉耦合对的位置。
(4)将其中一组电源端Vdd和地端Vss设置在交叉耦合单元外周且靠近MOS管M1和M3的一侧。另一组电源端Vdd和地端Vss设置在交叉耦合单元外周且靠近MOS管M2和M4的一侧。进而使得电源端Vdd和地端Vss在集成电路的片内物理距离最短。
作为本发明进一步的改进，仅在两个变压器单元T1和T2分布的环形区域内设置NT_N层；交叉耦合单元位于不含有NT_N层的环形区域内部；粗调电容阵列和细调电容阵列位于不含有NT_N层的环形区域外部。NT_N层为不掺杂的N型有源区，常用于射频版图的隔离使用。
作为本发明进一步的改进，粗调电容阵列和细调电容阵列构成全差分电容阵列，并在MOS管中源极和地端Vss间连接尾电感单元。尾电感单元从不含NT_N层的环形区域内部穿出至电源端Vdd下方。电源端Vdd和地端Vss之间连接一个电容器作为去耦合电容。
本发明还包括一种终端，该终端至少包括射频装置，以及如前所述的变压器型分布式多核振荡器的集成电路，变压器型分布式多核振荡器的集成电路用于为射频装置提供本地载波信号。
本发明提供的技术方案，具有如下有益效果：
1、本发明采用了一种新型的变压器型分布式多核振荡器的电路和元件连接方式；采用适当大小的尾电感和全差分电容阵列；进而解决了传统电路中共模回流路径不定的问题。这既保证了较低的热相位噪声，还避免了因为寄生电感的不确定性导致的传统电路中的闪烁噪声上调问题。
2、本发明提出了电路在制程工艺上的改良方法。在产品集成电路版图设计中将四个MOS采用特殊的“交叉耦合”连接方式在版图中央布局，将变压器和电容阵列布局在MOS管外侧。并采用特殊的Native layer版图设计，降低电路连接关系对变压器Q值影响。
3、本发明通过提出的1：1分布式变压器结构，在电路的“负相移饱和区间”有效地抑 制了低频闪烁相位噪声。另外，变压器增益还进一步抑制了热相位噪声。实现电路热相位噪声和低频闪烁相位噪声性能的同步提升。
4、本发明提供的变压器型分布式多核振荡器的输出信号的频率范围较宽，可以输出更高频的信号；且可以通过粗调电容阵列和细调电容阵列对输出信号进行精准调节。单个全功能的电路单元中就可以输出两路具有完全相同特性且相互不产生任何干扰的输出，进而可以适用于更加多样化的场景。
附图说明
图1为本发明实施例1中提供的一种变压器型分布式多核振荡器的电路图。
图2为本发明实施例2中提供的一种变压器型分布式多核振荡器的集成电路的版图。
图3为本发明实施例2中提及的一种典型的电感型分布式多核振荡器的集成电路版图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步地详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
实施例1
本实施例提供一种变压器型分布式多核振荡器，其用于在直流供电条件下产生所需的交流信号。如图1所示，变压器型分布式多核振荡器中包括：四个MOS管单元M1、M2、M3和M4；两个对称设置的变压器单元T1和T2，两组具有相同结构且对称设置的粗调电容阵列C G1和C G2；两组具有相同结构且对称设置的细调电容阵列C D1和C D2；两组尾电感单元L tail1和L tail2。
其中，MOS管M1和M2构成第一交叉耦合对，MOS管M3和M4构成第二交叉耦合对。变压器单元T1和T2中，靠内一侧的为内侧线圈L d，靠外一侧的为外侧线圈L g。两组细调电容阵列C D1和C D2分别串联在两个变压器单元T1和T2的内侧线圈L d的两端构成一个环路；两组粗调电容阵列C G1和C G2分别串联在两个变压器单元T1和T2的内侧线圈L g的两端构成另一个环路；且两个变压器单元T1和T2中的两个内侧线圈L d的两端交叉相连。MOS管M1和M2的漏极分别连接在细调电容阵列C D1的两端，MOS管M3和M4的漏极分别连接在细调电容阵列C D2的两端。MOS管M1和M2的栅极分别连接在粗调电容阵列C G1的两端，MOS管M3和M4的栅极分别连接在粗调电容阵列C G2的两端。MOS管M1和M3的源极直接连接并通过其中一组尾电感单元L tail1连接地端Vss，MOS管M2和M4的源极直接连接并通过另外一组尾电感单元L tail2连接地端Vss。变压器单元T1和T2中线圈的抽头端均与电源端Vdd电连接。
在本实施例中，分布式变压器结构和与其相连的电容阵列构成分布式多核谐振腔，用于产生振荡电路的交流输出信号；两个交叉耦合对(M1/M2和M3/M4)，为振荡器的振荡提供所需的能量；尾电感单元提供高共模阻抗，用于抑制输出信号二次谐波分量。三者一起工作，可将电源提供的直流能量转换为干净的交流能量输出。
在第一交叉耦合对和/或第二交叉耦合对中，交叉耦合对两个MOS管的漏极分别引出作为信号输出端口；本实施例的电路中，最多可以输出两路完全相同的信号。
结合图1的电路图可以发现，本发明的方案将电源端V DD和地端V SS都设置电路的左右两侧，使得电源端和地端的片内物理距离最短，极大的减少了去耦电容中的寄生电感。使得产生的振荡波形的上升沿、下降沿更加对称，解决电路中共模回流路径不定的问题，消除低频闪烁相位噪声的影响。
在本实施例的电路结构中，粗调电容阵列C G1和C G2，以及细调电容阵列C D1和C D2均由多个可关断的电容单元相互并联构成。粗调电容阵列和细调电容阵列的电容值可调。在变压器型分布式多核振荡器中，为了保持整个电路结构的对称性，进而保障整体电路的功能稳定性，两组粗调电容阵列C G1和C G2的规格参数完全相同；两组细调电容阵列C D1和C D2规格参数也完全相同。通过同步调节粗调电容阵列C G1和C G2，以及细调电容阵列C D1和C D2的电容值，进而调整输出的交流信号的频率。
两组电容阵列中，粗调电容阵列作为栅极谐振腔电容，细调电容阵列作为源级谐振腔电容。考虑到应该使得二者的调节灵敏具有差异，进而实现粗调和精调的效果，本实施例中将栅极谐振腔电容和源级谐振腔电容的电容值之比设置为2～4。
在本实施例的电路结构中，细调电容阵列和粗调电容阵列均采用全差分电容阵列的形式，地端Vss和电源端Vdd之间还连接一个电容器作为去耦合电容。同时在地端Vss和MOS管之间加入适当大小的尾电感。因此，该多核振荡器可以控制共模回流路径进入感性阻抗，并有效利用变压器的“负相移饱和区”，使得电路可以在宽调谐范围内有效抑制低频噪声。
交叉耦合对的闪烁电流噪声主要的影响是在V DS(漏极与源极的电压差)的上升沿和下降沿注入谐振腔，进而造成波形的相位偏移。产生的相位偏移的方向在上升沿和下降沿方向是相反的。而相位偏移的大小取决于上升沿和下降沿期间闪烁噪声的强度，以及电压上升或下降边沿的斜率。越陡峭的边沿对电流噪声的抵抗能力越好。如果振荡器波形上升沿和下降沿对称，则闪烁电流噪声有可能在一个周期内造成的相位偏移相互抵消，不转换为相位噪声。
在本实施例的方案中，通过加入适当大小的尾电感和采用全差分电容阵列，可以控制共模回流路径进入感性阻抗。这使得V DS的上升沿比下降沿更陡峭，即：同样大小的闪烁噪声,在上升沿引入的相移小于下降沿造成的相反的相移(净相位移不为0)。因此，闪烁噪声在一 个周期内会转化为相位噪声。然而，交叉耦合对的闪烁噪声的强度在一个周期内的幅度变化，主要取决于V GS(栅极与源极的电压差)。本实施例通过变压器结构引入V GS对V DS的负相位偏移(让V GS的顶端靠近V DS的陡峭的上升沿)可以增加上升沿期间噪声电流注入强度，并增加上升沿的相移引入，最终使得电路在一个信号周期内的净相移为0，闪烁电流噪声不能转换相位噪声。
在本实施例提供的变压器型分布式多核振荡器中。变压器单元T1和T2为全同的变压器结构，且在变压器单元T1和T2中，内侧线圈和外侧线圈的匝数比均为1:1。1:1的分布式变压器更加适合毫米波振荡器，同时它的等效电压增益大于1，进一步提高了电路对热相位噪声的抑制效果。
考虑到变压器型分布式多核振荡器主要在集成电路中应用，而在芯片上匝数比为1：1的平面变压器的等效增益比值为
Figure PCTCN2022139165-appb-000001
(大于1)，所以它仍然具有所需的变压器增益。而且在本实施例中，由于已经通过设置栅极谐振腔电容和源级谐振腔电容的比值为一个适当的范围(例如2～4)，因而可以使该振荡器工作在“变压器被动增益饱和区”。进而达到抑制MOS管的热噪声转换为热相位噪声，并同时实现较宽的调谐范围的目的。本实施例中采用的匝数比为1：1的变压器，相比以往匝数比为2：1的变压器，可以在变压器内径不变的情况下，使得变压器的整体电感值明显下降，并将振荡器的输出频率进一步提升，使得输出信号达到更高频的范围，更加适合作为毫米波振荡器应用，提升产品的实用价值。
综合上述分析可以发现：本实施例中提供的这种新型的变压器型分布式多核振荡器，能够在提升热相位噪声抑制效果的同时，进一步改善产生的低频闪烁相位噪声效果。因而非常适合应用于5G/6G等新型通信芯片中，提升通信芯片的信号传输速率。
实施例2
在实施例1设计的具有完整功能的变压器型分布式多核振荡器单元的基础上，本实施例进一步提供了一种变压器型分布式多核振荡器的集成电路。采用集成电路的形式，可以更加便于对变压器型分布式多核振荡器单元进行制造和应用。
本实施例提供的集成电路中包含如实施例1中的变压器型分布式多核振荡器的电路结构。为了进一步通过制程和工艺提升变压器型分布式多核振荡器的性能，还在集成电路的版图中，采用如下的布局方式：
(1)将第一交叉耦合对和第二交叉耦合对相邻设置构成交叉耦合单元，并将交叉耦合单元设置于电路的中央。交叉耦合单元中，四个MOS管按照M1、M2、M4、M3的循环顺序排列在一个矩形区域的四角；任意两个相邻的MOS管结构对称。
(2)将两个变压器单元设置在交叉耦合单元的外周，保持两个变压器单元结构对称。并将两个变压器单元T1和T2中的内侧线圈L d的两端交叉相连。
(3)将粗调电容阵列和细调电容阵列设置在交叉耦合单元的外周，并保持粗调电容阵列靠外，细调电容阵列靠内。将其中一组细调电容阵列C D1和粗调电容阵列C G1设置在靠近第一交叉耦合的位置。另外一组细调电容阵列C D2和粗调电容阵列C G2设置在靠近第二交叉耦合对的位置。
(4)将其中一组电源端Vdd和地端Vss设置在交叉耦合单元外周且靠近MOS管M1和M3的一侧。另一组电源端Vdd和地端Vss设置在交叉耦合单元外周且靠近MOS管M2和M4的一侧。进而使得电源端Vdd和地端Vss在集成电路的片内物理距离最短。
该集成电路中，变压器型分布式多核振荡器的具体的版图如图2所示。结合图2可以看出：本实施例仅在两个变压器单元T1和T2分布的环形区域内设置NT_N层；交叉耦合单元位于不含有NT_N层的环形区域内部；粗调电容阵列和细调电容阵列位于不含有NT_N层的环形区域外部。
NT_N层为不掺杂的N型有源区，常用于射频版图的隔离使用。本实施例通过采用镂空的NT_N层，完全覆盖线圈下方的衬底，进而达到减少衬底参杂的目的，有效提高衬底的电阻率和线圈的品质因数。同时，该工艺还把MOS管构成的交叉耦合对均置于NT_N层中央的镂空区中，MOS管处不采用NT_N层覆盖，因而可以避免晶体管中产生闩锁效应(latch-up)。
在本实施例的版图设计中，粗调电容阵列和细调电容阵列构成全差分电容阵列，并在MOS管中源极和地端Vss间连接尾电感单元。尾电感单元从不含NT_N层的环形区域内部穿出至电源端Vdd下方。电源端Vdd和地端Vss之间连接一个电容器作为去耦合电容。
特别地，本实施例将作为“负阻”的交叉耦合对(M1、M2和M3、M4)均放在了变压器内部，再通过版图布线的方式加入“直线形”的尾电感，进一步拉近了振荡器电路的电源端V DD和地端V SS之间的距离，从而减小V DD与V SS间的去耦合电容的寄生电感，避免因为寄生电感的不确定性，而导致传统电感型分布式的闪烁噪声上调的问题。
图3反映了一种典型的电感型分布式多核振荡器的版图(即为背景技术中提及的多核振荡器)，以及电路中去耦合电容内的共模回流路径(箭头部分)。图2则是本实施例的变压器型分布式多核振荡器的版图，其中也标记了电路中的共模回流路径(箭头部分)。结合图2和图3的对比可以发现。图3中采用了包含大量寄生电感和寄生电阻的复杂的去耦合电容阵列，但是该电路中的共模回流路径仍然是不定向。而在本实施例的电路中，只需要简单的一个电容器连接在V DD与V SS之间作为去耦合电容，即可实现完全确定的共模回流。
由此可见：本实施例提供的技术方案，通过创新的电路设计，以及更加优化的电路布局， 可以显著提高分布式多核振荡器的产品性能。
实施例3
本实施例在前述实施例的基础上，进一步提供了一种终端，该终端至少包括射频装置，以及如实施例2所述的变压器型分布式多核振荡器的集成电路，变压器型分布式多核振荡器的集成电路用于为射频装置提供本地载波信号。
在上述终端中，射频装置的类型并不局限于任何一种形式，例如可以是终端中的蜂窝移动通信模块、蓝牙模块、wifi模块、或者其它需要本地载波信号的装置。
本实施例中所指的终端仅仅是给出了实施例2中的变压器型分布式多核振荡器的集成电路一种应用场景。事实上，该变压器型分布式多核振荡器的集成电路的实际应用非常广泛。甚至包括锁相环产品、通信基站，需要实现通信功能的手机、电脑等终端设备，等等。
本实施例中提及的分布式多核振荡器的核心功能是在供电条件下，生成满足设计目标的交流信号的频率源。因此，任何直接使用或间接使用本实施例提供的方案中设计的变压器型分布式多核振荡器的的集成电路，来生成所需的具有低热相位噪声和低频闪烁相位噪声特性的频率信号的装置或系统，均属于本实施例所言的终端。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种变压器型分布式多核振荡器，其特征在于，其用于在直流供电条件下产生所需的交流信号；所述变压器型分布式多核振荡器包括：四个MOS管单元M1、M2、M3和M4；两个对称设置的变压器单元T1和T2；两组具有相同结构且对称设置的粗调电容阵列C G1和C G2；两组具有相同结构且对称设置的细调电容阵列C D1和C D2；两组尾电感单元L tail1和L tail2；
    其中，MOS管M1和M2构成第一交叉耦合对，MOS管M3和M4构成第二交叉耦合对；变压器单元T1和T2中，靠内一侧的为内侧线圈L d，靠外一侧的为外侧线圈L g；两组细调电容阵列C D1和C D2分别串联在两个变压器单元T1和T2的内侧线圈L d的两端构成一个环路；两组粗调电容阵列C G1和C G2分别串联在两个变压器单元T1和T2的内侧线圈L g的两端构成另一个环路；且两个变压器单元T1和T2中的两个内侧线圈L d的两端交叉相连；MOS管M1和M2的漏极分别连接在细调电容阵列C D1的两端，MOS管M3和M4的漏极分别连接在细调电容阵列C D2的两端；MOS管M1和M2的栅极分别连接在粗调电容阵列C G1的两端，MOS管M3和M4的栅极分别连接在粗调电容阵列C G2的两端；MOS管M1和M3的源极直接连接并通过其中一组尾电感单元L tail1连接地端Vss，MOS管M2和M4的源极直接连接并通过另外一组尾电感单元L tail2连接地端Vss；变压器单元T1和T2中线圈的抽头端均与电源端Vdd电连接；
    所述第一交叉耦合对和/或所述第二交叉耦合对中的两个MOS管的漏极分别引出作为信号输出端口。
  2. 如权利要求1所述的变压器型分布式多核振荡器，其特征在于：变压器单元T1和T2为全同的变压器结构，且在变压器单元T1和T2中，内侧线圈和外侧线圈的匝数比均为1:1。
  3. 如权利要求2所述的变压器型分布式多核振荡器，其特征在于：粗调电容阵列C G1和C G2，以及细调电容阵列C D1和C D2均由多个可关断的电容单元相互并联构成；粗调电容阵列和细调电容阵列的电容值可调。
  4. 如权利要求3所述的变压器型分布式多核振荡器，其特征在于：在所述变压器型分布式多核振荡器中，两组粗调电容阵列C G1和C G2的规格参数完全相同；两组细调电容阵列C D1和C D2规格参数也完全相同；通过同步调节所述粗调电容阵列C G1和C G2，以及细调电容阵列C D1和C D2的电容值，进而调整输出的交流信号的频率。
  5. 如权利要求4所述的变压器型分布式多核振荡器，其特征在于：在所述变压器型分布式多核振荡器中，粗调电容阵列作为栅极谐振腔电容，细调电容阵列作为源级谐振腔电容； 栅极谐振腔电容和源级谐振腔电容的电容值之比为2～4。
  6. 如权利要求5所述的变压器型分布式多核振荡器，其特征在于：所述地端Vss和电源端Vdd之间连接一个电容器作为去耦合电容。
  7. 一种变压器型分布式多核振荡器的集成电路，其特征在于：其中包含如权利要求1-6中任意一项所述变压器型分布式多核振荡器电路结构；在集成电路的版图中，所述变压器型分布式多核振荡器还采用如下的布局方式：
    (1)将第一交叉耦合对和第二交叉耦合对相邻设置构成交叉耦合单元，并将交叉耦合单元设置于电路的中央；所述交叉耦合单元中，四个MOS管按照M1、M2、M4、M3的循环顺序排列在一个矩形区域的四角；任意两个相邻的MOS管结构对称；
    (2)将两个变压器单元设置在交叉耦合单元的外周，保持两个变压器单元结构对称；并将两个变压器单元T1和T2中的内侧线圈L d的两端交叉相连；
    (3)将粗调电容阵列和细调电容阵列设置在交叉耦合单元的外周，并保持粗调电容阵列靠外，细调电容阵列靠内；将其中一组细调电容阵列C D1和粗调电容阵列C G1设置在靠近第一交叉耦合的位置；另外一组细调电容阵列C D2和粗调电容阵列C G2设置在靠近第二交叉耦合对的位置；
    (4)将其中一组电源端Vdd和地端Vss设置在交叉耦合单元外周且靠近MOS管M1和M3的一侧；另一组电源端Vdd和地端Vss设置在交叉耦合单元外周且靠近MOS管M2和M4的一侧；使得电源端Vdd和地端Vss在集成电路的片内物理距离最短。
  8. 如权利要求7所述的集成电路，其特征在于：仅在两个变压器单元T1和T2分布的环形区域内设置NT_N层；交叉耦合单元位于不含有NT_N层的环形区域内部；粗调电容阵列和细调电容阵列位于不含有NT_N层的环形区域外部。
  9. 如权利要求7所述的集成电路，其特征在于，所述粗调电容阵列和细调电容阵列构成全差分电容阵列，并在MOS管中源极和地端Vss间连接尾电感单元；尾电感单元从不含NT_N层的环形区域内部穿出至电源端Vdd下方；电源端Vdd和地端Vss之间连接一个电容器作为去耦合电容。
  10. 一种终端，其特征在于：所述终端至少包括射频装置，以及如权利要求7-9中任意一项所述的变压器型分布式多核振荡器的集成电路，所述变压器型分布式多核振荡器的集成电路用于为所述射频装置提供本地载波信号。
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