WO2017011936A1 - 低共模耦合效应的集成电路 - Google Patents

低共模耦合效应的集成电路 Download PDF

Info

Publication number
WO2017011936A1
WO2017011936A1 PCT/CN2015/084308 CN2015084308W WO2017011936A1 WO 2017011936 A1 WO2017011936 A1 WO 2017011936A1 CN 2015084308 W CN2015084308 W CN 2015084308W WO 2017011936 A1 WO2017011936 A1 WO 2017011936A1
Authority
WO
WIPO (PCT)
Prior art keywords
connection end
line
differential
inductor
integrated circuit
Prior art date
Application number
PCT/CN2015/084308
Other languages
English (en)
French (fr)
Inventor
吴悦
贾天宇
Original Assignee
无锡中星微电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡中星微电子有限公司 filed Critical 无锡中星微电子有限公司
Priority to PCT/CN2015/084308 priority Critical patent/WO2017011936A1/zh
Priority to CN201580000906.6A priority patent/CN108028248B/zh
Publication of WO2017011936A1 publication Critical patent/WO2017011936A1/zh
Priority to US15/826,675 priority patent/US10396711B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/2804—Printed windings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/2823—Wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/29—Terminals; Tapping arrangements for signal inductances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6638—Differential pair signal lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006—Functional aspects of oscillators
    • H03B2200/0088—Reduction of noise

Definitions

  • the present invention relates to the design of an integrated circuit, and more particularly to an integrated circuit that has a low common mode coupling effect.
  • CMOS Complementary Metal-Oxide-Semiconductor Transistor
  • RFIC radio frequency integrated circuit
  • on-chip inductor has become a key component in radio frequency integrated circuits, and is widely used in filters, LNA (noise amplifier) and VCO (voltage control). Oscillator) and other circuits.
  • LNA noise amplifier
  • VCO voltage control
  • Oscillator Either an integrated circuit based on a GaAs (GaAs) process or a COMS process often uses multiple on-chip inductors.
  • GaAs GaAs
  • COMS COMS process
  • the on-chip inductor has a large area, and its coupling performance to other components directly affects the overall performance of the circuit, so the decoupling design of the on-chip inductor is very important. Many common decoupling techniques have been developed in many previous studies.
  • the radio frequency integrated circuit includes a voltage controlled oscillator 110, a frequency divider 120, an upconverter 130, and a drive amplifier 140.
  • the voltage controlled oscillator 110 includes a capacitor C1 and an inductor L1 connected in parallel, which can generate an oscillation clock signal having a frequency of fVCO.
  • the driving amplifier 140 performs power amplification on the initial RF signal to obtain an amplified RF signal, and the amplified RF signal is transmitted through the antenna 150.
  • the upconverter 130 includes Inductor L2 and capacitor C2 are connected in parallel.
  • the driver amplifier 140 includes a capacitor C3 and an inductor L3 connected in parallel, and an inductor L4 coupled to the inductor L3 to form a transformer.
  • the frequency of the even harmonics of the RF signal is 2*fS, which is close to the frequency of the oscillating clock signal output by the voltage controlled oscillator. Therefore, even harmonics of the RF signal can affect the voltage controlled oscillator to cause unwanted noise in the oscillating clock signal output by the voltage controlled oscillator.
  • a complicated calibration circuit is added to the voltage controlled oscillator in the prior art, or a different local oscillation signal is used to generate the circuit, but this causes additional power loss and a larger chip area.
  • an integrated circuit formed in a same wafer includes: a first circuit including a first inductor, the first circuit operating at a first frequency a second circuit comprising a second inductor that processes the input signal based on the second inductance, the frequency of the even harmonic of the input signal is located near the first frequency, the second inductor includes a first connection end, a second connection end, an intermediate connection end, an intermediate node, a first line connected between the first connection end and the intermediate node, a second line connected between the intermediate node and the second connection end, and connected to the intermediate node and the middle
  • the intermediate tap between the terminals, the first line and the second line extending to form one or more turns, the first connection end, the second connection end and the intermediate connection end being located on the same side of the coil and adjacent to each other.
  • the second circuit is a pseudo differential circuit
  • the pseudo differential circuit further includes a first difference branch and a second difference branch, and the first connection end of the second inductor and the first difference branch a connecting end is connected, a second connecting end of the first differential branch is connected to the second power end; a second connecting end of the second inductor is connected to the first connecting end of the second differential branch, and the second differential branch is connected The second connecting end is connected to the second power end; the intermediate connecting end of the second inductor is connected to the first power end; the first differential branch is provided with a first differential tube, and the second differential branch is provided with a second differential tube The loss of the second circuit
  • the input signal is a pair of differential input signals respectively input to the control end of the first differential tube and the control end of the second differential tube; a supply voltage is applied between the first power supply terminal and the second power supply terminal.
  • the first differential branch further includes a first biasing tube
  • the second differential branch is provided with a second biasing tube
  • the first biasing tube and the first differential tube are sequentially connected in series to the first differential branch
  • the control end of the first bias tube is connected to the bias voltage
  • the second bias tube and the second differential tube are sequentially connected in series to the first connection end of the second difference branch and Between the two terminals, the control end of the second bias tube is connected to the bias voltage.
  • the second circuit further includes a tuning capacitor connected between the intermediate connection end of the second inductor and the second power supply end, the tuning capacitor and the second inductor form a trap, and the resonant frequency of the trap is close to Or equal to the frequency of the even harmonics of the input signal.
  • first line and the second line are axially symmetric along an axis of symmetry, the first connecting end is adjacent to the symmetry axis and located at one side of the symmetry axis, and the second connecting end is adjacent to the symmetry axis and located On the other side of the axis of symmetry, the center tap is located on the axis of symmetry.
  • the intermediate tap does not pass through the center of the coil.
  • the first connection end to the intermediate connection end, from the second connection end to the intermediate connection end, or when the current flows from the intermediate connection end to the first connection end, and from the intermediate connection end to the second connection end the first The magnetic fields generated by the current flowing through the coil formed by the line and the second line can substantially cancel each other out.
  • the intermediate tap passes through the center of the coil.
  • a current flowing through a winding formed by the first line and the second line directly connected to the intermediate node and a magnetic field generated by a current flowing through some or all of the intermediate taps Substantially cancel each other, the magnetic fields generated by the current flowing through the other turns of the first and second lines substantially cancel each other out.
  • the second inductance in the present invention when the current flows from the first connection end to the intermediate connection end, from the second connection end to the intermediate connection end, or when the current flows from the intermediate connection end to the first
  • the connecting end when flowing from the intermediate connecting end to the second connecting end, the magnetic fields generated by the currents on the first line, the second line and the intermediate tap can substantially cancel each other out. This can reduce the common mode coupling effect between the first inductance and the second inductance.
  • FIG. 1 is a schematic diagram showing the circuit structure of an existing radio frequency integrated circuit in one embodiment.
  • 3A is a structural example of an on-chip inductor in the present invention.
  • 3B is a counterexample of an example of the on-chip inductor of FIG. 3A;
  • 4A is another structural example of the on-chip inductor in the present invention.
  • FIG. 4B is a counterexample of an example of the on-chip inductance of FIG. 4A;
  • FIG. 5A is still another structural example of the on-chip inductor in the present invention.
  • FIG. 5B is a counterexample of an example of the on-chip inductor of FIG. 5A; FIG.
  • Figure 6 is a schematic illustration of the position of two on-chip inductors on a wafer
  • Figure 7 shows the common mode coupling effect between the transmitter and the receiver when the transmitter adopts the on-chip inductor structure shown in Figures 3A, 3B, 4A, 4B, 5A, and 5B. Schematic diagram of the curve;
  • FIG. 8 is another schematic structural diagram of a pseudo-difference circuit in which a tuning capacitor is added, and an inductance thereof is displayed by a physical map;
  • Figure 9 is a diagram showing the voltage fluctuation curve of the power supply voltage of the pseudo-difference circuit of Figure 8 due to the even harmonic current of the input signal, wherein L1 is the voltage fluctuation curve when the tuning capacitor is not set, and L2 is the setting of the tuning capacitor. Voltage fluctuation curve.
  • both the up-converter 130 and the driver amplifier 140 in FIG. 1 have pseudo-difference circuits, and the pseudo-differential circuits generate a larger harmonic current of the input signal. Since the frequencies of these even harmonic currents are close to the frequency of the oscillating clock signal output by the voltage controlled oscillator 110, these even harmonic currents are coupled to the voltage controlled oscillator 110 via the inductance of these pseudo differential circuits. Inductively, noise is generated by an oscillating clock signal that causes the voltage controlled oscillator 110 to output.
  • Figure 2 illustrates an example of a pseudo differential circuit.
  • the pseudo differential circuit includes an inductor L21, an inductor L22, a first bias transistor M3, a second bias transistor M4, a first differential transistor M1, and a second differential transistor M2.
  • One end of the inductor L21 is connected to one end of the inductor L22 and is connected to the power supply voltage terminal VDD.
  • the first biasing tube M3 and the first differential tube M1 are sequentially connected in series between the other end of the inductor L21 and the ground GND.
  • the tube M4 and the second differential tube M2 are sequentially connected in series between the other end of the inductor L22 and the ground GND.
  • One of the pair of differential input signals is input to the control terminal of the first differential tube M1, and the other of the pair of differential input signals is input to the control terminal of the second differential tube M2, and the control terminal of the first biasing transistor M3 is connected to the bias voltage.
  • the control terminal of the second biasing transistor M4 is connected to the bias voltage.
  • the first biasing tube M3 and the first differential tube M1 form a first differential branch
  • the second biasing tube M4 and the second differential tube M2 form a second differential branch.
  • the biasing tube and the differential tube may be MOS field effect transistors, or may be bipolar transistors, or other types of transistors.
  • some other devices such as resistors, inductors, or transistors, may also be added to the pseudo differential circuit.
  • Inductor L21 and inductor L22 are structurally the same inductor. The two can also be referred to as an inductor, the intermediate connection of which is connected to the supply voltage terminal VDD.
  • the impedances Z1 and Z2 connected to the power supply voltage terminal VDD and the ground terminal GND are the parasitic impedances of the connection leads of the power supply voltage terminal VDD and the ground terminal GND.
  • the directions of the currents I1 and I2 of the even harmonics of the input pair of differential signals are as shown in FIG. 2, flowing from the inductor L21 to the first differential branch, and from the inductor L22 to the second differential branch.
  • the directions of the currents I1 and I2 of the even harmonics of the input pair of differential signals flow from the first difference branch to the inductor L21, respectively, from the second difference branch to the inductor L22.
  • the current of the even harmonic can be referred to as a common mode current, and the current of the even harmonic generates a magnetic field externally through the inductors L21 and L22, so that the coupling affects the inductance in the voltage controlled oscillator.
  • Fig. 3A is a structural example of the on-chip inductor in the present invention.
  • the on-chip inductor includes a first connection terminal A, a second connection terminal B, an intermediate connection terminal M, an intermediate node D, and a first line connected between the first connection terminal A and the intermediate node D.
  • a second line connected between the intermediate node D and the second connection terminal B and an intermediate tap connected between the intermediate node D and the intermediate connection terminal M.
  • the first line and the second line extend to form two turns of the coil.
  • the intermediate tap does not need to pass through the center of the coil, so that the first connection end A, the second connection end B and the intermediate connection end M are located on the same side of the coil and mutually adjacent.
  • the first line and the second line are axisymmetric along an axis of symmetry Ax, the first connecting end A is adjacent to the axis of symmetry and is located on one side of the axis of symmetry Ax, and the second connecting end B is adjacent to the axis of symmetry and Located on the other side of the axis of symmetry Ax, the intermediate tap is located on the axis of symmetry Ax.
  • the portion where the first line and the second line intersect is located in a different structural layer.
  • the partial inductance from the first connection terminal A to the intermediate connection terminal M may be the inductance L21 in FIG. 2, and the partial inductance from the second connection terminal B to the intermediate connection terminal M may be the inductance L22 in FIG.
  • the inductor in FIG. 3A can be used not only in the pseudo differential circuit shown in FIG. 2 but also in other circuits.
  • the magnetic fields generated by the current flowing through the coils formed by the first line and the second line can substantially cancel each other out.
  • the magnetic field generated by the current at the position of two or three (the area where the first connection end A, the second connection end B, and the intermediate connection end M are located) surrounded by the respective dotted circles in FIG. 3A is To cancel each other out, the arrow in the line in Figure 3A is the direction of the current.
  • the on-chip inductor shown in Figure 3A uses a magnetic field differential structure.
  • the number of turns of the on-chip inductor is even and two turns.
  • the number of turns of the coil formed by the first line and the second line can be It is other even numbers, such as 4 ⁇ , 6 ⁇ , etc., and its structure is basically similar to the structure shown in Fig. 3A.
  • the intermediate taps do not need to cross the center of the coil to ensure the first connection end A, the second connection end B and the middle.
  • the terminals M are located on the same side of the coil and adjacent to each other.
  • FIG. 3B is a counterexample of an example of the on-chip inductance of FIG. 3A.
  • the on-chip inductance is substantially the same as that in FIG. 3B, and the number of turns of the coil is two turns. The difference between the two is that the middle tap of the on-chip inductor in FIG. 3B crosses the first.
  • the intermediate connection end M is not adjacent to the first connection end A and the second connection end B and is located on a different side of the coil.
  • the large magnetic field generated by the on-chip inductor as a whole has a large common mode coupling effect on other inductors in the same chip.
  • the on-chip inductor shown in Figure 3B does not employ a magnetic field differential structure.
  • Fig. 4A is a structural example of the on-chip inductor in the present invention.
  • the on-chip inductance shown in FIG. 4A is basically the same as the on-chip inductor shown in FIG. 3A, and the difference between the two is that the number of turns of the coil formed by the first line and the second line in FIG. 4A is three turns, and the center tap
  • the center of the coil can be made such that the intermediate connection end M is adjacent to the first connection end A and the second connection end B and is located on the same side of the coil.
  • the first line and the second line are The magnetic fields generated by the currents flowing through the even turns of the even turns (two turns) substantially cancel each other out, and the current and the part flowing through a coil formed by the first line and the second line directly connected to the intermediate node D
  • the magnetic fields generated by the current flowing through the center tap substantially cancel each other out.
  • the magnetic field generated by the current at the position of two or three (the area where the first connection end A, the second connection end B, and the intermediate connection end M are located) surrounded by the respective dotted circles in FIG.
  • the on-chip inductor shown in Figure 4A uses a magnetic field differential structure.
  • the number of turns of the on-chip inductor is an odd number and is three turns.
  • the number of turns of the coil formed by the first line and the second line can be It is other odd numbers, such as 1 ⁇ , 5 ⁇ , 6 ⁇ , etc., and its structure is basically similar to the structure shown in FIG. 4A.
  • the middle tap needs to pass through the center of the coil to ensure the first connection end A and the second connection end B.
  • the intermediate connection end M are located on the same side of the coil and adjacent to each other.
  • FIG. 4B is a counterexample of an example of the on-chip inductance of FIG. 4A.
  • the on-chip inductance is substantially the same as that in FIG. 4B, and the number of turns of the coil is three turns.
  • the difference between the two is that the middle tap of the on-chip inductor in FIG. 4B does not cross the first a center of a coil surrounded by a line and a second line, an intermediate connection end M and a first connection end A and the second connection end B are not adjacent and are located on different sides of the coil.
  • the on-chip inductor shown in Figure 4B does not employ a magnetic field differential structure.
  • Fig. 5A is another structural example of the on-chip inductor in the present invention.
  • the on-chip inductance shown in FIG. 5A is substantially the same as the on-chip inductor shown in FIG. 3A, and the difference is that each of the turns formed by the first line and the second line in FIG. 5A includes the upper side.
  • the sub-coil and the lower sub-coil are two parts, wherein the first line and the second line are surrounded by two turns, and since it is an even-numbered turn, the intermediate tap can ensure the intermediate connection M and the first connection without passing through the center of the coil End A and second connecting end B are adjacent and located on the same side of the coil.
  • the on-chip inductor shown in FIG. 5A also adopts a magnetic field differential structure. When a common mode current flows through it, the magnetic field generated by the on-chip inductor is very small, and the common mode coupling effect on other inductors in the same chip is also Was greatly reduced.
  • each of the coils of the on-chip inductor includes two sub-coils, and one of ordinary skill in the art will recognize that each coil of the on-chip inductor may also include more sub-coils, such as three. 4, the structure of which is basically the same as that shown in FIG. 5A.
  • each coil has several sub-coils, as long as the number of turns of the coil is an even number, the intermediate tap of the on-chip inductor does not need to traverse the center of the coil surrounded by the first line and the second line, thereby ensuring the intermediate connection end M and the A connecting end A and a second connecting end B are adjacent to each other and on the same side of the coil; as long as the number of turns of the coil is an odd number, the middle tap of the on-chip inductor needs to cross the coil of the first line and the second line
  • the center can ensure that the intermediate connection end M is adjacent to the first connection end A and the second connection end B and is located on the same side of the coil.
  • FIG. 5B is a counterexample of an example of the on-chip inductance of FIG. 5A.
  • the on-chip inductance illustrated in FIG. 5B is substantially the same as the structure in FIG. 5B, and the difference between the two is that the center tap of the on-chip inductor in FIG. 5B traverses the coil surrounded by the first line and the second line. Center, the intermediate connection end M is different from the first connection end A and the second connection end B Adjacent and located on different sides of the coil.
  • the on-chip inductor shown in Figure 5B does not use a magnetic field differential structure. When a common mode current flows through it, the large magnetic field generated by the on-chip inductor as a whole has a common mode coupling effect on other inductors in the same chip. It will be larger.
  • the inductors L21 and L22 in order to reduce the coupling effect of the even harmonic current of the input signal on the external inductance on the inductors L21 and L22 in the pseudo differential circuit, the inductors L21 and L22 preferably adopt FIG. 3A.
  • Figure 6 shows the positional representation of the two on-chip inductors on the wafer.
  • the first on-chip inductor 610 and the second on-chip inductor 620 are shown, and the centers of the two inductors have distances ⁇ X and ⁇ Y along the X-axis and the Y-axis, respectively.
  • the first on-chip inductor 610 can be used as the transmitter (TX) inductor Ltx
  • the on-chip inductor 620 that is coupled to the receiver can be used as the receiver (RX) inductor Lrx.
  • TX transmitter
  • RX receiver
  • the inductors L21 and L22 in the pseudo-difference circuit can be used as the transmitter inductance, and the inductance in the voltage-controlled oscillator can be used as the receiver inductance.
  • the inductance center distances ⁇ X and ⁇ Y are much larger than the inductor radii Rtx and Rrx, it can be considered that the variation of the inductor radius has little effect on the coupling between the inductors.
  • FIG. 7 is a schematic diagram showing a common mode coupling effect curve between a transmitter inductor and a receiver inductor when the transmitter inductor 610 adopts the on-chip inductor structure shown in FIGS. 3A, 3B, 4A, and 4B, wherein the diamond frame is used.
  • the curve formed is a common mode coupling effect curve between the transmitter inductance and the receiver inductance when the transmitter inductor 610 adopts the on-chip inductor structure shown in FIG.
  • the curve formed by the square frame is the transmitter inductor 610 adopts the method of FIG. 4B.
  • the common mode coupling effect curve between the transmitter inductance and the receiver inductance is the transmitter inductance 610 when the on-chip inductor structure shown in FIG. 3A is used, the transmitter inductance and The common mode coupling effect curve between the receiver inductors, the curve formed by the triangular frame is the common mode coupling effect curve between the transmitter inductance and the receiver inductance when the transmitter inductor 610 adopts the on-chip inductor structure shown in FIG. 4A.
  • the difference The frequency of the input signal is about 2.5 GHz.
  • the common-mode coupling of the TX inductor and the RX inductor at 5 GHz (the frequency of the second harmonic) of the structure shown in Figures 3A and 4A is approximately - 55dB to -50dB, the common mode coupling effect between the two is small, and the common mode coupling of the TX inductor and the RX inductor at 5GHz shown in Figures 3B and 4B is about -25dB.
  • the common mode coupling effect is about 25 dB larger than the TX inductor using the magnetic field differential structure.
  • connection lead connecting the power supply voltage terminal VDD and the ground terminal GND has a parasitic impedance, and the current of the even harmonic of the differential input signal in the pseudo differential circuit may also pass the parasitic impedance.
  • Z1 and Z2 cause a voltage fluctuation of the power supply voltage, which may eventually be conducted to the power supply voltage terminal of the voltage controlled oscillator, thereby adversely affecting the voltage controlled oscillator.
  • the on-chip inductors L21 and L22 adopt a display manner of a physical map.
  • the pseudo differential circuit further includes a tuning capacitor C1 connected between the intermediate connection terminal (ie, the intermediate connection end and the ground terminal of the on-chip inductor of FIG. 3A) connected to the inductors L21 and L22 and the ground terminal.
  • the tuning capacitor C1 and the inductors L21 and L22 form a trap having a resonant frequency that is close to or equal to the frequency of the even harmonics of the differential input signal.
  • the even harmonic current of the differential input signal can be circulated between the inductors L21 and L22, the biasing tubes M3, M4, the differential tubes M1 and M2, and the tuning capacitor C1, which greatly reduces leakage to the power supply voltage.
  • the even harmonic current Ileak of the terminal VDD and the ground GND greatly reduces the influence of the even harmonic current on the power supply voltage.
  • L1 is a voltage fluctuation curve of the power supply voltage VDD when the trap is not set
  • L2 is a voltage fluctuation of the power supply voltage VDD after the trap is set. Curve, it can be seen that due to the setting of the notch, the voltage fluctuation is reduced by at least 15dB.
  • the power supply voltage terminal VDD is disposed adjacent to the ground GND, and they are connected to the corresponding node through mutually parallel leads, so that the leakage of the even harmonic current Ileak can be further reduced. magnetic field.
  • the on-chip inductance of the present invention is not only It can only be applied to the pseudo-differential circuit in the radio frequency integrated circuit shown in FIG. 2, and can also be applied to other circuits that need to reduce the common mode coupling effect between the on-chip inductors.
  • the influence of the even-harmonic current of the pseudo-difference circuit of the voltage-controlled oscillator is taken as an example. It is obvious that the voltage-controlled oscillator can be replaced with any other operating frequency close to the differential input. The frequency of the even harmonics of the signal, with an on-chip inductor.
  • the voltage controlled oscillator and the pseudo differential circuit are both located in the same radio frequency integrated circuit, and it is obvious that the two circuits that generate the common mode coupling effect may not necessarily belong to the same function circuit, they It can be two two circuits that are completely independent in function.
  • the present invention provides an integrated circuit formed in the same wafer, which includes a first circuit and a second circuit, the first circuit and the second circuit being functionally related or unrelated.
  • the first circuit includes a first inductance and operates at a first frequency.
  • the second circuit includes a second inductor that processes the input signal, the frequency of the even harmonics of the input signal being located adjacent the first frequency.
  • the even harmonics of the input signal can affect the first inductance in the first circuit based on the second inductive coupling, and in turn affect the performance of the first circuit.
  • the second inductor may be configured by using a magnetic field differential structure as described above, such as the on-chip inductors shown in FIGS. 3A, 4A, and 5A.
  • the magnetic field generated when the common mode current flows through the second inductance is reduced.
  • the second circuit further includes a tuning capacitor connected between the intermediate connection end of the second inductor and the ground, the tuning capacitor and the second inductor forming a trap, the trap of the trap
  • the resonant frequency is close to or equal to the frequency of the even harmonics of the input signal. This can further reduce the effect of the even harmonic current on the supply voltage in the second circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种集成电路，其形成于同一个晶片内，其包括：工作于第一频率的第一电路，其包括第一电感；包括第二电感的第二电路，其对输入信号进行处理，该输入信号的偶次谐波的频率位于所述第一频率附近，该第二电感包括第一连接端（A）、第二连接端（B）、中间连接端（M）、中间节点（D）、连接于第一连接端（A）和中间节点（D）之间的第一线路、连接于中间节点（D）和第二连接端（B）之间的第二线路以及连接于中间节点（D）和中间连接端（M）之间的中间抽头，第一线路和第二线路延伸形成一匝或多匝线圈。在电流从第一连接端（A）流向中间连接端（M），从第二连接端（B）流向中间连接端（M）时，第一线路、第二线路和中间抽头上的电流产生的磁场能够基本互相抵消，从而降低了第二电路对第一电路的共模耦合的影响。

Description

低共模耦合效应的集成电路 技术领域
本发明涉及一种集成电路的设计，特别是涉及低共模耦合效应的集成电路。
背景技术
在CMOS(Complementary Metal-Oxide-Semiconductor Transistor)射频集成电路(RFIC)发展中，片上电感已成为射频集成电路中的关键元件，并被广泛应用于滤波器，LNA(噪声放大器)以及VCO(压控振荡器)等电路。无论是基于GaAs(砷化镓)工艺，还是COMS工艺的集成电路，往往都使用了多个片上电感。片上电感的面积大，而且其对于其他元件的耦合性能直接影响电路的整体性能，所以片上电感的去耦合设计十分重要。在之前的众多研究中，也已经形成了许多常用的去耦合技术。如在片上电感下方设计Patterned Shielding(格栅屏蔽)或电感四周设计Guard Ring(保护环)等结构减小电感对外耦合。但是之前的这些去耦合设计往往只是默认为在差模电流输入情况下，而忽略了共模输入电流的耦合影响。在现有技术中，对于如何消除片上电感之间的共模耦合影响并没有足够的重视和研究。
图1示出了现有的射频集成电路在一个实施例中的电路结构示意图。如图1所示，所述射频集成电路包括压控振荡器110、分频器120、上变频器130、驱动放大器140。
所述压控振荡器110包括有并联的电容C1和电感L1，其可以产生频率为fVCO振荡时钟信号。分频器120将振荡时钟信号进行二分频得到两个相位相差90度的本地振荡时钟信号，其中本地振荡时钟信号的频率fLO＝fVCO/2。上变频器130基于本地振荡时钟信号将基带输入信号调制为初始射频信号，其中基带输入信号的频率为fm，初始射频信号的频率为fS，其中fS＝fLO+fm。驱动放大器140将所述初始射频信号进行功率放大得到放大的射频信号，放大后的射频信号经过天线150发射出去。所述上变频器130包括有 并联的电感L2和电容C2。驱动放大器140包括并联的电容C3和电感L3，以及与电感L3耦合成变压器的电感L4。射频信号的偶次谐波的频率为2*fS，其与压控振荡器输出的振荡时钟信号的频率接近。因此，射频信号的偶次谐波会影响到所述压控振荡器，以导致所述压控振荡器输出的振荡时钟信号中存在不需要的噪声。为了克服这些问题，现有技术中或者在压控振荡器中加入复杂的校准电路，或者采用不同的本地振荡信号产生电路，然而这样会造成额外的功率损耗以及更大的芯片面积。
因此，有必要提出一种改进的技术方案来解决上述问题。
发明内容
本发明的目的在于提供一种集成电路，其可以降低集成电路中的两个电感之间的共模耦合效应。
为了实现上述目的，根据本发明的一个方面，本发明提供一种集成电路，其形成于同一个晶片内，其包括：第一电路，其包括第一电感，该第一电路工作于第一频率；第二电路，其包括第二电感，其基于第二电感对输入信号进行处理，该输入信号的偶次谐波的频率位于所述第一频率附近，该第二电感包括第一连接端、第二连接端、中间连接端、中间节点、连接于第一连接端和中间节点之间的第一线路、连接于中间节点和第二连接端之间的第二线路以及连接于中间节点和中间连接端之间的中间抽头，第一线路和第二线路延伸形成一匝或多匝线圈，第一连接端、第二连接端和中间连接端位于所述线圈的同侧且互相相邻。
进一步的，该第二电路为一个伪差分电路，该伪差分电路还包括有第一差分支路和第二差分支路，所述第二电感的第一连接端与第一差分支路的第一连接端相连，第一差分支路的第二连接端连接于第二电源端；所述第二电感的第二连接端与第二差分支路的第一连接端相连，第二差分支路的第二连接端连接于第二电源端；所述第二电感的中间连接端连接第一电源端；第一差分支路上设置有第一差分管，第二差分支路上设置有第二差分管，第二电路的所述输 入信号为一对差分输入信号，该对差分输入信号分别输入第一差分管的控制端和第二差分管的控制端；在第一电源端和第二电源端之间施加电源电压。
进一步的，第一差分支路还包括有第一偏置管，第二差分支路上设置有第二偏置管，第一偏置管和第一差分管依次串联于第一差分支路的第一连接端和第二连接端之间，第一偏置管的控制端与偏置电压相连，第二偏置管和第二差分管依次串联于第二差分支路的第一连接端和第二连接端之间，第二偏置管的控制端与偏置电压相连。
进一步的，第二电路还包括连接于所述第二电感的中间连接端和第二电源端之间的调谐电容，该调谐电容和第二电感形成陷波器，该陷波器的谐振频率接近或等于所述输入信号的偶次谐波的频率。
进一步的，在电流从第一连接端流向中间连接端，从第二连接端流向中间连接端时，或，在电流从中间连接端流向第一连接端，从中间连接端流向第二连接端时，第一线路、第二线路和中间抽头上的电流产生的磁场能够基本互相抵消。
进一步的，第一线路和第二线路沿一对称轴成轴对称图形，第一连接端与该对称轴相邻并位于该对称轴的一侧，第二连接端与该对称轴相邻并位于该对称轴的另一侧，所述中间抽头位于所述对称轴上。
进一步的，在所述线圈的匝数为偶数时，所述中间抽头未穿过所述线圈的中心。在电流从第一连接端流向中间连接端，从第二连接端流向中间连接端时，或，在电流从中间连接端流向第一连接端，从中间连接端流向第二连接端时，第一线路和第二线路形成的所述线圈上流过的电流产生的磁场能够基本互相抵消。
进一步的，在所述线圈的匝数为奇数时，所述中间抽头穿越所述线圈的中心。在电流从第一连接端流向中间连接端，从第二连接端流向中间连接端时，或，在电流从中间连接端流向第一连接端， 从中间连接端流向第二连接端时，与所述中间节点直接相连的由第一线路和第二线路形成的一匝线圈上流过的电流与部分或全部中间抽头上流过的电流所产生的磁场基本相互抵消，由第一线路和第二线路形成的其它匝线圈上流过的电流所产生的磁场基本相互抵消。
与现有技术相比，对于本发明中的第二电感，在电流从第一连接端流向中间连接端，从第二连接端流向中间连接端时，或，在电流从中间连接端流向第一连接端，从中间连接端流向第二连接端时，第一线路、第二线路和中间抽头上的电流产生的磁场能够基本互相抵消。这样可以降低第一电感和第二电感之间的共模耦合效应。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。其中：
图1为现有的射频集成电路在一个实施例中的电路结构示意图。
图2为伪差分电路的结构示意图；
图3A为本发明中的片上电感的一种结构示例；
图3B为图3A中的片上电感的示例的反例；
图4A为本发明中的片上电感的另一种结构示例；
图4B为图4A中的片上电感的示例的反例；
图5A为本发明中的片上电感的再一种结构示例；
图5B为图5A中的片上电感的示例的反例；
图6为晶片上的两个片上电感的位置示意；
图7示出了发射机采用图3A、图3B、图4A、图4B、图5A、图5B所示的片上电感结构时，发射机和接收机之间的共模耦合效 应曲线示意图；
图8为伪差分电路的另一种结构示意图，其中增加了调谐电容，其上的电感采用了实物图的显示方式；
图9示意出了图8中的伪差分电路的电源电压由于输入信号的偶次谐波电流导致的电压波动曲线，其中L1为未设置调谐电容时的电压波动曲线，L2为设置调谐电容后的电压波动曲线。
具体实施方式
下面结合附图来详细介绍一下本发明的具体实施方式。
根据分析和实验发现，图1中的上变频器130以及驱动放大器140中都具有伪差分电路，这些伪差分电路上会产生较大的输入信号的偶次谐波电流。由于这些偶次谐波电流的频率与压控振荡器110输出的振荡时钟信号的频率接近，因此这些偶次谐波电流就会经由这些伪差分电路的电感耦合至所述压控振荡器110的电感上，以导致所述压控振荡器110输出的振荡时钟信号产生噪声。
图2示意出了一种伪差分电路的示例。所述伪差分电路包括电感L21、电感L22、第一偏置管M3、第二偏置管M4、第一差分管M1和第二差分管M2。电感L21的一端和电感L22的一端相连后与电源电压端VDD相连，第一偏置管M3和第一差分管M1依次串联于所述电感L21的另一端和接地端GND之间，第二偏置管M4和第二差分管M2依次串联于所述电感L22的另一端和接地端GND之间。一对差分输入信号中的一个输入第一差分管M1的控制端，该对差分输入信号的另一个输入第二差分管M2的控制端，第一偏置管M3的控制端与偏置电压相连，第二偏置管M4的控制端与该偏置电压相连。第一偏置管M3和第一差分管M1形成了第一差分支路，第二偏置管M4和第二差分管M2形成了第二差分支路。
在具体实现时，所述偏置管和所述差分管可以是MOS场效应晶体管，也可以是双极型晶体管，或其他类型的晶体管。在有些的实施例中，还可以在伪差分电路中增加一些其他器件，比如电阻、电感或晶体管等。电感L21和电感L22在结构上属于同一个电感， 两者也可以被称为一个电感，该电感的中间连接端与电源电压端VDD相连。在图2中，与电源电压端VDD和接地端GND相连的阻抗Z1和Z2为电源电压端VDD和接地端GND的连接引线的寄生阻抗。
在一个时刻，输入的一对差分信号的偶次谐波的电流I1和I2的方向如图2所示的，是从电感L21流向第一差分支路，从电感L22流向第二差分支路。在另一个时刻，输入的一对差分信号的偶次谐波的电流I1和I2的方向，分别是从第一差分支路流向电感L21，是从第二差分支路流向电感L22。此时，该偶次谐波的电流可以被称为共模电流，该偶次谐波的电流会通过电感L21和L22对外产生磁场，以耦合影响到压控振荡器中的电感。
图3A为本发明中的片上电感的一种结构示例。如图3A所示的，所述片上电感包括第一连接端A、第二连接端B、中间连接端M、中间节点D、连接于第一连接端A和中间节点D之间的第一线路、连接于中间节点D和第二连接端B之间的第二线路以及连接于中间节点D和中间连接端M之间的中间抽头。第一线路和第二线路延伸形成两匝线圈。由于线圈的匝数为偶数，所述中间抽头无需穿过所述线圈的中心，就可以保证第一连接端A、第二连接端B和中间连接端M位于所述线圈的同侧且互相相邻。第一线路和第二线路沿一对称轴Ax成轴对称图形，第一连接端A与该对称轴相邻并位于该对称轴Ax的一侧，第二连接端B与该对称轴相邻并位于该对称轴Ax的另一侧，所述中间抽头位于所述对称轴Ax上。第一线路和第二线路交叉的部分位于不同的结构层中。
从第一连接端A至中间连接端M的部分电感可以是图2中的电感L21，从第二连接端B至中间连接端M的部分电感可以是图2中的电感L22。当然，图3A中的电感不仅可以用于图2所示的伪差分电路中，还可以用于其他电路中。
如图3A所示的，在该片上电感上流过共模电流时，即电流从A流向M且从B流向M，或者电流从M流向A且从M流向B时， 由于几乎所有相邻的线路中的电流都大小相等、方向相反，因此第一线路和第二线路形成的所述线圈上流过的电流产生的磁场能够基本互相抵消。举例来说，图3A中各个虚线圈所围绕的两个或三个(第一连接端A、第二连接端B和中间连接端M所在的区域)相邻线路的位置处电流产生的磁场是相互抵消的，图3A中线路中的箭头是电流的方向。这样，在该片上电感上流过共模电流时，片上电感整体上产生的磁场非常小，其对同晶片内的其他电感的共模耦合效应也被大大降低。简单来说，图3A所示的片上电感采用了磁场差分结构。
如图3A所示，其中的片上电感的线圈匝数是偶数，且为两匝，所属领域内的普通技术人员所能够知晓的是，第一线路和第二线路所形成的线圈的匝数可以是其他偶数匝，比如4匝、6匝等，其结构与图3A所示的结构基本类似，中间抽头都无需穿越线圈的中心，就可以确保第一连接端A、第二连接端B和中间连接端M位于所述线圈的同侧且互相相邻。
图3B为图3A中的片上电感的示例的反例。在图3B中，其示意出的片上电感与图3B的中结构基本相同，线圈的匝数都是两圈，两者的区别之处在于：图3B中的片上电感的中间抽头穿越了第一线路和第二线路围成的线圈的中心，中间连接端M与第一连接端A和第二连接端B不相邻且位于所述线圈的不同侧。很显然，在该片上电感上流过共模电流时，第一线路和第二线路形成的所述线圈上流过的电流产生的磁场依然能够基本互相抵消，然而长距离的中间抽头上的电流所产生的磁场则无法被抵消。这样，在图3B所示的片上电感上流过共模电流时，该片上电感会形成从第一连接端A和第二连接端B至中间连接端M的一条路径，其上流过的电流所生成的磁场无法被抵消，其余线路上的电流所产生的磁场都被互相抵消了。这样所述片上电感整体上会产生的较大的磁场，其对同晶片内的其他电感的共模耦合效应也会较大。简单的来说，图3B所示的片上电感未采用了磁场差分结构。
图4A为本发明中的片上电感的一种结构示例。图4A所示的片上电感与图3A所示的片上电感的结构基本相同，两者的差别是：图4A中的第一线路和第二线路所形成的线圈的匝数为三圈，中间抽头穿过所述线圈的中心才能够使得中间连接端M与第一连接端A、第二连接端B相邻且位于所述线圈的同侧。
如图4A所示的，在该片上电感上流过共模电流时，即电流从A流向M且从B流向M或者电流从M流向A且从M流向B时，由第一线路和第二线路形成的偶数匝(两匝)的线圈上流过的电流所产生的磁场基本相互抵消，与所述中间节点D直接相连的由第一线路和第二线路形成的一匝线圈上流过的电流与部分中间抽头上流过的电流所产生的磁场基本相互抵消。举例来说，图4A中各个虚线圈所围绕的两个或三个(第一连接端A、第二连接端B和中间连接端M所在的区域)相邻线路的位置处电流产生的磁场是相互抵消的，前两个线圈上的电流所产生的磁场是互相抵消的，最内侧的线圈与部分中间抽头形成两个环，它们上的电流所产生的磁场基本互相抵消。这样，在该片上电感上流过共模电流时，片上电感整体上产生的磁场非常小，其对同晶片内的其他电感的共模耦合效应也被大大降低。简单的来说，图4A所示的片上电感采用了磁场差分结构。
如图4A所示，其中的片上电感的线圈匝数是奇数，且为三匝，所属领域内的普通技术人员所能够知晓的是，第一线路和第二线路所形成的线圈的匝数可以是其他奇数匝，比如1匝、5匝、6匝等，其结构与图4A所示的结构基本类似，中间抽头需穿越线圈的中心，方可确保第一连接端A、第二连接端B和中间连接端M位于所述线圈的同侧且互相相邻。
图4B为图4A中的片上电感的示例的反例。在图4B中，其示意出的片上电感与图4B的中结构基本相同，线圈的匝数都是三圈，两者的区别之处在于：图4B中的片上电感的中间抽头未穿越了第一线路和第二线路围成的线圈的中心，中间连接端M与第一连接端 A和第二连接端B不相邻且位于所述线圈的不同侧。很显然，在该片上电感上流过共模电流时，最内侧的线圈上的电流所产生的磁场无法被抵消，其整体上会产生的较大的磁场，其对同晶片内的其他电感的共模耦合效应也会较大。简单的来说，图4B所示的片上电感未采用了磁场差分结构。
图5A为本发明中的片上电感的另一种结构示例。图5A所示的片上电感与图3A所示的片上电感的结构基本相同，两者的差别是：图5A中的第一线路和第二线路所形成的每匝线圈包括有位于上侧的上子线圈和下子线圈两部分，其中第一线路和第二线路围绕成的匝数为两匝，由于是偶数匝线圈，中间抽头无需穿过线圈的中心就可以保证中间连接端M与第一连接端A和第二连接端B相邻且位于所述线圈的同侧。同样的，图5A所示的片上电感也采用了磁场差分结构，在其上流过共模电流时，片上电感整体上产生的磁场非常小，其对同晶片内的其他电感的共模耦合效应也被大大降低。
如图5A所示，其中的片上电感的每个线圈包括有两个子线圈，所属领域内的普通技术人员所能够知晓的是，片上电感的每个线圈还可以包括更多个子线圈，比如3个，4个，其结构与图5A所示的结构基本相同。不论每个线圈具有几个子线圈，只要所述线圈的匝数为偶数，则片上电感的中间抽头无需穿越第一线路和第二线路围成的线圈的中心，即可确保中间连接端M与第一连接端A和第二连接端B相邻且位于所述线圈的同侧；只要是线圈的匝数为奇数，则片上电感的中间抽头需穿越第一线路和第二线路围成的线圈的中心，方可确保中间连接端M与第一连接端A和第二连接端B相邻且位于所述线圈的同侧。
图5B为图5A中的片上电感的示例的反例。在图5B中，其示意出的片上电感与图5B的中结构基本相同，两者的区别之处在于：图5B中的片上电感的中间抽头穿越了第一线路和第二线路围成的线圈的中心，中间连接端M与第一连接端A和第二连接端B不相 邻且位于所述线圈的不同侧。很显然，图5B所示的片上电感未采用了磁场差分结构，在其上流过共模电流时，片上电感整体上产生的较大的磁场，其对同晶片内的其他电感的共模耦合效应也会较大。
如图2所示的，为了降低所述伪差分电路中的电感L21和L22上因输入信号的偶次谐波电流对外部电感产生的耦合效应，所述电感L21和L22优选的采用图3A、图4A和图5A所示的采用磁场差分结构的片上电感。
图6示出了晶片上的两个片上电感的位置示意。如图6所示的，其示出了第一片上电感610和第二片上电感620，两个电感的中心沿X轴和Y轴的距离分别为△X和△Y。在讨论两个电感之间的耦合时，可以将第一片上电感610作为发射机(TX)电感Ltx，而被耦合影响到的片上电感620作为接收机(RX)电感Lrx。举例来说，在图1和图2所示的示例中，伪差分电路中的电感L21和L22可以作为发射机电感，而压控振荡器中的电感可以则作为接收机电感。在电感中心距△X和△Y远远大于电感半径Rtx和Rrx时，可以认为电感半径的变化对于电感间的耦合影响不大。
以图6中情况为例，设计Ltx＝1nH，Lrx＝2nH，△X＝△Y＝1000um>>Rtx,Rrx，Lrx的线圈为5匝。图7示出了发射机电感610采用图3A、图3B、图4A、图4B所示的片上电感结构时，发射机电感和接收机电感之间的共模耦合效应曲线示意图，其中菱形框所形成的曲线为发射机电感610采用图3B所示的片上电感结构时，发射机电感和接收机电感之间的共模耦合效应曲线，方形框所形成的曲线为发射机电感610采用图4B所示的片上电感结构时，发射机电感和接收机电感之间的共模耦合效应曲线，圆形框所形成的曲线为发射机电感610采用图3A所示的片上电感结构时，发射机电感和接收机电感之间的共模耦合效应曲线，三角形框所形成的曲线为发射机电感610采用图4A所示的片上电感结构时，发射机电感和接收机电感之间的共模耦合效应曲线。在一个实例中，差分 输入信号的频率为2.5GHz左右，从图7中可以看出，图3A和图4A所示的结构的TX电感与RX电感在5GHz(二次谐波的频率)处的共模耦合大约为-55dB至-50dB，两者之间的共模耦合影响很小，而图3B和图4B所示的结构的TX电感与RX电感在5GHz处的共模耦合大约为-25dB，两者之间的共模耦合影响较采用磁场差分结构的TX电感要大大约25dB。
经过分析发现，如图2所示的，连接电源电压端VDD和接地端GND的连接引线具有寄生阻抗，该伪差分电路中的差分输入信号的偶次谐波的电流还可能通过所述寄生阻抗Z1和Z2而导致电源电压产生电压波动，该电压波动可能会最终传导至所述压控振荡器的电源电压端，进而对压控振荡器产生不利影响。
为了解决该问题，在本发明提出了一种改进的伪差分电路，如图8所示的，所述片上电感L21和L22采用了实物图的显示方式。该伪差分电路还包括连接于电感L21和L22的中间连接端(即如图3A片上电感的中间连接端和接地端)和接地端之间连接调谐电容C1。该调谐电容C1和电感L21和L22形成陷波器，该陷波器的谐振频率接近或等于所述差分输入信号的偶次谐波的频率。这样，差分输入信号的偶次谐波电流可以在所述电感L21和L22、偏置管M3、M4、差分管M1和M2、调谐电容C1之间循环流通，这样大大的降低了泄漏至电源电压端VDD和接地端GND的偶次谐波电流Ileak，从而大大降低了偶次谐波电流对电源电压的影响。
如图9所示的，在存在输入信号的偶次谐波电流的情况下，L1为不设置陷波器时电源电压VDD的电压波动曲线，L2为设置陷波器后电源电压VDD的电压波动曲线，可见由于设置了陷波器，电压波动至少降低了15dB。
在一个更为优选的实施例中，电源电压端VDD与接地端GND相邻设置，他们通过相互平行的引线连接至对应的节点，这样，可以进一步的降低泄漏的偶次谐波电流Ileak产生的磁场。
所属领域内的技术人员所熟知的是，本发明中的片上电感不仅 仅可以应用于图2所示的射频集成电路中的伪差分电路中，还可以应用于其它需要降低片上电感之间的共模耦合效应的电路中。在上文中，以所述压控振荡器被伪差分电路的偶次谐波电流的影响为例进行介绍，很显然，所述压控振荡器可以被替换为其他任何工作频率接近所述差分输入信号的偶次谐波的频率的，具有一个片上电感的电路。此外，在上文中，所述压控振荡器和所述伪差分电路都位于同一个射频集成电路中，很显然，产生共模耦合效应的两个电路可以不一定属于同一个功能的电路，他们可以是两个功能上完全独立的两个电路。
综上所述，本发明在于提供一种形成于同一个晶片内的集成电路，其包括第一电路和第二电路，该第一电路和第二电路功能上可以相关，也可以不相关。该第一电路包括第一电感且工作于第一频率。第二电路包括第二电感，其对输入信号进行处理，该输入信号的偶次谐波的频率位于所述第一频率附近。这样，该输入信号的偶次谐波会基于第二电感耦合影响到第一电路中的第一电感，并进而影响到第一电路的性能。为了降低第一电感和第二电感之间的共模耦合影响，可以让该第二电感采用上文所述的采用了磁场差分结构，比如图3A、4A和图5A所示的片上电感，以降低在共模电流流过第二电感时所产生的磁场。
在一个优选的实施例中，第二电路还包括连接于所述第二电感的中间连接端和接地端之间的调谐电容，该调谐电容和第二电感形成陷波器，该陷波器的谐振频率接近或等于所述输入信号的偶次谐波的频率。这样可以进一步降低偶次谐波电流对第二电路中的电源电压造成的影响。
上述说明已经充分揭露了本发明的具体实施方式。需要指出的是，熟悉该领域的技术人员对本发明的具体实施方式所做的任何改动均不脱离本发明的权利要求书的范围。相应地，本发明的权利要求的范围也并不仅仅局限于前述具体实施方式。

Claims (12)

  1. 一种集成电路，其形成于同一个晶片内，其特征在于，其包括：
    第一电路，其包括第一电感，该第一电路工作于第一频率；
    第二电路，其包括第二电感，其基于第二电感对输入信号进行处理，该输入信号的偶次谐波的频率位于所述第一频率附近，
    该第二电感包括第一连接端、第二连接端、中间连接端、中间节点、连接于第一连接端和中间节点之间的第一线路、连接于中间节点和第二连接端之间的第二线路以及连接于中间节点和中间连接端之间的中间抽头，第一线路和第二线路延伸形成一匝或多匝线圈，第一连接端、第二连接端和中间连接端位于所述线圈的同侧且互相相邻。
  2. 根据权利要求1所述的集成电路，其特征在于，该第二电路为一个伪差分电路，该伪差分电路还包括有第一差分支路和第二差分支路，
    所述第二电感的第一连接端与第一差分支路的第一连接端相连，第一差分支路的第二连接端连接于第二电源端；所述第二电感的第二连接端与第二差分支路的第一连接端相连，第二差分支路的第二连接端连接于第二电源端；所述第二电感的中间连接端连接第一电源端；
    第一差分支路上设置有第一差分管，第二差分支路上设置有第二差分管，第二电路的所述输入信号为一对差分输入信号，该对差分输入信号分别输入第一差分管的控制端和第二差分管的控制端；
    在第一电源端和第二电源端之间施加电源电压。
  3. 根据权利要求2所述的集成电路，其特征在于，第一电源端为电源电压端，第二电源端为接地端，第一电源端与第二电源端相邻设置，他们通过相互平行的线路连接至对应的节点。
  4. 根据权利要求2所述的集成电路，其特征在于，第一差分支路还包括有第一偏置管，第二差分支路上设置有第二偏置管，第 一偏置管和第一差分管依次串联于第一差分支路的第一连接端和第二连接端之间，第一偏置管的控制端与偏置电压相连，第二偏置管和第二差分管依次串联于第二差分支路的第一连接端和第二连接端之间，第二偏置管的控制端与偏置电压相连。
  5. 根据权利要求1所述的集成电路，其特征在于，该第一电路为压控振荡器，其基于该第一电感生成第一频率的时钟信号。
  6. 根据权利要求1所述的集成电路，其特征在于，第二电路还包括连接于所述第二电感的中间连接端和第二电源端之间的调谐电容，
    该调谐电容和第二电感形成陷波器，该陷波器的谐振频率接近或等于所述输入信号的偶次谐波的频率。
  7. 根据权利要求1所述的集成电路，其特征在于，在电流从第一连接端流向中间连接端，从第二连接端流向中间连接端时，或，在电流从中间连接端流向第一连接端，从中间连接端流向第二连接端时，第一线路、第二线路和中间抽头上的电流产生的磁场能够基本互相抵消。
  8. 根据权利要求7所述的集成电路，其特征在于，第一线路和第二线路沿一对称轴成轴对称图形，第一连接端与该对称轴相邻并位于该对称轴的一侧，第二连接端与该对称轴相邻并位于该对称轴的另一侧，所述中间抽头位于所述对称轴上。
  9. 根据权利要求7所述的集成电路，其特征在于，在所述线圈的匝数为偶数时，所述中间抽头未穿过所述线圈的中心。
  10. 根据权利要求9所述的集成电路，其特征在于，在电流从第一连接端流向中间连接端，从第二连接端流向中间连接端时，或，在电流从中间连接端流向第一连接端，从中间连接端流向第二连接端时，第一线路和第二线路形成的所述线圈上流过的电流产生的磁场能够基本互相抵消。
  11. 根据权利要求7所述的集成电路，其特征在于，在所述线 圈的匝数为奇数时，所述中间抽头穿越所述线圈的中心。
  12. 根据权利要求11所述的集成电路，其特征在于，
    在电流从第一连接端流向中间连接端，从第二连接端流向中间连接端时，或，在电流从中间连接端流向第一连接端，从中间连接端流向第二连接端时，
    与所述中间节点直接相连的由第一线路和第二线路形成的一匝线圈上流过的电流与部分或全部中间抽头上流过的电流所产生的磁场基本相互抵消，由第一线路和第二线路形成的其它匝线圈上流过的电流所产生的磁场基本相互抵消。
PCT/CN2015/084308 2015-07-17 2015-07-17 低共模耦合效应的集成电路 WO2017011936A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/CN2015/084308 WO2017011936A1 (zh) 2015-07-17 2015-07-17 低共模耦合效应的集成电路
CN201580000906.6A CN108028248B (zh) 2015-07-17 2015-07-17 低共模耦合效应的集成电路
US15/826,675 US10396711B2 (en) 2015-07-17 2017-11-30 Integrated circuits having on-chip inductors with low common mode coupling effect

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2015/084308 WO2017011936A1 (zh) 2015-07-17 2015-07-17 低共模耦合效应的集成电路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/826,675 Continuation US10396711B2 (en) 2015-07-17 2017-11-30 Integrated circuits having on-chip inductors with low common mode coupling effect

Publications (1)

Publication Number Publication Date
WO2017011936A1 true WO2017011936A1 (zh) 2017-01-26

Family

ID=57833576

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/084308 WO2017011936A1 (zh) 2015-07-17 2015-07-17 低共模耦合效应的集成电路

Country Status (3)

Country Link
US (1) US10396711B2 (zh)
CN (1) CN108028248B (zh)
WO (1) WO2017011936A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI643216B (zh) * 2017-11-10 2018-12-01 瑞昱半導體股份有限公司 積體電感
WO2019218371A1 (zh) * 2018-05-18 2019-11-21 华为技术有限公司 一种振荡器的集成电路
KR102605442B1 (ko) 2019-01-10 2023-11-23 삼성전자주식회사 차동 신호를 처리하는 전자 회로를 포함하는 장치
CN112086429B (zh) * 2019-06-13 2022-07-05 中芯国际集成电路制造(上海)有限公司 电感结构及其形成方法
TWI722952B (zh) * 2019-09-11 2021-03-21 瑞昱半導體股份有限公司 電感裝置
TWI722946B (zh) * 2019-09-11 2021-03-21 瑞昱半導體股份有限公司 半導體裝置
TWI691979B (zh) * 2019-10-24 2020-04-21 威鋒電子股份有限公司 晶片內建電感結構
CN113130170B (zh) * 2019-12-31 2023-08-04 瑞昱半导体股份有限公司 电感装置
TWI697920B (zh) * 2019-12-31 2020-07-01 瑞昱半導體股份有限公司 積體電感
CN112968670B (zh) * 2021-02-01 2022-11-08 电子科技大学 一种小型化离散耦合多核振荡器
US11837995B2 (en) * 2021-05-25 2023-12-05 Mediatek Inc. One-coil multi-core inductor-capacitor oscillator
US11652444B2 (en) * 2021-09-20 2023-05-16 Apple Inc. Inductor topology for phase noise reduction
TWI796910B (zh) * 2021-12-29 2023-03-21 威鋒電子股份有限公司 多層式晶片內建電感結構
CN116403800A (zh) * 2023-06-09 2023-07-07 麦斯塔微电子(深圳)有限公司 电感装置、谐振电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8102216B1 (en) * 2009-05-06 2012-01-24 Qualcomm Atheros, Inc. Voltage controlled oscillator having reduced phase noise
CN103095217A (zh) * 2013-01-16 2013-05-08 东南大学 低相位噪声压控振荡器
CN103117745A (zh) * 2013-03-19 2013-05-22 苏州朗宽电子技术有限公司 一种具有低相位噪声的压控振荡器
CN103928446A (zh) * 2014-04-30 2014-07-16 无锡中星微电子有限公司 低共模耦合效应的片上电感及其设计方法
CN204425279U (zh) * 2015-03-26 2015-06-24 成都爱洁隆信息技术有限公司 一种高增益低噪声放大器

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7848713B2 (en) * 2007-09-10 2010-12-07 Qualcomm Incorporated Common mode signal attenuation for a differential duplexer
EP2669906B1 (en) * 2012-06-01 2018-08-29 Nxp B.V. An integrated circuit based transformer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8102216B1 (en) * 2009-05-06 2012-01-24 Qualcomm Atheros, Inc. Voltage controlled oscillator having reduced phase noise
CN103095217A (zh) * 2013-01-16 2013-05-08 东南大学 低相位噪声压控振荡器
CN103117745A (zh) * 2013-03-19 2013-05-22 苏州朗宽电子技术有限公司 一种具有低相位噪声的压控振荡器
CN103928446A (zh) * 2014-04-30 2014-07-16 无锡中星微电子有限公司 低共模耦合效应的片上电感及其设计方法
CN204425279U (zh) * 2015-03-26 2015-06-24 成都爱洁隆信息技术有限公司 一种高增益低噪声放大器

Also Published As

Publication number Publication date
US20180102737A1 (en) 2018-04-12
CN108028248B (zh) 2020-12-25
US10396711B2 (en) 2019-08-27
CN108028248A (zh) 2018-05-11

Similar Documents

Publication Publication Date Title
WO2017011936A1 (zh) 低共模耦合效应的集成电路
EP1929486B1 (en) Variable integrated inductor
US11770101B2 (en) Radio frequency oscillator
US7446631B2 (en) Radio frequency inductive-capacitive filter circuit topology
JP2005327931A (ja) 集積化インダクタおよびそれを用いた受信回路
US20200203060A1 (en) Inductor device and control method thereof
US9819323B2 (en) Integrated circuit fields canceller system
US8830011B2 (en) Band-pass filter using LC resonators
TW201328168A (zh) 壓控震盪器
TWI517601B (zh) 用於分析放大傳輸信號的傳輸裝置及方法
US11444572B2 (en) Integrated circuit including resonant circuit
US20150140937A1 (en) On-chip transmit and receive filtering
CN103928446A (zh) 低共模耦合效应的片上电感及其设计方法
US9276616B2 (en) Integrated circuit chip inductor configuration
US11601088B2 (en) Method, system and device providing enhanced quality factor resonant LC tank in an integrated circuits
Itoh et al. Twisted inductor VCO for supressing on-chip interferences
US20210126620A1 (en) Radio frequency filtering circuitry
TW202308332A (zh) 射頻裝置及其電感裝置
GB2520584A (en) On chip transmit and receive filtering
CN102314999B (zh) 变压器
CN115940825A (zh) 射频装置及其电感装置
JP2009017286A (ja) Ａｍ／ｆｍラジオ受信機およびこれに用いる受信用半導体集積回路
Scandurra et al. A new topology for transformer based CMOS active inductances
JPS6187411A (ja) Ｕｈｆテレビジヨンチユ−ナ回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15898492

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15898492

Country of ref document: EP

Kind code of ref document: A1