WO2019205736A1 - 电子组件以及投影设备 - Google Patents

电子组件以及投影设备 Download PDF

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Publication number
WO2019205736A1
WO2019205736A1 PCT/CN2019/070538 CN2019070538W WO2019205736A1 WO 2019205736 A1 WO2019205736 A1 WO 2019205736A1 CN 2019070538 W CN2019070538 W CN 2019070538W WO 2019205736 A1 WO2019205736 A1 WO 2019205736A1
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WIPO (PCT)
Prior art keywords
connector
address line
address
line connection
connection ports
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PCT/CN2019/070538
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English (en)
French (fr)
Inventor
黄国生
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深圳光峰科技股份有限公司
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Publication of WO2019205736A1 publication Critical patent/WO2019205736A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/12—Picture reproducers
    • H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/12—Picture reproducers
    • H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
    • H04N9/3141—Constructional details thereof

Definitions

  • the present application relates to the field of electronic technology, and more particularly to an electronic component and a projection device.
  • each device node in the system is usually configured with a unique identifier to distinguish other device nodes, such as an address code.
  • the master system needs to communicate with multiple subsystems, and each subsystem needs to be configured with an address code, so that the master system communicates with multiple subsystems based on the address codes of multiple subsystems.
  • Exchange information For example, in a suite system, the master system needs to communicate with multiple subsystems, and each subsystem needs to be configured with an address code, so that the master system communicates with multiple subsystems based on the address codes of multiple subsystems. Exchange information.
  • the address code of the subsystem is usually configured by setting a corresponding DIP switch for each subsystem.
  • the risk of dialing errors in the DIP switch causes communication errors between the main control system and the subsystem, and the setting of the DIP switch requires an additional setting of the plate for placing the DIP switch, resulting in waste of resources.
  • the present application proposes an electronic component and a projection device to improve the communication error between the main control system and the subsystem caused by the risk of dialing errors of the DIP switch, and the setting of the DIP switch requires additional settings for placing the dialing.
  • the plate of the code switch causes the problem of waste of resources.
  • the present application provides an electronic component including a main module and a plurality of submodules, wherein the main module is configured to control the plurality of submodules; each of the submodules includes a processing unit and a first connection
  • the first connector includes a plurality of address line connection ports for connecting address lines, the plurality of address line connection ports are connected to the processing unit, and the processing unit is configured to use the detected
  • the level of each of the address line connection ports determines the address code of the sub-module, and the level of each of the plurality of address line connection ports is determined by whether each of the plurality of address line connection ports is connected with an address line.
  • each of the sub-modules further includes a second connector, where the second connector includes a plurality of address line connection ports for connecting address lines; the plurality of sub-modules are sequentially arranged in a preset order a plurality of address line connection ports of the second connector of the previous sub-module configured to be connectable with a plurality of address line connection ports of the first connector of the subsequent sub-module, wherein the sub-order is sub- A plurality of address line connection ports of the first connector of the module are configured to connect to the main module with an address line.
  • the main module includes a control unit connected to each other and a third connector
  • the third connector includes a plurality of address line connection ports for connecting address lines, wherein the sub-module is sorted in the first position
  • the plurality of address line connection ports of the first connector are configured to connect the address lines to the plurality of address line connection ports of the third connector.
  • each of the sub-modules further includes a second connector, the second connector includes a plurality of address line connection ports for connecting the address lines; and the first connector of the at least one of the sub-modules
  • the address line connection port is configured to connect the address line with the main module, and the plurality of address line connection ports of the first connector of the remaining submodules except the at least one submodule are configured to be associated with any submodule
  • the plurality of address lines of the second connector connect the port to the address line.
  • a plurality of address line connection ports of the first connector of all of the sub-modules are configured to connect to the address line with the main module.
  • the first connector includes an address line connection port serially connected to the processing unit through a resistor, and a pull-up resistor is connected between the resistor and the processing unit; the second connector includes The address line connection port is grounded.
  • the second connector includes an address line connection port that is grounded through a resistor.
  • the present application provides a projection apparatus including a projection assembly and the electronic components described above.
  • each of the submodules includes a processing unit and a first connector, and the first connector includes a plurality of address line connection ports for connecting address lines
  • the manner of determining the level of each of the plurality of address line connection ports according to whether the plurality of address line connection ports are respectively connected to the address lines, and determining the sub-level according to the detection of the level of the connection port of the plurality of address lines The address code of the module, thus eliminating the need for the dial switch required to configure the address code, and the plate for placing the dial switch, saving resources, and also improving the main cause of the risk of dialing errors due to the dial switch.
  • FIG. 1 is a block diagram showing the structure of an electronic component proposed by the present application.
  • FIG. 2 is a structural block diagram of a submodule proposed by the present application.
  • FIG. 3 is a circuit schematic diagram of a submodule proposed by the present application.
  • FIG. 4 is a block diagram showing the structure of another electronic component proposed by the present application.
  • FIG. 5 is a schematic diagram showing a sub-module and a main module connection address line proposed by the present application
  • FIG. 6 is a structural block diagram of another seed module proposed by the present application.
  • FIG. 7 is a circuit schematic diagram of another seed module proposed by the present application.
  • FIG. 8 is a schematic diagram showing a plurality of sub-module connections proposed by the present application.
  • FIG. 9 is a structural block diagram of still another electronic component proposed by the present application.
  • FIG. 10 is a block diagram showing the structure of a projection apparatus proposed by the present application.
  • the address code usually used as an identity of an electronic module, distinguishes the electronic module from other electronic modules.
  • the main control system needs to communicate with multiple subsystems, and each subsystem needs to be configured with an address code, so that the main control system is based on the address codes of multiple subsystems, and The subsystems communicate with each other to exchange information.
  • the main control board often needs to communicate with multiple identical power supply modules.
  • multiple identical power modules need to be assigned address lines.
  • the inventors have found that during the setting of the address code, the address code of the subsystem is usually configured by setting a corresponding dial switch for each subsystem.
  • the risk of dialing errors in the DIP switch causes communication errors between the main control system and the subsystem, and the setting of the DIP switch requires an additional setting of the plate for placing the DIP switch, resulting in waste of resources.
  • the inventors have proposed that the risk of dialing errors in the DIP switch in the present application causes a communication error between the main control system and the subsystem, and the setting of the DIP switch requires an additional setting of a plate for placing the DIP switch, resulting in waste of resources.
  • an electronic component 100 provided by the present application includes a main module 110 and a plurality of submodules 120 .
  • the main module 110 is configured to control the plurality of submodules 120.
  • the main module 110 is a main control board integrated with a processor
  • the sub-module 120 is a power supply module for supplying power.
  • the number of sub-modules 120 in FIG. 1 is merely exemplary, and the number of sub-modules 120 may be increased or decreased according to the actual use environment, and the connection between the sub-module 120 and the main module 110 in FIG. 1 is not It represents the number of actual connections, but is used to characterize the signal transmission between each other.
  • each of the sub-modules 120 includes a processing unit 121 and a first connector 122.
  • the first connector 122 is configured to receive an externally transmitted address signal and a control signal
  • the processing unit 121 is configured to process the control signal and the address signal received by the first connector 122.
  • the circuit structure of the submodule 120 is further described below with reference to FIG.
  • the first connector 122 has a plurality of connection ports, and the numbers of the plurality of connection ports in FIG. 3 are sequentially 1-12.
  • the plurality of connection ports are all connected to the processing unit U1.
  • a plurality of connection ports for transmitting control signals and a plurality of address line connection ports for transmitting address signals are included in the plurality of connection ports.
  • the connection ports numbered 7 and 8 are used as address line connection ports, and the connection ports numbered 1-6 and 9-12 are used as connection ports for transmitting control signals.
  • the address code of each sub-module 120 is determined by the number of address lines connected to the address line connection port of the sub-module 120.
  • the address line for determining the address code of each of the sub-modules 120 may be connected to the address line connection port of the other sub-module 120 through the address line connection port of the sub-module 120, or may be connected through the address line of the sub-module 120.
  • the port is directly connected to the main module 110.
  • the processing unit U1 is configured to determine the address code of the submodule 120 shown in FIG. 3 according to the detected level of each of the plurality of address line connection ports.
  • the level of each of the plurality of address line connection ports is determined by whether each of the plurality of address line connection ports is connected to an address line. It can be understood that the address signals transmitted by the plurality of address line connection ports are signals of respective address levels of the plurality of address line connection ports.
  • the main module 110 includes a control unit 111 and a third connector 112.
  • the connection ports labeled 7 and 8 in the third connector 112 serve as address line connection ports, and the address line connection ports included in the third connector 112 can be grounded directly through the wires or through a lower resistance value.
  • the resistor is grounded, and the resistor with a lower resistance can be a resistor of 22R or a resistor of 100R.
  • the third connector 112 includes an address line connection port that is grounded through resistors R5 and R6.
  • connection ports of the first connector 122 labeled 7 and 8 are used as address line connection ports.
  • the plurality of address line connection ports included in the first connector 122 are connected in series with the processing unit through a resistor, and a pull-up resistor is connected between the resistor and the processing unit.
  • the address line connection port numbered 7 is connected in series with the processing unit through the resistor R4, and the address line connection port numbered 8 is connected in series with the processing unit through the resistor R3, and a pull-up resistor is connected between the resistor R4 and the processing unit U1.
  • R2 a pull-up resistor R1 is connected between the resistor R3 and the processing unit U1.
  • an address line is connected between the connection port numbered 7 of the first connector 122 and the connection port numbered 8 of the third connector 112, and the first connector 122 is numbered 8.
  • the processing unit U1 detects that the levels of the pins GP0 and GP1 are both If the level is low, the processing unit U1 recognizes that the address code of the sub-module 120 is 00.
  • connection port numbered 7 of the first connector 122 and the connection port numbered 8 of the third connector 112 are connected with an address line, and the port number of the first connector 122 is 8 and When the address line is not connected between the connection ports of the third connector 112, the processing unit U1 recognizes that the address code of the sub-module 120 is 01.
  • how many connection ports in the first connector 122 are specifically used as the address line connection port can be set as needed. For example, when a total of four sub-modules 120 need to configure an address code, the address codes of the four sub-modules 120 can be set to 00, 01, 10, and 11, respectively. Then, in this case, when the address lines are connected between the two sub-modules 120, only the two address lines are required to generate the above four address codes. For another example, when a total of eight sub-modules 120 need to configure an address code, the address codes of the eight sub-modules 120 can be set to 000, 001, 010, 011, 100, 101, 110, and 111, respectively.
  • the address lines are connected between the two sub-modules 120, only the three address lines are required to generate the above four address codes. That is to say, if n address lines are used, 2 n-th square address codes can be generated.
  • the number of address line connection ports used to connect the address lines in the first connector 122, the second connector 123, and the third connector 112 is the same as the number of bits of the configured address code, for example, When the address code is 2 bits, the address line connection port for connecting the address line is two, and when the address code is 3 bits, the address line connection port for connecting the address line is three.
  • each of the sub-modules 120 further includes a second connector 123, similar to the first connector 122, the second connector 123 includes a plurality of connection ports, which are The connection ports include a plurality of address line connection ports for transmitting address signals and a plurality of connection ports for transmitting control signals.
  • the address line connection port in the second connector 123 is grounded through the resistors R5 and R6.
  • the main module 110 and the plurality of sub-modules 120 may be sequentially arranged in a predetermined order, for example, in a ring-like manner.
  • the plurality of address line connection ports of the second connector 123 of the previous submodule 120 are configured to be connectable with a plurality of address line connection ports of the first connector 122 of the latter submodule 120,
  • the plurality of address line connection ports of the first connector 122 of the sub-module 120 sorted in the first place are configured to be connected to the address line of the main module 110.
  • the main module 110 includes a control unit 111 and a third connector 112 that are connected to each other, and the third connector 112 includes a plurality of address line connection ports for connecting address lines, wherein the sorting is in the first place.
  • the plurality of address line connection ports of the first connector 122 of the sub-module 120 are configured to connect to the address lines of the plurality of address lines of the third connector 112. Through such a looping manner, when the submodule 120 needs to be added, the address line of the submodule 120 that needs to be added and the plurality of address lines of the second connector 123 of the last submodule 120 can be directly connected to the port. Just connect.
  • sub-module 120a sub-module 120a
  • sub-module 120b sub-module 120c
  • sub-module 120d sub-module 120d
  • different address codes can be set to the submodule 120a, the submodule 120b, the submodule 120c, and the submodule 120d by connecting two address lines.
  • the third connector 112 connects two address lines with the first connector 122a of the sub-module 120a sorted in the first place, and the second connection of the sub-module 120a that is sorted in the first place.
  • One address line is connected between the first connector 122b of the latter submodule 120b and the first connector 122b of the latter submodule 120b.
  • the first connector 122b of the submodule 120b is connected to the first connector 122c of the latter submodule 120c.
  • the root address line is not connected to the address line between the second connector 123c of the submodule 120c and the first connector 122d of the latter submodule 120d, and the second connector 123d of the submodule 120d is also not connected to the address line.
  • the symbol "X" in the figure indicates that the address line is not connected here.
  • an electronic component 200 can also be configured to configure the address lines of all the sub-modules 120 as a uniform main module.
  • the 110 connection, or the address line of the partial sub-module 110 is configured to be connected to the main module 120. It can be understood that the connection between the main module 110 and the sub-module 120 in FIG. 9 is an address line between the address line connection ports, and the symbol "X" in the figure still indicates that the address line is not connected here.
  • a plurality of address line connection ports of the first connector of at least one of the sub-modules 120 are configured to be connected to the main module 110 with address lines, except for the at least one sub-module 120.
  • a plurality of address line connection ports of the first connector of module 120 are configured to connect to the address lines of the plurality of address lines of the second connector of any of the sub-modules 120.
  • an embodiment of the present application provides a projection device 300.
  • the projection device 300 includes a projection component 310 and an electronic component 320.
  • the electronic component 320 is configured to supply power to the projection component 310 and control the projection component 310 to operate based on the control instruction.
  • the internal structure of the electronic component 320 is the same as that of the electronic component 100 provided in the foregoing embodiment, and details are not described herein again.
  • the present application provides an electronic component and a projection device, each of which includes a processing unit and a first connector by providing each of the sub-modules, and the first connector includes a plurality of connection lines for connecting The manner in which the address lines are connected to the ports, so that the level of each of the plurality of address line connection ports can be determined according to whether each of the plurality of address line connection ports is connected with an address line, and then the ports are connected according to the detected multiple address lines.
  • the level of the level determines the address code of the sub-module, thereby eliminating the dial switch required for configuring the address code, and the plate for placing the dial switch, saving resources, and improving the dialing code of the dial switch.
  • the risk of error causes a communication error between the master system and the subsystem.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • the meaning of "a plurality” is at least two, such as two, three, etc., unless specifically defined otherwise.

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Abstract

本申请实施例公开了一种电子组件以及投影设备。该电子组件，包括主模块以及多个子模块，主模块用于对多个子模块进行控制；每个子模块均包括处理单元以及第一连接器；第一连接器包括用于连接地址线的多个地址线连接端口，多个地址线连接端口与处理单元连接，处理单元用于根据检测到的多个地址线连接端口各自的电平高低确定子模块的地址码，多个地址线连接端口各自的电平高低由多个地址线连接端口各自是否连接有地址线确定。该电子组件使得省去了配置地址码所需的拨码开关，以及用于放置拨码开关的板材，节省了资源，同时还改善了拨码开关存在拨码错误的风险造成主控系统和子系统之间通信错误的问题。

Description

电子组件以及投影设备 技术领域
本申请涉及电子技术领域，更具体地，涉及一种电子组件以及投影设备。
背景技术
在控制系统中，往往包含大量同类型的设备，这些设备相互连接，每台设备对应一个设备节点。当设备节点需要实现数据交换时，为识别每个独立的设备节点，系统中各设备节点通常配置具有唯一的标识，以此来区别其他设备节点，比如地址码。
例如，在套件系统中，主控系统需要和多个子系统之间通讯，就需要给每个子系统都配置地址码，以便主控系统基于多个子系统的地址码，和多个子系统之间相互通讯交换信息。
在地址码的设置过程中，通常是通过给每个子系统设置对应的拨码开关来配置子系统的地址码。但是，拨码开关存在拨码错误的风险造成主控系统和子系统之间通信错误，并且设置拨码开关需要额外设置用于放置拨码开关的板材，造成资源浪费。
发明内容
鉴于上述问题，本申请提出了一种电子组件以及投影设备，以改善拨码开关存在拨码错误的风险造成主控系统和子系统之间通信错误，并且设置拨码开关需要额外设置用于放置拨码开关的板材，造成资源浪费的问题。
第一方面，本申请提供了一种电子组件，包括主模块以及多个子模块，所述主模块用于对所述多个子模块进行控制；每个所述子模块均包括处理单元以及第一连接器；所述第一连接器包括用于连接地址线的多个地址线连接端口，所述多个地址线连接端口与所述处理单元连接，所述处理单元用于根据检测到的所述多个地址线连接端口各自的电平高低确定所述子模块的地址码，所述多个地址线连接端口各自的电平高低由所述多个地址线连接端口各自是否连接有地址线确定。
可选地，每个所述子模块还均包括第二连接器，所述第二连接器包括用 于连接地址线的多个地址线连接端口；所述多个子模块按照预设的顺序依次排布，其中，前一个子模块的第二连接器的多个地址线连接端口被配置为可与后一个子模块的第一连接器的多个地址线连接端口连接，其中，排序在首位的子模块的第一连接器的多个地址线连接端口被配置为与所述主模块连接地址线。
可选地，所述主模块包括相互连接的控制单元以及第三连接器，所述第三连接器包括用于连接地址线的多个地址线连接端口，其中，所述排序在首位的子模块的第一连接器的多个地址线连接端口被配置为与所述第三连接器的多个地址线连接端口连接地址线。
可选地，每个所述子模块还包括第二连接器，所述第二连接器包括用于连接地址线的多个地址线连接端口；至少一个所述子模块的第一连接器的多个地址线连接端口被配置为与所述主模块连接地址线，除所述至少一个子模块外的其余子模块的第一连接器的多个地址线连接端口，被配置为与任一子模块的第二连接器的多个地址线连接端口连接地址线。
可选地，所有子模块的第一连接器的多个地址线连接端口被配置为与所述主模块连接地址线。
可选地，所述第一连接器包括的地址线连接端口通过电阻与所述处理单元串接，所述电阻与所述处理单元之间连接有上拉电阻；所述第二连接器包括的地址线连接端口接地。
可选地，所述第二连接器包括的地址线连接端口通过电阻接地。
第二方面，本申请提供了一种投影设备，包括投影组件以及上述述的电子组件。
本申请提供的一种电子组件以及投影设备，通过设置每个所述子模块均包括处理单元以及第一连接器，且所述第一连接器包括用于连接地址线的多个地址线连接端口的方式，使得可以根据所述多个地址线连接端口各自是否连接有地址线确定多个地址线连接端口各自的电平高低，进而根据检测到多个地址线连接端口电平高低确定所述子模块的地址码，从而省去了配置地址码所需的拨码开关，以及用于放置拨码开关的板材，节省了资源，同时还改善由于拨码开关存在拨码错误的风险所造成的主控系统和子系统之间通信错误的问题。
本申请的这些方面或其他方面在以下实施例的描述中会更加简明易懂。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本申请提出的一种电子组件的结构框图；
图2示出了本申请提出的一种子模块的结构框图；
图3示出了本申请提出的一种子模块的电路原理图；
图4示出了本申请提出的另一种电子组件的结构框图；
图5示出了本申请提出的一种子模块和主模块连接地址线的示意图；
图6示出了本申请提出的另一种子模块的结构框图；
图7示出了本申请提出的另一种子模块的电路原理图；
图8示出了本申请提出的一种多个子模块连接的示意图；
图9示出了本申请提出的再一种电子组件的结构框图；
图10示出了本申请提出的一种投影设备的结构框图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
地址码，通常作为一个电子模块的身份标识，将该电子模块与其他的电子模块进行区分。在一些包括主控系统和子系统的套件系统中，主控系统需要和多个子系统之间通讯，就需要给每个子系统都配置地址码，以便主控系统基于多个子系统的地址码，和多个子系统之间相互通讯交换信息。
例如，在投影设备中，主控板往往需要和多个相同的电源模块之间进行通讯。而为了使主控板可以区分多个电源模块以进行信息交互，则需要给多个相同的电源模块均分配地址线。
但是，发明人发现，在地址码的设置过程中，通常是通过给每个子系统设置对应的拨码开关来配置子系统的地址码。但是，拨码开关存在拨码错误的风险造成主控系统和子系统之间通信错误，并且设置拨码开关需要额外设置用于放置拨码开关的板材，造成资源浪费。
因此，发明人提出了本申请中改善拨码开关存在拨码错误的风险造成主控系统和子系统之间通信错误，并且设置拨码开关需要额外设置用于放置拨码开关的板材，造成资源浪费的问题的电子组件以及投影设备。
下面将结合附图具体描述本申请的各实施例。
请参阅图1，本申请提供的一种电子组件100，包括主模块110以及多个子模块120。所述主模块110用于对所述多个子模块120进行控制。作为一种方式，主模块110为集成有处理器的主控板，而子模块120为用于供电的电源模块。需要说明的是，图1中子模块120的数量只是示例性的，子模块120的数量可以根据实际使用环境增加或者减少，且图1中子模块120与主模块110之间的连线并不代表实际连线的条数，而是用于表征相互之间有信号传输。
如图2所示，每个所述子模块120均包括处理单元121以及第一连接器122。第一连接器122用于接收外部传输的地址信号以及控制信号，处理单元121，用于对第一连接器122接收到的控制信号以及地址信号进行处理。下面通过图3进一步介绍子模块120的电路结构。
如图3所示，第一连接器122上有多个连接端口，该多个连接端口的在图3中的标号依次为1-12。该多个连接端口均与所述处理单元U1连接。在该多个连接端口中包括多个用于传输控制信号的连接端口，以及多个用于传输地址信号的多个地址线连接端口。示例性的，在图3中，将标号为7和8的连接端口作为地址线连接端口，将标号为1-6以及9-12的连接端口作为传输控制信号的连接端口。
每个子模块120的地址码，是通过子模块120的地址线连接端口所连接地址线的数量来确定的。而对于确定每个所述子模块120的地址码的地址线，可以通过子模块120的地址线连接端口连接到其他的子模块120的地址线连接端口，也可以通过子模块120的地址线连接端口直接和主模块110连接。
请继续参阅图3，在处理单元U1工作过程中，处理单元U1用于根据检测到的所述多个地址线连接端口各自的电平高低确定图3中所示子模块120的地址码，所述多个地址线连接端口各自的电平高低由所述多个地址线连接端口各自是否连接有地址线确定。可以理解的，多个地址线连接端口所传输的地址信号即为多个地址线连接端口各自电平高低的信号。
下面将根据图4以及图5介绍如何基于地址线连接端口各自是否连接有地址线确定电平高低。
如图4所示，作为一种方式，主模块110包括控制单元111以及第三连接器112。相同的，第三连接器112中标号为7和8的连接端口作为地址线连接端口，且第三连接器112包括的地址线连接端口可以直接通过导线接地，也可以通过一个阻值较低的电阻接地，该阻值较低的电阻可以为22R的电阻或者100R的电阻。在图4中，第三连接器112包括的地址线连接端口通过电阻R5以及R6接地。
如图5所示，作为一种方式，将第一连接器122的标号为7和8的连接端口作为地址线连接端口。第一连接器122包括的多个地址线连接端口均通过电阻与所述处理单元串接，所述电阻与所述处理单元之间连接有上拉电阻。其中，标号为7的地址线连接端口通过电阻R4与处理单元串接，标号为8的地址线连接端口通过电阻R3与处理单元串接，在电阻R4与处理单元U1之间连接有上拉电阻R2，在电阻R3与处理单元U1之间连接有上拉电阻R1。
在这种情况下，当第一连接器122的标号为7的连接端口与第三连接器112的标号为8的连接端口之间连接有地址线，且第一连接器122的标号为8的连接端口与第三连接器112的标号为7的连接端口之间连接有地址线时，上拉电阻R1以及R2均被短接，因此，处理单元U1检测到引脚GP0和GP1的电平均为低电平，则处理单元U1识别子模块120的地址码为00。再如果，当第一连接器122的标号为7的连接端口与第三连接器112的标号为8的连接端口之间连接有地址线，且第一连接器122的标号为8的连接端口与第三连接器112的标号为7的连接端口之间未连接有地址线时，则处理单元U1识别子模块120的地址码为01。
需要说明的是，对于子模块120中，具体将第一连接器122中的多少个连接端口作为地址线连接端口是可以根据需要进行设定的。例如，当共有四个子模块120需要配置地址码时，可以分别将四个子模块120的地址码设定为00、01、10以及11。那么在这种情况下，在两个子模块120之间连接地址线时，只需要2根地址线即可生成上述四个地址码。再例如，当共有八个子模块120需要配置地址码时，可以将八个子模块120的地址码分别设定为000、001、010、011、100、101、110以及111。那么在两个子模块120之间连接地址线时，只需要3根地址线即可生成上述四个地址码。也是说，如果用n根地址线，就可以产生2的n次方种地址码。可以理解的是，第一连接器122、第二连接器123以及第三连接器112中被用于连接地址线的地址线连接端口的数量和配置的地址 码的位数是相同的，例如，当地址码为2位时，用于连接地址线的地址线连接端口为2个，当地址码为3位时，用于连接地址线的地址线连接端口为3个。
作为一种方式，如图6所示，每个所述子模块120还均包括第二连接器123，与第一连接器122类似，所述第二连接器123包括多个连接端口，该多个连接端口包括用于传输地址信号的多个地址线连接端口以及多个用于传输控制信号的连接端口。作为一种方式，如图7所示，第二连接器123中的地址线连接端口通过电阻R5以及R6接地。在每个子模块120还均包括第二连接器123的情况下，可以将主模块110以及多个子模块120按照预设的顺序依次排布，例如，按照环形的方式连接。
在环形连接的情况下，前一个子模块120的第二连接器123的多个地址线连接端口被配置为可与后一个子模块120的第一连接器122的多个地址线连接端口连接，其中，排序在首位的子模块120的第一连接器122的多个地址线连接端口被配置为与所述主模块110连接地址线。与前述内容类似，主模块110包括相互连接的控制单元111以及第三连接器112，所述第三连接器112包括用于连接地址线的多个地址线连接端口，其中，所述排序在首位的子模块120的第一连接器122的多个地址线连接端口被配置为与所述第三连接器112的多个地址线连接端口连接地址线。通过这种环接的方式，可以使得在需要增加子模块120时，可以直接将需要增加的子模块120的地址线和最后一个子模块120的第二连接器123上的多个地址线连接端口连接即可。
下面基于图8，再次对多个子模块120依次进行环接的方式进行说明。图8中，包括四个子模块，该四个子模块分别为子模块120a、子模块120b、子模块120c以及子模块120d。需要说明的是，子模块120a、子模块120b、子模块120c以及子模块120d和前述子模块120的结构是相同的，此处是为了便于介绍各自连接关系而分别命名。
则通过连接2根地址线即可实现给子模块120a、子模块120b、子模块120c以及子模块120d设置不同的地址码。在这种情况下，作为一种方式，第三连接器112与排序在首位的子模块120a的第一连接器122a之间连接2根地址线，而排序在首位的子模块120a的第二连接器123a与后一个子模块120b的第一连接器122b之间连接1根地址线，类似的，子模块120b的第二连接器123b与后一个子模块120c的第一连接器122c之间连接1根地址线，而子模块120c的第二连接器123c与后一个子模块120d的第一连接器122d之间则不连接地址线，而 子模块120d的第二连接器123d也不连接地址线。其中，图中的符号“X”则表示此处不连接地址线。
当然，除了前述的将多个子模块120按照预设的顺序依次排布外，如图9所示提供的一种电子组件200，也可以将所有的子模块120的地址线配置为均和主模块110连接，或者部分子模块110的地址线配置为和主模块120连接。可以理解的是，图9中主模块110与子模块120之间的连线为地址线连接端口之间的地址线，图中符号“X”依然表征此处不连接地址线。
在这种情况下，至少一个所述子模块120的第一连接器的多个地址线连接端口被配置为与所述主模块110连接地址线，除所述至少一个子模块120外的其余子模块120的第一连接器的多个地址线连接端口，被配置为与任一子模块120的第二连接器的多个地址线连接端口连接地址线。
请参阅图10，本申请实施例提供了一种投影设备300，该投影设备300包括投影组件310以及电子组件320，电子组件320用于给投影组件310供电以及基于控制指令控制投影组件310进行工作，该电子组件320的内部结构与前述实施例内容中提供的电子组件100的结构相同，此处不再赘述。
综上所述，本申请提供的一种电子组件以及投影设备，通过设置每个所述子模块均包括处理单元以及第一连接器，且所述第一连接器包括用于连接地址线的多个地址线连接端口的方式，使得可以根据所述多个地址线连接端口各自是否连接有地址线确定多个地址线连接端口各自的电平高低，进而根据检测到的多个地址线连接端口各自的电平高低确定所述子模块的地址码，从而省去了配置地址码所需的拨码开关，以及用于放置拨码开关的板材，节省了资源，同时还改善拨码开关存在拨码错误的风险造成主控系统和子系统之间通信错误的问题。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
流程图中或在此以其他方式描述的任何过程或方法描述可以被理解为，表示包括一个或更多个用于实现特定逻辑功能或过程的步骤的可执行指令的代码的模块、片段或部分，并且本申请的优选实施方式的范围包括另外的实现，其中可以不按所示出或讨论的顺序，包括根据所涉及的功能按基本同时的方式或按相反的顺序，来执行功能，这应被本申请的实施例所属技术领域的技术人员所理解。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不驱使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (10)

  1. 一种电子组件，其特征在于，包括主模块以及多个子模块，所述主模块用于对所述多个子模块进行控制；
    每个所述子模块均包括处理单元以及第一连接器；所述第一连接器包括用于连接地址线的多个地址线连接端口，所述多个地址线连接端口与所述处理单元连接，所述处理单元用于根据检测到的所述多个地址线连接端口各自的电平高低确定所述子模块的地址码，所述多个地址线连接端口各自的电平高低由所述多个地址线连接端口各自是否连接有地址线确定。
  2. 根据权利要求1所述的电子组件，其特征在于，每个所述子模块还均包括第二连接器，所述第二连接器包括用于连接地址线的多个地址线连接端口；所述多个子模块按照预设的顺序依次排布，其中，前一个子模块的第二连接器的多个地址线连接端口被配置为可与后一个子模块的第一连接器的多个地址线连接端口连接，其中，排序在首位的子模块的第一连接器的多个地址线连接端口被配置为与所述主模块连接地址线。
  3. 根据权利要求2所述的电子组件，其特征在于，所述主模块包括相互连接的控制单元以及第三连接器，所述第三连接器包括用于连接地址线的多个地址线连接端口，其中，所述排序在首位的子模块的第一连接器的多个地址线连接端口被配置为与所述第三连接器的多个地址线连接端口连接地址线。
  4. 根据权利要求1所述的电子组件，其特征在于，每个所述子模块还包括第二连接器，所述第二连接器包括用于连接地址线的多个地址线连接端口；至少一个所述子模块的第一连接器的多个地址线连接端口被配置为与所述主模块连接地址线，除所述至少一个子模块外的其余子模块的第一连接器的多个地址线连接端口，被配置为与任一子模块的第二连接器的多个地址线连接端口连接地址线。
  5. 根据权利要求4所述的电子组件，其特征在于，所有子模块的第一连接器的多个地址线连接端口被配置为与所述主模块连接地址线。
  6. 根据权利要求1-5任一所述的电子组件，其特征在于，所述第一连接器包括的地址线连接端口通过电阻与所述处理单元串接，所述电阻与所述处理单元之间连接有上拉电阻；所述第二连接器包括的地址线连接端口接地。
  7. 根据权利要求6所述的电子组件，其特征在于，所述第二连接器包括的地址线连接端口通过电阻接地。
  8. 根据权利要求6所述的电子组件，其特征在于，所述上拉电阻的电阻值为4.7K欧姆，所述电阻为22R电阻或100R电阻。
  9. 根据权利要求1所述的电子组件，其特征在于，所述子模块为用于供电的电源模块。
  10. 一种投影设备，其特征在于，包括投影组件以及权利要求1-9任一所述的电子组件。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113301181A (zh) * 2021-05-19 2021-08-24 漳州科华技术有限责任公司 并机地址识别系统及机柜

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1825784A (zh) * 2006-04-07 2006-08-30 北京中科信电子装备有限公司 一种通讯方法及装置
CN104881382A (zh) * 2015-06-15 2015-09-02 刘晓辉 一种主从设备连接装置及其地址识别方法
JP2016224291A (ja) * 2015-06-01 2016-12-28 セイコーエプソン株式会社 表示装置、表示システム、及び、表示装置の制御方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11355848A (ja) * 1998-06-04 1999-12-24 Alps Electric Co Ltd データ通信の開始・終了方式
CN106095711B (zh) * 2016-08-25 2024-02-02 威胜能源技术股份有限公司 用于主从模块通信的连接装置和通信方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1825784A (zh) * 2006-04-07 2006-08-30 北京中科信电子装备有限公司 一种通讯方法及装置
JP2016224291A (ja) * 2015-06-01 2016-12-28 セイコーエプソン株式会社 表示装置、表示システム、及び、表示装置の制御方法
CN104881382A (zh) * 2015-06-15 2015-09-02 刘晓辉 一种主从设备连接装置及其地址识别方法

Cited By (2)

* Cited by examiner, † Cited by third party
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CN113301181A (zh) * 2021-05-19 2021-08-24 漳州科华技术有限责任公司 并机地址识别系统及机柜
CN113301181B (zh) * 2021-05-19 2023-08-22 漳州科华技术有限责任公司 并机地址识别系统及机柜

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