WO2019205236A1 - 驱动装置、驱动方法及显示系统 - Google Patents

驱动装置、驱动方法及显示系统 Download PDF

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Publication number
WO2019205236A1
WO2019205236A1 PCT/CN2018/090428 CN2018090428W WO2019205236A1 WO 2019205236 A1 WO2019205236 A1 WO 2019205236A1 CN 2018090428 W CN2018090428 W CN 2018090428W WO 2019205236 A1 WO2019205236 A1 WO 2019205236A1
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Prior art keywords
phy
signal
deserializer
connection terminal
mipi
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PCT/CN2018/090428
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English (en)
French (fr)
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沈利军
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武汉华星光电半导体显示技术有限公司
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Priority to US16/080,548 priority Critical patent/US11024213B2/en
Publication of WO2019205236A1 publication Critical patent/WO2019205236A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00—Solving problems of bandwidth in display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication

Definitions

  • the present invention relates to the field of driving display technologies, and in particular, to a driving device, a driving method, and a display system.
  • MIPI Alliance the Mobile Industry Processor Interface (MIPI) Alliance, is defined by its communication interface standard for communication between the host and peripheral devices.
  • the communication between the portable terminal device and the display module is typically MIPI D-PHY (Mobile Industry Processor Interface D-PHY), which consists of a pair of differential clock signals and one or more pairs of four pairs or less.
  • the differential data signals are communicated.
  • the MIPI D-PHY 1 Port can support display modules with a resolution of 1080*3*1920.
  • the MIPI C-PHY Mobile Industry Processor Interface C-PHY
  • the MIPI C-PHY is a newly-designated high-speed communication interface that satisfies the drive of a high-resolution display module in recent years. It uses three signal lines for communication, and three signal lines transmit high and medium respectively. The low three-value signal, the clock signal is buried in the three-value signal.
  • the MIPI C-PHY has a data rate of 2.85 Gbps per lane, and the rate per channel is about twice that of MIPI D-PHY, supporting higher resolution display modules.
  • IC vendors are also actively developing Driver ICs for MIPI C-PHY and MIPI D-PHY 1 port to handle high-definition display modules. Therefore, it is necessary to flexibly cope with the drive device using MIPI D-PHY and MIPI C-PHY communication.
  • the simplest method is to independently drive the display module by using the MIPI D-PHY communication drive device and the MIPI C-PHY communication drive device, or to integrate the communication modules of the two into the drive device independently.
  • the circuit is large in scale and high in cost.
  • a driving device comprising:
  • RGB module for receiving image data and converting to RGB signals
  • the first protocol processing module and the second protocol processing module are respectively connected to the RGB module, and the first protocol processing module outputs the first signal after receiving the RGB signal according to the first protocol standard, and the second protocol processing module After receiving the RGB signal, processing the second signal according to the second protocol standard;
  • a selector connected to the first protocol processing module and the second protocol processing module, selectively receiving the first signal and the second signal and outputting;
  • first deserializer and a second deserializer connected to the selector, the first deserializer for decoding the first signal and outputting a binary signal data column, the second deserializer for The second signal is decoded and outputs a binary signal data column;
  • the transmitter is connected to the first deserializer and the second deserializer, and the connection terminal is connected to the transmitter for receiving the binary signal data column and outputting the driving signal.
  • the driving device comprises:
  • RGB module for receiving image data and converting to RGB signals
  • the C-PHY protocol processing module and the D-PHY protocol processing module are respectively connected to the RGB module, and the C-PHY protocol processing module receives the RGB signal and outputs the MIPI C-PHY signal according to the protocol standard of the MIPI C-PHY.
  • the D-PHY protocol processing module receives the RGB signal and outputs the MIPI D-PHY signal according to the protocol standard of the MIPI D-PHY;
  • a C-PHY/D-PHY selector connected to the C-PHY protocol processing module and the D-PHY protocol processing module, selectively receiving and outputting the MIPI C-PHY signal and the MIPI D-PHY signal;
  • a C-PHY deserializer and a D-PHY deserializer are coupled to the C-PHY/D-PHY selector for decoding the MIPI C-PHY signal and outputting a binary signal a data column, the D-PHY deserializer is configured to decode the MIPI D-PHY signal and output a binary signal data column;
  • a plurality of transmitters and a plurality of connection terminals the transmitter is connected to the C-PHY deserializer and the D-PHY deserializer, and the connection terminal is connected to the transmitter for receiving the binary signal data column and outputting the driving signal.
  • the driving device further includes:
  • a clock module coupled to the C-PHY deserializer and the D-PHY deserializer, for generating a clock signal.
  • the driving device further includes:
  • the flip-flop being connected to the clock module, the C-PHY deserializer, and the D-PHY deserializer, and the trigger combining the clock signal to the binary value of the C-PHY deserializer and the D-PHY deserializer output
  • the signal data column is synchronously latched
  • the first flip-flop, the second flip-flop and the third flip-flop are respectively connected to the C-PHY deserializer and the clock module, and are configured to generate a trigger clock signal to perform a binary signal data sequence output by the C-PHY deserializer. Synchronous latch
  • the fourth flip-flop and the fifth flip-flop are respectively connected to the D-PHY deserializer and the clock module, and are configured to generate a trigger clock signal for synchronously latching the binary signal data column outputted by the D-PHY deserializer.
  • the transmitter comprises:
  • a first transmitter connected to the first trigger and the fourth trigger
  • a second emitter connected to the second trigger and the fifth trigger
  • a third transmitter connected to the third trigger and the clock signal
  • the first transmitter, the second transmitter, and the third transmitter are configured to transmit a binary signal data column outputted by the C-PHY deserializer, and convert the binary signal data column outputted by the D-PHY deserializer into a binary signal data column. It is a differential signal and is transmitted.
  • connection terminal comprises:
  • the MIPI C-PHY signal is transmitted through the first connection terminal, the third connection terminal, and the fifth connection terminal, and the MIPI D-PHY signal passes through the first connection terminal, the second connection terminal, the third connection terminal, and the fourth connection terminal.
  • the fifth connection terminal and the sixth connection terminal transmit.
  • an amplifier is provided in the transmitter.
  • a driving method comprising:
  • the S1 and RGB modules receive image data and convert to RGB signals
  • the first protocol processing module outputs the first signal after receiving the RGB signal according to the first protocol standard, or the second protocol processing module receives the RGB signal and then processes the second signal according to the second protocol standard;
  • the selector selectively receives the first signal and the second signal and outputs the same.
  • the first deserializer decodes the first signal and outputs a binary signal data column, or the second deserializer decodes the second signal and outputs a binary signal data column.
  • the transmitter receives the binary signal data sequence output by the first deserializer and outputs a binary signal through the connection terminal, or the transmitter receives the binary signal data sequence output by the second deserializer and converts the signal into a differential signal and outputs the signal. .
  • the driving method is specifically:
  • the S1 and RGB modules receive image data and convert to RGB signals
  • the S2, C-PHY protocol processing module receives the RGB signal and outputs the MIPI C-PHY signal according to the MIPI C-PHY protocol standard, or the D-PHY protocol processing module receives the RGB signal and processes according to the MIPI D-PHY protocol standard. After output MIPI D-PHY signal;
  • the S3, C-PHY/D-PHY selector selectively receives and outputs the MIPI C-PHY signal and the MIPI D-PHY signal;
  • the S4, C-PHY deserializer decodes the MIPI C-PHY signal and outputs a binary signal data column, or the D-PHY deserializer decodes the MIPI D-PHY signal and outputs a binary signal data column;
  • the transmitter receives the binary signal data sequence outputted by the C-PHY deserializer and outputs a binary signal through the connection terminal, or the transmitter receives the binary signal data column outputted by the D-PHY deserializer and converts into a differential signal.
  • the flip-flop After the output, the flip-flop combines the clock signal to synchronously latch the binary signal data column of the C-PHY deserializer and the D-PHY deserializer output.
  • a display system comprising:
  • the driving device is the driving device described above;
  • connection module being electrically connected to a connection terminal in the driving device
  • the display module being connected to the connection module for displaying data provided by the driving device.
  • the invention can realize driving by using MIPI D-PHY communication and MIPI C-PHY communication, reducing communication interface and circuit scale, and reducing cost.
  • Embodiment 1 is a schematic block diagram of a driving device in Embodiment 1 of the present invention.
  • FIG. 2 is a block diagram of MIPI C-PHY communication in Embodiment 2 of the present invention.
  • FIG. 3 is a block diagram of MIPI D-PHY communication in Embodiment 2 of the present invention.
  • FIG. 4 is a schematic structural diagram of a display system in Embodiment 3 of the present invention.
  • the invention discloses a driving device, comprising:
  • a driving device comprising:
  • RGB module for receiving image data and converting to RGB signals
  • the first protocol processing module and the second protocol processing module are respectively connected to the RGB module, and the first protocol processing module outputs the first signal after receiving the RGB signal according to the first protocol standard, and the second protocol processing module receives the RGB signal according to the first After the second protocol standard processing, the second signal is output;
  • a selector connected to the first protocol processing module and the second protocol processing module, selectively receiving the first signal and the second signal and outputting;
  • the first deserializer and the second deserializer are connected to the selector, the first deserializer is configured to decode the first signal and output a binary signal data column, and the second deserializer is configured to decode the second signal and Outputting a binary signal data column;
  • the transmitter is connected to the first deserializer and the second deserializer, and the connection terminal is connected to the transmitter for receiving the binary signal data column and outputting the driving signal.
  • the driving device in the present invention comprises:
  • RGB module for receiving image data and converting to RGB signals
  • the C-PHY protocol processing module and the D-PHY protocol processing module are respectively connected to the RGB module, and the C-PHY protocol processing module receives the RGB signal and outputs the MIPI C-PHY signal according to the protocol standard of the MIPI C-PHY, D-PHY. After receiving the RGB signal, the protocol processing module processes the MIPI D-PHY signal according to the protocol standard of the MIPI D-PHY;
  • the C-PHY/D-PHY selector is connected to the C-PHY protocol processing module and the D-PHY protocol processing module, and selectively receives and outputs the MIPI C-PHY signal and the MIPI D-PHY signal;
  • the C-PHY deserializer and the D-PHY deserializer are connected to a C-PHY/D-PHY selector, and the C-PHY deserializer is used to decode the MIPI C-PHY signal and output a binary signal data column, D a -PHY deserializer for decoding the MIPI D-PHY signal and outputting a binary signal data column;
  • a plurality of transmitters and a plurality of connection terminals the transmitter is connected to the C-PHY deserializer and the D-PHY deserializer, and the connection terminal is connected to the transmitter for receiving the binary signal data column and outputting the driving signal.
  • the driving device in the present invention further includes:
  • a clock module coupled to the C-PHY deserializer and the D-PHY deserializer, for generating a clock signal
  • a plurality of flip-flops the flip-flop is connected to the clock module, the C-PHY deserializer and the D-PHY deserializer, and the trigger combines the binary signal data of the clock signal to the C-PHY deserializer and the D-PHY deserializer output.
  • the column is synchronously latched.
  • the invention also discloses a driving method, comprising:
  • the S1 and RGB modules receive image data and convert to RGB signals
  • the first protocol processing module outputs the first signal after receiving the RGB signal according to the first protocol standard, or the second protocol processing module receives the RGB signal and then processes the second signal according to the second protocol standard;
  • the selector selectively receives the first signal and the second signal and outputs the same.
  • the first deserializer decodes the first signal and outputs a binary signal data column, or the second deserializer decodes the second signal and outputs a binary signal data column.
  • the transmitter receives the binary signal data sequence output by the first deserializer and outputs a binary signal through the connection terminal, or the transmitter receives the binary signal data sequence output by the second deserializer and converts the signal into a differential signal and outputs the signal. .
  • the driving method in the present invention is specifically:
  • the S1 and RGB modules receive image data and convert to RGB signals
  • the S2, C-PHY protocol processing module receives the RGB signal and outputs the MIPI C-PHY signal according to the MIPI C-PHY protocol standard, or the D-PHY protocol processing module receives the RGB signal and processes according to the MIPI D-PHY protocol standard. After output MIPI D-PHY signal;
  • the S3, C-PHY/D-PHY selector selectively receives and outputs the MIPI C-PHY signal and the MIPI D-PHY signal;
  • the S4, C-PHY deserializer decodes the MIPI C-PHY signal and outputs a binary signal data column, or the D-PHY deserializer decodes the MIPI D-PHY signal and outputs a binary signal data column;
  • the transmitter receives the binary signal data sequence outputted by the C-PHY deserializer and outputs a binary signal through the connection terminal, or the transmitter receives the binary signal data column outputted by the D-PHY deserializer and converts into a differential signal. After the output.
  • step S4 the method further includes:
  • the flip-flop combines the clock signal to synchronously latch the binary signal data column of the C-PHY deserializer and the D-PHY deserializer output.
  • the present invention also discloses a display system, including:
  • the driving device is the above driving device
  • connection module Connecting the module, the connection module is electrically connected to the connection terminal in the driving device;
  • a display module is connected to the connection module for displaying data provided by the driving device.
  • the driving device in this embodiment includes:
  • the RGB module 10 is for receiving image data and converting it into RGB signals.
  • the processor can be an FPGA/PSOC or the like.
  • the C-PHY protocol processing module 21 and the D-PHY protocol processing module 22 are respectively connected to the RGB module 10.
  • the C-PHY protocol processing module 21 receives the RGB signals and processes the MIPI C-PHY signals according to the protocol standard of the MIPI C-PHY.
  • the D-PHY protocol processing module 22 processes the MIPI D-PHY signal according to the protocol standard of the MIPI D-PHY.
  • the C-PHY/D-PHY selector 30 is connected to the C-PHY protocol processing module 21 and the D-PHY protocol processing module 22, and selectively receives and outputs the MIPI C-PHY signal and the MIPI D-PHY signal.
  • a C-PHY deserializer 41 and a D-PHY deserializer 42 are connected to the C-PHY/D-PHY selector 30, and the C-PHY deserializer 41 is used to decode the MIPI C-PHY signal and output a binary value.
  • the signal data column, D-PHY deserializer 42 is used to decode the MIPI D-PHY signal and output a binary signal data column.
  • the clock module 50 is connected to the C-PHY deserializer and the D-PHY deserializer for generating a clock signal
  • the flip-flop is connected to the clock module 50, the C-PHY deserializer 41 and the D-PHY deserializer 42, and the flip-flop combines the clock signal to the C-PHY deserializer and the D-PHY deserializer output.
  • the value signal data column is synchronously latched.
  • a plurality of transmitters and a plurality of connection terminals are connected to the C-PHY deserializer 41 and the D-PHY deserializer 42.
  • the connection terminals are connected to the transmitter for receiving the binary signal data columns and outputting the driving signals.
  • the first flip-flop 61, the second flip-flop 62 and the third flip-flop 63 are respectively connected to the C-PHY deserializer 41 and the clock module 50 for generating a trigger clock signal to the output of the C-PHY deserializer 41.
  • the binary signal data column is synchronously latched;
  • the fourth flip-flop 64 and the fifth flip-flop 65 are respectively connected to the D-PHY deserializer 42 and the clock module 50 for generating a trigger clock signal for the binary signal data sequence output by the D-PHY deserializer 42. Synchronous latching.
  • An amplifier is provided in the transmitter in this embodiment, wherein the transmitter includes:
  • a first emitter 71 connected to the first flip-flop 61 and the fourth flip-flop 64;
  • a second emitter 72 connected to the second trigger 62 and the fifth trigger 65;
  • a third emitter 73 connected to the third flip-flop 63 and the clock signal 50;
  • the first transmitter 71, the second transmitter 72, and the third transmitter 73 are configured to transmit a binary signal data sequence output by the C-PHY deserializer and binary signal data output by the D-PHY deserializer.
  • the column is converted to a differential signal and transmitted.
  • the signal in the driving device transmits the driving signal to the external display module through the connection terminal, and the connection terminal includes:
  • connection terminal 83 and a fourth connection terminal 84 disposed on the second transmitter 72;
  • connection terminal 85 and a sixth connection terminal 86 disposed on the third transmitter 73;
  • the MIPI C-PHY signal is transmitted through the first connection terminal 81, the third connection terminal 83, and the fifth connection terminal 85, and the MIPI D-PHY signal passes through the first connection terminal 81, the second connection terminal 82, and the third connection terminal. 83.
  • the fourth connection terminal 84, the fifth connection terminal 85, and the sixth connection terminal 86 transmit.
  • connection terminals are taken as an example.
  • the trigger and the connection terminal can be correspondingly increased. Quantity, no longer detailed examples here.
  • the driving method in this embodiment is exemplified by the driving device in Embodiment 1, and the driving method includes:
  • the RGB module receives image data and converts it into RGB signals
  • the C-PHY protocol processing module receives the RGB signal and outputs the MIPI C-PHY signal according to the MIPI C-PHY protocol standard, or the D-PHY protocol processing module receives the RGB signal and processes according to the MIPI D-PHY protocol standard. After output MIPI D-PHY signal;
  • the C-PHY/D-PHY selector selectively receives and outputs the MIPI C-PHY signal and the MIPI D-PHY signal;
  • the C-PHY deserializer decodes the MIPI C-PHY signal and outputs a binary signal data column, or the D-PHY deserializer decodes the MIPI D-PHY signal and outputs a binary signal data column;
  • the flip-flop combines the clock signal to synchronously latch the binary signal data column outputted by the C-PHY deserializer and the D-PHY deserializer.
  • the transmitter receives the binary signal data column outputted by the C-PHY deserializer and outputs a binary signal through the connection terminal, or the transmitter receives the binary signal data column outputted by the D-PHY deserializer and converts it into a differential signal. After the output.
  • the driving method in this embodiment includes two methods of MIPI C-PHY communication and MIPI D-PHY communication.
  • the C-PHY/D-PHY selector selects the MIPI C-PHY signal and transmits it to the MIPI C-PHY deserializer.
  • the MIPI C-PHY deserializer decodes the MIPI C-PHY signal output binary signal data column.
  • the MIPI D-PHY deserializer has no data column output.
  • the binary signal data column is received by the first flip-flop, the second flip-flop and the third flip-flop, and is clock-regenerated with the deserializer clock received by the clock module, and generates a flip-flop clock signal to synchronously latch the data column.
  • the binary signal data sequence generated by the trigger is transmitted to the transmitter, and the first to third transmitters transmit the data column to the first connection terminal, the third connection terminal, and the fifth connection terminal, and then transmit to the display module for driving.
  • the C-PHY/D-PHY selector selects the MIPI D-PHY signal and transmits it to the MIPI D-PHY deserializer.
  • the MIPI D-PHY deserializer decodes the MIPI D-PHY signal output binary signal data column.
  • the MIPI C-PHY deserializer has no data column output.
  • the data column of the binary signal is received by the fourth flip-flop and the fifth flip-flop, and the data column is synchronously latched with CLK.
  • the binary signal data sequence generated by the trigger is transmitted to the transmitter, and the first to third transmitters convert the received binary signal into a differential signal, and the connection terminal transmits the signal to the display through the first connection terminal to the sixth connection terminal. Module.
  • the display system in this implementation includes:
  • the driving device 100 can be the driving device in Embodiment 1, and details are not described herein.
  • the driving device provides display of desired image/audio video data and voltage;
  • connection module 200 is electrically connected to the connection terminal in the driving device 100.
  • the connection module may be an FPCA or a connection cable, and the connection terminal may be an interface mode such as ZIF/BTB/DIP;
  • the display module 300 is connected to the connection module 200 for displaying data provided by the driving device.
  • the display module may be a liquid crystal display panel or an AMOLED display panel, etc., and displays data such as images, audio and video provided by the driving device.
  • the protocol processing module in the foregoing embodiments uses the C-PHY protocol processing module and the D-PHY protocol processing module as an example for description.
  • the C-PHY protocol processing module and the D-PHY protocol processing module respectively follow MIPI C-
  • the PHY protocol standard and the MIPI D-PHY protocol standard process the RGB signal to output the MIPI C-PHY signal and the MIPI D-PHY signal;
  • the selector uses the C-PHY/D-PHY selector to selectively receive the MIPI C-PHY The signal and the MIPI D-PHY signal are outputted;
  • the deserializer includes a C-PHY deserializer and a D-PHY deserializer, respectively decoding the MIPI C-PHY signal and the MIPI D-PHY signal and outputting the binary signal data column .
  • different protocol processing modules, selectors, and deserializers may be selected according to different communication protocols and signals, and details are not described herein again.
  • An embodiment of the present invention further provides an electronic device.
  • the electronic device includes at least one processor and a memory coupled to the at least one processor, the memory for storing instructions executable by the at least one processor, the instructions being executed by the at least one processor
  • the at least one processor is caused to execute the driving method in the above embodiment.
  • the embodiment of the present invention further provides a non-transitory storage medium storing computer executable instructions, and the computer executable instructions are configured to execute the above driving method.
  • Embodiments of the present invention also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions, when the program instructions are executed by a computer When the computer is caused to execute the above-described driving method.
  • the driving device provided by the embodiment of the present invention can execute the driving method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the executing method.
  • the driving method provided by any embodiment of the present invention can execute the driving method provided by any embodiment of the present invention.
  • the present invention has the following beneficial effects:
  • the invention can realize driving by using MIPI D-PHY communication and MIPI C-PHY communication, reducing communication interface and circuit scale, and reducing cost.

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Abstract

一种驱动装置（100）、驱动方法及显示系统，能够利用两种通信方式实现驱动，减少了通信接口和电路规模，降低了成本。其中，驱动装置（100）包括：RGB模块（10）、C-PHY协议处理模块（21）及D-PHY协议处理模块（22）、C-PHY/D-PHY选择器（30）、C-PHY解串器（41）及D-PHY解串器（42）、若干发射器（71, 72, 73）及若干连接端子（81, 82, 83, 84, 85, 86）。

Description

驱动装置、驱动方法及显示系统 技术领域
本发明涉及驱动显示技术领域，特别是涉及一种驱动装置、驱动方法及显示系统。
背景技术
MIPI联盟，即移动产业处理器接口(Mobile Industry Processor Interface简称MIPI)联盟，由其确定的通信接口标准被用于主机和外围设备之间的通信。
目前便携式终端设备和显示模块的通信最典型的为MIPI D-PHY(Mobile Industry Processor Interface D-PHY)(Mobile Industry Processor Interface D-PHY)，其由一对差分时钟信号和一对以上四对以下差分数据信号进行通信，按照1.5Gpbs/Lane计算，MIPI D-PHY 1 Port可支持到分辨率为1080*3*1920的显示模块。
MIPI C-PHY(Mobile Industry Processor Interface C-PHY)是近年来满足高分辨率的显示模块的驱动而新规定的高速通信接口，其使用三条信号线来进行通信，三条信号线分别传输高、中、低三值信号，时钟信号被埋入到三值信号中。MIPI C-PHY每通道(Lane)的传输速率(data rate)可达到2.85Gbps，每通道的速率约是MIPI D-PHY的2倍，可支持到更高分辨率的显示模块。
对于高分辨率的显示模块驱动来说，IC供应商也在积极的开发MIPI C-PHY和MIPI D-PHY 1 port以上的Driver IC，以应对高精细化的显示模块。所以，需要利用MIPI D-PHY和MIPI C-PHY通信的驱动装置来灵活应对。最简单的方法是利用MIPI D-PHY通信的驱动装置和利用MIPI C-PHY通信的驱动装置独立驱动显示模块，或者将这二者的通信模块独立的集成到驱动装置中。但上述方法中电路规模大，成本高。
因此，针对上述技术问题，有必要提供一种驱动装置、驱动方法及显示系统。
发明内容
为克服现有技术的不足，本发明的目的在于提供一种驱动装置、驱动方法及显示系统。
为了实现上述目的，本发明一实施例提供的技术方案如下：
一种驱动装置，所述驱动装置包括：
RGB模块，用于接收图像数据并转换为RGB信号；
第一协议处理模块及第二协议处理模块，分别与所述RGB模块相连，所述第一协议处理模块接收RGB信号后按照第一协议标准处理后输出第一信号，所述第二协议处理模块接收RGB信号后按照第二协议标准处理后输出第二信号；
选择器，与所述第一协议处理模块及第二协议处理模块相连，选择性接收第一信号和第二信号并输出；
第一解串器及第二解串器，与所述选择器相连，所述第一解串器用于对第一信号进行解码并输出二值信号数据列，所述第二解串器用于对第二信号进行解码并输出二值信号数据列；
若干发射器及若干连接端子，发射器与第一解串器及第二解串器相连，连接端子与发射器相连，用于接收二值信号数据列并输出驱动信号。
作为本发明的进一步改进，所述驱动装置包括：
RGB模块，用于接收图像数据并转换为RGB信号；
C-PHY协议处理模块及D-PHY协议处理模块，分别与所述RGB模块相连，所述C-PHY协议处理模块接收RGB信号后按照MIPI C-PHY的协议标准处理后输出MIPI C-PHY信号，所述D-PHY协议处理模块接收RGB信号后按照MIPI D-PHY的协议标准处理后输出MIPI D-PHY信号；
C-PHY/D-PHY选择器，与所述C-PHY协议处理模块及D-PHY协议处理模块相连，选择性接收MIPI C-PHY信号和MIPI D-PHY信号并输出；
C-PHY解串器及D-PHY解串器，与所述C-PHY/D-PHY选择器相连，所述C-PHY解串器用于对MIPI C-PHY信号进行解码并输出二值信号数据列，所述D-PHY解串器用于对MIPI D-PHY信号进行解码并输出二值信号数据列；
若干发射器及若干连接端子，发射器与C-PHY解串器及D-PHY解串器相连，连接端子与发射器相连，用于接收二值信号数据列并输出驱动信号。
作为本发明的进一步改进，所述驱动装置还包括：
时钟模块，与C-PHY解串器及D-PHY解串器相连，用于生成时钟信号。
作为本发明的进一步改进，所述驱动装置还包括：
若干触发器，所述触发器与时钟模块、C-PHY解串器及D-PHY解串器相连，触发器结合时钟信号对C-PHY解串器及D-PHY解串器输出的二值信号数据列进行同步锁存，
第一触发器、第二触发器及第三触发器，分别与C-PHY解串器及时钟模块相连，用于生成触发器时钟信号对C-PHY解串器输出的二值信号数据列进行同步锁存；
第四触发器及第五触发器，分别与D-PHY解串器及时钟模块相连，用于生成触发器时钟信号对D-PHY解串器输出的二值信号数据列进行同步锁存。
作为本发明的进一步改进，所述发射器包括：
第一发射器，与第一触发器和第四触发器相连；
第二发射器，与第二触发器和第五触发器相连；
第三发射器，与第三触发器和时钟信号相连；
其中，所述第一发射器、第二发射器、第三发射器用于传输C-PHY解串器输出的二值信号数据列、以及将D-PHY解串器输出的二值信号数据列转化为差分信号并传输。
作为本发明的进一步改进，所述连接端子包括：
设于第一发射器上的第一连接端子和第二连接端子；
设于第二发射器上的第三连接端子和第四连接端子；
设于第三发射器上的第五连接端子和第六连接端子；
其中，MIPI C-PHY信号通过第一连接端子、第三连接端子和第五连接端子进行传输，MIPI D-PHY信号通过第一连接端子、第二连接端子、第三连接端子、第四连接端子、第五连接端子和第六连接端子进行传输。
作为本发明的进一步改进，所述发射器中设有放大器。
本发明另一实施例提供的技术方案如下：
一种驱动方法，所述驱动方法包括：
S1、RGB模块接收图像数据并转换为RGB信号；
S2、第一协议处理模块接收RGB信号后按照第一协议标准处理后输出第一信号，或，第二协议处理模块接收RGB信号后按照第二协议标准处理后输出第二信号；
S3、选择器选择性接收第一信号和第二信号并输出；
S4、第一解串器对第一信号进行解码并输出二值信号数据列，或，第二解串器对第二信号进行解码并输出二值信号数据列；
S5、发射器接收第一解串器输出的二值信号数据列并通过连接端子输出二值信号，或，发射器接收第二解串器输出的二值信号数据列并转化为差分信号后输出。
作为本发明的进一步改进，所述驱动方法具体为：
S1、RGB模块接收图像数据并转换为RGB信号；
S2、C-PHY协议处理模块接收RGB信号后按照MIPI C-PHY的协议标准处理后输出MIPI C-PHY信号，或，D-PHY协议处理模块接收RGB信号后按照MIPI D-PHY的协议标准处理后输出MIPI D-PHY信号；
S3、C-PHY/D-PHY选择器选择性接收MIPI C-PHY信号和MIPI D-PHY信号并输出；
S4、C-PHY解串器对MIPI C-PHY信号进行解码并输出二值信号数据列，或，D-PHY解串器对MIPI D-PHY信号进行解码并输出二值信号数据列；
S5、发射器接收C-PHY解串器输出的二值信号数据列并通过连接端子输出二值信号，或，发射器接收D-PHY解串器输出的二值信号数据列并转化为差分信号后输出，触发器结合时钟信号对C-PHY解串器及D-PHY解串器输出的二值信号数据列进行同步锁存。
本发明再一实施例提供的技术方案如下：
一种显示系统，所述显示系统包括：
驱动装置，所述驱动装置为上述的驱动装置；
连接模块，所述连接模块与驱动装置中的连接端子电性连接；
显示模块，所述显示模块与连接模块相连，用于显示驱动装置提供的数据。
本发明能够利用MIPI D-PHY通信和MIPI C-PHY通信实现驱动，减少了通信接口和电路规模，降低了成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例1中驱动装置的模块示意图。
图2为本发明实施例2中MIPI C-PHY通信框图。
图3为本发明实施例2中MIPI D-PHY通信框图。
图4为本发明实施例3中显示系统的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明中的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
本发明公开了一种驱动装置，包括：
一种驱动装置，驱动装置包括：
RGB模块，用于接收图像数据并转换为RGB信号；
第一协议处理模块及第二协议处理模块，分别与RGB模块相连，第一协议处理模块接收RGB信号后按照第一协议标准处理后输出第一信号，第二协议处理模块接收RGB信号后按照第二协议标准处理后输出第二信号；
选择器，与第一协议处理模块及第二协议处理模块相连，选择性接收第一信号和第二信号并输出；
第一解串器及第二解串器，与选择器相连，第一解串器用于对第一信号进行解码并输出二值信号数据列，第二解串器用于对第二信号进行解码并输出二值信号数据列；
若干发射器及若干连接端子，发射器与第一解串器及第二解串器相连，连接端子与发射器相连，用于接收二值信号数据列并输出驱动信号。
优选地，本发明中的驱动装置包括：
RGB模块，用于接收图像数据并转换为RGB信号；
C-PHY协议处理模块及D-PHY协议处理模块，分别与RGB模块相连，C-PHY协议处理模块接收RGB信号后按照MIPI C-PHY的协议标准处理后输出MIPI C-PHY信号，D-PHY协议处理模块接收RGB信号后按照MIPI D-PHY的协议标准处理后输出MIPI D-PHY信号；
C-PHY/D-PHY选择器，与C-PHY协议处理模块及D-PHY协议处理模块相连，选择性接收MIPI C-PHY信号和MIPI D-PHY信号并输出；
C-PHY解串器及D-PHY解串器，与C-PHY/D-PHY选择器相连，C-PHY解串器用于对MIPI C-PHY信号进行解码并输出二值信号数据列，D-PHY解串器用于对MIPI D-PHY信号进行解码并输出二值信号数据列；
若干发射器及若干连接端子，发射器与C-PHY解串器及D-PHY解串器相连，连接端子与发射器相连，用于接收二值信号数据列并输出驱动信号。
优选地，本发明中的驱动装置还包括：
时钟模块，与C-PHY解串器及D-PHY解串器相连，用于生成时钟信号；
若干触发器，触发器与时钟模块、C-PHY解串器及D-PHY解串器相连，触发器结合时钟信号对C-PHY解串器及D-PHY解串器输出的二值信号数据列进行同步锁存。
本发明还公开了一种驱动方法，包括：
S1、RGB模块接收图像数据并转换为RGB信号；
S2、第一协议处理模块接收RGB信号后按照第一协议标准处理后输出第一信号，或，第二协议处理模块接收RGB信号后按照第二协议标准处理后输出第二信号；
S3、选择器选择性接收第一信号和第二信号并输出；
S4、第一解串器对第一信号进行解码并输出二值信号数据列，或，第二解串器对第二信号进行解码并输出二值信号数据列；
S5、发射器接收第一解串器输出的二值信号数据列并通过连接端子输出二值信号，或，发射器接收第二解串器输出的二值信号数据列并转化为差分信号后输出。
优选地，本发明中的驱动方法具体为：
S1、RGB模块接收图像数据并转换为RGB信号；
S2、C-PHY协议处理模块接收RGB信号后按照MIPI C-PHY的协议标准处理后输出MIPI C-PHY信号，或，D-PHY协议处理模块接收RGB信号后按照MIPI D-PHY的协议标准处理后输出MIPI D-PHY信号；
S3、C-PHY/D-PHY选择器选择性接收MIPI C-PHY信号和MIPI D-PHY信号并输出；
S4、C-PHY解串器对MIPI C-PHY信号进行解码并输出二值信号数据列，或，D-PHY解串器对MIPI D-PHY信号进行解码并输出二值信号数据列；
S5、发射器接收C-PHY解串器输出的二值信号数据列并通过连接端子输出二值信号，或，发射器接收D-PHY解串器输出的二值信号数据列并转化为差分信号后输出。
进一步地，步骤S4后还包括：
触发器结合时钟信号对C-PHY解串器及D-PHY解串器输出的二值信号数据列进行同步锁存。
另外，本发明还公开了一种显示系统，包括：
驱动装置，驱动装置为上述的驱动装置；
连接模块，连接模块与驱动装置中的连接端子电性连接；
显示模块，显示模块与连接模块相连，用于显示驱动装置提供的数据。
以下结合具体实施例对本发明作进一步说明。
实施例1：
参图1所示，本实施例中的驱动装置包括：
RGB模块10，用于接收图像数据并转换为RGB信号。处理器可以为FPGA/PSOC等。
C-PHY协议处理模块21及D-PHY协议处理模块22，分别与RGB模块10相连，C-PHY协议处理模块21接收RGB信号后按照MIPI C-PHY的协议标准处理后输出MIPI C-PHY信号，D-PHY协议处理模块22接收RGB信号后按照MIPI D-PHY的协议标准处理后输出MIPI D-PHY信号。
C-PHY/D-PHY选择器30，与C-PHY协议处理模块21及D-PHY协议处理模块22相连，选择性接收MIPI C-PHY信号和MIPI D-PHY信号并输出。
C-PHY解串器41及D-PHY解串器42，与C-PHY/D-PHY选择器30相连，C-PHY解串器41用于对MIPI C-PHY信号进行解码并输出二值信号数据列，D-PHY解串器42用于对MIPI D-PHY信号进行解码并输出二值信号数据列。
时钟模块50，与C-PHY解串器及D-PHY解串器相连，用于生成时钟信号；
若干触发器，触发器与时钟模块50、C-PHY解串器41及D-PHY解串器42相连，触发器结合时钟信号对C-PHY解串器及D-PHY解串器输出的二值信号数据列进行同步锁存。
若干发射器及若干连接端子，发射器与C-PHY解串器41及D-PHY解串器42相连，连接端子与发射器相连，用于接收二值信号数据列并输出驱动信号。
其中，本实施例中的触发器包括：
第一触发器61、第二触发器62及第三触发器63，分别与C-PHY解串器41及时钟模块50相连，用于生成触发器时钟信号对C-PHY解串器41输出的二值信号数据列进行同步锁存；
第四触发器64及第五触发器65，分别与D-PHY解串器42及时钟模块50相连，用于生成触发器时钟信号对D-PHY解串器42输出的二值信号数据列进行同步锁存。
本实施例中的发射器中设有放大器，其中发射器包括：
第一发射器71，与第一触发器61和第四触发器64相连；
第二发射器72，与第二触发器62和第五触发器65相连；
第三发射器73，与第三触发器63和时钟信号50相连；
其中，第一发射器71、第二发射器72、第三发射器73用于传输C-PHY解串器输出的二值信号数据列、以及将D-PHY解串器输出的二值信号数据列转化为差分信号并传输。
驱动装置中的信号通过连接端子将驱动信号传输至外部显示模块，连接端子包括：
设于第一发射器71上的第一连接端子81和第二连接端子82；
设于第二发射器72上的第三连接端子83和第四连接端子84；
设于第三发射器73上的第五连接端子85和第六连接端子86；
其中，MIPI C-PHY信号通过第一连接端子81、第三连接端子83和第五连接端子85进行传输，MIPI D-PHY信号通过第一连接端子81、第二连接端子82、第三连接端子83、第四连接端子84、第五连接端子85和第六连接端子86进行传输。
本实施例中以5个触发器、3个发射器、6个连接端子为例进行说明，在其他实施例中，根据MIPI D-PHY的数据通道不同，可相应地增加触发器和连接端子的数量，此处不再详细举例说明。
实施例2：
本实施例中的驱动方法，以实施例1中的驱动装置为例，该驱动方法包括：
1、RGB模块接收图像数据并转换为RGB信号；
2、C-PHY协议处理模块接收RGB信号后按照MIPI C-PHY的协议标准处理后输出MIPI C-PHY信号，或，D-PHY协议处理模块接收RGB信号后按照MIPI D-PHY的协议标准处理后输出MIPI D-PHY信号；
3、C-PHY/D-PHY选择器选择性接收MIPI C-PHY信号和MIPI D-PHY信 号并输出；
4、C-PHY解串器对MIPI C-PHY信号进行解码并输出二值信号数据列，或，D-PHY解串器对MIPI D-PHY信号进行解码并输出二值信号数据列；
5、触发器结合时钟信号对C-PHY解串器及D-PHY解串器输出的二值信号数据列进行同步锁存。
6、发射器接收C-PHY解串器输出的二值信号数据列并通过连接端子输出二值信号，或，发射器接收D-PHY解串器输出的二值信号数据列并转化为差分信号后输出。
本实施例中的驱动方法包括MIPI C-PHY通信和MIPI D-PHY通信两种方式。
参图2所示，MIPI C-PHY通信时，C-PHY/D-PHY选择器选择MIPI C-PHY信号并传送到MIPI C-PHY解串器。MIPI C-PHY解串器解码MIPI C-PHY信号输出二值信号数据列，此时MIPI D-PHY解串器是没有数据列输出的。二值信号数据列被第一触发器、第二触发器和第三触发器接收，与时钟模块接收的解串器时钟进行时钟再生，生成触发器时钟信号对数据列进行同步锁存。触发器生成的二值信号数据列传送到发射器，第一至第三发射器将数据列传送到第一连接端子、第三连接端子和第五连接端子，进而传输到显示模块进行驱动。
参图3所示，MIPI D-PHY通信时，C-PHY/D-PHY选择器选择MIPI D-PHY信号并传送到MIPI D-PHY解串器。MIPI D-PHY解串器解码MIPI D-PHY信号输出二值信号数据列，此时MIPI C-PHY解串器是没有数据列输出的。二值信号的数据列被第四触发器和第五触发器接收，与CLK对数据列进行同步锁存。触发器生成的二值信号数据列传送到发射器，第一至第三发射器将接收的二值信号转化为差分信号，连接端子将信并通过第一连接端子至第六连接端子传输到显示模块。
实施例3：
参图4所示，本实施中的显示系统包括：
驱动装置100，驱动装置可以为实施例1中的驱动装置，此处不再进行赘述。驱动装置提供显示需要的图像/音视频数据和电压；
连接模块200，连接模块200与驱动装置100中的连接端子电性连接。连接模块可以是FPCA或者连接线缆，连接端子可以是ZIF/BTB/DIP等接口模式；
显示模块300，显示模块300与连接模块200相连，用于显示驱动装置提供的数据。显示模块可以是液晶显示面板或者AMOLED显示面板等，显示驱动装置提供的图像/音视频等数据。
应当理解的是，上述各实施例中协议处理模块以C-PHY协议处理模块及D-PHY协议处理模块为例进行说明，C-PHY协议处理模块及D-PHY协议处理模块分别按照MIPI C-PHY的协议标准及MIPI D-PHY的协议标准对RGB信号进行处理后输出MIPI C-PHY信号及MIPI D-PHY信号；选择器采用C-PHY/D-PHY选择器选择性接收MIPI C-PHY信号和MIPI D-PHY信号并输出；解串器包括C-PHY解串器及D-PHY解串器，分别对MIPI C-PHY信号及MIPI D-PHY信号进行解码并输出二值信号数据列。在其他实施方式中，可以根据不同的通信协议及信号选择不同的协议处理模块、选择器、及解串器，此处不再一一进行赘述。
本发明实施例还提供一种电子设备。所述电子设备包括至少一个处理器和与所述至少一个处理器连接的存储器，所述存储器用于存储可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行时，使所述至少一个处理器执行上述实施例中的驱动方法。
本发明实施例还提供了一种非暂态存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述的驱动方法。
本发明实施例还提供了一种计算机程序产品，所述计算机程序产品包括存储在非暂态计算机可读存储介质上的计算机程序，所述计算机程序包括程序指令，当所述程序指令被计算机执行时，使所述计算机执行上述的驱动方法。
本发明实施例提供的驱动装置可执行本发明任意实施例所提供的驱动方法，具备执行方法相应的功能模块和有益效果。未在上述实施例中详尽描述的 技术细节，可参见本发明任意实施例所提供的驱动方法。
与现有技术相比，本发明具有以下有益效果：
本发明能够利用MIPI D-PHY通信和MIPI C-PHY通信实现驱动，减少了通信接口和电路规模，降低了成本。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (16)

  1. 一种驱动装置，其中，所述驱动装置包括：
    RGB模块，用于接收图像数据并转换为RGB信号；
    第一协议处理模块及第二协议处理模块，分别与所述RGB模块相连，所述第一协议处理模块接收RGB信号后按照第一协议标准处理后输出第一信号，所述第二协议处理模块接收RGB信号后按照第二协议标准处理后输出第二信号；
    选择器，与所述第一协议处理模块及第二协议处理模块相连，选择性接收第一信号和第二信号并输出；
    第一解串器及第二解串器，与所述选择器相连，所述第一解串器用于对第一信号进行解码并输出二值信号数据列，所述第二解串器用于对第二信号进行解码并输出二值信号数据列；
    若干发射器及若干连接端子，发射器与第一解串器及第二解串器相连，连接端子与发射器相连，用于接收二值信号数据列并输出驱动信号。
  2. 根据权利要求1所述的驱动装置，其中，所述驱动装置包括：
    RGB模块，用于接收图像数据并转换为RGB信号；
    C-PHY协议处理模块及D-PHY协议处理模块，分别与所述RGB模块相连，所述C-PHY协议处理模块接收RGB信号后按照MIPI C-PHY的协议标准处理后输出MIPI C-PHY信号，所述D-PHY协议处理模块接收RGB信号后按照MIPI D-PHY的协议标准处理后输出MIPI D-PHY信号；
    C-PHY/D-PHY选择器，与所述C-PHY协议处理模块及D-PHY协议处理模块相连，选择性接收MIPI C-PHY信号和MIPI D-PHY信号并输出；
    C-PHY解串器及D-PHY解串器，与所述C-PHY/D-PHY选择器相连，所述C-PHY解串器用于对MIPI C-PHY信号进行解码并输出二值信号数据列， 所述D-PHY解串器用于对MIPI D-PHY信号进行解码并输出二值信号数据列；
    若干发射器及若干连接端子，发射器与C-PHY解串器及D-PHY解串器相连，连接端子与发射器相连，用于接收二值信号数据列并输出驱动信号。
  3. 根据权利要求2所述的驱动装置，其中，所述驱动装置还包括：
    时钟模块，与C-PHY解串器及D-PHY解串器相连，用于生成时钟信号。
  4. 根据权利要求3所述的驱动装置，其中，所述驱动装置还包括：
    若干触发器，所述触发器与时钟模块、C-PHY解串器及D-PHY解串器相连，触发器结合时钟信号对C-PHY解串器及D-PHY解串器输出的二值信号数据列进行同步锁存，所述触发器包括：
    第一触发器、第二触发器及第三触发器，分别与C-PHY解串器及时钟模块相连，用于生成触发器时钟信号对C-PHY解串器输出的二值信号数据列进行同步锁存；
    第四触发器及第五触发器，分别与D-PHY解串器及时钟模块相连，用于生成触发器时钟信号对D-PHY解串器输出的二值信号数据列进行同步锁存。
  5. 根据权利要求4所述的驱动装置，其中，所述发射器包括：
    第一发射器，与第一触发器和第四触发器相连；
    第二发射器，与第二触发器和第五触发器相连；
    第三发射器，与第三触发器和时钟信号相连；
    其中，所述第一发射器、第二发射器、第三发射器用于传输C-PHY解串器输出的二值信号数据列、以及将D-PHY解串器输出的二值信号数据列转化为差分信号并传输。
  6. 根据权利要求5所述的驱动装置，其中，所述连接端子包括：
    设于第一发射器上的第一连接端子和第二连接端子；
    设于第二发射器上的第三连接端子和第四连接端子；
    设于第三发射器上的第五连接端子和第六连接端子；
    其中，MIPI C-PHY信号通过第一连接端子、第三连接端子和第五连接端子进行传输，MIPI D-PHY信号通过第一连接端子、第二连接端子、第三连接端子、第四连接端子、第五连接端子和第六连接端子进行传输。
  7. 根据权利要求5所述的驱动装置，其中，所述发射器中设有放大器。
  8. 一种驱动方法，其中，所述驱动方法包括：
    S1、RGB模块接收图像数据并转换为RGB信号；
    S2、第一协议处理模块接收RGB信号后按照第一协议标准处理后输出第一信号，或，第二协议处理模块接收RGB信号后按照第二协议标准处理后输出第二信号；
    S3、选择器选择性接收第一信号和第二信号并输出；
    S4、第一解串器对第一信号进行解码并输出二值信号数据列，或，第二解串器对第二信号进行解码并输出二值信号数据列；
    S5、发射器接收第一解串器输出的二值信号数据列并通过连接端子输出二值信号，或，发射器接收第二解串器输出的二值信号数据列并转化为差分信号后输出。
  9. 根据权利要求8所述的驱动方法，其中，所述驱动方法具体为：
    S1、RGB模块接收图像数据并转换为RGB信号；
    S2、C-PHY协议处理模块接收RGB信号后按照MIPI C-PHY的协议标准处理后输出MIPI C-PHY信号，或，D-PHY协议处理模块接收RGB信号后按照MIPI D-PHY的协议标准处理后输出MIPI D-PHY信号；
    S3、C-PHY/D-PHY选择器选择性接收MIPI C-PHY信号和MIPI D-PHY信号并输出；
    S4、C-PHY解串器对MIPI C-PHY信号进行解码并输出二值信号数据列，或，D-PHY解串器对MIPI D-PHY信号进行解码并输出二值信号数据列，触发器结合时钟信号对C-PHY解串器及D-PHY解串器输出的二值信号数据列进行同步锁存；
    S5、发射器接收C-PHY解串器输出的二值信号数据列并通过连接端子输出二值信号，或，发射器接收D-PHY解串器输出的二值信号数据列并转化为差分信号后输出。
  10. 一种显示系统，其中，所述显示系统包括：
    驱动装置，所述驱动装置为权利要求1所述的驱动装置；
    连接模块，所述连接模块与驱动装置中的连接端子电性连接；
    显示模块，所述显示模块与连接模块相连，用于显示驱动装置提供的数据。
  11. 根据权利要求10所述的显示系统，其中，所述驱动装置包括：
    RGB模块，用于接收图像数据并转换为RGB信号；
    C-PHY协议处理模块及D-PHY协议处理模块，分别与所述RGB模块相连，所述C-PHY协议处理模块接收RGB信号后按照MIPI C-PHY的协议标准处理后输出MIPI C-PHY信号，所述D-PHY协议处理模块接收RGB信号后按照MIPI D-PHY的协议标准处理后输出MIPI D-PHY信号；
    C-PHY/D-PHY选择器，与所述C-PHY协议处理模块及D-PHY协议处理模块相连，选择性接收MIPI C-PHY信号和MIPI D-PHY信号并输出；
    C-PHY解串器及D-PHY解串器，与所述C-PHY/D-PHY选择器相连，所述C-PHY解串器用于对MIPI C-PHY信号进行解码并输出二值信号数据列，所述D-PHY解串器用于对MIPI D-PHY信号进行解码并输出二值信号数据列；
    若干发射器及若干连接端子，发射器与C-PHY解串器及D-PHY解串器相连，连接端子与发射器相连，用于接收二值信号数据列并输出驱动信号。
  12. 根据权利要求11所述的显示系统，其中，所述驱动装置还包括：
    时钟模块，与C-PHY解串器及D-PHY解串器相连，用于生成时钟信号。
  13. 根据权利要求12所述的显示系统，其中，所述驱动装置还包括：
    若干触发器，所述触发器与时钟模块、C-PHY解串器及D-PHY解串器相连，触发器结合时钟信号对C-PHY解串器及D-PHY解串器输出的二值信号数据列进行同步锁存，所述触发器包括：
    第一触发器、第二触发器及第三触发器，分别与C-PHY解串器及时钟模块相连，用于生成触发器时钟信号对C-PHY解串器输出的二值信号数据列进行同步锁存；
    第四触发器及第五触发器，分别与D-PHY解串器及时钟模块相连，用于生成触发器时钟信号对D-PHY解串器输出的二值信号数据列进行同步锁存。
  14. 根据权利要求13所述的显示系统，其中，所述发射器包括：
    第一发射器，与第一触发器和第四触发器相连；
    第二发射器，与第二触发器和第五触发器相连；
    第三发射器，与第三触发器和时钟信号相连；
    其中，所述第一发射器、第二发射器、第三发射器用于传输C-PHY解串器输出的二值信号数据列、以及将D-PHY解串器输出的二值信号数据列转化为差分信号并传输。
  15. 根据权利要求14所述的显示系统，其中，所述连接端子包括：
    设于第一发射器上的第一连接端子和第二连接端子；
    设于第二发射器上的第三连接端子和第四连接端子；
    设于第三发射器上的第五连接端子和第六连接端子；
    其中，MIPI C-PHY信号通过第一连接端子、第三连接端子和第五连接端子进行传输，MIPI D-PHY信号通过第一连接端子、第二连接端子、第三连接端子、第四连接端子、第五连接端子和第六连接端子进行传输。
  16. 根据权利要求15所述的显示系统，其中，所述发射器中设有放大器。
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