WO2019192365A1 - 像素驱动电路的布线结构、显示面板和显示装置 - Google Patents

像素驱动电路的布线结构、显示面板和显示装置 Download PDF

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Publication number
WO2019192365A1
WO2019192365A1 PCT/CN2019/079821 CN2019079821W WO2019192365A1 WO 2019192365 A1 WO2019192365 A1 WO 2019192365A1 CN 2019079821 W CN2019079821 W CN 2019079821W WO 2019192365 A1 WO2019192365 A1 WO 2019192365A1
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Prior art keywords
signal line
coupled
switching element
driving circuit
driving transistor
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PCT/CN2019/079821
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English (en)
French (fr)
Inventor
陈义鹏
刘利宾
李云飞
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/614,813 priority Critical patent/US11450723B2/en
Publication of WO2019192365A1 publication Critical patent/WO2019192365A1/zh
Priority to US17/891,211 priority patent/US20220406878A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a wiring structure, a display panel, and a display device of a pixel driving circuit.
  • OLED Organic Light Emitting Diode
  • LCD Liquid Crystal Display
  • a wiring structure of a pixel driving circuit includes: a first switching element, a control end of the first switching element is coupled to a scan signal line, and the first switching element The first end is coupled to the data signal line, the second end of the first switching element is coupled to the first node, and the driving transistor is coupled to the second node, the first end of the driving transistor The second signal end of the driving transistor is coupled to the third node; wherein the power signal line includes a first power signal line that is in the same direction as the data signal line, and the data signal line A first distance between the control terminals of the drive transistor is greater than a second distance between the first power signal line and the control terminal of the drive transistor.
  • the first power signal line and the data signal line are located on the same side of the control end of the driving transistor.
  • the pixel driving circuit further includes: a storage capacitor, the first node is coupled to the first plate of the storage capacitor through a first wire, and the second node passes The second wire is coupled to the second plate of the storage capacitor; wherein the scan signal line does not overlap with the first wire and/or the second wire.
  • the power signal line further includes a second power signal line that is in the same direction as the scan signal line, and the data signal that extends from the second power signal line
  • the line has an extension of the overlapping area.
  • the second power signal line is disposed in the same layer as the extension, the first power signal line is disposed in the same layer as the data signal line, and the second power signal is The line is disposed in a different layer from the first power signal line and communicates through the via.
  • an overlapping area between the data signal line and the extension portion is determined according to a voltage jump value of a control terminal and a first end of the driving transistor.
  • a first distance between the data signal line and a control terminal of the driving transistor is determined according to a voltage transition value of a control terminal and a first terminal of the driving transistor.
  • the pixel driving circuit further includes: a second switching element, a control end of the second switching element is coupled to the scan signal line, and the first of the second switching element The second end of the second switching element is coupled to the third node.
  • the first switching element and the second switching element are both MOS transistors.
  • a display panel including the above-described pixel driving circuit is provided.
  • a display device including the above display panel is provided.
  • FIG. 1 is a view schematically showing a wiring structure diagram of a pixel driving circuit in the related art
  • FIG. 2 is a schematic view showing a first schematic diagram of a pixel driving circuit in an exemplary embodiment of the present disclosure
  • FIG. 3 schematically shows a schematic diagram 2 of a pixel driving circuit in an exemplary embodiment of the present disclosure
  • FIG. 4 schematically shows a wiring structure diagram of a pixel driving circuit in an exemplary embodiment of the present disclosure.
  • a parasitic capacitance exists between a data signal line and a gate and a source of a driving transistor.
  • the gate of the driving transistor is driven when the voltage of the data signal line jumps.
  • the jump amplitude of the voltage Vg is greater than the jump amplitude of the source voltage Vs of the driving transistor, so that the gate-source voltage difference Vgs of the driving transistor changes accordingly, thereby causing a local brightness difference on the display screen of the display, which causes Crosstalk problem with the display.
  • Fig. 1 schematically shows a wiring structure diagram of a pixel driving circuit in the related art.
  • the jump width of the gate voltage Vg of the driving transistor DTFT is larger than the jump width of the source voltage Vs of the driving transistor DTFT.
  • the falling amplitude of the gate voltage Vg is greater than the falling amplitude of the source voltage Vs, so that the gate-source voltage difference Vgs of the driving transistor DTFT is reduced, thereby causing the display.
  • the local brightness rises; or when the voltage of the data signal line Data jumps to a high level, the rising range of the gate voltage Vg is greater than the rising range of the source voltage Vs, so that the gate-source voltage difference Vgs of the driving transistor DTFT Increased, resulting in a decrease in the local brightness of the display.
  • the present exemplary embodiment provides a wiring structure of a pixel driving circuit, which can be applied to a wiring design of an OLED pixel driving circuit, and the OLED pixel driving circuit can be a data signal line and a driving transistor determined by crosstalk testing.
  • the OLED pixel driving circuit can be a data signal line and a driving transistor determined by crosstalk testing.
  • There is a pixel driving circuit with different degrees of coupling between the gate and the source such as the pixel driving circuit shown in FIG. 2 and FIG. 3, and is not limited thereto.
  • the degree of coupling between the data signal line and the gate and source of the driving transistor can be tested, for example, by using an oscilloscope to test the gate lead and source of the driving transistor under the crosstalk test screen with voltage jump.
  • the jump condition of the pole lead line, the crosstalk test picture may be, for example, a test picture in which a black block or a white block is set in a background picture of a L128 gray level (the brightest is L255 gray level), wherein the black block indicates a voltage jump, a white block Indicates that the voltage jumps.
  • FIG. 2 schematically shows a first schematic diagram of a pixel driving circuit in an exemplary embodiment of the present disclosure.
  • the pixel driving circuit provided in the embodiment of the present disclosure may include a first switching element T1, a second switching element T2, a third switching element T3 (as a driving transistor DTFT), a fourth switching element T4, and a fifth.
  • the switching element T5, the sixth switching element T6, the seventh switching element T7, the eighth switching element T8, and the ninth switching element T9 may further include a storage capacitor C and an organic light emitting diode OLED.
  • the control end of the first switching element T1 can be coupled to the scanning signal line Gate.
  • the first end of the first switching element T1 can be coupled to the data signal line Data, and the second end of the first switching element T1 can be coupled.
  • the control end of the second switching element T2 can be coupled to the scan signal line Gate.
  • the first end of the second switching element T2 can be coupled to the second node N2, and the second end of the second switching element T2 can be coupled to the third node N3.
  • the control terminal (eg, the gate) of the driving transistor DTFT can be coupled to the second node N2.
  • the first terminal (eg, the source) of the driving transistor DTFT can be coupled to the first power signal line VDD, and the second end of the driving transistor DTFT (for example The drain) may be coupled to the third node N3.
  • the control terminal of the fourth switching component T4 can be coupled to the reset signal line Reset.
  • the first terminal of the fourth switching component T4 can be coupled to the second node N2, and the second terminal of the fourth switching component T4 can be coupled to the initialization signal line Vinit.
  • the control terminal of the fifth switching component T5 can be coupled to the reset signal line Reset.
  • the first terminal of the fifth switching component T5 can be coupled to the first node N1, and the second terminal of the fifth switching component T5 can be coupled to the initialization signal line Vinit.
  • the control end of the sixth switching element T6 can be coupled to the illumination control signal line EM.
  • the first end of the sixth switching element T6 can be coupled to the first node N1, and the second end of the sixth switching element T6 can be coupled to the initialization signal line Vinit.
  • the control terminal of the seventh switching element T7 can be coupled to the illumination control signal line EM, the first end of the seventh switching element T7 can be coupled to the third node N3, and the second end of the seventh switching element T7 can be coupled to the organic light emitting The first end of the diode OLED.
  • the control end of the eighth switching element T8 can be coupled to the reset signal line Reset, the first end of the eighth switching element T8 can be coupled to the second end of the seventh switching element T7, and the second end of the eighth switching element T8 can be coupled Initialize the signal line Vinit.
  • the control end of the ninth switching element T9 can be coupled to the illuminating control signal line EM, the first end of the ninth switching element T9 can be coupled to the second node N2, and the second end of the ninth switching element T9 is suspended, where the ninth switching element T9 is equivalent to a capacitor.
  • the first plate of the storage capacitor C can be coupled to the first node N1, and the second plate of the storage capacitor C can be coupled to the second node N2.
  • the second end of the organic light emitting diode OLED may be coupled to the third power signal line VSS.
  • FIG. 3 schematically shows a schematic diagram 2 of a pixel driving circuit in an exemplary embodiment of the present disclosure.
  • the pixel driving circuit provided in the embodiment of the present disclosure may include a first switching element T1, a second switching element T2, a third switching element T3 (as a driving transistor DTFT), a fourth switching element T4, and a fifth.
  • the switching element T5, the sixth switching element T6, the seventh switching element T7, and the eighth switching element T8 may further include a storage capacitor C and an organic light emitting diode OLED.
  • the control end of the first switching element T1 can be coupled to the scanning signal line Gate.
  • the first end of the first switching element T1 can be coupled to the data signal line Data, and the second of the first switching element T1.
  • the terminal can be coupled to the first node N1.
  • the control end of the second switching element T2 can be coupled to the scan signal line Gate.
  • the first end of the second switching element T2 can be coupled to the second node N2, and the second end of the second switching element T2 can be coupled to the third node N3.
  • the control terminal (eg, the gate) of the driving transistor DTFT can be coupled to the second node N2.
  • the first terminal (eg, the source) of the driving transistor DTFT can be coupled to the first power signal line VDD, and the second end of the driving transistor DTFT (for example The drain) may be coupled to the third node N3.
  • the control terminal of the fourth switching component T4 can be coupled to the reset signal line Reset.
  • the first terminal of the fourth switching component T4 can be coupled to the second node N2, and the second terminal of the fourth switching component T4 can be coupled to the initialization signal line Vinit.
  • the control terminal of the fifth switching component T5 can be coupled to the reset signal line Reset.
  • the first terminal of the fifth switching component T5 can be coupled to the first node N1, and the second terminal of the fifth switching component T5 can be coupled to the reference voltage signal line Vref. .
  • the control terminal of the sixth switching component T6 can be coupled to the illumination control signal line EM.
  • the first end of the sixth switching component T6 can be coupled to the first node N1, and the second end of the sixth switching component T6 can be coupled to the reference voltage signal line. Vref.
  • the control terminal of the seventh switching element T7 can be coupled to the illumination control signal line EM, the first end of the seventh switching element T7 can be coupled to the third node N3, and the second end of the seventh switching element T7 can be coupled to the organic light emitting The first end of the diode OLED.
  • the control end of the eighth switching element T8 can be coupled to the scan signal line Gate.
  • the first end of the eighth switching element T8 can be coupled to the second end of the seventh switching element T7, and the second end of the eighth switching element T8 can be coupled. Initialize the signal line Vinit.
  • the first plate of the storage capacitor C can be coupled to the first node N1, and the second plate of the storage capacitor C can be coupled to the second node N2.
  • the second end of the organic light emitting diode OLED may be coupled to the third power signal line VSS.
  • FIG. 4 schematically shows a wiring structure diagram of a pixel driving circuit in the present exemplary embodiment.
  • the pixel driving circuit provided by the embodiment of the present disclosure may include a scanning signal line Gate disposed in a first direction, for example, a lateral direction, a data signal line Data, which is disposed in the second direction, for example, a vertical direction, and a power signal line VDD.
  • the power signal line VDD may include at least a first power signal line VDD1 that is in the same direction as the data signal line Data.
  • the pixel driving circuit may further include: a first switching element T1, the control end of the first switching element T1 is coupled to the scanning signal line Gate, and the first end of the first switching element T1 is coupled to the data signal line Data
  • the second end of the first switching element T1 is coupled to the first node N1, and the second switching element T2 is coupled to the scanning signal line Gate and the first end of the first switching element T2.
  • the second node N2, the second end of the first switching element T2 is coupled to the third node N3, the driving transistor DTFT, the gate of the driving transistor DTFT is coupled to the second node N2, the source of the driving transistor DTFT is coupled to the power signal line VDD, The drain of the driving transistor DTFT is coupled to the third node N3; and the storage capacitor C, the first node N1 is coupled to the first plate 10 of the storage capacitor C, and the second node N2 is coupled to the storage capacitor The second plate 20 of C.
  • the first power signal line VDD1 and the data signal line Data are both disposed on the same side of the gate of the driving transistor DTFT, and between the data signal line Data and the gate of the driving transistor DTFT A distance is greater than a second distance between the first power signal line VDD1 and the gate of the driving transistor DTFT, that is, the first power signal line VDD1 is disposed near the gate of the driving transistor DTFT, and the data signal line Data is away from the driving transistor DTFT.
  • the gate setting is greater than a second distance between the first power signal line VDD1 and the gate of the driving transistor DTFT, that is, the first power signal line VDD1 is disposed near the gate of the driving transistor DTFT, and the data signal line Data is away from the driving transistor DTFT.
  • the pixel driving circuit provided by the exemplary embodiment of the present disclosure increases the distance between the data signal line Data and the gate of the driving transistor DTFT by adjusting the wiring position of the data signal line Data, thereby reducing the data signal line Data and
  • the degree of coupling of the gate of the driving transistor DTFT thereby achieving the effect of reducing the gate-to-source voltage difference of the driving transistor DTFT, can improve the local brightness unevenness of the display, thereby improving the crosstalk phenomenon of the display.
  • the first node N1 may be coupled to the first plate 10 through the first wire 100
  • the second node N2 may be coupled to the second plate 20 through the second wire 200.
  • FIG. 4 only exemplarily indicates the relative positions of the first plate 10 and the second plate 20, and may be the first plate 10 on the top and the second plate 20 on the bottom. The first plate 10 is on the lower side and the second plate 20 is on the top.
  • the data signal line Data has a strong coupling degree with the gate of the driving transistor DTFT except that it is closer to the gate of the driving transistor DTFT.
  • the line Data further generates a larger series capacitance between the first wire 100 (the first node N1) and the second wire 200 (the second node N2) through the scanning signal line Gate, thereby further enhancing the data signal line Data and the driving transistor.
  • the degree of coupling between the gates of the DTFT can control that there is no overlap between the scan signal line Gate and the first wire 100 and the second wire 200, thereby preventing the data signal line Data from passing through the scan signal line.
  • the gate generates a series capacitance between the first wire 100 (the first node N1) and the second wire 200 (the second node N2), thereby further reducing the degree of coupling between the data signal line Data and the gate of the driving transistor DTFT.
  • the scanning signal line Gate does not overlap with the first wire 100 and the second wire 200, for example, by moving the portion of the scanning signal line Gate originally overlapping the first wire 100 and the second wire 200, or This can be achieved by adjusting the position of the second end of the first switching element T1 and the first end of the second switching element T2.
  • the power supply signal line VDD may include a first power supply signal line VDD1 that is in the same direction as the data signal line Data, and may also include a first direction that is opposite to the scan signal line Gate.
  • the second power supply signal line VDD2 and the extension portion VDD3 extending from the second power supply signal line VDD2 and having an overlap region with the data signal line Data, thereby increasing the parasitic between the data signal line Data and the power supply signal line VDD capacitance. Since the power signal line VDD is connected to the source of the driving transistor DTFT, increasing the parasitic capacitance between the data signal line Data and the power signal line VDD increases the data signal line Data and the source of the driving transistor DTFT.
  • the first power signal line VDD1 and the data signal line Data can be disposed in the same layer
  • the second power signal line VDD2 and the extension VDD3 can be disposed in the same layer
  • the second power signal line VDD2 The first power signal line VDD1 may be disposed in a different layer and communicated through the via.
  • the first distance between the data signal line Data and the gate of the driving transistor DTFT and the overlapping area between the data signal line Data and the extension VDD3 of the power signal line VDD can be, for example, pre-acquired.
  • the voltage hopping value of the gate and source of the driving transistor DTFT is determined under test conditions. The test conditions have been described in detail above, and are not described herein again.
  • the present exemplary embodiment can reduce the degree of coupling between the data signal line Data and the gate of the driving transistor DTFT by adjusting the wiring position of the data signal line Data, and can control the scanning on the other hand.
  • the signal line Gate has no overlap with the first node N1 and the second node N2 to further reduce the degree of coupling between the data signal line Data and the gate of the driving transistor DTFT, and on the other hand, through setting and data signal lines.
  • Data has an extension VDD3 of the power supply signal line VDD of the overlap region to enhance the degree of coupling between the data signal line Data and the source of the drive transistor DTFT.
  • the stability of the gate-source voltage difference Vgs of the driving transistor DTFT can be ensured by the above-described wiring structure, thereby improving the problem of local brightness unevenness of the display, for example, in the crosstalk test screen, thereby solving the crosstalk problem of the display.
  • the first switching element T1 and the second switching element T2 may each be a MOS (Metal-Oxide-Semiconductor) transistor, such as a P-type MOS transistor or an N-type MOS transistor.
  • MOS Metal-Oxide-Semiconductor
  • the pixel driving circuit may further include a reset signal line Reset, an emission control signal line EM, an initialization signal line Vinit, a third power supply signal line VSS, and fourth to ninth switching elements (T4 to T9). .
  • Reset reset signal line Reset
  • EM emission control signal line
  • Vinit initialization signal line Vinit
  • VSS third power supply signal line
  • fourth to ninth switching elements T4 to T9
  • the pixel driving circuit may further include a reset signal line Reset, an emission control signal line EM, an initialization signal line Vinit, a third power signal line VSS, and fourth to eighth switching elements (T4 to T8). ). Based on this, in the actual wiring structure of the pixel driving circuit, the layout design of each switching element can be performed according to the coupling relationship shown in FIG. 2 or FIG. 3, which will not be enumerated here.
  • the example embodiment also provides a display panel including the above-described pixel driving circuit.
  • the display panel can exhibit better brightness stability when performing crosstalk test, and thus has good display quality.
  • the example embodiment also provides a display device including the above display panel.
  • the display device may include any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • modules or units of equipment for action execution are mentioned in the detailed description above, such division is not mandatory. Indeed, in accordance with embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one of the modules or units described above may be further divided into multiple modules or units.

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Abstract

提供一种像素驱动电路的布线结构、显示面板和显示装置。该像素驱动电路包括：第一开关元件（T1），控制端耦接扫描信号线（Gate）、第一端耦接数据信号线（Data）、第二端耦接第一节点（N1）；驱动晶体管（DTFT），控制端耦接第二节点（N2）、第一端耦接电源信号线（VDD）、第二端耦接第三节点（N3）；电源信号线包括与数据信号线同向的第一电源信号线（VDD1），数据信号线与驱动晶体管的控制端之间的第一距离大于第一电源信号线与驱动晶体管的控制端之间的第二距离。该驱动电路可改善由驱动晶体管的栅源电压跳变不一致而造成的串扰问题。

Description

像素驱动电路的布线结构、显示面板和显示装置
本公开要求申请日为2018年4月4日、申请号为CN201810300615.4、发明创造名称为《像素驱动电路的布线结构、显示面板和显示装置》的发明专利申请的优先权。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路的布线结构、显示面板和显示装置。
背景技术
随着自发光显示技术的发展，OLED(Organic Light Emitting Diode，有机发光二极管)显示器以其低能耗、低成本、宽视角、响应速度快等优点，逐渐开始取代传统的LCD(Liquid Crystal Display，液晶显示器)。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种像素驱动电路的布线结构，所述像素驱动电路包括：第一开关元件，所述第一开关元件的控制端耦接扫描信号线，所述第一开关元件的第一端耦接数据信号线，所述第一开关元件的第二端耦接第一节点；驱动晶体管，所述驱动晶体管的控制端耦接第二节点，所述驱动晶体管的第一端耦接电源信号线，所述驱动晶体管的第二端耦接第三节点；其中，所述电源信号线包括与所述数据信号线同向的第一电源信号线，所述数据信号线与所述驱动晶体管的控制端之间的第一距离大于所述第一电源信号线与所述驱动晶体管的控制端之间的第二距离。
本公开的一种示例性实施例中，所述第一电源信号线与所述数据信号线位于所述驱动晶体管的控制端的同侧。
本公开的一种示例性实施例中，所述像素驱动电路还包括：存储电容，所述第一节点通过第一导线耦接至所述存储电容的第一极板，所述第二节点通过第二导线耦接至所述存储电容的第二极板；其中，所述扫描信号线与所述第一导线和/或所述第二导线之间无交叠。
本公开的一种示例性实施例中，所述电源信号线还包括与所述扫描信号线同向的第二电源信号线，以及自所述第二电源信号线延伸出的与所述数据信号线具有交叠区域的延伸部。
本公开的一种示例性实施例中，所述第二电源信号线与所述延伸部同层设置，所述第一电源信号线与所述数据信号线同层设置，所述第二电源信号线与所述第一电源信号线异层设置且通过过孔相连通。
本公开的一种示例性实施例中，所述数据信号线与所述延伸部之间的交叠面积根据所述驱动晶体管的控制端与第一端的电压跳变值确定。
本公开的一种示例性实施例中，所述数据信号线与所述驱动晶体管的控制端之间的第一距离根据所述驱动晶体管的控制端与第一端的电压跳变值确定。本公开的一种示例性实施例中，所述像素驱动电路还包括：第二开关元件，所述第二开关元件的控制端耦接所述扫描信号线，所述第二开关元件的第一端耦接所述第二节点，所述第二开关元件的第二端耦接所述第三节点。
本公开的一种示例性实施例中，所述第一开关元件和所述第二开关元件均为MOS晶体管。
根据本公开的一个方面，提供一种显示面板，包括上述的像素驱动电路。
根据本公开的一个方面，提供一种显示装置，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性示出相关技术中像素驱动电路的布线结构图；
图2示意性示出本公开示例性实施例中像素驱动电路的示意图一；
图3示意性示出本公开示例性实施例中像素驱动电路的示意图二；
图4示意性示出本公开示例性实施例中像素驱动电路的布线结构图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能 实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
在AMOLED(Active-Matrix Organic Light Emitting Diode，有源矩阵有机发光二极管)显示器的像素驱动电路的相关布线结构中，数据信号线与驱动晶体管的栅极和源极之间均存在寄生电容。但由于数据信号线与驱动晶体管的栅极之间的耦合程度强于数据信号线与驱动晶体管的源极之间的耦合程度，因此在数据信号线的电压发生跳变时，驱动晶体管的栅极电压Vg的跳变幅度就会大于驱动晶体管的源极电压Vs的跳变幅度，使得驱动晶体管的栅源电压差Vgs随之发生变化，从而导致显示器的显示画面出现局部亮度差异，这样就会造成显示器的串扰问题。
图1示意性示出了相关技术中的像素驱动电路的布线结构图。
如图1所示，数据信号线Data与驱动晶体管DTFT的栅极01(耦接第二节点N2)和源极02(耦接电源信号线VDD)之间均存在寄生电容。由于数据信号线Data与驱动晶体管DTFT的栅极之间的距离较近，因此数据信号线Data与驱动晶体管DTFT的栅极01之间的耦合程度强于数据信号线Data与驱动晶体管DTFT的源极之间的耦合程度。这样一来，在数据信号线Data的电压发生跳变例如显示特定串扰测试画面时，驱动晶体管DTFT的栅极电压Vg的跳变幅度就会大于驱动晶体管DTFT的源极电压Vs的跳变幅度。例如在数据信号线Data的电压向低电平跳变时，栅极电压Vg的下降幅度就会大于源极电压Vs的下降幅度，使得驱动晶体管DTFT的栅源电压差Vgs减小，从而导致显示器的局部亮度升高；或者在数据信号线Data的电压向高电平跳变时，栅极电压Vg的上升幅度就会大于源极电压Vs的上升幅度，使得驱动晶体管DTFT的栅源电压差Vgs增大，从而导致显示器的局部亮度降低。
基于此，本示例实施方式提供了一种像素驱动电路的布线结构，可应用于OLED像素驱动电路的布线设计，该OLED像素驱动电路可以为通过串扰测试而判断出的数据信号线与驱动晶体管的栅极和源极之间存在不同耦合程度的像素驱动电路，例如图2和图3所示的像素驱动电路，且不以此为限。其中，数据信号线与驱动晶体管的栅极和源极之间的耦合程度例如可以采用如下方法进行测试：在具有电压跳变的串扰测试画面下，示波器分别测试驱动晶体管的栅极引出线和源极引出线的跳变情况，该串扰测试画面例如可以为在L128灰阶(最亮为L255灰阶)背景画面中设置黑块或白块的测试画面，其中黑块表示电压下跳，白块表示电压上跳。
图2示意性示出本公开示例性实施例中像素驱动电路的示意图一。
如图2所示，本公开实施例中提供的像素驱动电路可以包括第一开关元件T1、第二开关元件T2、第三开关元件T3(作为驱动晶体管DTFT)、第四开关元件T4、第五开关元件T5、第六开关元件T6、第七开关元件T7、第八开关元件T8和第九开关元件T9，还可以包括存储电容C和有机发光二极管OLED。
图2实施例中，第一开关元件T1的控制端可以耦接扫描信号线Gate，第一开关元件 T1的第一端可以耦接数据信号线Data，第一开关元件T1的第二端可以耦接第一节点N1。第二开关元件T2的控制端可以耦接扫描信号线Gate，第二开关元件T2的第一端可以耦接第二节点N2，第二开关元件T2的第二端可以耦接第三节点N3。驱动晶体管DTFT的控制端(例如栅极)可以耦接第二节点N2，驱动晶体管DTFT的第一端(例如源极)可以耦接第一电源信号线VDD，驱动晶体管DTFT的第二端(例如漏极)可以耦接第三节点N3。第四开关元件T4的控制端可以耦接复位信号线Reset，第四开关元件T4的第一端可以耦接第二节点N2，第四开关元件T4的第二端可以耦接初始化信号线Vinit。第五开关元件T5的控制端可以耦接复位信号线Reset，第五开关元件T5的第一端可以耦接第一节点N1，第五开关元件T5的第二端可以耦接初始化信号线Vinit。第六开关元件T6的控制端可以耦接发光控制信号线EM，第六开关元件T6的第一端可以耦接第一节点N1，第六开关元件T6的第二端可以耦接初始化信号线Vinit。第七开关元件T7的控制端可以耦接发光控制信号线EM，第七开关元件T7的第一端可以耦接第三节点N3，第七开关元件T7的第二端可以耦接所述有机发光二极管OLED的第一端。第八开关元件T8的控制端可以耦接复位信号线Reset，第八开关元件T8的第一端可以耦接第七开关元件T7的第二端，第八开关元件T8的第二端可以耦接初始化信号线Vinit。第九开关元件T9的控制端可以耦接发光控制信号线EM，第九开关元件T9的第一端可以耦接第二节点N2，第九开关元件T9的第二端悬空，这里第九开关元件T9等效于一个电容。存储电容C的第一极板可以耦接第一节点N1，存储电容C的第二极板可以耦接第二节点N2。有机发光二极管OLED的第二端可以耦接第三电源信号线VSS。
图3示意性示出本公开示例性实施例中像素驱动电路的示意图二。
如图3所示，本公开实施例中提供的像素驱动电路可以包括第一开关元件T1、第二开关元件T2、第三开关元件T3(作为驱动晶体管DTFT)、第四开关元件T4、第五开关元件T5、第六开关元件T6、第七开关元件T7和第八开关元件T8，还可以包括存储电容C和有机发光二极管OLED。
在图3所示实施例中，第一开关元件T1的控制端可以耦接扫描信号线Gate，第一开关元件T1的第一端可以耦接数据信号线Data，第一开关元件T1的第二端可以耦接第一节点N1。第二开关元件T2的控制端可以耦接扫描信号线Gate，第二开关元件T2的第一端可以耦接第二节点N2，第二开关元件T2的第二端可以耦接第三节点N3。驱动晶体管DTFT的控制端(例如栅极)可以耦接第二节点N2，驱动晶体管DTFT的第一端(例如源极)可以耦接第一电源信号线VDD，驱动晶体管DTFT的第二端(例如漏极)可以耦接第三节点N3。第四开关元件T4的控制端可以耦接复位信号线Reset，第四开关元件T4的第一端可以耦接第二节点N2，第四开关元件T4的第二端可以耦接初始化信号线Vinit。第五开关元件T5的控制端可以耦接复位信号线Reset，第五开关元件T5的第一端可以耦接第一节点N1，第五开关元件T5的第二端可以耦接参考电压信号线Vref。第六开关元件T6的控制端可以耦接发光控制信号线EM，第六开关元件T6的第一端可以耦接第一节点 N1，第六开关元件T6的第二端可以耦接参考电压信号线Vref。第七开关元件T7的控制端可以耦接发光控制信号线EM，第七开关元件T7的第一端可以耦接第三节点N3，第七开关元件T7的第二端可以耦接所述有机发光二极管OLED的第一端。第八开关元件T8的控制端可以耦接扫描信号线Gate，第八开关元件T8的第一端可以耦接第七开关元件T7的第二端，第八开关元件T8的第二端可以耦接初始化信号线Vinit。存储电容C的第一极板可以耦接第一节点N1，存储电容C的第二极板可以耦接第二节点N2。有机发光二极管OLED的第二端可以耦接第三电源信号线VSS。
图4示意性示出了本示例实施方式中的像素驱动电路的布线结构图。
如图4所示，本公开实施例提供的像素驱动电路可以包括沿第一方向例如横向设置的扫描信号线Gate，沿第二方向例如纵向设置的数据信号线Data，以及电源信号线VDD，该电源信号线VDD至少可以包括与数据信号线Data同向的第一电源信号线VDD1。
在此基础上，所述像素驱动电路还可以包括：第一开关元件T1，第一开关元件T1的控制端耦接扫描信号线Gate、第一开关元件T1的第一端耦接数据信号线Data、第一开关元件T1的第二端耦接第一节点N1；第二开关元件T2，第一开关元件T2的控制端耦接扫描信号线Gate、第一开关元件T2的第一端耦接第二节点N2、第一开关元件T2的第二端耦接第三节点N3；驱动晶体管DTFT，驱动晶体管DTFT的栅极耦接第二节点N2、驱动晶体管DTFT的源极耦接电源信号线VDD、驱动晶体管DTFT的漏极耦接第三节点N3；以及存储电容C，所述第一节点N1耦接至该存储电容C的第一极板10，所述第二节点N2耦接至该存储电容C的第二极板20。
在该像素驱动电路的布线结构中，第一电源信号线VDD1与数据信号线Data均设置在驱动晶体管DTFT的栅极的同侧，数据信号线Data与该驱动晶体管DTFT的栅极之间的第一距离大于第一电源信号线VDD1与该驱动晶体管DTFT的栅极之间的第二距离，即第一电源信号线VDD1靠近该驱动晶体管DTFT的栅极设置，数据信号线Data远离该驱动晶体管DTFT的栅极设置。
本公开示例性实施方式所提供的像素驱动电路，通过调整数据信号线Data的布线位置来增大数据信号线Data与驱动晶体管DTFT的栅极之间的距离，以此减小数据信号线Data与驱动晶体管DTFT的栅极的耦合程度，从而达到减小驱动晶体管DTFT的栅源电压差的效果，这样即可改善显示器的局部亮度不均的问题，从而改善显示器的串扰现象。
本示例实施方式中，第一节点N1可以通过第一导线100耦接至第一极板10，第二节点N2可以通过第二导线200耦接至第二极板20。需要说明的是：图4仅示例性标示了第一极板10和第二极板20的相对位置，在实际设置时可以是第一极板10在上、第二极板20在下，也可以是第一极板10在下、第二极板20在上。
参考图1所示，考虑到相关技术中数据信号线Data除了与驱动晶体管DTFT的栅极的距离较近而导致其与驱动晶体管DTFT的栅极之间的耦合程度较强之外，该数据信号线Data还会通过扫描信号线Gate与第一导线100(第一节点N1)和第二导线200(第二节 点N2)之间产生较大的串联电容，从而进一步增强数据信号线Data与驱动晶体管DTFT的栅极之间的耦合程度。为了解决上述问题，参考图4所示，本示例实施方式可以控制扫描信号线Gate与第一导线100和第二导线200之间均无交叠，以此来避免数据信号线Data通过扫描信号线Gate而与第一导线100(第一节点N1)和第二导线200(第二节点N2)之间产生串联电容，从而达到进一步降低数据信号线Data与驱动晶体管DTFT的栅极之间的耦合程度。其中，扫描信号线Gate与第一导线100和第二导线200之间均无交叠例如可以通过将扫描信号线Gate原本与第一导线100和第二导线200交叠的部分下移，或者也可以通过调整第一开关元件T1的第二端和第二开关元件T2的第一端的位置来实现。
本示例实施方式中，参考图4所示，所述电源信号线VDD除了可以包括与数据信号线Data同向的第一电源信号线VDD1之外，还可以包括与扫描信号线Gate同向的第二电源信号线VDD2，以及自该第二电源信号线VDD2延伸出的与数据信号线Data具有交叠区域的延伸部VDD3，这样即可增大数据信号线Data与电源信号线VDD之间的寄生电容。由于电源信号线VDD与驱动晶体管DTFT的源极相连，因此增大数据信号线Data与电源信号线VDD之间的寄生电容，即可增大数据信号线Data与驱动晶体管DTFT的源极之间的寄生电容，从而达到增大数据信号线Data与驱动晶体管DTFT的源极之间的耦合强度的效果，且数据信号线Data与电源信号线VDD的延伸部VDD3之间的交叠面积越大，数据信号线Data与驱动晶体管DTFT的源极之间耦合强度的增加就越为明显。
在此基础上，考虑到制备工艺的简化，第一电源信号线VDD1与数据信号线Data可以同层设置，第二电源信号线VDD2与延伸部VDD3可以同层设置，而第二电源信号线VDD2与第一电源信号线VDD1可以异层设置且通过过孔相连通。
本示例实施方式中，数据信号线Data与驱动晶体管DTFT的栅极之间的第一距离以及数据信号线Data与电源信号线VDD的延伸部VDD3之间的交叠面积例如均可根据预先获取的在测试条件下驱动晶体管DTFT的栅极与源极的电压跳变值进行确定。其中，所述测试条件已在上文中进行了详细的描述，这里不再赘述。
基于上述的布线结构可知，本示例实施方式一方面可以通过调整数据信号线Data的布线位置来减小数据信号线Data与驱动晶体管DTFT的栅极之间的耦合程度，另一方面可以通过控制扫描信号线Gate与第一节点N1和第二节点N2之间均无交叠来进一步降低数据信号线Data与驱动晶体管DTFT的栅极之间的耦合程度，再一方面还可以通过设置与数据信号线Data具有交叠区域的电源信号线VDD的延伸部VDD3来增强数据信号线Data与驱动晶体管DTFT的源极之间的耦合程度。本实施例通过上述的布线结构即可保证驱动晶体管DTFT的栅源电压差Vgs的稳定性，从而改善例如在串扰测试画面下的显示器局部亮度不均的问题，以此解决显示器的串扰问题。
本示例实施方式中，第一开关元件T1和第二开关元件T2均可以为MOS(Metal-Oxide-Semiconductor，金属-氧化物-半导体)晶体管，例如P型MOS晶体管或者N型MOS晶体管。需要说明的是：所述像素驱动电路的布线结构中还可以包括例如图2 或图3中的其它晶体管和信号线。以图2为例，该像素驱动电路中还可以包括复位信号线Reset、发光控制信号线EM、初始化信号线Vinit、第三电源信号线VSS、以及第四至第九开关元件(T4～T9)。或者以图3为例，该像素驱动电路中还可以包括复位信号线Reset、发光控制信号线EM、初始化信号线Vinit、第三电源信号线VSS、以及第四至第八开关元件(T4～T8)。基于此，在像素驱动电路的实际布线结构中，根据图2或图3所示的耦接关系可以对各个开关元件进行布局设计，这里对此不一一列举说明。
本示例实施方式还提供了一种显示面板，包括上述的像素驱动电路。该显示面板在进行串扰测试时能够表现出较佳的亮度稳定性，因此具有良好的显示品质。
本示例实施方式还提供了一种显示装置，包括上述的显示面板。其中，该显示装置例如可以包括手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。

Claims (11)

  1. 一种像素驱动电路的布线结构，所述像素驱动电路包括：
    第一开关元件，所述第一开关元件的控制端耦接扫描信号线，所述第一开关元件的第一端耦接数据信号线，所述第一开关元件的第二端耦接第一节点；
    驱动晶体管，所述驱动晶体管的控制端耦接第二节点，所述驱动晶体管的第一端耦接电源信号线，所述驱动晶体管的第二端耦接第三节点；
    其中，所述电源信号线包括与所述数据信号线同向的第一电源信号线，所述数据信号线与所述驱动晶体管的控制端之间的第一距离大于所述第一电源信号线与所述驱动晶体管的控制端之间的第二距离。
  2. 根据权利要求1所述的像素驱动电路的布线结构，其中，所述第一电源信号线与所述数据信号线位于所述驱动晶体管的控制端的同侧。
  3. 根据权利要求2所述的像素驱动电路的布线结构，其中，所述像素驱动电路还包括：
    存储电容，所述第一节点通过第一导线耦接至所述存储电容的第一极板，所述第二节点通过第二导线耦接至所述存储电容的第二极板；
    其中，所述扫描信号线与所述第一导线和/或所述第二导线之间无交叠。
  4. 根据权利要求1所述的像素驱动电路的布线结构，其中，所述电源信号线还包括与所述扫描信号线同向的第二电源信号线，以及自所述第二电源信号线延伸出的与所述数据信号线具有交叠区域的延伸部。
  5. 根据权利要求4所述的像素驱动电路的布线结构，其中，所述第二电源信号线与所述延伸部同层设置，所述第一电源信号线与所述数据信号线同层设置，所述第二电源信号线与所述第一电源信号线异层设置且通过过孔相连通。
  6. 根据权利要求4所述的像素驱动电路的布线结构，其中，所述数据信号线与所述延伸部之间的交叠面积根据所述驱动晶体管的控制端与第一端的电压跳变值确定。
  7. 根据权利要求1所述的像素驱动电路的布线结构，其中，所述数据信号线与所述驱动晶体管的控制端之间的第一距离根据所述驱动晶体管的控制端与第一端的电压跳变值确定。
  8. 根据权利要求1所述的像素驱动电路的布线结构，其中，所述像素驱动电路还包括：
    第二开关元件，所述第二开关元件的控制端耦接所述扫描信号线，所述第二开关元件的第一端耦接所述第二节点，所述第二开关元件的第二端耦接所述第三节点。
  9. 根据权利要求8所述的像素驱动电路的布线结构，其中，所述第一开关元件和所述第二开关元件均为MOS晶体管。
  10. 一种显示面板，包括权利要求1-9任一项所述的像素驱动电路的布线结构。
  11. 一种显示装置，包括权利要求10所述的显示面板。
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