WO2019184444A1 - 一种主从配置沟通协议、提高兼容性的方法以及电子设备 - Google Patents

一种主从配置沟通协议、提高兼容性的方法以及电子设备 Download PDF

Info

Publication number
WO2019184444A1
WO2019184444A1 PCT/CN2018/120263 CN2018120263W WO2019184444A1 WO 2019184444 A1 WO2019184444 A1 WO 2019184444A1 CN 2018120263 W CN2018120263 W CN 2018120263W WO 2019184444 A1 WO2019184444 A1 WO 2019184444A1
Authority
WO
WIPO (PCT)
Prior art keywords
configuration
master
slave
slave configuration
communication protocol
Prior art date
Application number
PCT/CN2018/120263
Other languages
English (en)
French (fr)
Inventor
邓俊
Original Assignee
无锡睿勤科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡睿勤科技有限公司 filed Critical 无锡睿勤科技有限公司
Priority to US17/042,896 priority Critical patent/US11175928B2/en
Priority to DE112018007129.4T priority patent/DE112018007129T5/de
Publication of WO2019184444A1 publication Critical patent/WO2019184444A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

Definitions

  • the present invention relates to the field of electronic communication technologies, and in particular, to a master-slave configuration communication protocol, a method for improving compatibility, and an electronic device.
  • Configuration refers to the hardware of the components of an electronic product.
  • the configuration of the computer mainly includes external devices such as CPU, motherboard, memory, hard disk, graphics card, sound card, network card, chassis, power supply, heat sink, display, optical drive, keyboard, mouse, audio, etc.
  • external devices such as CPU, motherboard, memory, hard disk, graphics card, sound card, network card, chassis, power supply, heat sink, display, optical drive, keyboard, mouse, audio, etc.
  • the higher the relevant configuration the representative The overall performance of the computer is stronger.
  • a corresponding communication protocol is required.
  • Patent CN106598887 describes a method for adapting different hardware according to pin information of GPIO (General Purpose Input Output, GPIO for short). Although this technical solution can distinguish each hardware configuration, it will cause serious GPIO resources. waste. For example, if there are three ABC vendors in the memory and five ABCDE vendors on the hard disk, according to the communication protocol provided by the patent, the memory and the hard disk cannot share the GPIO pins, and at least two GPIO pins must be used for the memory, and the hard disk must use at least 3 For GPIO pins, for some processors with fewer GPIO pins, there may be a serious shortage of GPIO pins.
  • GPIO General Purpose Input Output
  • Another object of the present invention is to provide a method for improving compatibility that allows the main configuration to be compatible with a plurality of slave configurations requiring different initialization codes.
  • a master-slave configuration communication protocol including:
  • the master configuration sends an analog address to the slave configuration via the GPIO pin;
  • the slave configuration receives, by the configuration, the analog address, and comparing the analog address with the self-configured address: if the analog address matches the self address, the slave configuration sends its own parameter information To the main configuration.
  • the method further includes:
  • the main configuration takes the signal line from the initial high level low (R+Y) clock cycles as a pre-transmit flag
  • the main configuration takes the signal line from the initial low level rise (R+Y) clock cycles as a pre-transmit flag
  • the value of the R is related to the number N of the types of the configuration (3), and the relationship is as follows:
  • L(log 2 N) represents a minimum integer greater than or equal to log 2 N
  • Y is related to the maximum value X of various manufacturers from the configuration, and the relationship is as follows:
  • L(log 2 X) represents the smallest integer greater than or equal to log 2 X.
  • the data bits of the analog address are (R-1) bits.
  • the method before the sending, by the configuration, the parameter information of the configuration to the master configuration, the method further includes:
  • the slave configuration sends 0 or 1 of R bits to the master configuration as a pre-feedback flag.
  • the main configuration before the signal line is pulled from the initial high level (R+Y) clock cycles as a pre-transmission flag further comprising: the main configuration setting the GPIO pin to an output state and Output high level;
  • the method further includes: the main configuration sets the GPIO pin to an output state and outputs a low power level.
  • the parameter information is a vendor number.
  • the data bit of the vendor number is V bits
  • each set of the initialization codes corresponding to a slave configuration of at least one vendor
  • a corresponding initialization code is called in the software according to the parameter information.
  • an electronic device comprising:
  • Main configuration the main configuration has at least one GPIO pin
  • At least one slave configuration the slave configurations being electrically connected to the same GPIO pin;
  • the master configuration invokes an initialization code corresponding to the slave configuration by the above-described method of improving compatibility.
  • the master-slave configuration communication protocol, the method for improving compatibility, and the electronic device provided by the embodiments of the present invention can enable the master configuration to obtain one or more slave configurations connected thereto through a GPIO pin.
  • Parameter information No matter how many slave configurations, how many vendors can be identified by the same GPIO pin, which enables compatibility with multiple hardware configurations using the same version of the software, which not only greatly saves GPIO pin resources, but also reduces Control costs and control risks for software versions.
  • FIG. 1 is a schematic diagram of a connection between a primary configuration and a secondary configuration according to Embodiment 1 of the present invention
  • FIG. 2 is a flowchart of a main configuration according to Embodiment 1 of the present invention.
  • FIG. 3 is a flowchart of a slave configuration according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic diagram of data before a primary configuration receives a pre-feedback flag according to Embodiment 4 of the present invention
  • FIG. 5 is a schematic diagram of data after receiving a pre-transmission flag from a configuration according to Embodiment 4 of the present invention.
  • this embodiment provides a master-slave configuration communication protocol, which includes the following steps:
  • the main configuration 1 is a processor having at least one GPIO pin 2, and the number of the slave configuration 3 is three, which are respectively a memory, a hard disk, and a graphics card.
  • the memory may be provided by the A vendor or the B vendor; the hard disk may be provided by the C vendor, the D vendor, or the E vendor; the graphics card may be provided by the F vendor or the G vendor.
  • the memory, the hard disk, the graphics card, and the like are connected from the configuration 3 to a GPIO pin 2 of the processor through a wire or the like.
  • the processor may be a conventional single chip microcomputer, an ARM (Advanced RISC Machines, ARM for short) processor, a DSP (Digital Signal Processing, abbreviated as DSP) processor, or an Intel CPU.
  • S20 Main configuration 1 sets GPIO pin 2 to the output state and outputs a high level.
  • the signal line initialization is raised, and the processor sets the GPIO pin 2 used for communication to the output state and causes the GPIO pin 2 to output a high level.
  • the main configuration 1 takes the signal line from the initial high level low (R+Y) clock cycles as a pre-transmit flag, and preferably, R and Y are both positive integers.
  • the processor lowers the high level signal by (R+Y) clock cycles, and the memory or the like receives the change information of the level signal from the configuration 3, enters the ready state, and prepares to receive the analog address.
  • the main configuration 1 pulls the signal line from the initial high level low (R+Y) clock cycles, which can be expressed as the binary value of the processor transmitting (R+Y) bits from the GPIO pin 2 to the configuration 3 0.
  • R may be a positive integer related to the number N of types from the configuration 3. Further, the relationship between R and N may be defined as follows:
  • the value of Y is related to the maximum value X of various manufacturers from the configuration, and the relationship is as follows:
  • L(log 2 X) represents the smallest integer greater than or equal to log 2 X.
  • Master configuration 1 sends an analog address to configuration 3 via GPIO pin 2.
  • the processor sends an analog address to the memory, hard disk, and graphics card.
  • the analog address can be pre-entered into the processor.
  • the programmer knows from the past experience that the processor is generally connected to the memory, the hard disk, and the graphics card according to the need, so the analog address of the memory, the hard disk, and the graphics card has been implanted in the processor in advance.
  • the programmer knows from the past experience that the processor of the mobile phone generally needs to be connected with the flash memory, the screen and the camera, so the analog address of the flash memory, the screen and the camera can be implanted in the processor in advance.
  • the data bits of the analog address can also be related to the number of species from the configuration 3, which is (R-1) bits.
  • S50 Receive the analog address from configuration 3 and compare the analog address with the address from configuration 3 itself:
  • the analog address matches its own address, send 0 (or 1) of the R bits from the configuration 3 to the main configuration 1 as a pre-feedback flag, and then send parameter information such as its own vendor number from the configuration 3 to the main configuration 1; If not, the analog address information sent from the main configuration 1 is ignored.
  • the memory compares with the address after receiving the analog address, and if it matches, the memory changes the input/output state of the GPIO pin 2, and the signal line is Raise and send the R bit 0 to the processor as the start flag.
  • the processor sends the analog address of the hard disk, the memory compares with the original address after receiving the analog address.
  • the memory ignores the analog address, and then the hard disk receives the analog address, and the hard disk receives the analog address and compares with the address. If they match, the hard disk changes the input/output status of GPIO pin 2. First, it sends the R bit 0 (or 1) to the processor as the start flag, and then sends the C vendor, D vendor or E to the processor. The manufacturer's manufacturer number, so the processor knows the information about the hard disk so that subsequent initialization code can be called. And so on, the address matching process of the graphics card is similar to the above process, and will not be described again. In this embodiment, the information returned from the configuration 3 may be a vendor number, or may be other information used to distinguish the slave configuration 3.
  • the data bit of the vendor number can be V bits, and the value of V is related to the number of vendors S of the configuration 3, and the relationship is as follows:
  • L(log 2 S) represents the smallest integer greater than or equal to log 2 S.
  • the processor as the main configuration 1 can analyze the received V bits of data, and can identify the vendors of the respective slave configurations 2.
  • the main configuration 1 After receiving the parameter information such as the manufacturer number, the main configuration 1 sets the GPIO pin 2 to the output state. From the configuration 3, the GPIO pin is set to the input state, and the S20 to S50 are repeatedly executed until all the configured manufacturers are detected. Until the parameter information such as the number.
  • the master configuration 1 can obtain one or more parameter information of the slave configuration 3 connected thereto through only one GPIO pin 2, and thus can be used for various types. Differentiating from configuration 3 greatly saves GPIO pin 2 resources.
  • This embodiment also provides a master-slave configuration communication protocol, and the steps are as follows:
  • S10 Electrically connect one GPIO pin of the master configuration with at least one slave configuration.
  • S20 The main configuration sets the GPIO pin to the output state and outputs a low level.
  • the signal line initialization is pulled low, and the processor sets the GPIO pin used for communication to the output state and causes the GPIO pin to output a low level.
  • S30 The main configuration takes the signal line from the initial low level rise (R+Y) clock cycles as a pre-transmit flag.
  • the processor raises the low-level signal (R+Y) clock cycles
  • the memory receives the change information of the level signal from the configuration, enters the ready state, and prepares to receive the analog address.
  • the master configuration raises the signal line from the initial low level (R+Y) clock cycles as a binary value of 1 (R+Y) bits transmitted by the processor to the slave configuration via the GPIO pin.
  • R and Y are the same as those in the first embodiment.
  • the master configuration sends an analog address to the slave configuration via the GPIO pin.
  • the data bits of the analog address can also be related to the number of configurations from the number of (R-1) bits.
  • S50 Receive the analog address from the configuration and compare the analog address with the configured own address:
  • the signal line is pulled high (or pulled low), then 0 (or 1) of R bits are sent from the configuration to the master configuration as a pre-feedback flag, and then the manufacturer number of itself is configured from the configuration.
  • the parameter information is sent to the main configuration; if not, the analog address information sent from the main configuration is ignored.
  • the main configuration After receiving the parameter information such as the manufacturer number, the main configuration sets the GPIO pin to the output state. From the configuration, the GPIO pin is set to the input state, and S20 to S50 are repeatedly executed until all the configured manufacturer numbers and other parameters are detected. Information so far.
  • the master configuration can obtain one or more parameter information of the slave configuration by using only one GPIO pin, thereby distinguishing various slave configurations. , greatly saving GPIO pin resources.
  • the embodiment Based on the master-slave configuration communication protocol provided in the first embodiment, the embodiment provides a method for improving compatibility, including:
  • A1 Preset multiple sets of initialization code in the software. Each set of initialization code corresponds to a slave configuration of at least one vendor.
  • the initialization code required by the memory of the A vendor, the B vendor, and other common memory vendors can be integrated into the software in advance, and the hard disks of the common hard disk manufacturers such as the C vendor, the D vendor, and the E vendor are required.
  • the initialization code is also integrated into the software, and the initialization code required by the graphics cards of many common graphics card manufacturers such as F manufacturers and G vendors, as well as the initialization codes of other common manufacturers from the configuration are integrated into the software, so that the software become a code base that contains a variety of initialization code from multiple vendors of configuration.
  • the software in this embodiment includes at least an initialization code of the A vendor, the B vendor, the C vendor, the D vendor, the E vendor, the F vendor, and the G vendor, and may also include initialization codes of other vendors.
  • A2 Through the communication protocol provided in Embodiment 1, the master configuration acquires key parameter information such as each vendor number of the configuration.
  • the processor obtains the manufacturer number of the A manufacturer of the memory or the manufacturer number of the B manufacturer, and also obtains the manufacturer number of the C manufacturer of the hard disk, the manufacturer number of the D manufacturer, or the manufacturer number of the E manufacturer, and also obtains the F of the graphics card. Manufacturer number or G manufacturer number.
  • A3 The corresponding initialization code is called from the software according to the parameter information obtained by S20.
  • the corresponding A vendor, B vendor, C vendor, D vendor, and E are invoked in the software.
  • Initialization code of the manufacturer, F manufacturer, or G vendor is invoked in the software.
  • the embodiment provides an electronic device, where the electronic device includes:
  • Main configuration the main configuration has at least one GPIO pin
  • the slave configuration is electrically connected to the same GPIO pin, and the master configuration obtains information such as the vendor number of the configuration through the communication protocol of the first embodiment;
  • the master configuration invokes the initialization code corresponding to the slave configuration by the method provided in the second embodiment, thereby making the master configuration compatible with the slave configuration.
  • the memory and the hard disk receive the pre-send flag b'00000, they wait for the address to be transmitted.
  • the master configuration After transmitting the vendor number data from the configuration, set the GPIO pin to the input state (ie, the initial state). After receiving the pre-feedback flag b'00, the master configuration starts processing the next received data b'01, that is, the module that uses the manufacturer B is identified by the memory, and then the GPIO pin is set to the output state, and the signal is pulled high. Line, return to the initial state.
  • b'1 is sent at the start address. If the hardware circuit is connected to the manufacturer D, it receives b'0. If the hardware circuit is connected to the manufacturer E, it receives b'1, and then calls the corresponding initialization code.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Information Transfer Systems (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

本发明涉及电子通讯技术领域，具体公开了一种主从配置沟通协议、提高兼容性的方法以及电子设备，所述主从配置沟通协议包括：使主配置的一个GPIO引脚与至少一种从配置电连接；主配置通过所述GPIO引脚向所述从配置发送模拟地址；所述从配置接收所述模拟地址，并将所述模拟地址与所述从配置的本身地址比较：若所述模拟地址与所述本身地址相匹配，则所述从配置将自身的参数信息发送至所述主配置。本发明实施例提供的主从配置沟通协议，可以使主配置通过一个GPIO引脚就获取与之相连的一种或多种从配置的参数信息，进而使主配置与从配置实现兼容，大大的节约了GPIO引脚资源。本发明还提供了一种提高兼容性的方法及电子设备。

Description

一种主从配置沟通协议、提高兼容性的方法以及电子设备
本申请要求于2018年03月30日提交中国专利局、申请号为201810291971.4、发明名称为“主从配置沟通协议、提高兼容性的方法以及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电子通讯技术领域，尤其涉及一种主从配置沟通协议、提高兼容性的方法以及电子设备。
背景技术
配置，是指电子产品的组成硬件。例如，电脑的配置主要有CPU、主板、内存、硬盘、显卡、声卡、网卡、机箱、电源、散热器、显示器、光驱、键盘、鼠标、音响等外部设备，相关的配置越高，则代表此电脑的综合性能越强悍。不同的配置之间要实现信息交换，就需要有相应的沟通协议。
专利CN106598887描述了一种根据GPIO(通用输入/输出，General Purpose Input Output，简称为GPIO)引脚信息兼容不同硬件的方法，该技术方案虽然可以区分各个硬件配置，但是却会造成严重的GPIO资源浪费。例如，如果内存有ABC三个厂商，硬盘有ABCDE五个厂商，按照该专利提供的沟通协议，内存和硬盘无法共用GPIO引脚，且内存至少要用2个GPIO引脚，硬盘至少要用3个GPIO引脚，对于一些GPIO引脚较少的处理器而言，可能会出现GPIO引脚的数量严重不足的情况。
发明内容
本发明的一个目的在于：提供一种主从配置沟通协议，可以使主配置通过一个GPIO引脚就获取到与之相连的一种或多种从配置的参数信息。
本发明的另一个目的在于：提供一种提高兼容性的方法，可以使主配置兼容多种需要不同的初始化代码的从配置。
本发明的又一个目的在于提供一种电子设备，其主配置可以兼容多种需 要不同的初始化代码的从配置。
为达此目的，本发明采用以下技术方案：
一方面，提供一种主从配置沟通协议，包括：
使主配置的一个GPIO引脚与至少一种从配置电连接；
主配置通过所述GPIO引脚向所述从配置发送模拟地址；
所述从配置接收所述模拟地址，并将所述模拟地址与所述从配置的本身地址比较：若所述模拟地址与所述本身地址相匹配，则所述从配置将自身的参数信息发送至所述主配置。
优选地，在所述主配置通过所述GPIO引脚向所述从配置发送模拟地址之前，还包括：
主配置把信号线从初始的高电平拉低(R+Y)个时钟周期作为预发送标志；
或者，
主配置把信号线从初始的低电平升高(R+Y)个时钟周期作为预发送标志；
其中，R和Y均为正整数。
优选地，所述R的数值与所述从配置(3)的种类数N相关，关系如下：
R＝L(log 2N)+1；
其中，L(log 2N)表示大于或等于log 2N的最小整数；
所述Y的数值与各种从配置的厂商个数的最大值X相关，关系如下：
Y＝L(log 2X)+1；
其中，L(log 2X)表示大于或等于log 2X的最小整数。
优选地，所述模拟地址的数据位为(R-1)个bit。
优选地，所述从配置将自身的参数信息发送至所述主配置之前，还包括：
所述从配置向所述主配置发送R个bit的0或1作为预反馈标志。
优选地，所述主配置把信号线从初始的高电平拉低(R+Y)个时钟周期作为预发送标志之前，还包括：所述主配置将所述GPIO引脚设置成输出态并输出高电平；
所述主配置把信号线从初始的低电平升高(R+Y)个时钟周期作为预发送标志之前，还包括：所述主配置将所述GPIO引脚设置成输出态并输出低电平。
优选地，所述参数信息为厂商编号。
优选地，所述厂商编号的数据位为V个bit，所述V的值与该种从配置的厂商数量S相关，关系如下：V＝L(log 2S)；其中，L(log 2S)表示大于或等于log 2S的最小整数。
另一方面，提供一种提高兼容性的方法，包括：
在软件中预设多套初始化代码，每套所述初始化代码对应至少一个厂商的一种从配置；
通过权利要求上述任一种主从配置沟通协议获取每一种从配置的参数信息；
根据所述参数信息在所述软件中调用相应的初始化代码。
又一方面，提供一种电子设备，包括：
主配置，所述主配置至少具备一个GPIO引脚；
至少一种从配置，所述从配置均与同一个所述GPIO引脚电连接；
所述主配置通过上述的提高兼容性的方法调用与所述从配置相应的初始化代码。
本发明的有益效果：本发明实施例提供的主从配置沟通协议、提高兼容性的方法以及电子设备，可以使主配置通过一个GPIO引脚就获取到与之相 连的一种或多种从配置的参数信息。不管多少个从配置，每个从配置有多少个厂商，均可通过同一个GPIO引脚进行识别，进而实现使用同一版软件兼容多种硬件配置，不仅大大节约了GPIO引脚资源，还可以降低对软件版本的管控成本和管控风险。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本发明实施例一提供的主配置与从配置的连接示意图；
图2为本发明实施例一提供的主配置的流程图；
图3为本发明实施例一提供的从配置的流程图；
图4为本发明实施例四提供的主配置接收预反馈标志前的数据示意图；
图5为本发明实施例四提供的从配置接收预发送标志后的数据示意图。
图中：
1、主配置；
2、GPIO引脚；
3、从配置。
具体实施方式
为使得本发明的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，下面所描述的实施例仅仅是本发明一部分实施例，而非全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
下面结合附图并通过具体实施方式来进一步说明本发明的技术方案。
本发明的描述中，需要说明的是，术语“前”、“后”、“左”、“右”、“顶”、 “底”等指示的方位或位置关系为基于图1所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
实施例一
如图1～图3所示，本实施例提供一种主从配置沟通协议，包括以下步骤：
S10：使主配置1的一个GPIO引脚2与至少一种从配置3电连接。
具体地，于本实施例中，主配置1为具备至少一个GPIO引脚2的处理器，从配置3的数量为三种，分别为内存、硬盘和显卡。其中，内存可能由A厂商或者B厂商提供；硬盘可能由C厂商、D厂商或者E厂商提供；显卡可能由F厂商或者G厂商提供。如图1所示，内存、硬盘和显卡等从配置3均通过导线等与处理器的一个GPIO引脚2连接。于本实施例中，处理器可以为普通单片机、ARM(Advanced RISC Machines，简称ARM)处理器、DSP(数字信号处理，Digital Signal Processing，缩写为DSP)处理器或者Intel CPU等处理器。
S20：主配置1将GPIO引脚2设置成输出态并输出高电平。
具体地，初始状态，信号线初始化会被升高，处理器将用来通讯的GPIO引脚2设置成输出态并使该GPIO引脚2输出高电平。
S30：主配置1把信号线从初始的高电平拉低(R+Y)个时钟周期作为预发送标志，优选地，R和Y均为正整数。
具体地，检测开始，处理器将高电平信号降低(R+Y)个时钟周期，内存等从配置3接收到电平信号的变化信息，进入准备状态，做好接收模拟地址的准备。优选地，主配置1把信号线从初始的高电平拉低(R+Y)个时钟周期可以表现为处理器通过GPIO引脚2向从配置3发送(R+Y)个bit的二进制数值0。
于本实施例中，为了避免误响应，可以使R为与从配置3的种类数N相关的正整数，进一步地，可以限定R与N的关系如下：
R＝L(log 2N)+1
其中，L(log 2N)表示大于或等于log 2N的最小整数，比如L(2)＝2,L(2.1)＝3。
于本实施例中，从配置3为内存、硬盘和显卡，所以N为3，R＝L(log 23)+1＝3。
于本实施例中，Y的数值与各种从配置的厂商个数的最大值X相关，关系如下：
Y＝L(log 2X)+1；
其中：
X为各种从配置2中厂商个数的最大值，假如有内存有2个厂商，硬盘有3个厂商，显卡有2个厂商，则X＝3；
L(log 2X)表示大于或等于log 2X的最小整数。
S40：主配置1通过GPIO引脚2向从配置3发送模拟地址。
具体地，处理器向内存、硬盘和显卡发送模拟地址。模拟地址可以预先输入到处理器中。例如，针对本实施例中的电子产品，程序员根据过往经验知道该处理器一般据需要与内存、硬盘和显卡连接，所以已经提前在处理器中植入了内存、硬盘和显卡的模拟地址。又如，如果针对手机，程序员根据过往经验知道手机的处理器一般需要与闪存、屏幕和摄像头连接，所以可以提前在处理器中植入闪存、屏幕和摄像头的模拟地址。
优选地，可以使模拟地址的数据位也与从配置3的种数相关，为(R-1)个bit。
S50：从配置3接收模拟地址，并将模拟地址与从配置3的本身地址比较：
若模拟地址与本身地址相匹配，则从配置3向主配置1发送R个bit的0(或1)作为预反馈标志，然后从配置3将自身的厂商编号等参数信息发送至主配置1；若否，则忽略从主配置1发来的模拟地址信息。
具体地，于本实施例中，如果处理器发送内存的模拟地址，内存接收到该模拟地址后与本身地址比较，若相匹配，则内存改变GPIO引脚2的输入/输出状态，把信号线升高并向处理器发送R个bit的0作为开始的标志，当然，也可以选择把信号线拉低并向处理器发送R个bit的1作为开始的标志，然后再向处理器发送A厂商或B厂商的厂商编号，于是，处理器就知道内存的相关信息，以便于后续调用相关的初始化代码。如果处理器发送硬盘的模拟地址，内存接收到该模拟地址后与本身地址比较，若不匹配，内存忽略该模拟地址，然后由硬盘接收该模拟地址，硬盘接收到该模拟地址后与本身地址比较，若相匹配，则硬盘改变GPIO引脚2的输入/输出状态，先向处理器发送R个bit的0(或1)作为开始的标志，然后再向处理器发送C厂商、D厂商或E厂商的厂商编号，于是，处理器就知道硬盘的相关信息，以便于后续调用相关的初始化代码。如此类推，显卡的地址匹配过程与上述过程相似，不再赘述。于本实施例中，从配置3返回的信息可以为厂商编号，也可以为其它用于区分从配置3的信息。
优选地，可以使厂商编号的数据位为V个bit，V的值与该种从配置3的厂商数量S相关，关系如下：
V＝L(log 2S)
同样的，L(log 2S)表示大于或等于log 2S的最小整数。
具体地，内存可能由A厂商或者B厂商提供，则内存的S＝2；硬盘可能由C厂商、D厂商或者E厂商提供,则内存的S＝3；显卡由F厂商或者G厂商提供，则显卡的S＝2。
进一步地，作为主配置1的处理器对接收到的V个bit的数据进行解析，便可以识别出各从配置2的厂商。
S60：主配置1接收厂商编号等参数信息后，将GPIO引脚2设置为输出态，从配置3则将GPIO引脚设置为输入态，重复执行S20～S50，直至检测完所有从配置的厂商编号等参数信息为止。
具体地，通过本实施例提供的主从配置3沟通协议，主配置1仅通过一 个GPIO引脚2就可以获取与之相连的一种或多种从配置3的参数信息，进而可以对各种从配置3进行区分，大大的节省了GPIO引脚2资源。
实施例二
本实施例也提供一种主从配置沟通协议，其步骤如下：
S10：使主配置的一个GPIO引脚与至少一种从配置电连接。
S20：主配置将GPIO引脚设置成输出态并输出低电平。
具体地，初始状态，信号线初始化会被拉低，处理器将用来通讯的GPIO引脚设置成输出态并使该GPIO引脚输出低电平。
S30：主配置把信号线从初始的低电平升高(R+Y)个时钟周期作为预发送标志。
具体地，检测开始，处理器将低电平信号升高(R+Y)个时钟周期，内存等从配置接收到电平信号的变化信息，进入准备状态，做好接收模拟地址的准备。优选地，主配置把信号线从初始的低电平升高(R+Y)个时钟周期可以表现为处理器通过GPIO引脚向从配置发送(R+Y)个bit的二进制数值1。于本实施例中，R与Y的定义与实施例一相同。
S40：主配置通过GPIO引脚向从配置发送模拟地址。
优选地，可以使模拟地址的数据位也与从配置的种数相关，为(R-1)个bit。
S50：从配置接收模拟地址，并将模拟地址与从配置的本身地址比较：
若模拟地址与本身地址相匹配，则把信号线拉高(或拉低)，接着从配置向主配置发送R个bit的0(或1)作为预反馈标志，然后从配置将自身的厂商编号等参数信息发送至主配置；若否，则忽略从主配置发来的模拟地址信息。
S60：主配置接收厂商编号等参数信息后，将GPIO引脚设置为输出态， 从配置则将GPIO引脚设置为输入态，重复执行S20～S50，直至检测到所有从配置的厂商编号等参数信息为止。
具体地，通过本实施例提供的主从配置沟通协议，主配置仅通过一个GPIO引脚就可以获取与之相连的一种或多种从配置的参数信息，进而可以对各种从配置进行区分，大大的节省了GPIO引脚资源。
实施例三
基于实施例一提供的主从配置沟通协议，本实施例提供一种提高兼容性的方法，包括：
A1：在软件中预设多套初始化代码，每套初始化代码对应至少一个厂商的一种从配置。
具体地，可以预先将包括A厂商、B厂商以及其它常见的内存厂商的内存所需要的初始化代码集成到软件中，也将C厂商、D厂商和E厂商等多个常见硬盘厂商的硬盘所需要的初始化代码也集成到该软件中，也将F厂商和G厂商等多个常见显卡厂商的显卡所需要的初始化代码以及其它常见从配置的常见厂家的初始化代码集成到该软件中，使该软件成为一个包含多种从配置的多种厂商的初始化代码的代码库。结合实施例一，本实施例的软件至少包含A厂商、B厂商、C厂商、D厂商、E厂商、F厂商和G厂商的初始化代码，也可以包含其它厂商的初始化代码。
A2：通过实施例一提供的沟通协议，使主配置获取每种从配置的厂商编号等关键的参数信息。
具体地，处理器获取到内存的A厂商的厂商编号或者B厂商的厂商编号，也获取到硬盘的C厂商的厂商编号、D厂商的厂商编号或者E厂商的厂商编号，还获取到显卡的F厂商编号或者G厂商编号。
A3：根据S20获取到的参数信息从软件中调用相应的初始化代码。
具体地，根据获取到的A厂商、B厂商、C厂商、D厂商、E厂商、F 厂商或者G厂商的厂商编号，到软件中调用相应的A厂商、B厂商、C厂商、D厂商、E厂商、F厂商或者G厂商的初始化代码。如此，便实现了通过一个软件使主配置兼容多种从配置，而且只使用了一个GPIO引脚作为通讯引脚，大大节省GPIO引脚资源。
实施例四
基于实施例三提供的提高兼容性的方法，本实施例提供一种电子设备，电子设备包括：
主配置，主配置至少具备一个GPIO引脚；
至少一种从配置，从配置均与同一个GPIO引脚电连接，且主配置通过实施例一的沟通协议获取从配置的厂商编号等信息；
主配置通过实施例二提供的方法调用与从配置相应的初始化代码，进而使主配置与从配置实现兼容。
以下以一个电子设备中有两个从配置(内存和硬盘)为例，内存有三个厂商(A、B、C)，硬盘有两个厂商(D、E)，下面进行内存三个厂商的识别。
(1)主配置把与从配置通讯的GPIO引脚初始化为输出态，并输出高电平；主配置输出R+Y＝L(log 2N)+1+L(log 2X)+1＝L(log 22)+1+L(log 23)+1＝5个时钟周期的低电平，即输出二进制数b'00000；
(2)主配置继续送出(R-1)＝1个bit的模拟地址，本实施例中预先定义内存的模拟地址为b'0，硬盘的模拟地址为b'1。则此步骤主配置送出b'0。
(3)把GPIO引脚设置成输入态。其中，步骤(1)～(3)的数据示意图如图4所示。
(4)内存和硬盘接收到预发送标志b'00000时开始等待地址的传输，当收到地址b'0时，硬盘检测到与自身地址不符，丢弃数据，继续等待预发送标志b'00的到来。内存检测到地址与自身相符，则设置GPIO引脚为输出引脚，并拉高信号线，接着输出预反馈标志，长度为R＝2个bit，即b'00。
(5)内存共有三个厂商A、B、C，则厂商编号的长度V＝L(log 2S)＝L (log 23)＝2，假设厂商编号分别设为b'00、b'01、b'10。本实施例以厂商B为例，假设现在硬件电路上接的是厂商B，则内存这边返回的便是b'01。步骤(4)～(5)的数据示意图如图5所示。
(6)从配置发送完厂商编号数据后，把GPIO引脚设置成输入态(即初始状态)。主配置收到预反馈标志b'00后，开始处理接下来收到的数据b'01，即识别出内存所用的是厂商B的模块，接着把GPIO引脚设置成输出态，并拉高信号线，恢复成初始状态。
(7)然后从包含多种初始化代码的软件中调用厂商B的初始化代码。同理，当硬件电路上接的是厂商A和C，以同样的方法识别并执行厂商A和C的初始化代码。
(8)同理，识别硬盘时，则在开始的地址处发送b'1。若硬件电路接的是厂商D则收到b'0,若硬件电路接的是厂商E则收到b'1，接着调用相应的初始化代码。
以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (10)

  1. 一种主从配置沟通协议，其特征在于，包括：
    使主配置(1)的一个GPIO引脚(2)与至少一种从配置(3)电连接；
    主配置(1)通过所述GPIO引脚(2)向所述从配置(3)发送模拟地址；
    所述从配置(3)接收所述模拟地址，并将所述模拟地址与所述从配置(3)的本身地址比较：若所述模拟地址与所述本身地址相匹配，则所述从配置(3)将自身的参数信息发送至所述主配置(1)。
  2. 根据权利要求1所述的主从配置沟通协议，其特征在于，在所述主配置(1)通过所述GPIO引脚(2)向所述从配置(3)发送模拟地址之前，还包括：
    主配置(1)把信号线从初始的高电平拉低(R+Y)个时钟周期作为预发送标志；
    或者，
    主配置(1)把信号线从初始的低电平升高(R+Y)个时钟周期作为预发送标志；
    其中，R和Y均为正整数。
  3. 根据权利要求2所述的主从配置沟通协议，其特征在于，
    所述R的数值与所述从配置(3)的种类数N相关，关系如下：
    R＝L(log 2N)+1；
    其中，L(log 2N)表示大于或等于log 2N的最小整数；
    所述Y的数值与各种从配置的厂商个数的最大值X相关，关系如下：
    Y＝L(log 2X)+1；
    其中，L(log 2X)表示大于或等于log 2X的最小整数。
  4. 根据权利要求2或3所述的主从配置沟通协议，其特征在于，所述模拟地址的数据位为(R-1)个bit。
  5. 根据权利要求2所述的主从配置沟通协议，其特征在于，所述从配置(3)将自身的参数信息发送至所述主配置(1)之前，还包括：
    所述从配置(3)向所述主配置(1)发送R个bit的0或1作为预反馈标志。
  6. 根据权利要求2所述的主从配置沟通协议，其特征在于，
    所述主配置(1)把信号线从初始的高电平拉低(R+Y)个时钟周期作为预发送标志之前，还包括：所述主配置(1)将所述GPIO引脚(2)设置成输出态并输出高电平；
    所述主配置(1)把信号线从初始的低电平升高(R+Y)个时钟周期作为预发送标志之前，还包括：所述主配置(1)将所述GPIO引脚(2)设置成输出态并输出低电平。
  7. 根据权利要求1所述的主从配置沟通协议，其特征在于，所述参数信息为厂商编号。
  8. 根据权利要求7所述的主从配置沟通协议，其特征在于，所述厂商编号的数据位为V个bit，所述V的值与该种从配置(3)的厂商数量S相关，关系如下：
    V＝L(log 2S)；
    其中，L(log 2S)表示大于或等于log 2S的最小整数。
  9. 一种提高兼容性的方法，其特征在于，包括：
    在软件中预设多套初始化代码，每套所述初始化代码对应至少一个厂商的一种从配置(3)；
    通过权利要求1～8任一项所述的主从配置沟通协议获取每一种从配置(3)的参数信息；
    根据所述参数信息在所述软件中调用相应的初始化代码。
  10. 一种电子设备，其特征在于，包括：
    主配置(1)，所述主配置(1)至少具备一个GPIO引脚(2)；
    至少一种从配置(3)，所述从配置(3)均与同一个所述GPIO引脚(2)电连接；
    所述主配置(1)通过权利要求9所述的方法调用与所述从配置(3)相应的初始化代码。
PCT/CN2018/120263 2018-03-30 2018-12-11 一种主从配置沟通协议、提高兼容性的方法以及电子设备 WO2019184444A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US17/042,896 US11175928B2 (en) 2018-03-30 2018-12-11 Master-slave configuration communication protocol, method for improving compatibility, and electronic device
DE112018007129.4T DE112018007129T5 (de) 2018-03-30 2018-12-11 Kommunikationsprotokoll für Master-Slave-Konfiguration, Verfahren zur Erhöhung der Kompatibilität und elektrisches Gerät

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810291971.4A CN108664429B (zh) 2018-03-30 2018-03-30 主从配置沟通协议、提高兼容性的方法以及电子设备
CN201810291971.4 2018-03-30

Publications (1)

Publication Number Publication Date
WO2019184444A1 true WO2019184444A1 (zh) 2019-10-03

Family

ID=63782154

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/120263 WO2019184444A1 (zh) 2018-03-30 2018-12-11 一种主从配置沟通协议、提高兼容性的方法以及电子设备

Country Status (4)

Country Link
US (1) US11175928B2 (zh)
CN (1) CN108664429B (zh)
DE (1) DE112018007129T5 (zh)
WO (1) WO2019184444A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111221583A (zh) * 2020-01-03 2020-06-02 广东岭南通股份有限公司 多智能卡启动管理装置及系统

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108664429B (zh) 2018-03-30 2020-07-24 无锡睿勤科技有限公司 主从配置沟通协议、提高兼容性的方法以及电子设备
JP2022529111A (ja) * 2019-04-15 2022-06-17 コヴィディエン リミテッド パートナーシップ ロボットカートアームのアセンブリ識別のためのシステムおよび方法
CN110750394B (zh) * 2019-09-25 2023-05-30 深圳震有科技股份有限公司 一种基于gpio管脚实现主备单板的控制方法及终端
CN112069103A (zh) * 2020-09-07 2020-12-11 歌尔科技有限公司 一种多模块与主机通信的方法及系统
CN117251403B (zh) * 2023-11-08 2024-05-14 北京紫光芯能科技有限公司 一种spi协议主从设备的通讯模式配置方法及装置
CN117851308A (zh) * 2024-02-18 2024-04-09 荣耀终端有限公司 一种集线电路、集线电路运行方法、pcb和电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104571948A (zh) * 2014-12-11 2015-04-29 乐视致新电子科技（天津）有限公司 一种兼容多种ddr的方法及系统
US20150242201A1 (en) * 2014-02-21 2015-08-27 Samsung Electronics Co., Ltd. Method for updating firmware and electronic device thereof
CN106598887A (zh) * 2016-12-05 2017-04-26 北京小米移动软件有限公司 Ddr内存配置方法、装置以及电子设备
CN108664429A (zh) * 2018-03-30 2018-10-16 无锡睿勤科技有限公司 主从配置沟通协议、提高兼容性的方法以及电子设备

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7779143B2 (en) * 2007-06-28 2010-08-17 Alcatel-Lucent Usa Inc. Scalable methods for detecting significant traffic patterns in a data network
US7912068B2 (en) * 2007-07-20 2011-03-22 Oracle America, Inc. Low-latency scheduling in large switches
US20110016310A1 (en) * 2009-07-20 2011-01-20 Infineon Technologies Ag Secure serial interface with trusted platform module
US20110161468A1 (en) * 2009-12-31 2011-06-30 Schneider Electric USA, Inc. Method and system for cascading peer-to-peer configuration of large systems of ieds
US10311010B2 (en) * 2011-10-05 2019-06-04 Analog Devices, Inc. Two-wire communication systems and applications
WO2017000119A1 (en) * 2015-06-29 2017-01-05 Thomson Licensing Initialization method for use in i2c system and master device
KR102560778B1 (ko) * 2016-02-22 2023-07-27 삼성전자주식회사 데이터를 추출하는 장치 및 방법
US10649945B1 (en) * 2018-12-10 2020-05-12 Analog Devices International Unlimited Company Non-native digital interface support over a two-wire communication bus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150242201A1 (en) * 2014-02-21 2015-08-27 Samsung Electronics Co., Ltd. Method for updating firmware and electronic device thereof
CN104571948A (zh) * 2014-12-11 2015-04-29 乐视致新电子科技（天津）有限公司 一种兼容多种ddr的方法及系统
CN106598887A (zh) * 2016-12-05 2017-04-26 北京小米移动软件有限公司 Ddr内存配置方法、装置以及电子设备
CN108664429A (zh) * 2018-03-30 2018-10-16 无锡睿勤科技有限公司 主从配置沟通协议、提高兼容性的方法以及电子设备

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111221583A (zh) * 2020-01-03 2020-06-02 广东岭南通股份有限公司 多智能卡启动管理装置及系统
CN111221583B (zh) * 2020-01-03 2022-02-25 广东岭南通股份有限公司 多智能卡启动管理装置及系统

Also Published As

Publication number Publication date
US11175928B2 (en) 2021-11-16
CN108664429A (zh) 2018-10-16
DE112018007129T5 (de) 2020-12-10
US20210055939A1 (en) 2021-02-25
CN108664429B (zh) 2020-07-24

Similar Documents

Publication Publication Date Title
WO2019184444A1 (zh) 一种主从配置沟通协议、提高兼容性的方法以及电子设备
US20190302867A1 (en) Method and apparatus for reducing continuous-wakeup delay of bluetooth loudspeaker, and bluetooth loudspeaker
CN105700732A (zh) 用于传输触摸传感器信息的装置、系统和方法
JP4587639B2 (ja) 無線接続を確立するシステムおよび方法
US20210048850A1 (en) Firmware setup menu options for docking stations
WO2023147748A1 (zh) 一种服务器初始化智能网卡的方法、装置、设备及介质
US20200356389A1 (en) Copy and paste in virtual console with keyboard play
CN107506323B (zh) 一种热插拔处理方法及装置
CN112835839A (zh) PCIe接口的设备枚举方法、装置、设备及存储介质
US20070156934A1 (en) High-speed PCI Interface System and A Reset Method Thereof
US10419227B2 (en) Network card
US20020084988A1 (en) Apparatus and method for automatically detecting USB mode and PS/2 mode computer keyboard
CN113204510A (zh) 一种服务器管理架构和服务器
WO2023030275A1 (zh) 监测器件地址管理方法及装置、基板管理控制器、设备
US10521385B2 (en) Inter-device digital audio
CN116599788A (zh) 通信电路、方法、设备以及存储介质
CN116226008A (zh) 端口地址配置器、配置方法及终端
TWI764648B (zh) 主機板、主機板的外接裝置以及主機板的開機方法
CN112003928B (zh) 多功能屏幕同步控制方法、装置及设备
CN111723032B (zh) 一种中断管控方法及电子设备
CN114064545A (zh) 串口功能识别方法、装置、主控芯片、家电设备及介质
CN116483760B (zh) 交互方法、装置、芯片、键盘、电子设备及介质
US10360167B1 (en) Systems and methods for using a bus exchange switch to control processor affinity
CN106354683B (zh) 微控制装置及应用于微控制装置的输入/输出系统
TWI774429B (zh) 處理晶片、插件裝置以及運作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18912167

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 18912167

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 18912167

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 19/03/2021)

122 Ep: pct application non-entry in european phase

Ref document number: 18912167

Country of ref document: EP

Kind code of ref document: A1