WO2019154138A1 - 一种用于逆变器或整流器的电桥电路 - Google Patents

一种用于逆变器或整流器的电桥电路 Download PDF

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Publication number
WO2019154138A1
WO2019154138A1 PCT/CN2019/073278 CN2019073278W WO2019154138A1 WO 2019154138 A1 WO2019154138 A1 WO 2019154138A1 CN 2019073278 W CN2019073278 W CN 2019073278W WO 2019154138 A1 WO2019154138 A1 WO 2019154138A1
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Prior art keywords
switch
field effect
effect transistor
electrically connected
diode
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PCT/CN2019/073278
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English (en)
French (fr)
Inventor
张春涛
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华为技术有限公司
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Priority to EP19751026.6A priority Critical patent/EP3618256A4/en
Publication of WO2019154138A1 publication Critical patent/WO2019154138A1/zh
Priority to US16/711,939 priority patent/US20200119658A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0051—Diode reverse recovery losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0095—Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to the field of power electronics, and in particular, to a bridge circuit.
  • Pulse Width Modulation (PWM) inverters are widely used in power electronics, especially in the fields of uninterruptible power supplies, solar inverters, wind energy converters, motor drives, fuel cells, etc.
  • Phase three-level inverters are the most widely used.
  • a bridge circuit for a single-phase three-level inverter generally uses four field effect transistors as switches, or four bipolar transistors are respectively connected in reverse parallel with a diode as a switch.
  • the disadvantage of using a bipolar transistor in parallel with a diode as a switch is that a spike voltage is generated under a high-speed switch, which may cause breakdown of components, so the switching frequency is limited, and the switching speed is slow; The switching speed is fast, but the reverse recovery characteristic of the internal parasitic diode is very poor.
  • the reverse recovery current generated by the parasitic diode causes the switching loss to increase and the output voltage to have a spike. Affects the output voltage and reduces the life of the switch.
  • Embodiments of the present invention provide a bridge circuit for an inverter or rectifier to reduce switching losses in the bridge circuit and remove output voltage spikes.
  • FET Field Effect Transistor
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • NMOS Negative channel MOS: N-type MOS tube. Refers to a p-type substrate, an n-channel, and a MOS tube that carries current by electron flow.
  • BJT Bipolar Junction Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • MOS Metal Organic Switches
  • PWM Pulse Width Modulation
  • the semiconductor switch in the embodiment of the present invention may be a high withstand voltage field effect transistor or a combined field effect transistor, wherein the combined field effect transistor includes a high withstand voltage field effect transistor and a low withstand voltage field effect transistor connected in reverse series.
  • the semiconductor switch is a high withstand voltage field effect transistor
  • the drain of the high withstand voltage field effect transistor is defined as the first end of the semiconductor switch
  • the source of the high withstand voltage field effect transistor is defined as the semiconductor.
  • the second end of the switch when the semiconductor switch is a high withstand voltage field effect transistor, the drain of the high withstand voltage field effect transistor is defined as the first end of the semiconductor switch, and the source of the high withstand voltage field effect transistor is defined as the semiconductor. The second end of the switch.
  • the semiconductor switch is a combined field effect transistor
  • the high withstand voltage field effect transistor in the electrical connection mode of the first combined field effect transistor, the high withstand voltage field effect transistor is electrically connected to the source of the low withstand voltage field effect transistor, and the high withstand voltage field effect transistor
  • the drain is defined as the first end of the semiconductor switch
  • the drain of the low withstand voltage field effect transistor is defined as the second end of the semiconductor switch, and the gate voltage of the high withstand voltage field effect transistor and the low withstand voltage field effect transistor Connection for receiving a switch control signal, such as a PWM signal
  • the high withstand voltage field effect transistor in the second connection field effect transistor, the high withstand voltage field effect transistor is electrically connected to the drain of the low withstand voltage field effect transistor, and the high withstand voltage
  • the source of the field effect transistor is defined as the first end of the semiconductor switch
  • the source of the low withstand voltage field effect transistor is defined as the second end of the semiconductor switch, at this time, the high withstand voltage field effect transistor and the low withstand voltage field
  • the field effect transistor in the embodiment of the present invention may be a MOSFET, a JFET, or other types of bidirectional field effect transistors.
  • the electrical connection in the embodiment of the present invention may be a physical contact connection, or may be an electrical connection through a resistor, an inductor, a capacitor or other electronic components.
  • a bridge circuit in an embodiment of the present invention, including:
  • a first DC source port configured to electrically connect the anode of the first DC source
  • a second DC source port configured to electrically connect the anode of the second DC source, wherein the anode of the first DC source and the anode of the second DC source are electrically connected;
  • a first load port for electrically connecting one end of the load circuit
  • a second load port configured to electrically connect the other end of the load circuit, and electrically connect the anode of the first DC voltage source and the anode of the second DC voltage source;
  • a second switch the first end of which is electrically connected to the second end of the first switch, and the second end of the second switch is electrically connected to the first load port;
  • a third switch the first end of which is electrically connected to the second end of the second switch, and electrically connected to the first load port;
  • the fourth switch is electrically connected to the second end of the third switch, and the second end of the fourth switch is electrically connected to the second DC source port;
  • one of the first switch and the second switch is a combined field effect transistor
  • the other switch is a combined field effect tube or a high withstand voltage field effect tube
  • one of the third switch and the fourth switch is a combined field The effect tube, the other switch is a combined field effect tube or a high withstand voltage field effect tube.
  • the combined field effect transistor includes a high withstand voltage field effect tube and a low withstand voltage field effect tube, wherein the high withstand voltage field effect tube and the low withstand voltage field effect tube are connected in series;
  • a first diode wherein an anode of the first diode is electrically connected to the first load port, and a cathode of the first diode is electrically connected to the first end of the first switch;
  • a second diode wherein an anode of the second diode is electrically connected to the second end of the fourth switch, and a cathode of the second diode is electrically connected to the first load port;
  • a third diode wherein an anode of the third diode is electrically connected to the second load port, and a cathode of the third diode is electrically connected to the first end of the second switch;
  • a fourth diode wherein an anode of the fourth diode is electrically connected to the first end of the fourth switch, and a cathode of the fourth diode is electrically connected to the second load port.
  • the freewheeling current is reversed in the combined FET Blocked by the series of parasitic diodes, the freewheeling current must pass through the reverse recovery of the first diode and the second diode with better characteristics, avoiding switching losses and spikes caused by reverse current in the parasitic diode.
  • the first switch is a combined field effect transistor
  • the second switch is a combined field effect transistor
  • the third switch is a combined field effect transistor
  • the fourth switch is a combined field effect transistor
  • the first switch is a combined field effect transistor
  • the second switch is a high withstand voltage field effect transistor
  • the third switch is a high withstand voltage field effect transistor
  • the fourth switch is a combined field effect transistor.
  • the first switch is a high withstand voltage field effect transistor
  • the second switch is a combined field effect transistor
  • the third switch is a combined field effect transistor
  • the fourth switch is a high withstand voltage field effect transistor. Since the first switch and the fourth switch operate longer in one cycle, using the high withstand voltage field effect transistor as the first switch and the fourth switch can reduce the conduction loss.
  • an embodiment of the present invention provides a single-phase three-level inverter, including:
  • a first DC voltage source the anode of which is electrically connected to the first DC source port of the bridge circuit, and the cathode is electrically connected to the first node;
  • the filter circuit includes an inductor and a capacitor connected in series, wherein one end of the inductor is connected to the first load port, the other end is connected to one end of the capacitor, and the other end of the capacitor is connected to the second load port.
  • the freewheeling current is reversed in the combined FET Blocked by the series of parasitic diodes, the freewheeling current must pass through the reverse recovery of the first diode and the second diode with better characteristics, avoiding switching losses and spikes caused by reverse current in the parasitic diode.
  • an embodiment of the present invention provides a multi-phase three-level inverter, including:
  • a first DC voltage source the anode of which is electrically connected to the first DC source port of the plurality of bridge circuits, and the cathode is electrically connected to the first node;
  • a second DC voltage source the anode thereof is electrically connected to the first node, and the cathode is electrically connected to the second DC source port of the plurality of bridge circuits;
  • a plurality of filter circuits in a possible implementation of the second aspect wherein one end of each filter circuit is electrically connected to the first load port, and the other end is electrically connected to the first node. Since at least one combined FET is provided on the two paths from the first load port to the first DC source port and the second DC source port to the first load port, the freewheeling current is reversed in the combined FET Blocked by the series of parasitic diodes, the freewheeling current must pass through the reverse recovery of the first diode and the second diode with better characteristics, avoiding switching losses and spikes caused by reverse current in the parasitic diode.
  • an embodiment of the present invention provides a bridge circuit for a three-level rectifier, including:
  • a first load port for electrically connecting one end of an alternating voltage source
  • a second load port for electrically connecting the other end of the alternating voltage source, and electrically connecting the anode of the first diode and the cathode of the second diode;
  • a second switch the first end of which is electrically connected to the second end of the first switch, and the second end of the second switch is electrically connected to the first load port;
  • a third switch the first end of which is electrically connected to the second end of the second switch, and electrically connected to the first load port;
  • the fourth switch is electrically connected to the second end of the third switch, and the second end of the fourth switch is electrically connected to the second DC source port;
  • one of the first switch and the second switch is a combined field effect transistor
  • the other switch is a combined field effect tube or a high withstand voltage field effect tube
  • one of the third switch and the fourth switch is a combined field The effect tube, the other switch is a combined field effect tube or a high withstand voltage field effect tube.
  • the combined field effect transistor includes a high withstand voltage field effect tube and a low withstand voltage field effect tube, wherein the high withstand voltage field effect tube and the low withstand voltage field effect tube are connected in series;
  • a first diode wherein an anode of the first diode is electrically connected to the first load port, and a cathode of the first diode is electrically connected to the first end of the first switch;
  • a second diode wherein an anode of the second diode is electrically connected to the second end of the fourth switch, and a cathode of the second diode is electrically connected to the first load port;
  • a third diode wherein an anode of the third diode is electrically connected to the second load port, and a cathode of the third diode is electrically connected to the first end of the second switch;
  • the fourth diode wherein the anode of the fourth diode is electrically connected to the first end of the fourth switch, and the cathode of the fourth diode is electrically connected to the second load port.
  • an embodiment of the present invention provides a single-phase three-level rectifier, including:
  • An alternating voltage source wherein two ends of the alternating voltage source are electrically connected to the first load port and the second load port of the bridge circuit, respectively.
  • the high withstand voltage FET has a withstand voltage of 60V to 900V, typically 600V.
  • the low withstand voltage FET has a withstand voltage of 20V to 100V, typically 60V.
  • the field effect transistor is a MOSFET, ie a metal oxide semiconductor field effect transistor.
  • FIG. 1 is a schematic diagram of a bridge circuit of a full MOSFET switch in the prior art
  • Figure 2 is a current-time diagram of the reverse recovery current of the diode
  • FIG. 3 is a schematic diagram of a bridge circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a three-level inverter according to an embodiment of the present invention.
  • FIG. 5 is a waveform diagram of a output voltage and an output current of a three-level inverter according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of voltage-time of a first load port N1 of a three-level inverter according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of another bridge circuit for a single-phase three-level inverter according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of another bridge circuit for a single-phase three-level inverter according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a three-phase three-level inverter according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a single-phase three-level rectifier according to an embodiment of the present invention.
  • FET Field Effect Transistor
  • MOSFET Metallic Oxide Semiconductor Field Effect Transistor
  • BJT Bipolar transistors
  • IGBT Insulated Gate Bipolar Transistor
  • the IGBT when used as a high-speed switch, a spike voltage is generated, which may cause breakdown of components, so the switching frequency is limited, the switching speed is slow, and the frequency limitation causes the volume of the filter circuit as the load circuit to increase. Increase product volume.
  • some manufacturers adopt a full MOSFET scheme. Although the MOSFET is turned on faster, the internal parasitic diode has a very poor reverse recovery characteristic. When the current flows through the parasitic diode, an additional oscillating current is generated, which increases the switching loss. At the same time affect the output voltage.
  • FIG. 1 Shown in Figure 1 is a bridge circuit 100 for a full MOSFET switch of a three level inverter.
  • the bridge circuit 100 includes four MOSFET switches Q1, Q2, Q3, and Q4, two diodes D5 and D6, wherein Q1, Q2, Q3, and Q4 respectively include parasitic diodes D1, D2, D3, and D4 connected in anti-parallel thereto.
  • the positive DC source port BUS1 and the negative DC source port BUS2 are respectively used for electrically connecting the positive DC voltage source and the negative DC voltage source to obtain a DC voltage; the first load port N1 and the second load port N2 are respectively used for the load circuit
  • the terminal is electrically connected, and the load circuit is usually a filter circuit including a capacitor and an inductor connected in series; the second load port N2 can be electrically connected to the ground.
  • Four PWM pulse width modulated waveforms are input to the gates of switches Q1, Q2, Q3, and Q4, respectively, and the turn-on and turn-off of each MOSFET switch is controlled by a PWM pulse width modulated waveform.
  • the PWM waveform-modulated waveform can be output using a commonly used waveform generator to control the on and off of four switches.
  • Diodes D5 and D6 provide current to the path of the second load port N2 when switches Q1 and Q4 are in the off state.
  • the parasitic diodes D1, D2, D3, and D4 generated on the MOSFET due to the limitations of the fabrication process are used as the freewheeling current and the negative DC from the first load port N1 to the positive DC source port BUS1 in the conduction bridge circuit 100.
  • Figure 2 shows the diode current characteristic diagram 200, in which the diode is forward-conducting in the 0-t 1 phase, the charge in the PN junction is accumulated, and the forward current of the size I F flows in the diode; at t 1 -t In the 2nd stage, when the diodes suddenly abut the reverse voltage drop, the accumulated charge in the PN junction will be released and a reverse recovery current will be formed. The current in the diode will not be cut off immediately, but will be changed by the positive I F first.
  • the reverse current recovery characteristic of the parasitic diode of the MOSFET is poor, that is, the reverse current I R is large, and the recovery time t3-t1 is long, so the parasitic diodes D1, D2, D3, and D4 are used as paths for reverse current conduction. This causes the switch recovery characteristics to deteriorate, reduce the switching speed, and cause harmful oscillating current to the bridge circuit.
  • an embodiment of the present invention provides a bridge circuit 300, which can be used for a three-level inverter, including: a semiconductor switch Q1, a semiconductor switch Q2, a semiconductor switch Q3, and a semiconductor switch.
  • the semiconductor switches Q1, Q2, Q3 and Q4, Q1 and Q2 have at least one combined field effect transistor, and Q3 and Q4 have at least one combined field effect transistor.
  • the semiconductor switches Q1, Q2, Q3 and Q4 are combined field effect transistors, that is, the semiconductor switch Q1 includes a high withstand voltage field effect transistor M1 and a low withstand voltage field effect transistor M2, and the semiconductor switch Q2 includes a high Withstand voltage field effect transistor M3 and low withstand voltage field effect transistor M4, semiconductor switch Q3 includes high withstand voltage field effect transistor M5 and low withstand voltage field effect transistor M6, semiconductor switch Q4 includes high withstand voltage field effect transistor M7 and low withstand voltage Field effect transistor M8.
  • the combined field effect transistor is formed by a reverse connection of a high withstand voltage field effect transistor and a low withstand voltage field effect transistor. Wherein, the combined FET has at least two reverse series modes.
  • the source of the high withstand voltage field effect transistor is electrically connected to the source of the low withstand voltage field effect transistor, and the gates of the two field effect transistors are electrically connected as the semiconductor switch a control terminal for receiving a control signal, such as a PWM signal;
  • the drain of the high withstand voltage FET is electrically connected to the drain of the low withstand voltage field effect transistor, and the two fields
  • the gates of the effect transistors receive two control signals, for example two PWM signals, respectively.
  • the high withstand voltage FET has a high withstand voltage, that is, the voltage drop between the collector and the source can be 60V-900V, in one example, it can be 600V; the low-voltage FET has The lower withstand voltage, that is, the voltage drop that can be withstood between the collector and the source is 20V to 100V, and in one example can be 60V.
  • the drain terminal of the high withstand voltage field effect transistor in the combined field effect transistor is used as the first end of the switch, and the drain terminal of the field effect transistor having a low withstand voltage is used as The second end of the switch; in the second reverse series mode, the source terminal of the high withstand voltage field effect transistor in the combined field effect transistor is used as the first end of the switch, and the source terminal of the low withstand voltage field effect transistor is used as the switch The second end.
  • the electrical connection point of the first end of the semiconductor switch Q1 and the positive DC source port BUS1 serves as the node A, and the electrical connection point of the second end of the semiconductor switch Q1 and the positive terminal of the semiconductor switch Q2 is taken as Node B; the electrical connection point of the second end of the semiconductor switch Q2 and the first end of the semiconductor switch Q3 as the first load port N1; the electrical connection point of the second end of the semiconductor switch Q3 and the first end of the semiconductor switch Q4 is a node C; the electrical connection point of the second end of the semiconductor switch Q4 and the negative DC source port BUS2 is taken as the node E; the cathode of the diode D1 is electrically connected to the node A, the anode thereof is electrically connected to the first load port N1; the cathode of the diode D2 is A load port N1 is electrically connected, an anode thereof is electrically connected to the node E; a cathode of the diode D3 is electrically connected to the node
  • the positive DC source port BUS1 and the negative DC source port BUS2 are respectively used for electrically connecting the positive DC voltage source and the negative DC voltage source to obtain a DC voltage;
  • the first load port N1 and the second load port N2 are respectively connected to the load circuit, usually It is a filter circuit, wherein the filter circuit is usually composed of a capacitor and an inductor connected in series.
  • the field effect transistors in the semiconductor switches Q1, Q2, Q3, and Q4 can be MOSFETs, JFETs, or other types of bidirectional FETs.
  • Diodes D1, D2, D3, and D4 can be common silicon diodes, germanium diodes, or other types of diodes, with diodes D1 and D2 being diodes with better reverse current recovery characteristics.
  • a three-level inverter 400 includes a bridge circuit 300, a filter circuit 410, a DC voltage source DC1, and a DC voltage source DC2.
  • the filter circuit 410 includes an inductor L and a capacitor C connected in series. One end of the inductor L is electrically connected to the first load port N1, the other end is electrically connected to the node C, and the other end of the capacitor C is electrically connected to the second load port N2.
  • the positive pole of the DC voltage source DC1 is electrically connected to the positive DC source port BUS1, and the cathode thereof is electrically connected to the second load port N2; the anode of the DC voltage source DC2 is electrically connected to the second load port N2, and the cathode and the positive DC source port thereof are electrically connected.
  • BUS2 is electrically connected.
  • the on and off of the semiconductor switches Q1, Q2, Q3, and Q4 are controlled by controlling the PWM modulation waveform, and the sine wave/cosine wave voltage and the sine wave/cosine wave current are outputted at the node M through the filter circuit 410.
  • Fig. 5 is a waveform diagram of the output voltage U and the output current I at the node M of the inverter 400 in one cycle, and the current flow direction corresponding to the different stages.
  • the output voltage U and the output current I of the node M are both sinusoidal and have a certain phase difference.
  • the output waveform can be divided into four stages. According to the conduction state of the switch, each stage can be divided into two states.
  • the output voltage U is positive
  • the output current I is positive
  • the semiconductor switch Q4 remains off
  • the semiconductor switch Q2 remains on
  • the inverter 400 switches back and forth between the first state and the second state.
  • Q1 is turned on
  • Q3 is turned off
  • current I passes from the positive DC source port BUS1 through the semiconductor switch Q1 and the semiconductor switch Q2 to the first load port N1; when in the second state, Q3 leads
  • the Q1 is turned off, the current I sequentially reaches the first load port N1 from the second load port N2 through the diode D3 and the semiconductor switch Q2.
  • the output voltage U is negative, the output current I is positive, the semiconductor switch Q1 remains off, the semiconductor switch Q3 remains on, and the inverter 400 switches back and forth between the third state and the fourth state.
  • Q4 is turned on, Q2 is turned off, current I passes from the negative DC source port BUS2 through the semiconductor switch Q4 and the semiconductor switch Q3 to the first load port N1; when in the fourth state, Q2 leads
  • the Q4 is turned off, the current I sequentially reaches the first load port N1 from the node N through the diode D3 and the semiconductor switch Q2.
  • stage 503 the output voltage U is negative, the output current I is negative, the semiconductor switch Q1 remains off, the semiconductor switch Q3 remains on, and the inverter 400 switches back and forth between the fifth state and the sixth state.
  • Q2 is turned on, Q4 is turned off, current I is sequentially passed from the first load port N1 through the semiconductor switch Q3 and the semiconductor switch D4 to the second load port N2; when in the sixth state, Q4 is When the Q2 is turned off, the current I sequentially passes from the first load port N1 through the semiconductor switch Q3 and the semiconductor switch Q4 to the negative DC source port BUS2.
  • the output voltage U is positive, the output current I is negative, the semiconductor switch Q4 remains off, the semiconductor switch Q2 remains on, and the inverter 400 switches back and forth between the seventh state and the eighth state.
  • Q3 is turned on, Q1 is turned off, current I is sequentially passed from the first load port N1 through the semiconductor switch Q3 and the diode Q4 to the second load port N2;
  • Q1 is turned on.
  • Q3 is turned off, and the current I sequentially reaches the positive DC source port BUS1 through the semiconductor switch Q2 and the semiconductor switch Q1 from the first load port N1.
  • stage 502 during the transition of the third state and the fourth state of the inverter 400, the semiconductor switch Q2 and the semiconductor switch Q4 enter a short, simultaneous off state, at which time the inductance L and the capacitance C of the filter circuit 410 are There is still a freewheeling current through, and the direction of the freewheeling current is from the negative DC source port BUS2 to the first load port N1 and then to the second load port N2.
  • the freewheeling current will pass from the negative DC source port BUS2 through the parasitic diode of the semiconductor switch Q4 and the parasitic diode of the semiconductor switch Q3 to the first load port N1, and the parasitic diode bears short The effect of time conducting current.
  • the reverse current recovery characteristic of the parasitic diode when the voltage drop at both ends changes from positive to negative, there is a long reverse current in the parasitic diode, thus causing the switching speed to be slow, the switching loss to become large, and in the circuit. Produces harmful oscillating currents.
  • the parasitic diodes of the two FETs included in each semiconductor switch are actually reverse series structures, which block the path of the parasitic diode current and avoid
  • the prior art uses only a single FET as a semiconductor switch, so that electrical problems due to reverse currents occur in the parasitic diode of the FET.
  • the function of conducting the freewheeling current is performed by an anti-parallel diode D2, that is, current flows from the negative DC source port BUS2 through the diode D2 and the filter circuit to the second load port N2.
  • the current path formed by the anti-parallel diode D2 replaces the current path formed by the parasitic diode of a single field effect transistor in the prior art.
  • the switch When the switch is turned on, the on-resistance equivalent resistance of the high withstand voltage field effect transistor is large, and the on-resistance equivalent resistance of the low withstand voltage field effect transistor is small, so when the switch is turned on, the series has a high resistance.
  • the extra pressure drop caused by the FET is negligible compared to the pressure drop of the high withstand FET.
  • the semiconductor switch Q1 and the semiconductor switch Q4 enter a short simultaneous off state.
  • the freewheeling current reaches the positive DC source port BUS1 from the second load port N2 through the filter circuit 410 and the diode D1.
  • the current path formed by the antiparallel diode D1 replaces the current path formed by the parasitic diode of a single field effect transistor in the prior art.
  • the diodes D1 and D2 in the inverter 400 have better reverse current recovery characteristics than the parasitic diodes, the reverse currents of the diodes D1 and D2 from turn-on to off are small, and the recovery time is short, which can be avoided. An oscillating current is generated in the circuit.
  • 6 is a voltage-time diagram of the bridge circuit 100 and the bridge circuit 300 at the first load port N1.
  • 610 is a voltage-time diagram of the first load port N1 of the bridge circuit 100 when a freewheeling current is generated, wherein, at times t1, t2, and t3, the states of the switches are respectively from off to on, at t1.
  • the rising edges of the square wave at t2 and t3 respectively have spikes; when at least one of the switches Q1 and Q2 is combined with at least one of the field effect transistors, Q3 and Q4, 620 is the bridge circuit 300.
  • an embodiment of the present invention further provides a bridge circuit 700 for a three-level inverter, the circuit structure of which is similar to that of the bridge circuit 300, and the details are not described herein again.
  • the positive DC source port BUS1 and the negative DC source port BUS2 are respectively used for electrically connecting the positive DC voltage source and the negative DC voltage source, and the first load port N1 and the second load port N2 are respectively connected to the filter circuit to realize single phase.
  • the function of a three-level inverter In the bridge circuit 700, the semiconductor switch Q2 and the semiconductor switch Q3 are replaced with ordinary high-voltage FETs.
  • the bridge circuit 700 not only reduces the number of required field effect transistors, but also solves the parasitic diode reverse recovery current problem of the high withstand voltage field effect transistor.
  • an embodiment of the present invention further provides a bridge circuit 800 for a three-level inverter, the circuit structure of which is similar to that of the bridge circuit 300, and the same portions are not described herein again.
  • the positive DC source port BUS1 and the negative DC source port BUS2 are respectively used for electrically connecting the positive DC voltage source and the negative DC voltage source, and the first load port N1 and the second load port N2 are respectively connected to the filter circuit to realize single phase.
  • the function of a three-level inverter In the bridge circuit 800, the semiconductor switch Q1 and the semiconductor switch Q4 are replaced with a common high withstand voltage field effect transistor, and the semiconductor switches Q2 and Q3 are combined field effect transistors.
  • the bridge circuit 800 avoids the problem of poor reverse recovery characteristics of the parasitic diode and reduces the number of FETs required, further reducing switching losses.
  • the inverter In the process of outputting a full cycle of voltage, the inverter will go through the 501 phase, the 502 phase, the 503 phase, and the 504 phase.
  • the four phases described above differ in the duration of a complete cycle, with the 501 phase and the 503 phase occupying a longer period of a complete cycle, while the 502 phase and the 504 phase occupy a shorter time within a full cycle.
  • the semiconductor switch Q2 remains on
  • the semiconductor switch Q4 remains off
  • the semiconductor switch Q1 and the semiconductor switch Q3 are complementarily turned on.
  • the direction in which the current flows is: in the first state, the first load port N1 is sequentially passed from the positive DC source port BUS1 through the semiconductor switch Q1 and the semiconductor switch Q2; in the second state, the diode D3 is sequentially passed from the second load port N2. And the semiconductor switch Q2 reaches the first load port N1. Therefore, the circuit is continuously switched between the first state and the second state, and the conduction loss of the semiconductor switching transistor Q1 is maximized. Similarly, in the 503 stage, the circuit continuously switches between the fifth state and the sixth state, and the conduction loss of the semiconductor switching transistor Q4 is maximized.
  • the conduction loss of the combined FET is greater than that of the high-voltage FET during the switching process, resulting in waste of energy. Therefore, the use of the combined field effect transistor as the semiconductor switches Q2 and Q3 and the ordinary high withstand voltage field effect transistor as the semiconductor switches Q1 and Q4 can further reduce the conduction loss.
  • the bridge circuit 300, the bridge circuit 700, and the bridge circuit 800 can be used for a single-phase three-level inverter circuit, a three-phase three-level inverter circuit, or a three-phase inverter circuit of more phases.
  • the bridge circuit 300, the bridge circuit 700 and the bridge circuit 800 can be used as a bridge of a three-phase or multi-phase three-level inverter circuit, and the output thereof is equivalent to a three-phase or multi-phase three-level inverter. The output of one of the phase voltages in the circuit.
  • the positive DC voltage port BUS1 of the bridge circuit is electrically connected to the positive DC voltage source, and the negative DC voltage port BUS2 and the negative DC voltage source are connected. Electrically connected, the first load port N1 and the second load port N2 are respectively connected to both ends of the load circuit to obtain a sine wave/cosine wave voltage.
  • the embodiment of the present invention further provides a three-phase three-level inverter 900.
  • the positive side bus 910 extending from the positive DC voltage port BUS1 and the negative side bus 911 extending from the negative DC voltage port BUS2 are provided.
  • the parallel bridge circuit 920, the bridge circuit 921 and the bridge circuit 922 are respectively connected, and the first load port in each bridge is used as the output point of the phase, that is, the corresponding outputs of the three phases are 931, 932 and 933 respectively.
  • Bridge circuit 920, bridge circuit 921, and bridge circuit 922 can be any of the bridge circuits provided in accordance with embodiments of the present invention.
  • the positive DC source port BUS1 and the negative DC source port BUS2 are respectively used for electrically connecting the positive DC voltage source and the negative DC voltage source to obtain a DC voltage; the output terminals 931, 932 and 933 can be electrically connected to the plurality of filter circuits 410 respectively to obtain A sinusoidal voltage in which one end of each filter circuit 410 is electrically coupled to the output terminals 931, 932, and 933, and the other end is electrically connected to the electrical connection points of the capacitor 941 and the capacitor 942.
  • the capacitance values of the two capacitors 941 and 942 in series can be equal, and the voltage on the DC side is balanced.
  • the bridge circuit 920, the bridge circuit 921, and the bridge circuit 922 adopt the bridge circuit provided by the embodiment of the present invention, the switching loss on each bridge is improved, and the switch caused by the reverse recovery current of the parasitic diode is avoided. Speed limited, pulse current damage switch and other issues.
  • the above inverters can be used in an Uninterruptible Power Supply (UPS) system.
  • UPS Uninterruptible Power Supply
  • the inverters in the UPS operate primarily in stages 501 and 503. Since the combined FET is used to replace the IGBT or the high voltage MOSFET in the prior art, the inverter in the UPS has smaller loss, higher efficiency, lower cost, and avoids the switching speed caused by the reverse recovery current of the parasitic diode. Restricted, pulsed current damage switches and other issues.
  • the bridge circuit in the embodiment of the invention can also be used in a rectifier.
  • the first load port and the second load port are respectively electrically connected to the two ends of the AC voltage source, and the positive DC voltage source BUS1 and the negative DC voltage source BUS2 may be Get DC voltage output.
  • an embodiment of the present invention further provides a single-phase three-level rectifier 1000 for converting an alternating current voltage into a direct current voltage.
  • the single-phase three-level rectifier 1000 includes a bridge circuit 1010 and an AC input circuit 1020, wherein the bridge circuit 1010 can be any of the bridge circuits in the embodiments of the present invention.
  • the AC input circuit 1020 includes an inductor L in series and an AC voltage source AC. The one end of the AC input circuit 1020 is electrically connected to the first load port N1, and the other end is electrically connected to the second load port N2.
  • the positive DC source port BUS1 and the negative DC source port BUS2 are respectively used for electrical connection with both ends of the load circuit to obtain a DC voltage output.
  • any of the bridge circuits of the embodiments of the present invention can also be used for other rectifier circuits, such as three-phase three-level rectifiers, or three-phase rectifiers of more phases.

Abstract

一种用于逆变器或整流器的电桥电路，涉及电力电子技术领域，包括相互串联的、电连接于正负直流电压源之间的第一开关、第二开关、第三开关、第四开关。其中，第一开关和第二开关与第一二极管反向并联，第一开关和第二开关中至少包括一个组合场效应管；第三开关和第四开关与第二二极管反向并联，第三开关和第四开关中至少包括一个组合场效应管。组合场效应管为源极或漏极互相电连接的一个高耐压场效应管和一个低耐压场效应管。由于组合场效应管中的寄生二极管反向串联，阻断了续流电流在寄生二极管中的通路，减小了续流电流造成的开关损耗和尖峰电压。

Description

一种用于逆变器或整流器的电桥电路 技术领域
本发明涉及电力电子技术领域，尤其涉及一种电桥电路。
背景技术
脉宽调制(Pulse Width Modulation，PWM)逆变器目前在电力电子领域被广泛的应用，尤其是在不间断电源、太阳能逆变器、风能变流器、电动机驱动、燃料电池等领域，其中单相三电平逆变器应用最为广泛。现有技术中，用于单相三电平逆变器的电桥电路通常采用4个场效应晶体管作为开关，或者4个双极性晶体管分别与二极管反向并联作为开关。其中，将双极性晶体管与二极管反向并联作为开关的缺点是高速开关下产生尖峰电压，可能造成元器件的击穿，因此开关频率受限，开关速度较慢；将场效应管作为开关虽然开关速度较快，但由于内部寄生二极管反向恢复特性非常差，在电流通过寄生二极管续流时，由于寄生二极管产生的反向恢复电流导致开关损耗增大、输出电压带有尖峰等问题，从而影响输出电压并降低开关的寿命。
发明内容
本发明的实施例提供了一种用于逆变器或整流器的电桥电路，以降低电桥电路中的开关损耗、去除输出电压尖峰。
为了详细描述本发明，将使用以下术语、缩写或符号：
FET(Field Effect Transistor)：场效应晶体管。多数载流子参与导电的电压控制型半导体器件。
MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)：金氧半场效晶体管。
NMOS(Negative channel MOS)：N型MOS管。指p型衬底、n沟道，靠电子的流动运送电流的MOS管。
BJT(Bipolar Junction Transistor)：双极结型晶体管。一种由两个PN结结合在一起的电流控制的器件。
IGBT(Insulated Gate Bipolar Transistor)：绝缘栅双极型晶体管。由BJT和MOS组成的复合全控型电压驱动式功率半导体器件。
PWM(Pulse Width Modulation)：脉冲宽度调制。利用微处理器的数字输出来对模拟电路进行控制的技术。
本发明实施例中的半导体开关可以为高耐压场效应管或组合场效应管，其中组合场效应管包括反向串联的一个高耐压场效应管和一个低耐压场效应管。为了详细描述本发明，当半导体开关为高耐压场效应管时，将高耐压场效应管的漏极定义为半导体开关的第一端，将高耐压场效应管的源极定义为半导体开关的第二端。当半导体开关为组合场效应管时，在第一种组合场效 应管的电连接方式中，高耐压场效应管与低耐压场效应管的源极电连接，将高耐压场效应管的漏极定义为半导体开关的第一端，将低耐压场效应管的漏极定义为半导体开关的第二端，此时高耐压场效应管和低耐压场效应管的栅极电连接，用于接收开关控制信号，例如PWM信号；在第二种组合场效应管的电连接方式中，高耐压场效应管与低耐压场效应管的漏极电连接，将高耐压场效应管的源极定义为半导体开关的第一端，将低耐压场效应管的源极定义为半导体开关的第二端，此时高耐压场效应管和低耐压场效应管的栅极分别接收开关控制信号，优选的，开关控制信号为两个控制信号，例如两个PWM信号。
本发明实施例中的场效应管可以是MOSFET、JFET，或者其他类型的双向场效应管。本发明实施例中的电连接可以是物理上的接触连接，也可以是通过电阻、电感、电容或其他电子元器件实现电学的连接。
第一方面，在本发明的实施例中提供一种电桥电路，包括：
第一直流源端口，用于电连接第一直流源的正极；
第二直流源端口，用于电连接第二直流源的负极，其中第一直流源的负极和第二直流源的正极电连接；
第一负载端口，用于电连接负载电路的一端；
第二负载端口，用于电连接所述负载电路的另一端，以及电连接第一直流电压源的负极和第二直流电压源的正极；
第一开关，其第一端与第一直流源端口电连接；
第二开关，其第一端与第一开关的第二端电连接，第二开关的第二端与第一负载端口电连接；
第三开关，其第一端与第二开关的第二端电连接，以及电连接第一负载端口；
第四开关，其第一端与第三开关的第二端电连接，第四开关的第二端与第二直流源端口电连接；
其中，第一开关和第二开关中，一个开关为组合场效应管，另一个开关为组合场效应管或高耐压场效应管；第三开关和第四开关中，有一个开关为组合场效应管，另一个开关为组合场效应管或高耐压场效应管。
组合场效应管包括一个高耐压场效应管和一个低耐压场效应管，其中，高耐压场效应管和低耐压场效应管反向串联；
第一二极管，其中，第一二极管的阳极电连接于第一负载端口，第一二极管的阴极电连接于第一开关的第一端；
第二二极管，其中，第二二极管的阳极电连接于第四开关的第二端，第二二极管的阴极电连接于第一负载端口；
第三二极管，其中，第三二极管的阳极电连接于第二负载端口，第三二极管的阴极电连接于所述第二开关的第一端；
第四二极管，其中，第四二极管的阳极电连接于第四开关的第一端，第 四二极管的阴极电连接于第二负载端口。
由于在第一负载端口到第一直流源端口和第二直流源端口到第一负载端口的两个通路上均有至少一个组合场效应管，使得续流电流被组合场效应管中反向串联的寄生二极管所阻断，续流电流必须通过反向恢复特性较好的第一二极管和第二二极管，避免了寄生二极管中出现反向电流而导致的开关损耗和尖峰电压。
在一个可能的设计中，第一开关为组合场效应管，第二开关为组合场效应管，第三开关为组合场效应管，第四开关为组合场效应管。
在一个可能的设计中，第一开关为组合场效应管，第二开关为高耐压场效应管，第三开关为高耐压场效应管，第四开关为组合场效应管。将高耐压场效应管用作第二开关和第三开关，因此在第一负载端口到第一直流源端口和第二直流源端口到第一负载端口的通路上至少有一个组合场效应管，在保证续流电流不会通过寄生二极管的同时，减少了场效应管的数量，缩小电桥电路的体积。
在一个可能的设计中，第一开关为高耐压场效应管，第二开关为组合场效应管，第三开关为组合场效应管，第四开关为高耐压场效应管。由于第一开关和第四开关在一个周期中工作的时间更长，因此将高耐压场效应管用作第一开关和第四开关能减少导通损耗。
第二方面，本发明实施例提供一种单相三电平逆变器，包括：
第一方面的所有可能的实施方式中的任意一种电桥电路；
第一直流电压源，其正极与电桥电路的第一直流源端口电连接，负极与第一节点电连接；
第二直流电压源，其正极与第一节点电连接，负极与电桥电路的第二直流源端口电连接；
滤波电路，其中滤波电路的一端电连接于第一负载端口，另一端电连接于第一节点。
在一个可能的设计中，滤波电路包括串联的电感和电容，其中，电感的一端与第一负载端口连接，另一端与电容的一端连接，电容的另一端与第二负载端口连接。
由于在第一负载端口到第一直流源端口和第二直流源端口到第一负载端口的两个通路上均有至少一个组合场效应管，使得续流电流被组合场效应管中反向串联的寄生二极管所阻断，续流电流必须通过反向恢复特性较好的第一二极管和第二二极管，避免了寄生二极管中出现反向电流而导致的开关损耗和尖峰电压。
第三方面，本发明实施例提供一种多相三电平逆变器，包括：
第一方面的所有可能的实施方式中的多个电桥电路；
第一直流电压源，其正极与多个电桥电路的第一直流源端口电连接，负极与第一节点电连接；
第二直流电压源，其正极与第一节点电连接，负极与多个电桥电路的第二直流源端口电连接；
第二方面的可能的实施方式中的多个滤波电路，其中每个滤波电路的一端电连接于第一负载端口，另一端电连接于第一节点。由于在第一负载端口到第一直流源端口和第二直流源端口到第一负载端口的两个通路上均有至少一个组合场效应管，使得续流电流被组合场效应管中反向串联的寄生二极管所阻断，续流电流必须通过反向恢复特性较好的第一二极管和第二二极管，避免了寄生二极管中出现反向电流而导致的开关损耗和尖峰电压。
第四方面，本发明实施例提供一种用于三电平整流器的电桥电路，包括：
第一直流源端口和第二直流源端口，用于电连接负载电路的两端；
第一负载端口，用于电连接交流电压源的一端；
第二负载端口，用于电连接所述交流电压源的另一端，以及电连接第一二极管的阳极和第二二极管的阴极；
第一开关，其第一端与第一直流源端口电连接；
第二开关，其第一端与第一开关的第二端电连接，第二开关的第二端与第一负载端口电连接；
第三开关，其第一端与第二开关的第二端电连接，以及电连接第一负载端口；
第四开关，其第一端与第三开关的第二端电连接，第四开关的第二端与第二直流源端口电连接；
其中，第一开关和第二开关中，一个开关为组合场效应管，另一个开关为组合场效应管或高耐压场效应管；第三开关和第四开关中，有一个开关为组合场效应管，另一个开关为组合场效应管或高耐压场效应管。
组合场效应管包括一个高耐压场效应管和一个低耐压场效应管，其中，高耐压场效应管和低耐压场效应管反向串联；
第一二极管，其中，第一二极管的阳极电连接于第一负载端口，第一二极管的阴极电连接于第一开关的第一端；
第二二极管，其中，第二二极管的阳极电连接于第四开关的第二端，第二二极管的阴极电连接于第一负载端口；
第三二极管，其中，第三二极管的阳极电连接于第二负载端口，第三二极管的阴极电连接于所述第二开关的第一端；
第四二极管，其中，第四二极管的阳极电连接于第四开关的第一端，第四二极管的阴极电连接于第二负载端口。
第五方面，本发明实施例提供一种单相三电平整流器，包括：
第四方面的所有可能的实施方式中的任意一种电桥电路；
交流电压源，其中，交流电压源的两端分别与电桥电路的第一负载端口和第二负载端口电连接。
在一个可能的设计中，高耐压场效应管的耐受电压为60V～900V，通常为 600V。
在一个可能的设计中，低耐压场效应管的耐受电压为20V～100V，通常为60V。
在一个可能的设计中，场效应晶体管为MOSFET，即金属氧化物半导体场效应管。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1为现有技术中一种全MOSFET开关的电桥电路的示意图；
图2为二极管的反向恢复电流的电流——时间图；
图3为本发明实施例中一种电桥电路示意图；
图4为本发明实施例中一种三电平逆变器的示意图；
图5为本发明实施例中一种三电平逆变器输出电压、输出电流波形图和电流流向图；
图6为本发明实施例中一种三电平逆变器的第一负载端口N1的电压——时间示意图；
图7为本发明实施例中另一种用于单相三电平逆变器的电桥电路示意图；
图8为本发明实施例中又一种用于单相三电平逆变器的电桥电路示意图；
图9为本发明实施例中一种三相三电平逆变器的示意图。
图10为本发明实施例中一种单相三电平整流器的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
电力电子领域最常用的开关器件之一是场效应晶体管(Field Effect Transistor,FET)，如最常见的金属氧化场效应晶体管(Metallic Oxide Semiconductor Field Effect Transistor,MOSFET)，其次是双极性晶体管(Bipolar Junction Transistor,BJT)，如最常见的绝缘栅双极性晶体管(Insulated Gate Bipolar Transistor,IGBT)。现有技术中，应用最广泛的、用于单相三电平逆变器的电桥电路采用IGBT作为开关来控制输出波形。由于成本低，可靠性高，目前业界绝大多数厂商采用此方案,尤其是中大功率逆变器。但将IGBT作为高速开关时会产生尖峰电压，可能造成元器件的击穿，因此开关频率受限，开关速度较慢，而频率受限还会使作为负载电路的滤波电路的体积增大，从而增大产品体积。另外，也有一些厂商采用全MOSFET的方案，虽然MOSFET开通速度较快，但由于内部寄生二极管反向恢复特性非常差，在电流通过寄生二极管续流时，产生额外的振荡电流，在增大开关损耗的同时影响输出电压。
图1所示的是一种用于三电平逆变器的全MOSFET开关的电桥电路100。电桥电路100包括4个MOSFET开关Q1、Q2、Q3和Q4、两个二极管D5 和D6，其中Q1、Q2、Q3和Q4分别包括与其反向并联的寄生二极管D1、D2、D3和D4。正直流源端口BUS1和负直流源端口BUS2分别用于电连接正直流电压源和负直流电压源，以获得直流电压；第一负载端口N1和第二负载端口N2分别用于和负载电路的两端电连接，负载电路通常为滤波电路，包括串联的一个电容和一个电感；第二负载端口N2可以与地端电连接。4个PWM脉宽调制波形分别输入到开关Q1、Q2、Q3和Q4的栅极，并通过PWM脉宽调制波形来控制每个MOSFET开关的导通与断开。当输入到栅极的信号为高电平，则MOSFET开关导通，电流可以从漏极到源极；当输入到栅极的信号为低电平，则MOSFET开关断开，电流不能通过MOSFET开关。可以使用常用的波形发生器来输出PWM脉宽调制波形，从而控制4个开关的导通与断开。二极管D5和D6在开关Q1和Q4处于断开状态时给电流提供到第二负载端口N2的通路。由于制作工艺的限制而在MOSFET上产生的寄生二极管D1、D2、D3和D4，用作导通电桥电路100中从第一负载端口N1到正直流源端口BUS1的续流电流和从负直流源端口BUS2到第一负载端口N1的续流电流。
如图2所示为二极管电流特性图200，其中在0-t 1阶段，二极管正向导通，PN结内的电荷被积累，二极管中流通大小为I F的正向电流；在t 1-t 2阶段，当二极管两端突然承受反向压降时，PN结内积累的电荷将释放并形成一个反向恢复电流，二极管中的电流并不立刻截止，而是先由正向的I F变为很大的反向电流I R，并维持一段时间；在t 2之后，反向电流逐渐下降，经过一段恢复时间后稳定到一个很小的数值0.1I R，并进入反向截止状态。MOSFET的寄生二极管的反向电流恢复特性较差，即反向电流I R较大，恢复时间t3-t1较长，因此将寄生二极管D1、D2、D3和D4作为反向电流导通的路径会导致开关恢复特性变差、降低开关速度并给电桥电路带来有害的振荡电流。
为了克服上述问题，如图3所示，本发明实施例提供了一种电桥电路300，可以用于三电平逆变器，包括：半导体开关Q1、半导体开关Q2、半导体开关Q3、半导体开关Q4、二极管D1、二极管D2、二极管D3、二极管D4。半导体开关Q1、Q2、Q3和Q4中，Q1和Q2至少有一个组合场效应管，Q3和Q4至少有一个组合场效应管。在电桥电路300中，半导体开关Q1、Q2、Q3和Q4均为组合场效应管，即，半导体开关Q1包括高耐压场效应管M1和低耐压场效应管M2，半导体开关Q2包括高耐压场效应管M3和低耐压场效应管M4，半导体开关Q3包括高耐压场效应管M5和低耐压场效应管M6，半导体开关Q4包括高耐压场效应管M7和低耐压场效应管M8。组合场效应管为一个高耐压场效应管和一个低耐压场效应管反向串联而成。其中，所述组合场效应管至少具有两种反向串联方式。在第一种反向串联方式中，高耐压场效应管的源极和低耐压场效应管的源极电连接，并且这两个场效应管的栅极电连接，作为上述半导体开关的控制端，用于接收控制信号，例如PWM信号；在第二种反向串联方式中，高耐压场效应管的漏极和低耐压场效应管 的漏极电连接，并且这两个场效应管的栅极分别接收两个控制信号，例如两个PWM信号。高耐压场效应管具有较高的耐受电压，即集电极和源极之间能承受的压降为60V～900V，在一种示例中可以取值为600V；低耐压场效应管具有较低的耐受电压，即集电极和源极之间能承受的压降为20V～100V，在一种示例中可以取值为60V。
为了方便表述，在上述第一种反向串联方式中，将组合场效应管中高耐压场效应管的漏极端作为开关的第一端，将具有低耐受电压的场效应管的漏极端作为开关的第二端；在上述第二种反向串联方式中，将组合场效应管中高耐压场效应管的源极端作为开关的第一端，将低耐压场效应管的源极端作为开关的第二端。图3所示的电桥电路300中，半导体开关Q1的第一端与正直流源端口BUS1的电连接点作为节点A，半导体开关Q1的第二端与半导体开关Q2的正极的电连接点作为节点B；半导体开关Q2的第二端与半导体开关Q3的第一端的电连接点作为第一负载端口N1；半导体开关Q3的第二端与半导体开关Q4的第一端的电连接点为节点C；半导体开关Q4的第二端与负直流源端口BUS2的电连接点作为节点E；二极管D1的阴极与节点A电连接，其阳极与第一负载端口N1电连接；二极管D2的阴极与第一负载端口N1电连接，其阳极与节点E电连接；二极管D3的阴极与节点B电连接；二极管D4的阴极与二极管D3的阳极的电连接点为第二负载端口N2，其阳极与节点C电连接。
正直流源端口BUS1和负直流源端口BUS2分别用于电连接正直流电压源和负直流电压源，以获得直流电压；第一负载端口N1和第二负载端口N2两端接入负载电路，通常为滤波电路，其中滤波电路通常为一个电容和一个电感串联组成。
半导体开关Q1、Q2、Q3和Q4中的场效应管可以是MOSFET、JFET，或者其他类型的双向场效应管。二极管D1、D2、D3和D4可以是常见的硅二极管，锗二极管，或其他类型的二极管，其中二极管D1和D2可以选用具有较好的反向电流恢复特性的二极管。
如图4所示的是根据本发明实施例提供的一种三电平逆变器400，包括电桥电路300、滤波电路410、直流电压源DC1和直流电压源DC2。其中，滤波电路410包括串联的电感L和电容C，电感L的一端与第一负载端口N1电连接，另一端与电容C电连接于节点M，电容C的另一端与第二负载端口N2电连接；直流电压源DC1的正极与正直流源端口BUS1电连接，其负极与第二负载端口N2电连接；直流电压源DC2的正极与第二负载端口N2电连接，其负极与正直流源端口BUS2电连接。通过控制PWM调制波形来控制半导体开关Q1、Q2、Q3和Q4的导通与截止，并通过滤波电路410在节点M输出正弦波/余弦波电压与正弦波/余弦波电流。
以下通过工作状态的转换来进一步说明单相三电平逆变器400的工作原理。图5为一个周期内逆变器400的节点M处的输出电压U和输出电流I的 波形图，以及不同阶段对应的电流流向。如图5所示，节点M的输出电压U和输出电流I均为正弦波，且具有一定的相位差。根据输出电流I和输出电压U的正负，输出波形可以分为4个阶段，根据开关的导通状态，每一个阶段又可以分为两种状态。
图5所示的501阶段，输出电压U为正，输出电流I为正，半导体开关Q4保持关断，半导体开关Q2保持导通，逆变器400在第一状态和第二状态之间来回转换。当处在第一状态时，Q1导通，Q3关断，电流I从正直流源端口BUS1依次通过半导体开关Q1和半导体开关Q2到达第一负载端口N1；当处在第二状态时，Q3导通，Q1关断，电流I依次从第二负载端口N2通过二极管D3和半导体开关Q2到达第一负载端口N1。在502阶段，输出电压U为负，输出电流I为正，半导体开关Q1保持关断，半导体开关Q3保持导通，逆变器400在第三状态和第四状态之间来回转换。当处在第三状态时，Q4导通，Q2关断，电流I从负直流源端口BUS2依次通过半导体开关Q4和半导体开关Q3到达第一负载端口N1；当处在第四状态时，Q2导通，Q4关断，电流I依次从节点N通过二极管D3和半导体开关Q2到达第一负载端口N1。在503阶段，输出电压U为负，输出电流I为负，半导体开关Q1保持关断，半导体开关Q3保持导通，逆变器400在第五状态和第六状态之间来回转换。当处在第五状态时，Q2导通，Q4关断，电流I从第一负载端口N1依次通过半导体开关Q3和半导体开关D4到达第二负载端口N2；当处在第六状态时，Q4导通，Q2关断，电流I依次从第一负载端口N1通过半导体开关Q3和半导体开关Q4到达负直流源端口BUS2。在504阶段，输出电压U为正，输出电流I为负，半导体开关Q4保持关断，半导体开关Q2保持导通，逆变器400在第七状态和第八状态之间来回转换。当处在第七状态时，Q3导通，Q1关断，电流I从第一负载端口N1依次通过半导体开关Q3和二极管Q4到达第二负载端口N2；当处在第八状态时，Q1导通，Q3关断，电流I依次从第一负载端口N1通过半导体开关Q2和半导体开关Q1到达正直流源端口BUS1。
在502阶段，逆变器400在第三状态和第四状态的转换期间，半导体开关Q2和半导体开关Q4会进入一个短暂的、同时截止的状态，此时滤波电路410的电感L和电容C中依然有续流电流通过，且续流电流的方向为从负直流源端口BUS2到第一负载端口N1，再到第二负载端口N2。如果半导体开关Q3和Q4采用普通的高压场效应管，则续流电流会从负直流源端口BUS2通过半导体开关Q4的寄生二极管和半导体开关Q3的寄生二极管到达第一负载端口N1，寄生二极管承担短时间导通电流的作用。但由于寄生二极管反向电流恢复特性，当两端的压降由正变为负时，寄生二极管中存在较长时间的反向电流，因此导致开关速度变慢、开关损耗变大，并在电路中产生有害的振荡电流。由于半导体开关Q1、Q2、Q3和Q4均为组合场效应管，每个半导体开关包含的两个场效应管的寄生二极管实际上是反向串联结构，阻断了 寄生二极管电流的通路，避免了现有技术只使用单个场效应管作为半导体开关，以至于场效应管的寄生二极管中出现反向电流而导致的电气问题。导通续流电流的功能由一个反向并联的二极管D2来完成，即电流从负直流源端口BUS2经过二极管D2和滤波电路到达第二负载端口N2。反向并联的二极管D2形成的电流通路代替了现有技术中单个场效应管的寄生二极管形成的电流通路。在开关导通时，高耐压场效应管的导通等效电阻较大，而低耐压场效应管的导通等效电阻较小，因此，当开关导通时，串联一个具有高耐压场效应管带来的额外压降相对于高耐压场效应管的压降可以忽略。
同样的，在504阶段，当逆变器400在第七状态和第八状态之间进行转换时，半导体开关Q1和半导体开关Q4会进入一个短暂的同时截止的状态。此时，续流电流从第二负载端口N2通过滤波电路410和二极管D1到达正直流源端口BUS1。反向并联的二极管D1形成的电流通路代替了现有技术中单个场效应管的寄生二极管形成的电流通路。
由于逆变器400中的二极管D1和D2比寄生二极管具有更好的反向电流恢复特性，因此二极管D1和D2从导通变为截止时反向电流较小，且恢复时间较短，可以避免在电路中产生振荡电流。
图6为电桥电路100和电桥电路300在第一负载端口N1处的电压——时间图。其中，610为电桥电路100在有续流电流产生时第一负载端口N1的电压——时间图，其中，在t1、t2、t3时刻，开关的状态分别从截止到导通，在t1、t2和t3时刻方波的上升沿分别出现了尖刺；当开关Q1和Q2中至少有一个组合场效应管、Q3和Q4中至少有一个组合场效应管时，620为电桥电路300在有续流电流产生时第一负载端口N1的电压——时间图，其中，在t1、t2和t3时刻方波的上升沿几乎没有尖刺出现。
如图7所示，本发明实施例还提供了一种用于三电平逆变器的电桥电路700，其电路结构与电桥电路300相似，相同之处不再赘述。将正直流源端口BUS1和负直流源端口BUS2分别用于电连接正直流电压源和负直流电压源，将第一负载端口N1和第二负载端口N2两端接入滤波电路，可实现单相三电平逆变器的功能。电桥电路700中，半导体开关Q2和半导体开关Q3被替换成普通的高耐压场效应管。这样一来，从第一负载端口N1到正直流电压端口BUS1，或者从负直流电压端口BUS2到第一负载端口N1的电流通路上，依然存在一个组合场效应管，即图7中的半导体开关Q1和Q4。因此，当电路处在图5中的502阶段的第三状态和第四状态的转换期间，由于半导体开关Q4中两个场效应管的寄生二极管反向串联的缘故，续流电流从二极管D2中流过，避免了由于场效应管内部寄生二极管的反向恢复特性差导致的相关电气问题；当电路处在图5中的504阶段的第七状态和第八状态的转换期间，由于半导体开关Q1中两个场效应管的寄生二极管反向串联的缘故，电流从二极管D1中流过，同样可以避免由于场效应管内部寄生二极管的反向恢复特性差导致的相关电气问题。因此，与图3中的电桥电路300相比，电桥电 路700不但缩减了需要的场效应管数量，而且也可以解决高耐压场效应管的寄生二极管反向恢复电流问题。
如图8所示，本发明实施例还提供了一种用于三电平逆变器的电桥电路800，其电路结构与电桥电路300相似，相同之处不再赘述。将正直流源端口BUS1和负直流源端口BUS2分别用于电连接正直流电压源和负直流电压源，将第一负载端口N1和第二负载端口N2两端接入滤波电路，可实现单相三电平逆变器的功能。电桥电路800中，半导体开关Q1和半导体开关Q4被替换成普通的高耐压场效应管，而半导体开关Q2和Q3为组合场效应管。这样一来，从第一负载端口N1到正直流电压端口BUS1，或者从负直流电压端口BUS2到第一负载端口N1的电流通路上，依然存在一个组合场效应管，即图8中的半导体开关Q1和Q4。电桥电路800避免了寄生二极管反向恢复特性差的问题的，并且缩减了需要的场效应管数量，还进一步减小了开关损耗。
在输出一个完整周期的电压的过程中，逆变器会经历501阶段、502阶段、503阶段和504阶段。上述四个阶段在一个完整周期内所持续的时间不同，其中501阶段和503阶段占据一个完整周期内的较长时间，而502阶段和504阶段占据一个完整周期内的较短时间。在501阶段，半导体开关Q2保持导通，半导体开关Q4保持断开，而半导体开关Q1和半导体开关Q3互补导通。而电流流过的方向为：在第一状态，从正直流源端口BUS1依次通过半导体开关Q1和半导体开关Q2到达第一负载端口N1；在第二状态，依次从第二负载端口N2通过二极管D3和半导体开关Q2到达第一负载端口N1。因此，电路在第一状态和第二状态之间不断切换，半导体开关管Q1所承受的导通损耗最大。同理，在503阶段，电路在第五状态和第六状态之间不断切换，半导体开关管Q4所承受的导通损耗最大。由于组合场效应管包括串联的高耐压场效应管和低耐压场效应管，在开关过程中，组合场效应管的导通损耗大于高耐压场效应管，导致能量的浪费。因此，将组合场效应管用作半导体开关Q2和Q3而普通的高耐压场效应管用作半导体开关Q1和Q4能进一步减少导通损耗。
需要注意的是，本发明所有实施例中给出的描述既没有限定电桥电路中组合场效应管的数量，也没有限定其所处的位置。实际上，半导体开关Q1和半导体开关Q2这两个开关中，如果至少有一个半导体开关为组合场效应管，从第一负载端口N1通往直流正直流源端口BUS1的电流就不会经过半导体开关Q1的寄生二极管或半导体开关Q2的寄生二极管。同样的，半导体开关Q3和半导体开关Q4也需要至少一个半导体开关为组合场效应管。
电桥电路300、电桥电路700和电桥电路800均可用于单相三电平逆变器电路、三相三电平逆变器电路，或更多相的三电平逆变器电路。其中，电桥电路300、电桥电路700和电桥电路800可以作为三相或多相三电平逆变器电路的一个电桥，其输出相当于三相或多相三电平逆变器电路中的其中一相电压的输出。
当本发明实施例的任意一种电桥电路用于其他三电平逆变器时，电桥电路的正直流电压端口BUS1与正直流电压源电连接，负直流电压端口BUS2与负直流电压源电连接，第一负载端口N1与第二负载端口N2分别与负载电路的两端连接，以获得正弦波/余弦波电压。
如图9所示，本发明实施例还提供了一种三相三电平逆变器900，在正直流电压端口BUS1延伸的正侧总线910和负直流电压端口BUS2延伸的负侧总线911之间分别并联电桥电路920、电桥电路921和电桥电路922，将每一个电桥中的第一负载端口作为该相位的输出点，即三相分别对应的输出端为931、932和933。电桥电路920、电桥电路921和电桥电路922可以是根据本发明实施例提供的任意一种电桥电路。正直流源端口BUS1和负直流源端口BUS2分别用于电连接正直流电压源和负直流电压源，以获得直流电压；输出端931、932和933可以分别电连接多个滤波电路410，以获得正弦波电压，其中每个滤波电路410的一端与输出端931、932和933电连接，另一端与电容941和电容942的电连接点形成电连接。串联的两个电容941和电容942的电容值可以相等，起到均衡直流侧电压的作用。由于电桥电路920、电桥电路921和电桥电路922采用了本发明实施例提供的电桥电路，每个电桥上的开关损耗得到了改善，同时规避寄生二极管反向恢复电流导致的开关速度受限、脉冲电流损坏开关等问题。
上述逆变器均可用于不间断电源(Uninterruptible Power Supply，UPS)系统。在典型负载的情况下，UPS中的逆变器主要工作在501和503阶段。由于采用组合场效应管代替现有技术中的IGBT或者高耐压MOSFET，使得UPS中的逆变器损耗更小，效率更高，成本更低，同时规避寄生二极管反向恢复电流导致的开关速度受限、脉冲电流损坏开关等问题。
本发明实施例中的电桥电路还可以用于整流器中。本发明实施例中的任意一种电桥电路，将第一负载端口和第二负载端口分别与交流电压源的两端电连接，则在正直流电压源BUS1和负直流电压源BUS2之间可以得到直流电压输出。
如图10所示，本发明实施例还提供了一种单相三电平整流器1000，以实现将交流电压转换为直流电压。单相三电平整流器1000包括电桥电路1010和交流输入电路1020，其中电桥电路1010可以为本发明实施例中任意一种电桥电路。交流输入电路1020包括串联的电感L和交流电压源AC。其中，交流输入电路1020的一端与第一负载端口N1电连接，另一端与第二负载端口N2电连接。正直流源端口BUS1和负直流源端口BUS2分别用于与负载电路的两端电连接，以获得直流电压输出。
本发明实施例中的任意一种电桥电路也可以用于其他整流器电路，例如三相三电平整流器，或更多相的三电平整流器。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种电桥电路，其特征在于，包括：
    第一直流源端口，用于电连接第一直流电压源的正极；
    第二直流源端口，用于电连接第二直流电压源的负极；
    第一负载端口，用于电连接负载电路的一端；
    第二负载端口，用于电连接所述负载电路的另一端，以及电连接所述第一直流电压源的负极和所述第二直流电压源的正极；
    第一开关，其中，所述第一开关的第一端与所述第一直流源端口电连接；
    第二开关，其中，所述第二开关的第一端与所述第一开关的第二端电连接，所述第二开关的第二端与所述第一负载端口电连接；
    第三开关，其中，所述第三开关的第一端与所述第二开关的第二端电连接；
    第四开关，其中，所述第四开关的第一端与所述第三开关的第二端电连接，所述第四开关的第二端与所述第二直流源端口电连接；
    其中，所述第一开关和所述第二开关中，一个开关为组合场效应管，另一个开关为组合场效应管或高耐压场效应管；所述第三开关和第四开关中，一个开关为组合场效应管，另一个开关为组合场效应管或高耐压场效应管；
    所述组合场效应管包括一个高耐压场效应管和一个低耐压场效应管，其中，所述高耐压场效应管与所述低耐压场效应管反向串联；
    第一二极管，其中，所述第一二极管的阳极电连接于所述第一负载端口，所述第一二极管的阴极电连接于所述第一开关的第一端；
    第二二极管，其中，所述第二二极管的阳极电连接于所述第四开关的第二端，所述第二二极管的阴极电连接于所述第一负载端口；
    第三二极管，其中，所述第三二极管的阳极电连接于所述第二负载端口，所述第三二极管的阴极电连接于所述第二开关的第一端；
    第四二极管，其中，所述第四二极管的阳极电连接于所述第四开关的第一端，第四二极管的阴极电连接于所述第二负载端口。
  2. 根据权利要求1所述的电桥电路，其特征在于，所述第一开关为组合场效应管，所述第二开关为组合场效应管，所述第三开关为组合场效应管，所述第四开关为组合场效应管。
  3. 根据权利要求1所述的电桥电路，其特征在于，所述第一开关为组合场效应管，所述第二开关为高耐压场效应管，所述第三开关为高耐压场效应管，所述第四开关为组合场效应管。
  4. 根据权利要求1所述的电桥电路，其特征在于，所述第一开关为高耐压场效应管，所述第二开关为组合场效应管，所述第三开关为组合场效应管，所述第四开关为高耐压场效应管。
  5. 根据权利要求1至4任意一项所述的电桥电路，其特征在于，所述高耐 压场效应管的耐受电压为60V～900V。
  6. 根据权利要求1至5任意一项所述的电桥电路，其特征在于，所述低耐压场效应管的耐受电压为20V～100V。
  7. 根据权利要求1至6任意一项所述的电桥电路，其特征在于，所述场效应晶体管为金属氧化物半导体场效应管。
  8. 一种单相三电平逆变器，其特征在于，包括：
    如权利要求1至7所述的任意一种电桥电路；
    第一直流电压源，其中，所述第一直流电压源的正极与所述电桥电路的所述第一直流源端口电连接，所述第一直流电压源的负极与所述第二负载端口电连接；
    第二直流电压源，其中，所述第二直流电压源的正极与所述第二负载端口电连接，所述第二直流电压源的负极与所述第二直流源端口电连接；
    滤波电路，其中所述滤波电路的一端电连接于所述第一负载端口，所述滤波电路的另一端电连接于所述第二负载端口。
  9. 一种多相三电平逆变器，其特征在于，包括：
    多个如权利要求1至7所述的任意一种电桥电路，以及与所述多个电桥电路一一对应的多个滤波电路；
    第一直流电压源，其中，所述第一直流电压源的正极与所述多个电桥电路的第一直流源端口电连接，所述第一直流电压源的负极与所述多个电桥电路的第二负载端口电连接；
    第二直流电压源，其中，所述第二直流电压源的正极与所述多个电桥电路的第二负载端口电连接，所述第二直流电压源的负极与所述多个电桥电路的第二直流源端口电连接；
    其中，所述多个所述滤波电路中每个滤波电路的一端电连接于对应的电桥电路的第一负载端口，所述每个滤波电路的另一端电连接于所述对应的电桥电路的第二负载端口。
  10. 一种电桥电路，其特征在于，包括：
    第一直流源端口和第二直流源端口，用于分别电连接负载电路的两端；
    第一负载端口，用于电连接交流电压源的一端；
    第二负载端口，用于电连接所述交流电压源的另一端，以及电连接第一二极管的阳极和第二二极管的阴极；
    第一开关，其中，所述第一开关的第一端与所述第一直流源端口电连接；
    第二开关，其中，所述第二开关的第一端与所述第一开关的第二端电连接，所述第二开关的第二端与所述第二负载端口电连接；
    第三开关，其中，所述第三开关的第一端与所述第二开关的第二端电连接；
    第四开关，其中，所述第四开关的第一端与所述第三开关的第二端电连接，所述第四开关的第二端与所述第二直流源端口电连接；
    其中，所述第一开关和所述第二开关中，一个开关为组合场效应管，另一个开关为组合场效应管或高耐压场效应管；所述第三开关和第四开关中，一个开关为组合场效应管，另一个开关为组合场效应管或高耐压场效应管；
    所述组合场效应管包括一个高耐压场效应管和一个低耐压场效应管，其中，所述高耐压场效应管与所述低耐压场效应管反向串联；
    所述第一二极管，其中，所述第一二极管的阳极电连接于所述第一负载端口，所述第一二极管的阴极电连接于所述第一开关的第一端；
    所述第二二极管，其中，所述第二二极管的阳极电连接于所述第四开关的第二端，所述第二二极管的阴极电连接于所述第一负载端口；
    第三二极管，其中，所述第三二极管的阳极电连接于所述第二负载端口，所述第三二极管的阴极电连接于所述第二开关的第一端；
    第四二极管，其中，所述第四二极管的阳极电连接于所述第四开关的第一端，第四二极管的阴极电连接于所述第二负载端口。
  11. 一种单相三电平整流器，其特征在于，包括：
    如权利要求10所述的一种电桥电路；
    交流电压源，其中，所述交流电压源的一端与所述第一负载端口电连接，所述交流电压源的另一端与所述第二负载端口电连接。
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