WO2019148470A1 - Circuit de protection et système de commande de puce logique programmable - Google Patents

Circuit de protection et système de commande de puce logique programmable Download PDF

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Publication number
WO2019148470A1
WO2019148470A1 PCT/CN2018/075173 CN2018075173W WO2019148470A1 WO 2019148470 A1 WO2019148470 A1 WO 2019148470A1 CN 2018075173 W CN2018075173 W CN 2018075173W WO 2019148470 A1 WO2019148470 A1 WO 2019148470A1
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WO
WIPO (PCT)
Prior art keywords
programmable logic
logic chip
protection circuit
feedback
chip
Prior art date
Application number
PCT/CN2018/075173
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English (en)
Chinese (zh)
Inventor
刘勇
Original Assignee
深圳配天智能技术研究院有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 深圳配天智能技术研究院有限公司 filed Critical 深圳配天智能技术研究院有限公司
Priority to PCT/CN2018/075173 priority Critical patent/WO2019148470A1/fr
Priority to CN201880002361.6A priority patent/CN109313427B/zh
Publication of WO2019148470A1 publication Critical patent/WO2019148470A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/054—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0428—Safety, monitoring
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1103—Special, intelligent I-O processor, also plc can only access via processor

Definitions

  • the present application relates to the technical field of industrial control, and relates to a protection circuit and a control system for a programmable logic chip.
  • the prior art control system 10 includes a central processing chip 101, a programmable logic chip 102, and a memory 103.
  • the central processing chip 101 is connected to the programmable logic chip 102 and the memory 103, respectively.
  • the central processing chip 101 is backed up to ensure that the control system 10 works normally.
  • the central processing chip 101 controls the programmable logic chip 102 to enter the load mode by a control signal to load the programmable logic chip 102 from the program read from the memory 103.
  • the control signal outputted by the central processing chip 101 becomes untestable, which may cause the programmable logic chip 102 to enter the loading mode after the program is loaded, so that the programmable logic chip 102 is disabled, so the control system The function of 10 is invalid.
  • the present application provides a protection circuit and a control system for a programmable logic chip.
  • the embodiment of the present application provides a protection circuit for a programmable logic chip, which is respectively connected to a central processing chip and a programmable logic chip, and an input end of the protection circuit is connected to an output end of the central processing chip for
  • the central processing chip receives the first control signal; the output end of the protection circuit is connected to the input end of the programmable logic chip; the control end of the protection circuit is connected to the feedback end of the programmable logic chip, wherein: when the programmable logic chip loads the program, The control end of the protection circuit receives the first feedback signal from the feedback end of the programmable logic chip, and the protection circuit sends the first control signal to the programmable logic chip according to the first feedback signal, and the programmable logic chip is centrally controlled according to the first control signal
  • the processing chip receives the program and loads the program; after the programmable logic chip loads the program, the control end of the protection circuit receives the second feedback signal from the feedback end of the programmable logic chip, and the protection circuit generates the
  • control system which at least includes:
  • Central processing chip connected to the memory
  • the input end of the protection circuit is connected to the output end of the central processing chip, and is configured to receive the first control signal from the central processing chip;
  • the output end of the protection circuit is connected to the input end of the programmable logic chip, and the control end of the protection circuit is connected to the feedback end of the programmable logic chip;
  • the control end of the protection circuit receives the first feedback signal from the feedback end of the programmable logic chip, and the protection circuit sends the first control signal to the programmable logic chip according to the first feedback signal, and is programmable.
  • the logic chip receives the program from the central processing chip according to the first control signal, and loads the program;
  • the control end of the protection circuit receives a second feedback signal from the feedback end of the programmable logic chip, and the protection circuit generates a second control signal according to the second feedback signal and the first control signal, and is programmable
  • the logic chip receives the second control signal and stops receiving the program according to the second control signal.
  • the protection circuit is respectively connected to the central processing chip and the programmable logic chip, and the input end of the protection circuit is connected to the output end of the central processing chip for receiving the first control signal from the central processing chip;
  • the output end is connected to the input end of the programmable logic chip;
  • the control end of the protection circuit is connected with the feedback end of the programmable logic chip; after the programmable logic chip loading process is completed, the control end of the protection circuit is from the feedback end of the programmable logic chip
  • Receiving a second feedback signal the protection circuit generates a second control signal according to the second feedback signal and the first control signal, and the programmable logic chip receives the second control signal, and stops receiving the program according to the second control signal, thereby avoiding central processing
  • the chip fails and causes the programmable logic chip to load the program again, thereby avoiding the failure of the entire control system and ensuring the safety of the operation.
  • Figure 1 is a schematic view of a frame of a prior art control system
  • FIG. 2 is a schematic diagram of a frame of a control system of a first embodiment of the present application
  • FIG. 3 is a circuit diagram of a protection circuit of a second embodiment of the present application.
  • FIG. 4 is a circuit diagram of a protection circuit of a third embodiment of the present application.
  • Figure 5 is a circuit diagram of a protection circuit of a fourth embodiment of the present application.
  • Fig. 6 is a circuit diagram of a protection circuit of a fifth embodiment of the present application.
  • FIG. 2 is a schematic diagram of a frame of a control system according to a first embodiment of the present application.
  • the protection circuit 21 disclosed in this embodiment is applied to the control system 20, and the protection circuit 21 is connected to the central processing chip 22 and the programmable logic chip 23 of the control system 20, respectively.
  • the control system 20 of the present application can be applied to an industrial robot for controlling an industrial robot; since the industrial robot needs to operate in a complicated electromagnetic environment, and the control system 20 is subjected to severe electromagnetic signal interference, the control system 20 may be caused.
  • the central processing chip 22 fails. Therefore, the present application protects the programmable logic chip 23 from other signals by setting the protection circuit 21 to avoid the failure of the programmable logic chip 23, thereby ensuring the safety of the operation.
  • the input end 211 of the protection circuit 21 is connected to the output end 221 of the central processing chip 22 for receiving the first control signal from the central processing chip 22; the output end 212 of the protection circuit 21 and the input end 231 of the programmable logic chip 23
  • the control terminal 213 of the protection circuit 21 is connected to the feedback terminal 232 of the programmable logic chip 23 for receiving a feedback signal from the programmable logic chip 23. Since the programmable logic chip 23 has no memory, the programmable logic chip 23 cannot save the program in the case of power failure, and the programmable logic chip 23 needs to load the program from the outside each time it is powered on.
  • the first output end 222 of the central processing chip 22 is connected to the first input end 233 of the programmable logic chip 23; after the control system 20 is powered on, the central processing chip 22 passes through the first output end 222 and the programmable logic chip 23 The first input 233 sends the program to the programmable logic chip 23, which loads the program.
  • the protection circuit 21 acquires the first control signal from the central processing chip 22 and acquires the first feedback signal from the programmable logic chip 23, and transmits the first control signal to the first feedback signal according to the first feedback signal.
  • the programming logic chip 23, the programmable logic chip 23 loads the program according to the first control signal, that is, after the first control signal is received at the input terminal 231 of the programmable logic chip 23, the central processing chip 22 passes through the first output terminal 222 and is programmable.
  • the first input 233 of the logic chip 23 sends the program to the programmable logic chip 23, which loads the program.
  • the first feedback signal is at a first level.
  • the protection circuit 21 acquires a second feedback signal from the programmable logic chip 23, and generates a second control signal according to the second feedback signal and the first control signal, the input of the programmable logic chip 23.
  • the terminal 231 receives the second control signal, and the programmable logic chip 23 controls the first input terminal 233 to stop receiving the program transmitted by the first output terminal 222 of the central processing chip 22 according to the second control signal.
  • the second feedback signal is at a second level.
  • Control system 20 further includes a memory 24 that is coupled to memory 24 for storing the above described programs.
  • the central processing chip 22 acquires the program from the memory 24.
  • the central processing chip 22 may further include an online upgrade port 223, and the online upgrade port 223 of the central processing chip 22 is connected to the server 25.
  • the central processing chip 22 can be upgraded from the server through the online upgrade port 223. 25 Acquire the online upgrade package of the program, the programmable logic chip 23 receives the online upgrade package from the central processing chip 22, and implements online upgrade of the program by the online upgrade package.
  • the input terminal 231 of the programmable logic chip 23 receives the second control signal from the protection circuit 21, and the programmable logic chip 23 controls the first input terminal 233 to stop according to the second control signal.
  • the program sent by the first output terminal 222 of the central processing chip 22 is received to avoid the program loading of the programmable logic chip 23 again due to the failure of the central processing chip 22, thereby avoiding the failure of the entire control system 20 and ensuring the safety of the operation.
  • the present application provides a protection circuit of the second embodiment, which is described on the basis of the protection circuit disclosed in the first embodiment.
  • the protection circuit 21 disclosed in this embodiment includes a first resistor R1 and an OR gate 35.
  • the first input terminal 351 of the OR gate 35 is an input terminal 211 of the protection circuit 21, or a second input of the gate 35.
  • the terminal 352 is the control terminal 213 of the protection circuit 21, and the output terminal 353 of the OR gate 35 is the output terminal 212 of the protection circuit 21.
  • the feedback terminal 232 of the programmable logic chip 23 is grounded through the first resistor R1, that is, one end of the first resistor R1 is respectively connected to the feedback terminal 232 of the programmable logic chip 23 and the second input terminal 352 of the OR gate 35, first The other end of the resistor R1 is grounded; the first input 351 of the OR gate 35 is connected to the output 221 of the central processing chip 22, and the output 353 of the OR gate 35 is connected to the input 231 of the programmable logic chip 23.
  • the feedback terminal 232 of the programmable logic chip 23 When the programmable logic chip 23 loads the program, the feedback terminal 232 of the programmable logic chip 23 is in a high impedance state, that is, the feedback terminal 232 of the programming logic chip 23 neither outputs a high level nor outputs a low level;
  • the feedback terminal 232 of the programming logic chip 23 is grounded through the first resistor R1, and the first feedback signal outputted by the feedback terminal 232 of the programmable logic chip 23 is at a low level;
  • the first control signal outputted by the output terminal 221 of the central processing chip 22 is Low level, the output terminal 353 of the OR gate 35 outputs a low level, that is, the protection circuit 21 sends the first control signal to the programmable logic chip 23 according to the first feedback signal, and the programmable logic chip 23 passes the first control signal according to the first control signal.
  • An input 233 receives the program from the central processing chip 22, and the programmable logic chip 23 loads the program.
  • the feedback terminal 232 of the programmable logic chip 23 outputs a high level, that is, the second feedback signal is at a high level, or the output terminal 353 of the gate 35 outputs a high level, that is, an OR gate.
  • the second control signal outputted by the output terminal 353 of the 35 is a high level; wherein the programmable logic chip 23 controls the first input terminal 233 to stop receiving the program sent by the first output terminal 222 of the central processing chip 22 according to the second control signal,
  • the program logic chip 23 is prevented from being loaded again due to the failure of the central processing chip 22, thereby avoiding the failure of the entire control system 20 and ensuring the safety of the operation.
  • the present application provides a protection circuit of the third embodiment, which is described on the basis of the protection circuit disclosed in the first embodiment.
  • the protection circuit 21 disclosed in this embodiment includes a first resistor R1, a first inverter 45, and a second inverter 46.
  • the input terminal 451 of the first inverter 45 is the protection circuit 21.
  • the input terminal 211, the enable terminal 453 of the first inverter 45 and the enable terminal 463 of the second inverter 46 are the control terminal 213 of the protection circuit 21, and the output terminal 462 of the second inverter 46 is the protection circuit 21.
  • Output 212 is the protection circuit 21.
  • the input end 451 of the first inverter 45 is connected to the output end 221 of the central processing chip 22, and the output end 452 of the first inverter 45 is connected to the input end 461 of the second inverter 46.
  • the output 462 of the processor 46 is connected to the input terminal 231 of the programmable logic chip 23, and the enable terminal 453 of the first inverter 45 and the enable terminal 463 of the second inverter 46 are both fed back to the programmable logic chip 23.
  • the terminal 232 is connected.
  • One end of the first resistor R1 is connected to the feedback terminal 232 of the programmable logic chip 23, and the other end of the first resistor R1 is grounded.
  • the feedback terminal 232 of the programmable logic chip 23 When the programmable logic chip 23 loads the program, the feedback terminal 232 of the programmable logic chip 23 is in a high impedance state, that is, the feedback terminal 232 of the programming logic chip 23 neither outputs a high level nor outputs a low level;
  • the feedback terminal 232 of the programming logic chip 23 is grounded through the first resistor R1, and the first feedback signal outputted by the feedback terminal 232 of the programmable logic chip 23 is at a low level, and the first inverter 45 and the second inverter 46 operate;
  • the first control signal outputted by the output terminal 221 of the central processing chip 22 is at a low level, the output terminal 452 of the first inverter 45 outputs a high level, and the output terminal 462 of the second inverter 46 outputs a low level.
  • the protection circuit 21 sends the first control signal to the programmable logic chip 23 according to the first feedback signal, and the programmable logic chip 23 receives the program from the central processing chip 22 through the first input terminal 233 according to the first control signal, the programmable logic. Chip 23 loads the program.
  • the feedback terminal 232 of the programmable logic chip 23 outputs a high level, that is, the second feedback signal is at a high level, and the first inverter 45 and the second inverter 46 at this time.
  • the input terminal 231 of the programmable logic chip 23 is suspended, that is, the second control signal is at a high level; the programmable logic chip 23 controls the first input terminal 233 to stop receiving the first output of the central processing chip 22 according to the second control signal.
  • the program sent by the terminal 222 prevents the programmable logic chip 23 from loading the program again due to the failure of the central processing chip 22, thereby avoiding the failure of the entire control system 20 and ensuring the safety of the operation.
  • the present application provides a protection circuit of the fourth embodiment, which is described on the basis of the protection circuit disclosed in the first embodiment.
  • the protection circuit 21 disclosed in this embodiment includes a first resistor R1, a second resistor R2, and a switch tube 55.
  • the second end 552 of the switch tube 55 is an input end 211 of the protection circuit 21, and the switch tube 55
  • the third end 553 is the control end 213 of the protection circuit 21, and the first end 551 of the switch tube 55 is the output end 212 of the protection circuit 21.
  • the second end 552 of the switch tube 55 is connected to the output end 221 of the central processing chip 22, the third end 553 of the switch tube 55 is connected to the feedback end 232 of the programmable logic chip 23, and the first end of the second resistor R2 receives the first end.
  • the other end of the second resistor R2 is connected to the first end 551 of the switch 55 and the input end 231 of the programmable logic chip 23; one end of the first resistor R1 is connected to the feedback end 232 of the programmable logic chip 23, The other end of the first resistor R1 is grounded.
  • the switch tube 55 of this embodiment may be a PNP type transistor, wherein the first end 551 of the switch tube 55 is the emitter of the triode, the second end 552 of the switch tube 55 is the base of the triode, and the third end 553 of the switch tube 55 It is the collector of the triode.
  • the switch tube 55 can be other types of switch tubes, for example, the switch tube 55 can be a MOS tube.
  • the feedback terminal 232 of the programmable logic chip 23 When the programmable logic chip 23 loads the program, the feedback terminal 232 of the programmable logic chip 23 is in a high impedance state, that is, the feedback terminal 232 of the programmable logic chip 23 neither outputs a high level nor outputs a low level;
  • the feedback terminal 232 of the programmable logic chip 23 is grounded through the first resistor R1, the first feedback signal outputted by the feedback terminal 232 of the programmable logic chip 23 is at a low level, and the first control signal outputted by the output terminal 221 of the central processing chip 22 is When it is low, when the switch 55 is turned on, the voltage of the output of the protection circuit 21 satisfies the following formula:
  • V1 (VCC-V CE )*R1/(R1+R2)
  • V CE is the turn-on voltage of the switch 55.
  • the output terminal 212 of the protection circuit 21 outputs a low level, so the protection circuit 21 sends the first control signal to the programmable according to the first feedback signal.
  • the logic chip 23, the programmable logic chip 23 receives the program from the central processing chip 22 through the first input terminal 233 according to the first control signal, and the programmable logic chip 23 loads the program.
  • the feedback terminal 232 of the programmable logic chip 23 outputs a high level, that is, the second feedback signal is at a high level; at this time, the switch tube 55 is turned off, that is, the switch tube 55 stops working, and the protection is performed.
  • the output of the output terminal 212 of the circuit 21 is VCC, that is, the second control signal is at a high level; the programmable logic chip 23 controls the first input terminal 233 to stop receiving the first output terminal 222 of the central processing chip 22 according to the second control signal.
  • the program is sent to prevent the programmable logic chip 23 from loading the program again due to the failure of the central processing chip 22, thereby avoiding the failure of the entire control system 20 and ensuring the safety of the operation.
  • the present application provides a protection circuit of a fifth embodiment, which is described on the basis of the protection circuit disclosed in the first embodiment.
  • the protection circuit 21 disclosed in this embodiment includes a first resistor R1, an opto-isolator 65, a second resistor R2, and a third resistor R3.
  • the opto-isolator 65 includes a light-emitting diode 651 and a light receiver 652.
  • the negative terminal of the diode 651 is the input end 211 of the protection circuit 21
  • the second end 654 of the photoreceiver 652 is the control end 213 of the protection circuit 21
  • the first end 653 of the photoreceiver 652 is the output end 212 of the protection circuit 21.
  • the anode of the light-emitting diode 651 is connected to one end of the second resistor R2, the other end of the second resistor R2 receives the first reference voltage VCC1, and the cathode of the LED 651 is connected to the output end 221 of the central processing chip 22;
  • the first end 653 is connected to one end of the third resistor R3 and the input end 231 of the programmable logic chip 23, and the other end of the third resistor R3 receives the second reference voltage VCC2, and the second end 654 of the photoreceiver 652 and the programmable logic
  • the feedback terminal 232 of the chip 23 is connected; one end of the first resistor R1 is connected to the feedback terminal 232 of the programmable logic chip 23, and the other end of the first resistor R1 is grounded.
  • the feedback terminal 232 of the programmable logic chip 23 can neither output a high level nor output a low level;
  • the feedback terminal 232 of the programmable logic chip 23 is grounded through the first resistor R1, and the first feedback signal output from the feedback terminal 232 of the programmable logic chip 23 is at a low level.
  • the first control signal outputted from the output terminal 221 of the central processing chip 22 is at a low level, the LED 651 emits light, and the photodetector 652 is turned on, and the voltage output from the protection circuit 21 satisfies the following formula:
  • V1 (VCC2-V CE )*R1/(R1+R3)
  • V CE is the turn-on voltage of the photodetector 652.
  • the resistance of the first resistor R1 and the resistance of the third resistor R3 are set such that the output 212 of the protection circuit 21 outputs a low level, so the protection circuit 21 sends the first control signal to the programmable logic according to the first feedback signal.
  • the chip 23, the programmable logic chip 23 receives the program from the first output terminal 222 of the central processing chip 22 through the first input terminal 233 according to the first control signal, and the programmable logic chip 23 loads the program.
  • the feedback terminal 232 of the programmable logic chip 23 outputs a high level, that is, the second feedback signal is at a high level; the first control signal outputted at the output terminal 221 of the central processing chip 22 When the level is low, the LED 651 emits light, the photodetector 652 is turned on, and the second control signal is equal to the second feedback signal, that is, the second control signal is at a high level; if the output end 221 of the central processing chip 22 outputs the first When the control signal is at a high level, the LED 651 does not emit light, the photodetector 652 is turned off, the second control signal is the first reference voltage VCC, that is, the second control signal is at a high level; and the programmable logic chip 23 is according to the second control signal.
  • the first input terminal 233 is controlled to stop receiving the program sent by the first output terminal 222 of the central processing chip 22, so as to prevent the programmable logic chip 23 from loading the program again due to the failure of the central processing chip 22, thereby avoiding the failure of the entire control system 20 and ensuring the operation. Safety.
  • the present application further provides a control system.
  • the control system 20 disclosed in this embodiment includes a memory 24, a central processing chip 22, a protection circuit 21, and a programmable logic chip 23, wherein the central processing chip 22 and the memory 24, the protection circuit 21 is connected to the central processing chip 22 and the programmable logic chip 23 respectively.
  • the protection circuit 21 is the protection circuit of the above embodiment, and details are not described herein again.
  • the protection circuit of the present application is respectively connected to the central processing chip and the programmable logic chip, and the input end of the protection circuit is connected to the output end of the central processing chip for receiving the first control signal from the central processing chip;
  • the output end is connected to the input end of the programmable logic chip;
  • the control end of the protection circuit is connected with the feedback end of the programmable logic chip; after the programmable logic chip loading process is completed, the control end of the protection circuit is from the feedback end of the programmable logic chip
  • Receiving a second feedback signal the protection circuit generates a second control signal according to the second feedback signal and the first control signal
  • the programmable logic chip receives the second control signal, and stops receiving the program sent by the central processing chip according to the second control signal To avoid the failure of the central processing chip to cause the programmable logic chip to load the program again, thereby avoiding the failure of the entire control system and ensuring the safety of the operation.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne un système de commande et un circuit de protection de celui-ci, une borne d'entrée du circuit de protection étant connectée à une borne de sortie d'une puce de traitement centrale; une borne de sortie du circuit de protection étant connectée à une borne d'entrée d'une puce logique programmable; une borne de commande du circuit de protection étant connectée à une borne de rétroaction de la puce logique programmable; après que la puce logique programmable a terminé de charger un programme, la borne de commande du circuit de protection reçoit un deuxième signal de rétroaction provenant de la borne de rétroaction de la puce logique programmable, le circuit de protection produit un deuxième signal de commande selon le deuxième signal de rétroaction et un premier signal de commande, et la puce logique programmable reçoit le deuxième signal de commande et arrête de recevoir le programme selon le deuxième signal de commande. La présente invention est capable d'empêcher une puce logique programmable de recharger un programme à cause de la défaillance d'une puce de traitement centrale, ce qui empêche la défaillance d'un système de commande entier et permet d'assurer la sécurité de l'opération.
PCT/CN2018/075173 2018-02-02 2018-02-02 Circuit de protection et système de commande de puce logique programmable WO2019148470A1 (fr)

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PCT/CN2018/075173 WO2019148470A1 (fr) 2018-02-02 2018-02-02 Circuit de protection et système de commande de puce logique programmable
CN201880002361.6A CN109313427B (zh) 2018-02-02 2018-02-02 一种可编程逻辑芯片的保护电路及控制系统

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PCT/CN2018/075173 WO2019148470A1 (fr) 2018-02-02 2018-02-02 Circuit de protection et système de commande de puce logique programmable

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