WO2019142394A1 - Élément de suppression de tension transitoire - Google Patents

Élément de suppression de tension transitoire Download PDF

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Publication number
WO2019142394A1
WO2019142394A1 PCT/JP2018/034132 JP2018034132W WO2019142394A1 WO 2019142394 A1 WO2019142394 A1 WO 2019142394A1 JP 2018034132 W JP2018034132 W JP 2018034132W WO 2019142394 A1 WO2019142394 A1 WO 2019142394A1
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Prior art keywords
transient voltage
voltage suppression
external connection
suppression circuit
connection terminal
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PCT/JP2018/034132
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English (en)
Japanese (ja)
Inventor
紀行 植木
Original Assignee
株式会社村田製作所
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Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN201890000306.9U priority Critical patent/CN209766397U/zh
Priority to JP2019502264A priority patent/JP6516080B1/ja
Publication of WO2019142394A1 publication Critical patent/WO2019142394A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

Definitions

  • the present invention relates to a transient voltage suppression element that protects an electronic circuit from a transient voltage due to electrostatic discharge or the like.
  • Patent Document 1 discloses a bidirectional transient voltage suppression element having two external connection terminals.
  • the transient voltage suppression device described in Patent Document 1 has a semiconductor substrate on which a transient voltage suppression circuit portion, a wiring portion, and an external connection terminal are formed, and the external connection terminals are respectively arranged along two opposing sides of the semiconductor substrate. It is a transient voltage suppression element of CSP type (Chip Size Package) formed.
  • CSP type Chip Size Package
  • a transient voltage suppression circuit portion is formed between two external connection terminals in a plan view of a semiconductor substrate.
  • the CSP type transient voltage suppression element can not make the semiconductor substrate smaller than the total area of the external connection terminals. That is, the semiconductor substrate needs to be at least larger than the total area of the external connection terminals.
  • a low-capacitance transient voltage suppression element having a capacitance between terminals of, for example, 0.5 pF or less is formed of a CSP type
  • the transient voltage suppression circuit portion is formed in a very small area on the semiconductor substrate. That is, the transient voltage suppression circuit portion is formed in a relatively small area relatively to the area of the semiconductor substrate.
  • an object of the present invention is to provide a transient voltage suppression element capable of forming various transient voltage suppression elements having different transient voltage suppression characteristics and high frequency characteristics at low cost by effectively using the area of a semiconductor substrate. It is.
  • the transient voltage suppression device of the present invention has a semiconductor substrate on which the transient voltage suppression circuit portion, the wiring portion and the external connection terminal are formed, and the transient voltage suppression circuit portion and the wiring portion constitute a transient voltage suppression circuit Transient voltage suppression element.
  • the external connection terminals are three or more terminals disposed along the main surface of the semiconductor substrate.
  • the transient voltage suppression circuit unit has a plurality of first transient voltage suppression circuit units each having a series connection circuit of a zener diode and a first diode, and a plurality of second transient voltage suppression circuit units each having a second diode. .
  • the plurality of first transient voltage suppression circuit portions sandwich at least one second transient voltage suppression circuit portion among the plurality of second transient voltage suppression circuit portions in plan view in a direction perpendicular to the main surface of the semiconductor substrate. And a plurality of first transient voltage suppression circuits and a plurality of first transient voltage suppression circuits such that the plurality of second transient voltage suppression circuits sandwich at least one of the plurality of first transient voltage suppression circuits.
  • a second transient voltage suppression circuit unit is disposed. Further, at least a portion of the plurality of first transient voltage suppression circuit portions are symmetrically arranged in plan view in a direction perpendicular to the main surface of the semiconductor substrate, and at least a portion of the plurality of second transient voltage suppression circuit portions Are arranged symmetrically.
  • a plurality of channels of transient voltage suppression circuit units can be configured.
  • transient voltage suppression elements having different transient voltage suppression characteristics or high frequency characteristics Can be configured.
  • the wiring portion can be made symmetrical, the influence of the parasitic component (parasitic inductance or parasitic capacitance) of the wiring portion can be equalized between the external connection terminals or between the channels. Therefore, even if the orientations of the external connection terminals in the mounted state on the circuit board are different, the high frequency characteristics can be equalized. In addition, when transient voltage suppression circuits for a plurality of channels are formed, high frequency characteristics can be equalized between the channels.
  • At least a portion of the plurality of first transient voltage suppression circuit portions are disposed in line symmetry with respect to the reference line in plan view from a direction perpendicular to the main surface of the semiconductor substrate, and second transient voltage suppression At least a part of the circuit portion is disposed in line symmetry with respect to the reference line, and at least one of the external connection terminals is disposed on the reference line of the above-mentioned symmetrical arrangement as viewed from a direction perpendicular to the main surface of the semiconductor substrate. Is preferred.
  • the external connection terminals provided on the reference line be directly connected to the ground. According to this structure, since the external connection terminal connected to the ground which is the common conductor is disposed at the center of the transient voltage suppression element, the plurality of transient voltage suppression circuit portions can be easily arranged symmetrically.
  • the plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units are preferably formed such that current paths are generated in a direction perpendicular to the main surface of the semiconductor substrate. According to this structure, the planar areas of the first transient voltage suppression circuit unit and the second transient voltage suppression circuit unit can be reduced, respectively, and a large number of first transient voltage suppression circuit units and the second transient voltage suppression circuit unit can be formed within a limited area of the semiconductor substrate.
  • a transient voltage suppression circuit can be arranged.
  • the plurality of first transient voltage suppression circuit units are disposed respectively at the four vertices of the square and inside the square, and the plurality of second transient voltage suppression circuit units are adjacent among the four vertices. Preferably, they are respectively disposed between the vertices. According to this structure, since the plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units are disposed close to each other, the plurality of first transient voltages are not drawn long in the wiring portion of the wiring portion.
  • a transient voltage suppression circuit unit including the suppression circuit unit and the plurality of second transient voltage suppression circuit units can be configured.
  • the semiconductor substrate has a first side and a second side facing each other, and the external connection terminal has a first external connection terminal, a second external connection terminal, and a third external connection terminal.
  • the external connection terminal is disposed in the vicinity of the first side of the semiconductor substrate, and the second external connection terminal is disposed in the vicinity of the second side of the semiconductor substrate, and between the first external connection terminal and the second external connection terminal A third external connection terminal is arranged.
  • the first external connection terminal and the second external connection terminal are connected through the wiring portion, and between the first external connection terminal and the third external connection terminal, and the second external connection terminal and the third external connection terminal Between and transient voltage suppression circuits are respectively connected.
  • the first external connection terminal and the second external connection terminal are respectively connected to the signal line, and the third external connection terminal is connected to the ground.
  • the signal line is connected across the ground on the circuit board, and a transient voltage suppression circuit is connected between the signal line and the ground.
  • the semiconductor substrate has the first side and the second side facing each other, and the external connection terminal has the first external connection terminal, the second external connection terminal, and the third external connection terminal, and the first The external connection terminal is disposed in the vicinity of the first side of the semiconductor substrate, and the second external connection terminal is disposed in the vicinity of the second side of the semiconductor substrate, and the first external connection terminal is disposed between the first external connection terminal and the second external connection terminal.
  • the transient voltage suppression circuit includes a first transient voltage suppression circuit and a second transient voltage suppression circuit. A first transient voltage suppression circuit is connected between the first external connection terminal and the third external connection terminal, and a second transient voltage suppression circuit is connected between the second external connection terminal and the third external connection terminal. Is connected.
  • the first external connection terminal is connected to the first signal line
  • the second external connection terminal is connected to the second signal line
  • the third external connection terminal is connected to the ground.
  • the transient voltage suppression circuit is connected between the two signal lines and the ground across the ground on the circuit board.
  • At least one first transient voltage suppression circuit unit may not be connected to the external connection terminal.
  • the number of channels of the transient voltage suppression circuit can be set by selectively using the necessary first transient voltage suppression circuit unit. Further, various transient voltage suppression elements having different transient voltage suppression characteristics and high frequency characteristics can be commercialized at low cost.
  • At least one second transient voltage suppression circuit unit may not be connected to the external connection terminal. Also according to this structure, the number of channels of the transient voltage suppression circuit can be set by selectively using the necessary second transient voltage suppression circuit unit. Further, various transient voltage suppression elements having different transient voltage suppression characteristics and high frequency characteristics can be commercialized at low cost.
  • transient voltage suppression element capable of commercializing various kinds of transient voltage suppression elements having different transient voltage suppression characteristics and high frequency characteristics at low cost by effectively utilizing the area of the semiconductor substrate.
  • FIG. 1 is a plan view showing a transient voltage suppression circuit portion of the transient voltage suppression element according to the first embodiment.
  • FIG. 2 (A) is a plan view showing the structure of the first transient voltage suppression circuit
  • FIG. 2 (B) is a cross-sectional view thereof
  • FIG. 2 (C) is a circuit diagram thereof.
  • FIG. 3A is a plan view showing the structure of the second transient voltage suppression circuit
  • FIG. 3B is a cross-sectional view thereof
  • FIG. 3C is a circuit diagram thereof.
  • FIG. 4 is a plan view showing a configuration of a first wiring portion for connecting in parallel the first transient voltage suppression circuit portion and the second transient voltage suppression circuit portion.
  • FIG. 5 is a partial cross-sectional view at a position passing through the first transient voltage suppression circuit unit SC10 and the second transient voltage suppression circuit unit SC2141.
  • 6 (A), 6 (B), 6 (C), 6 (D), 6 (E), 6 (F) and 6 (G) show the semiconductor substrate of the transient voltage suppression element. It is a top view which shows each pattern in upper each layer.
  • FIG. 7 is a cross-sectional view of the transient voltage suppression element at a predetermined position.
  • FIG. 8 is a circuit diagram of the transient voltage suppressing element of the first embodiment.
  • FIG. 9 is a diagram showing the mounting state of the transient voltage suppression element 101 on the circuit board.
  • FIG. 10C are diagrams showing a transient voltage suppression element 101 as a comparative example of the second embodiment.
  • FIG. 11A, FIG. 11B, and FIG. 11C are diagrams showing the transient voltage suppression element 102 according to the second embodiment.
  • FIG. 12 is a view showing a mounting state on a circuit board in the case of applying two transient voltage suppression elements 102 to a differential line.
  • FIG. 13A is a plan view showing a pattern of a first wiring portion connecting a plurality of transient voltage suppression elements in the transient voltage suppression element 103 of the third embodiment.
  • FIG. 13B is a circuit diagram of the transient voltage suppression element 103 according to the third embodiment.
  • FIG. 14 is a plan view showing a first wiring portion configuration of the transient voltage suppression element 104 according to the fourth embodiment.
  • FIG. 16 is a circuit diagram of the transient voltage suppression element 104. As shown in FIG. FIG. 17 is a diagram showing the mounting state of the transient voltage suppression element 104 on the circuit board.
  • FIG. 18 is a plan view showing the shape and the arrangement of a plurality of transient voltage suppression circuits of the transient voltage suppression element according to the fifth embodiment.
  • FIG. 1 is a plan view showing a transient voltage suppression circuit portion of the transient voltage suppression element according to the first embodiment.
  • portions denoted by reference numerals starting with “SC” are transient voltage suppression circuits.
  • a plurality of transient voltage suppression circuit parts are formed on the semiconductor substrate 1.
  • Wiring portions and external connection terminals are formed on the semiconductor substrate 1 in addition to the transient voltage suppression circuit portion, which will be described later.
  • portions marked with a code beginning with “SC1” are first transient voltage suppression circuit units, and portions marked with a symbol starting with “SC2” are second transient voltage suppression circuit units.
  • the first transient voltage suppression circuit unit has a series connection circuit of a Zener diode and a first diode.
  • the second transient voltage suppression circuit unit is formed of a second diode.
  • the first transient voltage suppression circuit portions SC11, SC12, SC13, and SC14 connect these four first transient voltage suppression circuit portions.
  • the first transient voltage suppression circuit unit SC10 is disposed inside the virtual quadrangle (preferably, the center of the quadrangle) which can In this arrangement relationship, a first straight line passing through the first transient voltage suppression circuit units SC11 and SC13 and a second straight line passing through the first transient voltage suppression circuit units SC12 and SC14 form an intersection point, or this intersection point or In other words, the first transient voltage suppression circuit unit SC10 is disposed in the vicinity of the intersection point.
  • the first transient voltage suppression circuit unit SC10 has a doubled area in a plan view from the direction perpendicular to the main surface of the semiconductor substrate 1 as compared with the first transient voltage suppression circuit units SC11, SC12, SC13, and SC14. .
  • the transient voltage suppression element of the present embodiment has a portion where the first transient voltage suppression circuit portion sandwiches the second transient voltage suppression circuit portion in plan view in a direction perpendicular to the main surface of the semiconductor substrate 1, and the second There is a place where the transient voltage suppression circuit part sandwiches the first transient voltage suppression circuit part.
  • the plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units are disposed. Specifically, it is as follows.
  • the second transient voltage suppression circuit units SC211, SC212, SC221, and SC222 are sandwiched between the first transient voltage suppression circuit unit SC11 and the first transient voltage suppression circuit unit SC12.
  • the second transient voltage suppression circuit units SC231, SC232, SC241, and SC242 are sandwiched between the first transient voltage suppression circuit unit SC13 and the first transient voltage suppression circuit unit SC14.
  • the second transient voltage suppression circuit units SC2141 and SC2142 are sandwiched between the first transient voltage suppression circuit unit SC11 and the first transient voltage suppression circuit unit SC14.
  • the second transient voltage suppression circuit units SC2231 and SC2232 are sandwiched between the first transient voltage suppression circuit unit SC12 and the first transient voltage suppression circuit unit SC13.
  • first transient voltage suppression circuit unit SC10 is sandwiched between the second transient voltage suppression circuit units SC211 and SC221 and the second transient voltage suppression circuit units SC231 and SC241. Further, the first transient voltage suppression circuit unit SC10 is sandwiched between the second transient voltage suppression circuit unit SC2141 and the second transient voltage suppression circuit unit SC2231.
  • the first straight line passing through the first transient voltage suppression circuit units SC11 and SC13 and the second straight line passing through the first transient voltage suppression circuit units SC12 and SC14 make the region on the semiconductor substrate 1 four.
  • the positional relationship between the first transient voltage suppression circuit unit and the second transient voltage suppression circuit unit described above is dispersedly arranged in such a manner that the first transient voltage suppression circuit unit and the second transient voltage suppression circuit unit are interpolated with each other. It can also be said that
  • the first transient voltage suppression circuit portion is symmetrically disposed in plan view in a direction perpendicular to the main surface of the semiconductor substrate 1, and the second transient voltage suppression circuit portion is symmetrically disposed. It is done. Specifically, it is as follows.
  • the first transient voltage suppression circuit units SC11 and SC12 are arranged in line symmetry with respect to the reference line SLY.
  • the first transient voltage suppression circuit units SC13 and SC14 are disposed in line symmetry with respect to the reference line SLY.
  • the first transient voltage suppression circuit units SC11 and SC14 are disposed in line symmetry with respect to the reference line SLX.
  • the first transient voltage suppression circuit units SC12 and SC13 are disposed in line symmetry with respect to the reference line SLX.
  • the second transient voltage suppression circuit units SC211, SC212, SC213, SC241, SC242, SC243, SC2141, SC2142 and the second transient voltage suppression circuit units SC221, SC222, SC223, SC231, SC232, SC233, SC2231, SC2232 , And are arranged symmetrically with respect to the reference line SLY.
  • the second transient voltage suppression circuit units SC211, SC212, SC213, SC221, SC222, SC223 and the second transient voltage suppression circuit units SC241, SC242, SC243, SC231, SC232, SC233 with respect to the reference line SLX. It is arranged in line symmetry.
  • the reference lines SLY and SLX are straight lines passing through the centers of the plurality of transient voltage suppression circuit area formation regions.
  • all the first transient voltage suppression circuit parts and all the second transient voltage suppression circuit parts are symmetrically arranged in a plan view from the direction perpendicular to the main surface of semiconductor substrate 1.
  • at least a part of the first transient voltage suppression circuit unit may be arranged symmetrically.
  • at least a part of the second transient voltage suppression circuit unit may be arranged symmetrically.
  • the first meaning of “at least a part is symmetrical arrangement” is that "a part of circuit parts (for example, eight) among a plurality of transient voltage suppression circuit parts (for example, ten) are arranged symmetrically. It is Further, the second meaning of the “at least partially symmetrical arrangement” is “a pair of transient voltage suppression circuit units (one transient voltage suppression circuit unit and another transient voltage suppression circuit unit forming a pair) "Includes symmetrical parts and non-symmetrical parts”.
  • symmetrical arrangement does not necessarily mean that they are arranged symmetrically in a strict sense. For example, when the first transient voltage suppression circuit unit SC11 is moved to a position that is line symmetrical with respect to the reference line SLY in plan view in a direction perpendicular to the main surface of the semiconductor substrate 1, SC12 partially overlaps It can be said that the first transient voltage suppression circuit unit SC11 and the first transient voltage suppression circuit unit SC12 are symmetrically disposed even in the arrangement relationship that matches each other.
  • symmetrically arranged may mean not only an arrangement relation that is line-symmetrical to a reference line such as the reference lines SLY and SLX, but also an arrangement relation that is point-symmetrical to a reference point.
  • a reference line such as the reference lines SLY and SLX
  • point-symmetrical may mean not only an arrangement relation that is point-symmetrical to a reference point.
  • the first transient voltage suppression circuit unit SC11 and the first transient voltage suppression circuit unit SC13 have a point symmetry relationship.
  • the first transient voltage suppression circuit unit SC12 and the first transient voltage suppression circuit unit SC14 are in a point-symmetrical relationship.
  • symmetrically arranged may mean not only an arrangement relation that is point symmetrical with respect to a reference point, but also a relation of rotational symmetry with the reference point as a rotation center.
  • the relationship between the first transient voltage suppression circuit SC11 and the first transient voltage suppression circuit SC12 is approximately 90 degrees rotational symmetric. It is in.
  • the first transient voltage suppression circuit unit SC11 and the first transient voltage suppression circuit unit SC14 are in a relationship of about 90 degrees rotational symmetry.
  • first transient voltage suppression circuit unit SC13 and the first transient voltage suppression circuit unit SC14 are in a relationship of about 90 degrees rotational symmetry.
  • first transient voltage suppression circuit unit SC13 and the first transient voltage suppression circuit unit SC12 are in a relationship of about 90 degrees rotational symmetry.
  • FIG. 2 (A) is a plan view showing the structure of the first transient voltage suppression circuit
  • FIG. 2 (B) is a cross-sectional view thereof
  • FIG. 2 (C) is a circuit diagram thereof.
  • N-type epitaxial layers N-EPI1 and N-EPI2 are formed on the surface of the Si-P-type semiconductor substrate 1, and an N-type region is formed in the N-type epitaxial layer N-EPI1.
  • the P-type region is formed in the N-type epitaxial layer N-EPI2.
  • a first N-type epitaxial layer N-EPI1 is formed on the surface of a P-type semiconductor substrate, an N-type diffusion region is formed in this layer, and then a second N-type epitaxial layer N is formed.
  • the film is formed in a process of forming an EPI 2 film and forming a P-type diffusion region in this layer.
  • a Zener diode ZD is formed by (at the interface with) the P-type semiconductor substrate 1 and the N-type diffusion region, and the second N-type epitaxial layer N-EPI2 and the P-type diffusion region
  • a first diode HSD is formed at the interface between the epitaxial layer N-EPI2 and the P-type diffusion region.
  • the first transient voltage suppression circuit unit is configured by a series connection circuit of the Zener diode ZD and the first diode HSD. Further, the first transient voltage suppression circuit portion is formed such that a current path is generated in a direction perpendicular to the main surface of the semiconductor substrate. The periphery of the first transient voltage suppression circuit portion is isolated from other regions by a trench TR.
  • FIG. 3A is a plan view showing the structure of the second transient voltage suppression circuit
  • FIG. 3B is a cross-sectional view thereof
  • FIG. 3C is a circuit diagram thereof.
  • N-type epitaxial layers N-EPI1 and N-EPI2 are formed on the surface of P-type semiconductor substrate 1, and an N-type region is formed in N-type epitaxial layer N-EPI2. .
  • a first N-type epitaxial layer N-EPI1 is formed on the surface of the P-type semiconductor substrate 1, and then a second N-type epitaxial layer N-EPI2 is formed.
  • An N-type diffusion region is formed in the N-type epitaxial layer N-EPI2 of FIG.
  • the P-type semiconductor substrate 1 and the N-type epitaxial layer N-EPI 1 form (at the interface thereof) a second diode LSD.
  • the second transient voltage suppression circuit unit is configured of the second diode LSD. Further, the second transient voltage suppression circuit portion is formed such that a current path is generated in a direction perpendicular to the main surface of the semiconductor substrate. The periphery of the second transient voltage suppression circuit portion is isolated from other regions by a trench TR.
  • the “Zener diode” is a diode that applies a reverse bias voltage to the PN junction region to utilize the Zener effect.
  • the “first diode” and the “second diode” are diodes that apply a forward bias or reverse bias voltage to the PN junction region to utilize its rectifying function.
  • FIG. 4 is a plan view showing a configuration of a first wiring portion for connecting in parallel the first transient voltage suppression circuit portion and the second transient voltage suppression circuit portion.
  • FIG. 5 is a partial cross-sectional view at a position passing through the first transient voltage suppression circuit unit SC10 and the second transient voltage suppression circuit unit SC2141 (a position indicated by a dashed dotted line in FIG. 4).
  • the anode of the first diode of the first transient voltage suppression circuit unit SC10 and the cathode of the second diode of the second transient voltage suppression circuit unit SC2141 and SC2231 are connected by the first wiring unit WP10. Further, the anode of the first diode of the first transient voltage suppression circuit unit SC12 and the cathode of the second diode of the second transient voltage suppression circuit unit SC221 are connected by the first wiring unit WP11. Similarly, the anode of the first diode of the first transient voltage suppression circuit unit SC14 and the cathode of the second diode of the second transient voltage suppression circuit unit SC241 are connected by the first wiring unit WP12.
  • the first wiring parts WP10, WP11, WP12 are point-symmetrical shapes (180-degree rotational symmetry) centered on the centers of the plurality of transient voltage suppression circuit part formation regions.
  • a pair of parallel connection circuits of one first transient voltage suppression circuit unit and two second transient voltage suppression circuit units, one first transient voltage suppression circuit unit, and one second transient voltage suppression circuit Two sets of parallel connection circuits with the unit are configured.
  • FIG. 7 schematically shows a cross-sectional view of the transient voltage suppression element at a predetermined position. In more detail, it is as follows.
  • first transient voltage suppression circuit units including first transient voltage suppression circuit units SC10, SC12, and SC14, and second transient voltage suppression circuit units SC221, SC241, SC2141, and the like in the semiconductor substrate 1 are shown.
  • the state which formed several 2nd transient voltage suppression circuit parts containing SC2231 is shown.
  • one of these circuit units is represented as a circuit unit "SC".
  • FIG. 6B shows a state in which the first insulating film IF1 is formed on the upper portion of the circuit formation portion shown in FIG. 6A, and thereafter, the opening AP1 for via formation is formed in the first insulating film IF1. .
  • FIG. 6C shows a state in which the first wiring parts WP10, WP11, and WP12 are formed on the first insulating film IF1 shown in FIG. 6B.
  • one of the first wiring portions is represented as a first wiring portion "WP1".
  • a portion of the first wiring portion formed in the opening AP1 is a first via V1.
  • FIG. 6D shows a state in which the second insulating film IF2 is formed on the first wiring parts WP10, WP11, and WP12, and then the opening AP2 for via formation is formed in the second insulating film IF2.
  • FIG. 6E shows a state in which the second wiring portions WP20, WP21, and WP22 are formed on the second insulating film IF2.
  • one of the second wiring portions is represented as a second wiring portion "WP2".
  • a portion of the second wiring portion formed in the opening AP2 is a second via V2.
  • FIG. 6F shows a state in which the plating film M is further formed on the second wiring portion WP2.
  • FIG. 6G shows a state in which the third insulating film IF3 is formed on the second wiring portion WP2 and the plating film M, and then the plating opening AP3 is formed.
  • Parts of the plating film M exposed from the plating opening AP3 are external connection terminals P1, P2, P3, P4, P5, and P6.
  • the pattern of the circuit formation layer shown in FIG. 6A is as shown in FIG.
  • the pattern of the first wiring portion is as shown in FIG.
  • the first via V1 interlayer-connects the transient voltage suppression circuit SC and the first wiring portion WP1 at a predetermined position.
  • the second wiring portion WP2 is a wiring for leading the transient voltage suppression circuit portion SC to the external terminal.
  • the second via V2 interconnects the first wiring portion WP1 and the second wiring portion WP2 at predetermined positions.
  • the plating film M is formed at a predetermined position of the second wiring portion WP2.
  • the plating opening AP3 exposes the plating film at a portion to be an external connection terminal.
  • the external connection terminals P1 and P4 shown in FIG. 6 correspond to the "first external connection terminal” according to the present invention, and the external connection terminals P3 and P6 correspond to the “second external connection terminal” according to the present invention.
  • the terminals P2 and P5 correspond to the "third external connection terminal” according to the present invention.
  • the external connection terminals P2 and P5 connected to the ground are arranged on the reference line SLY in a symmetrical arrangement as viewed from a direction perpendicular to the main surface of the semiconductor substrate. As described later, the external connection terminals P2 and P5 are terminals connected to the ground.
  • the semiconductor substrate 1 of the transient voltage suppression element 101 of the present embodiment has the first side S1 and the second side S2 facing each other, and the first external connection terminals (P1, P4) are on the first side S1 of the semiconductor substrate 1.
  • the second external connection terminals P3 and P6 are disposed in the vicinity of the second side S2 of the semiconductor substrate 1, and the first external connection terminals P1 and P4 and the second external connection terminals P3 and P6 are disposed.
  • third external connection terminals (P2, P5) are third external connection terminals.
  • the first insulating film IF1 is a SiN film
  • the first wiring portion WP1 is a patterned Al film
  • the second insulating film IF2 is an epoxy resin film
  • the second wiring portion WP2 is a patterned Cu film.
  • the plating film M is a plating film whose base is a Ni film and whose surface is an Au film.
  • the third insulating film IF3 is an epoxy resin film. Each layer of the second insulating film IF2 or more is formed by the rewiring process.
  • FIG. 8 is a circuit diagram of the transient voltage suppression element of this embodiment.
  • FIG. 9 is a diagram showing the mounting state of the transient voltage suppression element 101 on the circuit board.
  • the transient voltage suppression element 101 has a transient voltage suppression circuit connected between the first external connection terminal (P1, P4) and the second external connection terminals (P3, P6) and the third external connection terminal (P2, P5). Structure.
  • the first external connection terminals (P1, P4) and the second external connection terminals (P3, P6) are connected to the signal line SL.
  • the third external connection terminals (P2, P5) are connected to the ground conductor pattern GND.
  • the transient voltage suppression element 101 is mounted across the ground conductor pattern GND, and the signal line SL and the signal line SL are connected via the transient voltage suppression element 101.
  • the main factor that the transient voltage suppression element is destroyed by electrostatic discharge (ESD) or the like is that the current flows through the transient voltage suppression element and the resistance component of the transient voltage suppression element generates heat.
  • ESD electrostatic discharge
  • the external connection terminals P2 and P5 are arranged on the reference line SLY in a symmetrical arrangement when viewed from a direction perpendicular to the main surface of the semiconductor substrate 1, and are connected to the external connection terminals P2 and P5, respectively (wiring portions
  • the path lengths of the wirings of the first wiring portion WP1 or the second wiring portion WP2) are made equal. Therefore, the influence of the parasitic component (parasitic inductance or parasitic capacitance) of the wiring portion is equal between the external connection terminals. Therefore, the same high frequency characteristics can be obtained regardless of the mounting direction of the transient voltage suppression element.
  • the external connection terminals P2 and P5 provided on the reference line SLY are terminals connected to the ground, that is, the external connection connected to the ground which is a common conductor Since the connection terminal is disposed at the center of the transient voltage suppression element, the plurality of transient voltage suppression circuit portions can be easily arranged symmetrically.
  • the first transient voltage suppression circuit unit and the second transient voltage suppression circuit unit are formed such that the current path is generated in the direction perpendicular to the main surface of the semiconductor substrate 1.
  • the area of the second transient voltage suppression circuit unit can be reduced, and a large number of first transient voltage suppression circuit units and second transient voltage suppression circuit units can be disposed within the limited area of the semiconductor substrate.
  • the first transient voltage suppression circuit unit is disposed at each of four vertices of the virtual square and the center (or near the center) of the square, and the second transient voltage suppression circuit unit includes four vertexes.
  • the plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units are disposed in proximity to each other because they are respectively disposed between adjacent apexes.
  • a plurality of first transient voltage suppression circuit units including an unused first transient voltage suppression circuit unit not connected to the external connection terminal, and an external connection among the plurality of second transient voltage suppression circuit units Since the unused second transient voltage suppression circuit unit not connected to the terminal is provided, the required first transient voltage suppression circuit unit and the second transient voltage suppression circuit unit are selectively used to provide transient voltage suppression characteristics and high frequency characteristics.
  • Various different transient voltage suppressors can be commercialized at low cost.
  • FIG. 10A is a plan view showing a pattern of a first wiring portion connecting a plurality of transient voltage suppression elements
  • FIG. 10B is a plan view showing a pattern of a second wiring portion and an external connection terminal. is there.
  • FIG. 10C is a diagram showing the path of the discharge current flowing to the external connection terminals P2 and P5 by arrows.
  • the structures shown in FIG. 10A, FIG. 10B and FIG. 10C are the same as the transient voltage suppression element 101 shown in the first embodiment.
  • FIG. 11A, FIG. 11B, and FIG. 11C are diagrams showing the transient voltage suppression element 102 according to the second embodiment.
  • FIG. 11A is a plan view showing a pattern of the first wiring portion WP1 (WP10, WP11, WP13), and
  • FIG. 11B shows a second wiring portion WP2 (WP20, WP21, WP22) and an external connection terminal. It is a top view which shows the pattern of P1, P2, P3, P4, P5, and P6.
  • FIG. 11C is a diagram showing the path of the discharge current flowing to the external connection terminal P2 by an arrow.
  • the transient voltage suppression element 102 and the transient voltage suppression element 101 are different only in the pattern of the first wiring portion WP1, and the other configurations are the same.
  • the first wiring parts WP10, WP11, and WP13 have a linear symmetry with respect to the reference line SLY.
  • the first wiring portion WP13 connects the first transient voltage suppression circuit SC11 and the second transient voltage suppression circuit SC211.
  • the external connection terminal P2 since the first wiring portions WP11 and WP13 conduct to the external connection terminal P2, the external connection terminal P2 is The first transient voltage suppression circuit units SC11 and SC12 and the second transient voltage suppression circuit units SC211 and SC221 are connected. Also, the external connection terminal P5 is not connected to any transient voltage suppression element. Therefore, the transient voltage suppressor shown in FIGS. 10A, 10B and 10C, and the transient voltage suppressor shown in FIGS. 11A, 11B and 11C. The circuit with is the same.
  • the inter-terminal capacitance between the external connection terminals P1, P3, P4 and P6 and the external connection terminal P2 is the same as the external connection terminals P1, P3, P4 and P6 in FIG. 10 (B) and FIG. 10 (C). It is the same as the capacitance between the external connection terminals P2 and P5.
  • FIG. 12 is a view showing a mounting state on a circuit board in the case of applying two transient voltage suppression elements 102 to a differential line.
  • the transient voltage suppression element 102 connected to the first signal line SL1 and the transient voltage suppression element 102 connected to the second signal line SL2 are mounted such that the external connection terminals P2 are adjacent to each other.
  • the two transient voltage suppression elements are connected via the ground conductor pattern GND on the circuit board. Affected by parasitic inductance.
  • the transient voltage suppression element 101 according to the first embodiment When the transient voltage suppression element 101 according to the first embodiment is mounted on a circuit board, the current path flowing through the ground conductor pattern GND on the circuit board connects the external connection terminals P2 with the path CP1 connecting the external connection terminals P2 with each other. The route CP2 is formed.
  • the transient voltage suppressing element 102 of the second embodiment when the transient voltage suppressing element 102 of the second embodiment is mounted as shown in FIG. 12, the current path flowing through the ground conductor pattern GND on the circuit board is only the path CP1 connecting the external connection terminals P2. . Therefore, by mounting the transient voltage suppression element 102 as shown in FIG. 12, the parasitic inductance is reduced and deterioration of the high frequency characteristics of the differential line can be suppressed.
  • the transient voltage suppression characteristics and the high frequency characteristics are different by selecting the connection structure of the wiring portion using the plurality of first transient voltage suppression circuit portions and the plurality of second transient voltage suppression circuit portions.
  • a transient voltage suppression element can be configured.
  • FIG. 13A is a plan view showing a pattern of a first wiring portion connecting a plurality of transient voltage suppression elements in the transient voltage suppression element 103 of the third embodiment.
  • the first wiring unit WP10 connects the first transient voltage suppression circuit unit SC10 and the second transient voltage suppression circuit units SC2141, SC2142, SC2231, and SC2232.
  • the first wiring portion WP11 also connects the first transient voltage suppression circuit SC12 and the second transient voltage suppression circuit SC211 and SC221.
  • the first wiring unit WP12 connects the first transient voltage suppression circuit unit SC14 and the second transient voltage suppression circuit units SC231 and SC241.
  • the configuration other than the first wiring portion is the same as that shown in the first embodiment.
  • the first wiring parts WP10, WP11, and WP12 are point-symmetrical shapes (180-degree rotational symmetry) centered on the centers of the plurality of transient voltage suppression circuit part formation regions.
  • FIG. 13B is a circuit diagram of the transient voltage suppression element 103 according to the third embodiment.
  • the circuit differs from the circuit of transient voltage suppression element 101 shown in the eighth point in that second transient voltage suppression circuit units SC231, SC2142, SC2232, and SC211 are connected.
  • the number of second transient voltage suppression circuit parts is increased, and ESD discharge characteristics and ESD tolerance higher than those of the transient voltage suppression element 101 shown in the first embodiment are increased. Is obtained.
  • FIG. 14 is a plan view showing a first wiring portion configuration of the transient voltage suppression element 104 according to the fourth embodiment.
  • the configuration of the plurality of transient voltage suppression circuits formed on the semiconductor substrate is the same as that shown in FIG.
  • the first wiring portion WP14 shown in FIG. 14 connects the first transient voltage suppression circuit units SC11 and SC14 and the second transient voltage suppression circuit units SC2142, SC211 and SC241.
  • the first wiring unit WP15 connects the first transient voltage suppression circuit units SC12 and SC13 and the second transient voltage suppression circuit units SC2232, SC221, and SC231.
  • the first wiring portion WP10 is the same as that shown in the first and second embodiments.
  • 15 (A), 15 (B), 15 (C), 15 (D), 15 (E), 15 (F) and 15 (G) are on the semiconductor substrate of the transient voltage suppression element. It is a top view which shows each pattern in each layer of.
  • the pattern of the circuit formation layer is as shown in FIG.
  • the pattern of the first wiring portion is as shown in FIG.
  • the first via connects the transient voltage suppression circuit portion and the first wiring portion in an interlayer at a predetermined position.
  • the second wiring portion is a wiring for leading the plurality of transient voltage suppression circuit portions to the external terminal.
  • the second via interconnects the first wiring portion and the second wiring portion at a predetermined position.
  • the plating film is formed at a predetermined position of the second wiring portion.
  • the plating opening is for exposing the plating film at a portion to be an external connection terminal.
  • the second wiring portion WP23 is electrically connected to the first wiring portion WP10 through the second via.
  • the second wiring portion WP24 is electrically connected to the first wiring portion WP14 through the second via.
  • the second wiring portion WP25 is electrically connected to the first wiring portion WP15 via the second via.
  • the patterns of the first via, the first wiring portion, the second via, and the second wiring portion are different from those shown in FIG. 6 in the first embodiment. Others are the same.
  • the external connection terminals P1 and P4 shown in FIG. 15 correspond to the "first external connection terminal” according to the present invention, and the external connection terminals P3 and P6 correspond to the “second external connection terminal” according to the present invention.
  • the terminals P2 and P5 correspond to the "third external connection terminal” according to the present invention. These are the same as the transient voltage suppression element 101 shown in the first embodiment.
  • FIG. 16 is a circuit diagram of the transient voltage suppression element 104 of this embodiment.
  • FIG. 17 is a diagram showing the mounting state of the transient voltage suppression element 104 on the circuit board.
  • the transient voltage suppression element 104 has a first transient voltage suppression circuit connected between the first external connection terminal (P1, P4) and the third external connection terminal (P2, P5), and the second external connection terminal A second transient voltage suppression circuit is connected between P3 and P6) and the third external connection terminal (P2 and P5).
  • the first external connection terminals (P1, P4) are connected to the first signal line SL1.
  • the second external connection terminals (P3, P6) are connected to the second signal line SL2.
  • the third external connection terminals (P2, P5) are connected to the ground conductor pattern GND.
  • the transient voltage suppression element for one channel and the transient voltage suppression element for two channels can be obtained simply by changing the wiring portion and via pattern while using the same semiconductor substrate. Can be selectively manufactured.
  • the plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units are symmetrically disposed, and the first wiring portions WP10, WP14, WP15, and the second wiring portions WP23, WP24, WP25 Since each is also symmetrical, the influence of the parasitic component (parasitic inductance or parasitic capacitance) of the wiring part is equal for the two channels. Therefore, high frequency characteristics between channels can be equalized.
  • FIG. 18 is a plan view showing the shape and the arrangement of a plurality of transient voltage suppression circuits of the transient voltage suppression element according to the fifth embodiment.
  • the embodiments are different from the embodiments described above in that first transient voltage suppression circuit units SC10A and SC10B are provided.
  • the planar areas of all the first transient voltage suppression circuit units SC10A, SC10B, SC11, SC12, SC13, and SC14 are the same.
  • the first transient voltage suppression circuit units SC10A and SC10B are disposed in line symmetry with respect to the reference line SLY.
  • all of the plurality of first transient voltage suppression circuit units may have the same area.
  • the semiconductor substrate is not limited to P-type, and may be N-type. That is, in each of the Zener diode ZD, the first diode, and the second diode, the P-type and the N-type shown in the respective drawings may have an inverse relationship.
  • three external connection terminals may be provided.
  • the external connection terminals P1 and P4 shown in FIGS. 11B and 11C are combined into one
  • the external connection terminals P3 and P6 are combined into one
  • the external connection terminals P2 and P5 are combined into one.
  • the three-terminal transient voltage suppression element may be configured by putting it together.
  • first transient voltage suppression circuit units having different sizes may be provided.
  • second transient voltage suppression circuit units of different sizes may be provided.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un élément de suppression de tension transitoire, comprenant un circuit de suppression de tension transitoire configuré par connexion d'une pluralité d'éléments de circuit de suppression de tension transitoire dans une section de câblage. La pluralité d'éléments de circuit de suppression de tension transitoire comprend une pluralité de premiers éléments de circuit de suppression de tension transitoire dotés chacun d'un circuit de montage en série d'une diode Zener et d'une première diode, et une pluralité de seconds éléments de circuit de suppression de tension transitoire dotés chacun d'une seconde diode. Les premiers et seconds éléments de circuit de suppression de tension transitoire sont répartis selon une relation d'interpolation réciproque. Au moins certains éléments parmi les premiers éléments de circuit de suppression de tension transitoire sont agencés symétriquement et au moins certains éléments parmi les seconds éléments de circuit de suppression de tension transitoire sont agencés symétriquement.
PCT/JP2018/034132 2018-01-19 2018-09-14 Élément de suppression de tension transitoire WO2019142394A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201890000306.9U CN209766397U (zh) 2018-01-19 2018-09-14 瞬态电压抑制元件
JP2019502264A JP6516080B1 (ja) 2018-01-19 2018-09-14 過渡電圧抑制素子

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JP2018007154 2018-01-19
JP2018-007154 2018-01-19

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023058553A1 (fr) * 2021-10-04 2023-04-13 株式会社村田製作所 Élément d'absorption de surtension

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101083001B1 (ko) * 2010-12-23 2011-11-14 김진형 정전기 보호용 반도체 소자 및 그 제조 방법
US20140319598A1 (en) * 2013-04-24 2014-10-30 Madhur Bobde Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)
JP2015126149A (ja) * 2013-12-27 2015-07-06 パナソニックＩｐマネジメント株式会社 低容量半導体装置およびその製造方法
JP2015179776A (ja) * 2014-03-19 2015-10-08 株式会社東芝 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101083001B1 (ko) * 2010-12-23 2011-11-14 김진형 정전기 보호용 반도체 소자 및 그 제조 방법
US20140319598A1 (en) * 2013-04-24 2014-10-30 Madhur Bobde Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)
JP2015126149A (ja) * 2013-12-27 2015-07-06 パナソニックＩｐマネジメント株式会社 低容量半導体装置およびその製造方法
JP2015179776A (ja) * 2014-03-19 2015-10-08 株式会社東芝 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023058553A1 (fr) * 2021-10-04 2023-04-13 株式会社村田製作所 Élément d'absorption de surtension

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