WO2019142394A1 - Transient voltage suppression element - Google Patents

Transient voltage suppression element Download PDF

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WO2019142394A1
WO2019142394A1 PCT/JP2018/034132 JP2018034132W WO2019142394A1 WO 2019142394 A1 WO2019142394 A1 WO 2019142394A1 JP 2018034132 W JP2018034132 W JP 2018034132W WO 2019142394 A1 WO2019142394 A1 WO 2019142394A1
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transient voltage
voltage suppression
external connection
suppression circuit
connection terminal
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PCT/JP2018/034132
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French (fr)
Japanese (ja)
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紀行 植木
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株式会社村田製作所
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Priority to CN201890000306.9U priority Critical patent/CN209766397U/en
Priority to JP2019502264A priority patent/JP6516080B1/en
Publication of WO2019142394A1 publication Critical patent/WO2019142394A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

Abstract

A transient voltage suppression element includes a transient voltage suppression circuit configured by connecting a plurality of transient voltage suppression circuit elements in a wiring section. The plurality of transient voltage suppression circuit elements is constituted by a plurality of first transient voltage suppression circuit elements with each having a serial connection circuit of a Zener diode and a first diode and a plurality of second transient voltage suppression circuit elements with each having a second diode. The first transient voltage suppression circuit elements and the second transient voltage suppression circuit elements are dispersed in a mutually interpolated relationship. At least some of the first transient voltage suppression circuit elements are symmetrically disposed and at least some of the second transient voltage suppression circuit elements are symmetrically disposed.

Description

過渡電圧抑制素子Transient voltage suppressor
　本発明は、電子回路を静電気放電などによる過渡電圧から保護する過渡電圧抑制素子に関する。 The present invention relates to a transient voltage suppression element that protects an electronic circuit from a transient voltage due to electrostatic discharge or the like.
　特許文献１には、二つの外部接続端子を有する、双方向型の過渡電圧抑制素子が示されている。 Patent Document 1 discloses a bidirectional transient voltage suppression element having two external connection terminals.
　特許文献１に記載の過渡電圧抑制素子は、過渡電圧抑制回路部、配線部、および外部接続端子が形成された半導体基板を有し、半導体基板の対向する２辺に沿ってそれぞれ外部接続端子が形成されたCSP型（Chip Size Package）の過渡電圧抑制素子である。 The transient voltage suppression device described in Patent Document 1 has a semiconductor substrate on which a transient voltage suppression circuit portion, a wiring portion, and an external connection terminal are formed, and the external connection terminals are respectively arranged along two opposing sides of the semiconductor substrate. It is a transient voltage suppression element of CSP type (Chip Size Package) formed.
特開２０１４－１６７８７０号公報JP 2014-167870 A
　特許文献１に示されているCSP型の過渡電圧抑制素子は、半導体基板の平面視において、二つの外部接続端子の間に過渡電圧抑制回路部が形成されている。ここで、CSP型の過渡電圧抑制素子は、半導体基板を外部接続端子の総面積より小さくできない。つまり、半導体基板は、少なくとも外部接続端子の総面積より大きくする必要がある。一方、端子間の容量が例えば0.5pF以下の低容量の過渡電圧抑制素子をCSP型で構成する場合、過渡電圧抑制回路部は、半導体基板上の非常に小さな領域に形成される。すなわち、半導体基板の面積に対して、相対的に非常に小さな領域に過渡電圧抑制回路部が形成されることになる。 In the CSP type transient voltage suppression element disclosed in Patent Document 1, a transient voltage suppression circuit portion is formed between two external connection terminals in a plan view of a semiconductor substrate. Here, the CSP type transient voltage suppression element can not make the semiconductor substrate smaller than the total area of the external connection terminals. That is, the semiconductor substrate needs to be at least larger than the total area of the external connection terminals. On the other hand, when a low-capacitance transient voltage suppression element having a capacitance between terminals of, for example, 0.5 pF or less is formed of a CSP type, the transient voltage suppression circuit portion is formed in a very small area on the semiconductor substrate. That is, the transient voltage suppression circuit portion is formed in a relatively small area relatively to the area of the semiconductor substrate.
　したがって、半導体基板の面積が有効に利用されていないという問題があった。また、過渡電圧抑制特性や高周波特性の異なる多種の過渡電圧抑制素子を商品化する際、それら特性に応じて個別に過渡電圧抑制素子を設計し、製造する必要があったため、低コスト化が困難であるという問題があった。 Therefore, there is a problem that the area of the semiconductor substrate is not effectively used. Moreover, when commercializing various transient voltage suppression elements having different transient voltage suppression characteristics and high-frequency characteristics, it is necessary to design and manufacture the transient voltage suppression elements individually according to the characteristics, so it is difficult to reduce costs. Was a problem.
　そこで、本発明の目的は、半導体基板の面積を有効に利用して、過渡電圧抑制特性や高周波特性の異なる多種の過渡電圧抑制素子を低コストで構成できるようにした過渡電圧抑制素子を提供することにある。 Therefore, an object of the present invention is to provide a transient voltage suppression element capable of forming various transient voltage suppression elements having different transient voltage suppression characteristics and high frequency characteristics at low cost by effectively using the area of a semiconductor substrate. It is.
（１）本発明の過渡電圧抑制素子は、過渡電圧抑制回路部、配線部および外部接続端子が形成された半導体基板を有し、過渡電圧抑制回路部と配線部とによって過渡電圧抑制回路が構成された過渡電圧抑制素子である。外部接続端子は、半導体基板の主面に沿って配置された３つ以上の端子である。過渡電圧抑制回路部は、それぞれツェナーダイオードと第１ダイオードとの直列接続回路を有する複数の第１過渡電圧抑制回路部と、それぞれ第２ダイオードを有する複数の第２過渡電圧抑制回路部とを有する。そして、半導体基板の主面に垂直な方向から平面視して、複数の第１過渡電圧抑制回路部が複数の第２過渡電圧抑制回路部のうち少なくとも１つの第２過渡電圧抑制回路部を挟み、且つ複数の第２過渡電圧抑制回路部が複数の第１過渡電圧抑制回路部のうち少なくとも１つの第１過渡電圧抑制回路部を挟むように、複数の第１過渡電圧抑制回路部と複数の第２過渡電圧抑制回路部とが配置される。また、半導体基板の主面に垂直な方向から平面視して、複数の第１過渡電圧抑制回路部は少なくとも一部が対称配置されていて、複数の第２過渡電圧抑制回路部は少なくとも一部が対称配置されている。 (1) The transient voltage suppression device of the present invention has a semiconductor substrate on which the transient voltage suppression circuit portion, the wiring portion and the external connection terminal are formed, and the transient voltage suppression circuit portion and the wiring portion constitute a transient voltage suppression circuit Transient voltage suppression element. The external connection terminals are three or more terminals disposed along the main surface of the semiconductor substrate. The transient voltage suppression circuit unit has a plurality of first transient voltage suppression circuit units each having a series connection circuit of a zener diode and a first diode, and a plurality of second transient voltage suppression circuit units each having a second diode. . The plurality of first transient voltage suppression circuit portions sandwich at least one second transient voltage suppression circuit portion among the plurality of second transient voltage suppression circuit portions in plan view in a direction perpendicular to the main surface of the semiconductor substrate. And a plurality of first transient voltage suppression circuits and a plurality of first transient voltage suppression circuits such that the plurality of second transient voltage suppression circuits sandwich at least one of the plurality of first transient voltage suppression circuits. A second transient voltage suppression circuit unit is disposed. Further, at least a portion of the plurality of first transient voltage suppression circuit portions are symmetrically arranged in plan view in a direction perpendicular to the main surface of the semiconductor substrate, and at least a portion of the plurality of second transient voltage suppression circuit portions Are arranged symmetrically.
　上記構成によれば、複数の第１過渡電圧抑制回路部と、複数の第２過渡電圧抑制回路部とを備えることで、例えば複数チャンネルの過渡電圧抑制回路部を構成できる。また、複数の第１過渡電圧抑制回路部と、複数の第２過渡電圧抑制回路部とを用い、配線部の接続構造を選ぶことで、例えば過渡電圧抑制特性や高周波特性の異なる過渡電圧抑制素子が構成できる。 According to the above configuration, by including the plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units, for example, a plurality of channels of transient voltage suppression circuit units can be configured. Further, by selecting the connection structure of the wiring portion using a plurality of first transient voltage suppression circuit units and a plurality of second transient voltage suppression circuit units, for example, transient voltage suppression elements having different transient voltage suppression characteristics or high frequency characteristics Can be configured.
　また、上記構成によれば、配線部も対称にできるので、配線部の寄生成分（寄生インダクタンスまたは寄生容量）の影響は、外部接続端子間またはチャンネル間で等しくできる。そのため、回路基板への実装状態での外部接続端子の向きが異なっても、高周波特性を等しくできる。また、複数チャンネル分の過渡電圧抑制回路が構成される場合に、チャンネル間での高周波特性を等しくできる。 Further, according to the above configuration, since the wiring portion can be made symmetrical, the influence of the parasitic component (parasitic inductance or parasitic capacitance) of the wiring portion can be equalized between the external connection terminals or between the channels. Therefore, even if the orientations of the external connection terminals in the mounted state on the circuit board are different, the high frequency characteristics can be equalized. In addition, when transient voltage suppression circuits for a plurality of channels are formed, high frequency characteristics can be equalized between the channels.
（２）半導体基板の主面に垂直な方向から平面視して、複数の第１過渡電圧抑制回路部は少なくとも一部が基準線を中心に線対称に配置されていて、第２過渡電圧抑制回路部は少なくとも一部が基準線を中心に線対称に配置されており、外部接続端子の少なくとも１つは、半導体基板の主面に垂直な方向から視て、上記対称配置の基準線上に配置されていることが好ましい。この構造によれば、基準線上に配置されている外部接続端子に接続される配線部の配線の経路長を等しくしやすく、そのことで、配線部の寄生成分（寄生インダクタンスまたは寄生容量）のばらつきをより小さくできる。そのため、回路基板への実装状態での外部接続端子の向きが異なっても、高周波特性をより等しくできる。また、複数チャンネル分の過渡電圧抑制回路が構成される場合に、チャンネル間での高周波特性をより等しくできる。 (2) At least a portion of the plurality of first transient voltage suppression circuit portions are disposed in line symmetry with respect to the reference line in plan view from a direction perpendicular to the main surface of the semiconductor substrate, and second transient voltage suppression At least a part of the circuit portion is disposed in line symmetry with respect to the reference line, and at least one of the external connection terminals is disposed on the reference line of the above-mentioned symmetrical arrangement as viewed from a direction perpendicular to the main surface of the semiconductor substrate. Is preferred. According to this structure, it is easy to equalize the path lengths of the wires of the wiring portion connected to the external connection terminal arranged on the reference line, and thereby, the variation of the parasitic component (parasitic inductance or parasitic capacitance) of the wiring portion Can be made smaller. Therefore, even if the orientations of the external connection terminals in the mounted state on the circuit board are different, the high frequency characteristics can be made more equal. In addition, when transient voltage suppression circuits for a plurality of channels are formed, the high frequency characteristics between the channels can be made more equal.
（３）外部接続端子のうち、上記基準線上に設けられている外部接続端子はグランドに直接接続されることが好ましい。この構造によれば、共通の導体であるグランドに接続される外部接続端子が過渡電圧抑制素子の中央に配置されることになるので、複数の過渡電圧抑制回路部を容易に対称配置できる。 (3) Of the external connection terminals, it is preferable that the external connection terminals provided on the reference line be directly connected to the ground. According to this structure, since the external connection terminal connected to the ground which is the common conductor is disposed at the center of the transient voltage suppression element, the plurality of transient voltage suppression circuit portions can be easily arranged symmetrically.
（４）複数の第１過渡電圧抑制回路部および複数の第２過渡電圧抑制回路部は、半導体基板の主面に垂直な方向に電流経路が生じるように形成されていることが好ましい。この構造によれば、第１過渡電圧抑制回路部および第２過渡電圧抑制回路部の平面積をそれぞれ小さくでき、半導体基板の限られた面積内に多数の第１過渡電圧抑制回路部および第２過渡電圧抑制回路部を配置できる。 (4) The plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units are preferably formed such that current paths are generated in a direction perpendicular to the main surface of the semiconductor substrate. According to this structure, the planar areas of the first transient voltage suppression circuit unit and the second transient voltage suppression circuit unit can be reduced, respectively, and a large number of first transient voltage suppression circuit units and the second transient voltage suppression circuit unit can be formed within a limited area of the semiconductor substrate. A transient voltage suppression circuit can be arranged.
（５）複数の第１過渡電圧抑制回路部は、四角形の四つの頂点と、この四角形の内部とにそれぞれ配置され、複数の第２過渡電圧抑制回路部は、上記四つの頂点のうち隣接する頂点の間にそれぞれ配置されることが好ましい。この構造によれば、複数の第１過渡電圧抑制回路部と複数の第２過渡電圧抑制回路部とが互いに近接配置されるので、配線部の配線を長く引き回すことなく、複数の第１過渡電圧抑制回路部と複数の第２過渡電圧抑制回路部とを備える過渡電圧抑制回路部が構成できる。 (5) The plurality of first transient voltage suppression circuit units are disposed respectively at the four vertices of the square and inside the square, and the plurality of second transient voltage suppression circuit units are adjacent among the four vertices. Preferably, they are respectively disposed between the vertices. According to this structure, since the plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units are disposed close to each other, the plurality of first transient voltages are not drawn long in the wiring portion of the wiring portion. A transient voltage suppression circuit unit including the suppression circuit unit and the plurality of second transient voltage suppression circuit units can be configured.
（６）例えば、前記半導体基板は互いに対向する第１辺および第２辺を有し、外部接続端子は、第１外部接続端子、第２外部接続端子および第３外部接続端子を有し、第１外部接続端子は半導体基板の第１辺の近傍に配置され、第２外部接続端子は半導体基板の第２辺の近傍に配置され、第１外部接続端子と第２外部接続端子との間に第３外部接続端子が配置される。そして、第１外部接続端子と第２外部接続端子とは配線部を介して接続され、第１外部接続端子と第３外部接続端子との間、および第２外部接続端子と第３外部接続端子との間に過渡電圧抑制回路がそれぞれ接続される。ここで、第１外部接続端子および第２外部接続端子は信号ラインにそれぞれ接続され、第３外部接続端子はグランドに接続される。 (6) For example, the semiconductor substrate has a first side and a second side facing each other, and the external connection terminal has a first external connection terminal, a second external connection terminal, and a third external connection terminal. (1) The external connection terminal is disposed in the vicinity of the first side of the semiconductor substrate, and the second external connection terminal is disposed in the vicinity of the second side of the semiconductor substrate, and between the first external connection terminal and the second external connection terminal A third external connection terminal is arranged. The first external connection terminal and the second external connection terminal are connected through the wiring portion, and between the first external connection terminal and the third external connection terminal, and the second external connection terminal and the third external connection terminal Between and transient voltage suppression circuits are respectively connected. Here, the first external connection terminal and the second external connection terminal are respectively connected to the signal line, and the third external connection terminal is connected to the ground.
　上記構成により、回路基板上のグランドを跨いで信号ラインを繋ぐとともに、この信号ラインとグランドとの間に過渡電圧抑制回路が接続される。 According to the above configuration, the signal line is connected across the ground on the circuit board, and a transient voltage suppression circuit is connected between the signal line and the ground.
（７）例えば、半導体基板は互いに対向する第１辺および第２辺を有し、外部接続端子は、第１外部接続端子、第２外部接続端子および第３外部接続端子を有し、第１外部接続端子は半導体基板の第１辺の近傍に配置され、第２外部接続端子は半導体基板の第２辺の近傍に配置され、第１外部接続端子と第２外部接続端子との間に第３外部接続端子が配置される。過渡電圧抑制回路は第１の過渡電圧抑制回路と第２の過渡電圧抑制回路とを含む。そして、第１外部接続端子と第３外部接続端子との間に第１の過渡電圧抑制回路が接続され、第２外部接続端子と第３外部接続端子との間に第２の過渡電圧抑制回路が接続される。ここで、第１外部接続端子は第１信号ラインに接続され、第２外部接続端子は第２信号ラインに接続され、第３外部接続端子はグランドに接続される。 (7) For example, the semiconductor substrate has the first side and the second side facing each other, and the external connection terminal has the first external connection terminal, the second external connection terminal, and the third external connection terminal, and the first The external connection terminal is disposed in the vicinity of the first side of the semiconductor substrate, and the second external connection terminal is disposed in the vicinity of the second side of the semiconductor substrate, and the first external connection terminal is disposed between the first external connection terminal and the second external connection terminal. 3 External connection terminals are arranged. The transient voltage suppression circuit includes a first transient voltage suppression circuit and a second transient voltage suppression circuit. A first transient voltage suppression circuit is connected between the first external connection terminal and the third external connection terminal, and a second transient voltage suppression circuit is connected between the second external connection terminal and the third external connection terminal. Is connected. Here, the first external connection terminal is connected to the first signal line, the second external connection terminal is connected to the second signal line, and the third external connection terminal is connected to the ground.
　上記構成により、回路基板上のグランドを跨いで、二つの信号ラインとグランドとの間に過渡電圧抑制回路がそれぞれ接続される。 According to the above configuration, the transient voltage suppression circuit is connected between the two signal lines and the ground across the ground on the circuit board.
（８）複数の第１過渡電圧抑制回路部のうち、少なくとも一つの第１過渡電圧抑制回路部は外部接続端子に接続されていない構造であってもよい。この構造によれば、必要な第１過渡電圧抑制回路部を選択的に用いて、過渡電圧抑制回路のチャンネル数を設定できる。また、過渡電圧抑制特性や高周波特性の異なる多種の過渡電圧抑制素子を低コストで商品化できる。 (8) Of the plurality of first transient voltage suppression circuit units, at least one first transient voltage suppression circuit unit may not be connected to the external connection terminal. According to this structure, the number of channels of the transient voltage suppression circuit can be set by selectively using the necessary first transient voltage suppression circuit unit. Further, various transient voltage suppression elements having different transient voltage suppression characteristics and high frequency characteristics can be commercialized at low cost.
（９）複数の第２過渡電圧抑制回路部のうち、少なくとも一つの第２過渡電圧抑制回路部は外部接続端子に接続されていない構造であってもよい。この構造によっても、必要な第２過渡電圧抑制回路部を選択的に用いて、過渡電圧抑制回路のチャンネル数を設定できる。また、過渡電圧抑制特性や高周波特性の異なる多種の過渡電圧抑制素子を低コストで商品化できる。 (9) Of the plurality of second transient voltage suppression circuit units, at least one second transient voltage suppression circuit unit may not be connected to the external connection terminal. Also according to this structure, the number of channels of the transient voltage suppression circuit can be set by selectively using the necessary second transient voltage suppression circuit unit. Further, various transient voltage suppression elements having different transient voltage suppression characteristics and high frequency characteristics can be commercialized at low cost.
　本発明によれば、半導体基板の面積を有効に利用して、過渡電圧抑制特性や高周波特性の異なる多種の過渡電圧抑制素子を低コストで商品化できるようにした過渡電圧抑制素子が得られる。 According to the present invention, it is possible to obtain a transient voltage suppression element capable of commercializing various kinds of transient voltage suppression elements having different transient voltage suppression characteristics and high frequency characteristics at low cost by effectively utilizing the area of the semiconductor substrate.
図１は第１の実施形態に係る過渡電圧抑制素子の過渡電圧抑制回路部を示す平面図である。FIG. 1 is a plan view showing a transient voltage suppression circuit portion of the transient voltage suppression element according to the first embodiment. 図２（Ａ）は第１過渡電圧抑制回路部の構造を示す平面図であり、図２（Ｂ）はその断面図であり、図２（Ｃ）はその回路図である。FIG. 2 (A) is a plan view showing the structure of the first transient voltage suppression circuit, FIG. 2 (B) is a cross-sectional view thereof, and FIG. 2 (C) is a circuit diagram thereof. 図３（Ａ）は第２過渡電圧抑制回路部の構造を示す平面図であり、図３（Ｂ）はその断面図であり、図３（Ｃ）はその回路図である。FIG. 3A is a plan view showing the structure of the second transient voltage suppression circuit, FIG. 3B is a cross-sectional view thereof, and FIG. 3C is a circuit diagram thereof. 図４は、第１過渡電圧抑制回路部と第２過渡電圧抑制回路部とを並列接続するための第１配線部の構成を示す平面図である。FIG. 4 is a plan view showing a configuration of a first wiring portion for connecting in parallel the first transient voltage suppression circuit portion and the second transient voltage suppression circuit portion. 図５は、第１過渡電圧抑制回路部ＳＣ１０と第２過渡電圧抑制回路部ＳＣ２１４１とを通る位置での部分断面図である。FIG. 5 is a partial cross-sectional view at a position passing through the first transient voltage suppression circuit unit SC10 and the second transient voltage suppression circuit unit SC2141. 図６（Ａ）、図６（Ｂ）、図６（Ｃ）、図６（Ｄ）、図６（Ｅ）、図６（Ｆ）、図６（Ｇ）は、過渡電圧抑制素子の半導体基板上の各層における各パターンを示す平面図である。6 (A), 6 (B), 6 (C), 6 (D), 6 (E), 6 (F) and 6 (G) show the semiconductor substrate of the transient voltage suppression element. It is a top view which shows each pattern in upper each layer. 図７は過渡電圧抑制素子の所定位置での断面図である。FIG. 7 is a cross-sectional view of the transient voltage suppression element at a predetermined position. 図８は第１の本実施形態の過渡電圧抑制素子の回路図である。FIG. 8 is a circuit diagram of the transient voltage suppressing element of the first embodiment. 図９は、回路基板への過渡電圧抑制素子１０１の実装状態を示す図である。FIG. 9 is a diagram showing the mounting state of the transient voltage suppression element 101 on the circuit board. 図１０（Ａ）、図１０（Ｂ）、図１０（Ｃ）は第２の実施形態の比較例としての過渡電圧抑制素子１０１について示す図である。FIG. 10A, FIG. 10B, and FIG. 10C are diagrams showing a transient voltage suppression element 101 as a comparative example of the second embodiment. 図１１（Ａ）、図１１（Ｂ）、図１１（Ｃ）は第２の実施形態に係る過渡電圧抑制素子１０２について示す図である。FIG. 11A, FIG. 11B, and FIG. 11C are diagrams showing the transient voltage suppression element 102 according to the second embodiment. 図１２は二つの過渡電圧抑制素子１０２を差動線路に適用する場合の回路基板への実装状態を示す図である。FIG. 12 is a view showing a mounting state on a circuit board in the case of applying two transient voltage suppression elements 102 to a differential line. 図１３（Ａ）は第３の実施形態の過渡電圧抑制素子１０３において、複数の過渡電圧抑制素子を接続する第１配線部のパターンを示す平面図である。図１３（Ｂ）は第３の実施形態の過渡電圧抑制素子１０３の回路図である。FIG. 13A is a plan view showing a pattern of a first wiring portion connecting a plurality of transient voltage suppression elements in the transient voltage suppression element 103 of the third embodiment. FIG. 13B is a circuit diagram of the transient voltage suppression element 103 according to the third embodiment. 図１４は第４の実施形態に係る過渡電圧抑制素子１０４の第１配線部構成を示す平面図である。FIG. 14 is a plan view showing a first wiring portion configuration of the transient voltage suppression element 104 according to the fourth embodiment. 図１５（Ａ）、図１５（Ｂ）、図１５（Ｃ）、図１５（Ｄ）、図１５（Ｅ）、図１５（Ｆ）、図１５（Ｇ）は過渡電圧抑制素子の半導体基板上の各層における各パターンを示す平面図である。15 (A), 15 (B), 15 (C), 15 (D), 15 (E), 15 (F) and 15 (G) are on the semiconductor substrate of the transient voltage suppression element. It is a top view which shows each pattern in each layer of. 図１６は過渡電圧抑制素子１０４の回路図である。FIG. 16 is a circuit diagram of the transient voltage suppression element 104. As shown in FIG. 図１７は、回路基板への過渡電圧抑制素子１０４の実装状態を示す図である。FIG. 17 is a diagram showing the mounting state of the transient voltage suppression element 104 on the circuit board. 図１８は第５の実施形態に係る過渡電圧抑制素子の、複数の過渡電圧抑制回路部の形状および配置を示す平面図である。FIG. 18 is a plan view showing the shape and the arrangement of a plurality of transient voltage suppression circuits of the transient voltage suppression element according to the fifth embodiment.
　以降、図を参照して幾つかの具体的な例を挙げて、本発明を実施するための複数の形態を示す。各図中には同一箇所に同一符号を付している。要点の説明または理解の容易性を考慮して、便宜上実施形態を分けて示すが、異なる実施形態で示した構成の部分的な置換または組み合わせは可能である。第２の実施形態以降では第１の実施形態と共通の事柄についての記述を省略し、異なる点についてのみ説明する。特に、同様の構成による同様の作用効果については実施形態毎には逐次言及しない。 Hereinafter, some specific examples will be described with reference to the drawings to show a plurality of modes for carrying out the present invention. The same reference numerals are given to the same parts in each drawing. Although the embodiments are shown separately for convenience in consideration of the description of the main points or the ease of understanding, partial replacement or combination of the configurations shown in the different embodiments is possible. In the second and subsequent embodiments, descriptions of matters in common with the first embodiment will be omitted, and only different points will be described. In particular, the same operation and effect by the same configuration will not be sequentially referred to in each embodiment.
《第１の実施形態》
　図１は第１の実施形態に係る過渡電圧抑制素子の過渡電圧抑制回路部を示す平面図である。 First Embodiment
FIG. 1 is a plan view showing a transient voltage suppression circuit portion of the transient voltage suppression element according to the first embodiment.
　図１において、“ＳＣ”で始まる符号を付した箇所はそれぞれ過渡電圧抑制回路部である。このように、半導体基板１に複数の過渡電圧抑制回路部が形成されている。半導体基板１には、過渡電圧抑制回路部以外に配線部および外部接続端子が形成されるが、それらについては後に示す。 In FIG. 1, portions denoted by reference numerals starting with “SC” are transient voltage suppression circuits. Thus, a plurality of transient voltage suppression circuit parts are formed on the semiconductor substrate 1. Wiring portions and external connection terminals are formed on the semiconductor substrate 1 in addition to the transient voltage suppression circuit portion, which will be described later.
　図１において、“ＳＣ１”で始まる符号を付した箇所はそれぞれ第１過渡電圧抑制回路部であり、“ＳＣ２”で始まる符号を付した箇所はそれぞれ第２過渡電圧抑制回路部である。第１過渡電圧抑制回路部は、それぞれツェナーダイオードと第１ダイオードとの直列接続回路を有する。また、第２過渡電圧抑制回路部はそれぞれ第２ダイオードで構成される。 In FIG. 1, portions marked with a code beginning with “SC1” are first transient voltage suppression circuit units, and portions marked with a symbol starting with “SC2” are second transient voltage suppression circuit units. The first transient voltage suppression circuit unit has a series connection circuit of a Zener diode and a first diode. In addition, the second transient voltage suppression circuit unit is formed of a second diode.
　本実施形態の過渡電圧抑制素子は、複数の第１過渡電圧抑制回路部のうち、第１過渡電圧抑制回路部ＳＣ１１，ＳＣ１２，ＳＣ１３，ＳＣ１４は、これら４つの第１過渡電圧抑制回路部を結んでできる仮想的な四角形の内部（好ましくは四角形の中心）に、第１過渡電圧抑制回路部ＳＣ１０が配置されている。なお、この配置関係は、第１過渡電圧抑制回路部ＳＣ１１，ＳＣ１３を通る第１の直線と、第１過渡電圧抑制回路部ＳＣ１２，ＳＣ１４を通る第２の直線が交点を形成し、この交点または交点の近傍に第１過渡電圧抑制回路部ＳＣ１０が配置されていると言い換えることもできる。第１過渡電圧抑制回路部ＳＣ１０は、第１過渡電圧抑制回路部ＳＣ１１，ＳＣ１２，ＳＣ１３，ＳＣ１４に比べて、半導体基板１の主面に垂直な方向から平面視した場合の面積が２倍である。 In the transient voltage suppression element of the present embodiment, among the plurality of first transient voltage suppression circuit portions, the first transient voltage suppression circuit portions SC11, SC12, SC13, and SC14 connect these four first transient voltage suppression circuit portions. The first transient voltage suppression circuit unit SC10 is disposed inside the virtual quadrangle (preferably, the center of the quadrangle) which can In this arrangement relationship, a first straight line passing through the first transient voltage suppression circuit units SC11 and SC13 and a second straight line passing through the first transient voltage suppression circuit units SC12 and SC14 form an intersection point, or this intersection point or In other words, the first transient voltage suppression circuit unit SC10 is disposed in the vicinity of the intersection point. The first transient voltage suppression circuit unit SC10 has a doubled area in a plan view from the direction perpendicular to the main surface of the semiconductor substrate 1 as compared with the first transient voltage suppression circuit units SC11, SC12, SC13, and SC14. .
　本実施形態の過渡電圧抑制素子は、半導体基板１の主面に垂直な方向から平面視して、第１過渡電圧抑制回路部が第２過渡電圧抑制回路部を挟む箇所があり、且つ第２過渡電圧抑制回路部が第１過渡電圧抑制回路部を挟む箇所がある。このような関係で、複数の第１過渡電圧抑制回路部と複数の第２過渡電圧抑制回路部とが配置されている。具体的には次のとおりである。 The transient voltage suppression element of the present embodiment has a portion where the first transient voltage suppression circuit portion sandwiches the second transient voltage suppression circuit portion in plan view in a direction perpendicular to the main surface of the semiconductor substrate 1, and the second There is a place where the transient voltage suppression circuit part sandwiches the first transient voltage suppression circuit part. In such a relationship, the plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units are disposed. Specifically, it is as follows.
　先ず、第２過渡電圧抑制回路部ＳＣ２１１，ＳＣ２１２，ＳＣ２２１，ＳＣ２２２は第１過渡電圧抑制回路部ＳＣ１１と第１過渡電圧抑制回路部ＳＣ１２とで挟まれている。同様に、第２過渡電圧抑制回路部ＳＣ２３１，ＳＣ２３２，ＳＣ２４１，ＳＣ２４２は第１過渡電圧抑制回路部ＳＣ１３と第１過渡電圧抑制回路部ＳＣ１４とで挟まれている。 First, the second transient voltage suppression circuit units SC211, SC212, SC221, and SC222 are sandwiched between the first transient voltage suppression circuit unit SC11 and the first transient voltage suppression circuit unit SC12. Similarly, the second transient voltage suppression circuit units SC231, SC232, SC241, and SC242 are sandwiched between the first transient voltage suppression circuit unit SC13 and the first transient voltage suppression circuit unit SC14.
　また、第２過渡電圧抑制回路部ＳＣ２１４１，ＳＣ２１４２は第１過渡電圧抑制回路部ＳＣ１１と第１過渡電圧抑制回路部ＳＣ１４とで挟まれている。同様に、第２過渡電圧抑制回路部ＳＣ２２３１，ＳＣ２２３２は第１過渡電圧抑制回路部ＳＣ１２と第１過渡電圧抑制回路部ＳＣ１３とで挟まれている。 The second transient voltage suppression circuit units SC2141 and SC2142 are sandwiched between the first transient voltage suppression circuit unit SC11 and the first transient voltage suppression circuit unit SC14. Similarly, the second transient voltage suppression circuit units SC2231 and SC2232 are sandwiched between the first transient voltage suppression circuit unit SC12 and the first transient voltage suppression circuit unit SC13.
　また、第１過渡電圧抑制回路部ＳＣ１０は第２過渡電圧抑制回路部ＳＣ２１１，ＳＣ２２１と第２過渡電圧抑制回路部ＳＣ２３１，ＳＣ２４１とで挟まれている。また、第１過渡電圧抑制回路部ＳＣ１０は第２過渡電圧抑制回路部ＳＣ２１４１、と第２過渡電圧抑制回路部ＳＣ２２３１とで挟まれている。 Further, the first transient voltage suppression circuit unit SC10 is sandwiched between the second transient voltage suppression circuit units SC211 and SC221 and the second transient voltage suppression circuit units SC231 and SC241. Further, the first transient voltage suppression circuit unit SC10 is sandwiched between the second transient voltage suppression circuit unit SC2141 and the second transient voltage suppression circuit unit SC2231.
　ここで、第１過渡電圧抑制回路部ＳＣ１１，ＳＣ１３を通る第１の直線と、第１過渡電圧抑制回路部ＳＣ１２，ＳＣ１４を通る第２の直線とにより、半導体基板１上の領域を４つに分割した場合、４つの領域にそれぞれ少なくとも１つ以上の第２過渡電圧抑制回路部が配置されていることが好ましい。 Here, the first straight line passing through the first transient voltage suppression circuit units SC11 and SC13 and the second straight line passing through the first transient voltage suppression circuit units SC12 and SC14 make the region on the semiconductor substrate 1 four. In the case of division, it is preferable that at least one or more second transient voltage suppression circuit units are disposed in each of the four regions.
　上述の、第１過渡電圧抑制回路部と第２過渡電圧抑制回路部の位置関係は、第１過渡電圧抑制回路部と第２過渡電圧抑制回路部とが、互いに補間する関係で分散配置されている、ということもできる。 The positional relationship between the first transient voltage suppression circuit unit and the second transient voltage suppression circuit unit described above is dispersedly arranged in such a manner that the first transient voltage suppression circuit unit and the second transient voltage suppression circuit unit are interpolated with each other. It can also be said that
　本実施形態の過渡電圧抑制素子は、半導体基板１の主面に垂直な方向から平面視して、第１過渡電圧抑制回路部は対称配置されていて、第２過渡電圧抑制回路部は対称配置されている。具体的には次のとおりである。 In the transient voltage suppression element of this embodiment, the first transient voltage suppression circuit portion is symmetrically disposed in plan view in a direction perpendicular to the main surface of the semiconductor substrate 1, and the second transient voltage suppression circuit portion is symmetrically disposed. It is done. Specifically, it is as follows.
　先ず、半導体基板１の主面に垂直な方向から平面視して、第１過渡電圧抑制回路部ＳＣ１１，ＳＣ１２は基準線ＳＬＹに対して線対称に配置されている。同様に、第１過渡電圧抑制回路部ＳＣ１３，ＳＣ１４は基準線ＳＬＹに対して線対称に配置されている。また、第１過渡電圧抑制回路部ＳＣ１１，ＳＣ１４は基準線ＳＬＸに対して線対称に配置されている。同様に、第１過渡電圧抑制回路部ＳＣ１２，ＳＣ１３は基準線ＳＬＸに対して線対称に配置されている。 First, in a plan view in a direction perpendicular to the main surface of the semiconductor substrate 1, the first transient voltage suppression circuit units SC11 and SC12 are arranged in line symmetry with respect to the reference line SLY. Similarly, the first transient voltage suppression circuit units SC13 and SC14 are disposed in line symmetry with respect to the reference line SLY. The first transient voltage suppression circuit units SC11 and SC14 are disposed in line symmetry with respect to the reference line SLX. Similarly, the first transient voltage suppression circuit units SC12 and SC13 are disposed in line symmetry with respect to the reference line SLX.
　また、第２過渡電圧抑制回路部ＳＣ２１１，ＳＣ２１２，ＳＣ２１３，ＳＣ２４１，ＳＣ２４２，ＳＣ２４３，ＳＣ２１４１，ＳＣ２１４２と、第２過渡電圧抑制回路部ＳＣ２２１，ＳＣ２２２，ＳＣ２２３，ＳＣ２３１，ＳＣ２３２，ＳＣ２３３，ＳＣ２２３１，ＳＣ２２３２とは、基準線ＳＬＹに対して線対称に配置されている。同様に、第２過渡電圧抑制回路部ＳＣ２１１，ＳＣ２１２，ＳＣ２１３，ＳＣ２２１，ＳＣ２２２，ＳＣ２２３と、第２過渡電圧抑制回路部ＳＣ２４１，ＳＣ２４２，ＳＣ２４３，ＳＣ２３１，ＳＣ２３２，ＳＣ２３３とは、基準線ＳＬＸに対して線対称に配置されている。 In addition, the second transient voltage suppression circuit units SC211, SC212, SC213, SC241, SC242, SC243, SC2141, SC2142 and the second transient voltage suppression circuit units SC221, SC222, SC223, SC231, SC232, SC233, SC2231, SC2232 , And are arranged symmetrically with respect to the reference line SLY. Similarly, the second transient voltage suppression circuit units SC211, SC212, SC213, SC221, SC222, SC223 and the second transient voltage suppression circuit units SC241, SC242, SC243, SC231, SC232, SC233 with respect to the reference line SLX. It is arranged in line symmetry.
　基準線ＳＬＹ，ＳＬＸは複数の過渡電圧抑制回路部形成領域の中心を通る直線である。 The reference lines SLY and SLX are straight lines passing through the centers of the plurality of transient voltage suppression circuit area formation regions.
　なお、図１に示した例では、全ての第１過渡電圧抑制回路部と全ての第２過渡電圧抑制回路部とが、半導体基板１の主面に垂直な方向から平面視して対称配置されているが、第１過渡電圧抑制回路部の少なくとも一部が対称配置されていてもよい。同様に、第２過渡電圧抑制回路部の少なくとも一部が対称配置されていてもよい。 In the example shown in FIG. 1, all the first transient voltage suppression circuit parts and all the second transient voltage suppression circuit parts are symmetrically arranged in a plan view from the direction perpendicular to the main surface of semiconductor substrate 1. However, at least a part of the first transient voltage suppression circuit unit may be arranged symmetrically. Similarly, at least a part of the second transient voltage suppression circuit unit may be arranged symmetrically.
　ここで、「少なくとも一部が対称配置」の第１の意味は、「複数個の過渡電圧抑制回路部（例えば１０個）のうち一部の回路部（例えば８個）が対称に配置されている」ということである。また、この「少なくとも一部が対称配置」の第２の意味は、「一対の過渡電圧抑制回路部（１個の過渡電圧抑制回路部と、それに対を成す別の過渡電圧抑制回路部と）が、対称な部分と、対称でない部分とを含む」ということである。 Here, the first meaning of "at least a part is symmetrical arrangement" is that "a part of circuit parts (for example, eight) among a plurality of transient voltage suppression circuit parts (for example, ten) are arranged symmetrically. It is Further, the second meaning of the “at least partially symmetrical arrangement” is “a pair of transient voltage suppression circuit units (one transient voltage suppression circuit unit and another transient voltage suppression circuit unit forming a pair) "Includes symmetrical parts and non-symmetrical parts".
　また、「対称配置」とは、必ずしも厳密な意味で対称に配置されていることを意味するものではない。例えば、半導体基板１の主面に垂直な方向から平面視して、第１過渡電圧抑制回路部ＳＣ１１を基準線ＳＬＹに対して線対称となる位置に移動させた場合、ＳＣ１２と一部が重なりあうような配置関係であっても、第１過渡電圧抑制回路部ＳＣ１１と第１過渡電圧抑制回路部ＳＣ１２は対称配置されているといえる。 Also, "symmetrical arrangement" does not necessarily mean that they are arranged symmetrically in a strict sense. For example, when the first transient voltage suppression circuit unit SC11 is moved to a position that is line symmetrical with respect to the reference line SLY in plan view in a direction perpendicular to the main surface of the semiconductor substrate 1, SC12 partially overlaps It can be said that the first transient voltage suppression circuit unit SC11 and the first transient voltage suppression circuit unit SC12 are symmetrically disposed even in the arrangement relationship that matches each other.
　また、「対称配置」とは、基準線ＳＬＹ，ＳＬＸ等の基準線に対して線対称となる配置関係のみならず、基準点に対して点対称となる配置関係を意味していてもよい。例えば図１において、基準線ＳＬＸと基準線ＳＬＹとの交点を基準点と見なせば、第１過渡電圧抑制回路部ＳＣ１１と、第１過渡電圧抑制回路部ＳＣ１３とは点対称の関係にある。同様に、第１過渡電圧抑制回路部ＳＣ１２と、第１過渡電圧抑制回路部ＳＣ１４とは点対称の関係にある。 Furthermore, “symmetrically arranged” may mean not only an arrangement relation that is line-symmetrical to a reference line such as the reference lines SLY and SLX, but also an arrangement relation that is point-symmetrical to a reference point. For example, in FIG. 1, when the intersection of the reference line SLX and the reference line SLY is regarded as a reference point, the first transient voltage suppression circuit unit SC11 and the first transient voltage suppression circuit unit SC13 have a point symmetry relationship. Similarly, the first transient voltage suppression circuit unit SC12 and the first transient voltage suppression circuit unit SC14 are in a point-symmetrical relationship.
　また、「対称配置」とは、基準点に対して点対称となる配置関係だけでなく、基準点を回転中心として回転対称の関係であることを意味していてもよい。例えば図１において、基準線ＳＬＸと基準線ＳＬＹとの交点を基準点と見なせば、第１過渡電圧抑制回路部ＳＣ１１と、第１過渡電圧抑制回路部ＳＣ１２とは略９０度回転対称の関係にある。また、第１過渡電圧抑制回路部ＳＣ１１と、第１過渡電圧抑制回路部ＳＣ１４とは略９０度回転対称の関係にある。同様に、第１過渡電圧抑制回路部ＳＣ１３と、第１過渡電圧抑制回路部ＳＣ１４とは略９０度回転対称の関係にある。また、第１過渡電圧抑制回路部ＳＣ１３と、第１過渡電圧抑制回路部ＳＣ１２とは略９０度回転対称の関係にある。 Furthermore, “symmetrically arranged” may mean not only an arrangement relation that is point symmetrical with respect to a reference point, but also a relation of rotational symmetry with the reference point as a rotation center. For example, in FIG. 1, if the intersection of the reference line SLX and the reference line SLY is regarded as a reference point, the relationship between the first transient voltage suppression circuit SC11 and the first transient voltage suppression circuit SC12 is approximately 90 degrees rotational symmetric. It is in. In addition, the first transient voltage suppression circuit unit SC11 and the first transient voltage suppression circuit unit SC14 are in a relationship of about 90 degrees rotational symmetry. Similarly, the first transient voltage suppression circuit unit SC13 and the first transient voltage suppression circuit unit SC14 are in a relationship of about 90 degrees rotational symmetry. Further, the first transient voltage suppression circuit unit SC13 and the first transient voltage suppression circuit unit SC12 are in a relationship of about 90 degrees rotational symmetry.
　図２（Ａ）は第１過渡電圧抑制回路部の構造を示す平面図であり、図２（Ｂ）はその断面図であり、図２（Ｃ）はその回路図である。 FIG. 2 (A) is a plan view showing the structure of the first transient voltage suppression circuit, FIG. 2 (B) is a cross-sectional view thereof, and FIG. 2 (C) is a circuit diagram thereof.
　第１過渡電圧抑制回路部において、Ｓｉ－Ｐ型半導体基板１の表面にＮ型エピタキシャル層N-EPI1，N-EPI2が形成されていて、このＮ型エピタキシャル層N-EPI1にＮ型領域が形成されていて、Ｎ型エピタキシャル層N-EPI2にＰ型領域が形成されている。これらの層は、先ず、Ｐ型半導体基板表面に第１のＮ型エピタキシャル層N-EPI1を成膜し、この層にＮ型拡散領域を形成し、次に、第２のＮ型エピタキシャル層N-EPI2を成膜し、この層にＰ型拡散領域を形成する、という工程で形成される。 In the first transient voltage suppression circuit portion, N-type epitaxial layers N-EPI1 and N-EPI2 are formed on the surface of the Si-P-type semiconductor substrate 1, and an N-type region is formed in the N-type epitaxial layer N-EPI1. The P-type region is formed in the N-type epitaxial layer N-EPI2. In these layers, first, a first N-type epitaxial layer N-EPI1 is formed on the surface of a P-type semiconductor substrate, an N-type diffusion region is formed in this layer, and then a second N-type epitaxial layer N is formed. The film is formed in a process of forming an EPI 2 film and forming a P-type diffusion region in this layer.
　図２（Ｂ）において、Ｐ型半導体基板１とＮ型拡散領域とで（その界面で）ツェナーダイオードＺＤが構成され、第２Ｎ型エピタキシャル層N-EPI2とＰ型拡散領域とで（第２Ｎ型エピタキシャル層N-EPI2とＰ型拡散領域との界面で）第１ダイオードＨＳＤが構成される。 In FIG. 2B, a Zener diode ZD is formed by (at the interface with) the P-type semiconductor substrate 1 and the N-type diffusion region, and the second N-type epitaxial layer N-EPI2 and the P-type diffusion region A first diode HSD is formed at the interface between the epitaxial layer N-EPI2 and the P-type diffusion region.
　このように、第１過渡電圧抑制回路部は、ツェナーダイオードＺＤと第１ダイオードＨＳＤとの直列接続回路で構成される。また、第１過渡電圧抑制回路部は、半導体基板の主面に垂直な方向に電流経路が生じるように形成されている。第１過渡電圧抑制回路部の周囲はトレンチＴＲで他の領域から隔離されている。 As described above, the first transient voltage suppression circuit unit is configured by a series connection circuit of the Zener diode ZD and the first diode HSD. Further, the first transient voltage suppression circuit portion is formed such that a current path is generated in a direction perpendicular to the main surface of the semiconductor substrate. The periphery of the first transient voltage suppression circuit portion is isolated from other regions by a trench TR.
　図３（Ａ）は第２過渡電圧抑制回路部の構造を示す平面図であり、図３（Ｂ）はその断面図であり、図３（Ｃ）はその回路図である。 FIG. 3A is a plan view showing the structure of the second transient voltage suppression circuit, FIG. 3B is a cross-sectional view thereof, and FIG. 3C is a circuit diagram thereof.
　第２過渡電圧抑制回路部において、Ｐ型半導体基板１の表面にＮ型エピタキシャル層N-EPI1，N-EPI2が形成されていて、Ｎ型エピタキシャル層N-EPI2にＮ型領域が形成されている。これらの層は、先ず、Ｐ型半導体基板１の表面に第１のＮ型エピタキシャル層N-EPI1を成膜し、次に、第２のＮ型エピタキシャル層N-EPI2を成膜し、この第２のＮ型エピタキシャル層N-EPI2にＮ型拡散領域を形成する、という手順で形成される。 In the second transient voltage suppression circuit portion, N-type epitaxial layers N-EPI1 and N-EPI2 are formed on the surface of P-type semiconductor substrate 1, and an N-type region is formed in N-type epitaxial layer N-EPI2. . In these layers, first, a first N-type epitaxial layer N-EPI1 is formed on the surface of the P-type semiconductor substrate 1, and then a second N-type epitaxial layer N-EPI2 is formed. An N-type diffusion region is formed in the N-type epitaxial layer N-EPI2 of FIG.
　図３（Ｂ）において、Ｐ型半導体基板１とＮ型エピタキシャル層N-EPI1とで（その界面で）第２ダイオードＬＳＤが構成される。 In FIG. 3B, the P-type semiconductor substrate 1 and the N-type epitaxial layer N-EPI 1 form (at the interface thereof) a second diode LSD.
　このように、第２過渡電圧抑制回路部は、第２ダイオードＬＳＤで構成される。また、第２過渡電圧抑制回路部は、半導体基板の主面に垂直な方向に電流経路が生じるように形成されている。第２過渡電圧抑制回路部の周囲はトレンチＴＲで他の領域から隔離されている。 Thus, the second transient voltage suppression circuit unit is configured of the second diode LSD. Further, the second transient voltage suppression circuit portion is formed such that a current path is generated in a direction perpendicular to the main surface of the semiconductor substrate. The periphery of the second transient voltage suppression circuit portion is isolated from other regions by a trench TR.
　なお、本発明において「ツェナーダイオード」は、ＰＮ接合領域に逆バイアス電圧が印加されて、そのツェナー効果を利用するダイオードである。また、「第１ダイオード」、「第２ダイオード」は、ＰＮ接合領域に順バイアスまたは逆バイアスの電圧が印加されてその整流作用を利用するダイオードである。 In the present invention, the “Zener diode” is a diode that applies a reverse bias voltage to the PN junction region to utilize the Zener effect. The “first diode” and the “second diode” are diodes that apply a forward bias or reverse bias voltage to the PN junction region to utilize its rectifying function.
　図４は、第１過渡電圧抑制回路部と第２過渡電圧抑制回路部とを並列接続するための第１配線部の構成を示す平面図である。図５は、第１過渡電圧抑制回路部ＳＣ１０と第２過渡電圧抑制回路部ＳＣ２１４１とを通る位置（図４において一点鎖線で示す位置）での部分断面図である。 FIG. 4 is a plan view showing a configuration of a first wiring portion for connecting in parallel the first transient voltage suppression circuit portion and the second transient voltage suppression circuit portion. FIG. 5 is a partial cross-sectional view at a position passing through the first transient voltage suppression circuit unit SC10 and the second transient voltage suppression circuit unit SC2141 (a position indicated by a dashed dotted line in FIG. 4).
　この例では、第１過渡電圧抑制回路部ＳＣ１０の第１ダイオードのアノードと、第２過渡電圧抑制回路部ＳＣ２１４１，ＳＣ２２３１の第２ダイオードのカソードとが、第１配線部ＷＰ１０によって接続されている。また、第１過渡電圧抑制回路部ＳＣ１２の第１ダイオードのアノードと、第２過渡電圧抑制回路部ＳＣ２２１の第２ダイオードのカソードとが、第１配線部ＷＰ１１によって接続されている。同様に、第１過渡電圧抑制回路部ＳＣ１４の第１ダイオードのアノードと、第２過渡電圧抑制回路部ＳＣ２４１の第２ダイオードのカソードとが、第１配線部ＷＰ１２によって接続されている。 In this example, the anode of the first diode of the first transient voltage suppression circuit unit SC10 and the cathode of the second diode of the second transient voltage suppression circuit unit SC2141 and SC2231 are connected by the first wiring unit WP10. Further, the anode of the first diode of the first transient voltage suppression circuit unit SC12 and the cathode of the second diode of the second transient voltage suppression circuit unit SC221 are connected by the first wiring unit WP11. Similarly, the anode of the first diode of the first transient voltage suppression circuit unit SC14 and the cathode of the second diode of the second transient voltage suppression circuit unit SC241 are connected by the first wiring unit WP12.
　第１配線部ＷＰ１０，ＷＰ１１，ＷＰ１２は、複数の過渡電圧抑制回路部形成領域の中心を中心とする点対称の形状（１８０度回転対称形）である。 The first wiring parts WP10, WP11, WP12 are point-symmetrical shapes (180-degree rotational symmetry) centered on the centers of the plurality of transient voltage suppression circuit part formation regions.
　この構造により、一つの第１過渡電圧抑制回路部と二つの第２過渡電圧抑制回路部との並列接続回路一組と、一つの第１過渡電圧抑制回路部と一つの第２過渡電圧抑制回路部との並列接続回路二組が構成される。 According to this structure, a pair of parallel connection circuits of one first transient voltage suppression circuit unit and two second transient voltage suppression circuit units, one first transient voltage suppression circuit unit, and one second transient voltage suppression circuit Two sets of parallel connection circuits with the unit are configured.
　図４に示す第１過渡電圧抑制回路部ＳＣ１０，ＳＣ１２，ＳＣ１４と第２過渡電圧抑制回路部ＳＣ２１４１，ＳＣ２２３１，ＳＣ２２１，ＳＣ２４１以外の第１過渡電圧抑制回路部および第２過渡電圧抑制回路部は外部接続端子に接続されない、つまり、それらは不使用の回路部である。 The first transient voltage suppression circuit unit and the second transient voltage suppression circuit unit other than the first transient voltage suppression circuit units SC10, SC12, and SC14 and the second transient voltage suppression circuit units SC2141, SC2231, SC221, and SC241 shown in FIG. They are not connected to the connection terminals, ie they are unused circuit parts.
　図６（Ａ）、図６（Ｂ）、図６（Ｃ）、図６（Ｄ）、図６（Ｅ）、図６（Ｆ）、図６（Ｇ）は、過渡電圧抑制素子の半導体基板上の各層における各パターンを示す平面図である。図７は過渡電圧抑制素子の所定位置での断面図を簡略的に示したものである。より詳細には、次に述べるとおりである。 6 (A), 6 (B), 6 (C), 6 (D), 6 (E), 6 (F) and 6 (G) show the semiconductor substrate of the transient voltage suppression element. It is a top view which shows each pattern in upper each layer. FIG. 7 schematically shows a cross-sectional view of the transient voltage suppression element at a predetermined position. In more detail, it is as follows.
　図６（Ａ）は、半導体基板１に、第１過渡電圧抑制回路部ＳＣ１０，ＳＣ１２，ＳＣ１４を含む複数の第１過渡電圧抑制回路部と、第２過渡電圧抑制回路部ＳＣ２２１，ＳＣ２４１，ＳＣ２１４１，ＳＣ２２３１を含む複数の第２過渡電圧抑制回路部を形成した状態を示す。図７においては、これら回路部の一つを代表して回路部“ＳＣ”として表している。 In FIG. 6A, a plurality of first transient voltage suppression circuit units including first transient voltage suppression circuit units SC10, SC12, and SC14, and second transient voltage suppression circuit units SC221, SC241, SC2141, and the like in the semiconductor substrate 1 are shown. The state which formed several 2nd transient voltage suppression circuit parts containing SC2231 is shown. In FIG. 7, one of these circuit units is represented as a circuit unit "SC".
　図６（Ｂ）は、図６（Ａ）に示した回路形成部の上部に第１絶縁膜ＩＦ１を形成し、その後、第１絶縁膜ＩＦ１にビア形成用の開口ＡＰ１を形成した状態を示す。 FIG. 6B shows a state in which the first insulating film IF1 is formed on the upper portion of the circuit formation portion shown in FIG. 6A, and thereafter, the opening AP1 for via formation is formed in the first insulating film IF1. .
　図６（Ｃ）は、図６（Ｂ）に示した第１絶縁膜ＩＦ１の上に、第１配線部ＷＰ１０，ＷＰ１１，ＷＰ１２を形成した状態を示す。図７においては、これら第１配線部の一つを代表して第１配線部“ＷＰ１”として表している。第１配線部のうち上記開口ＡＰ１に形成された部分が第１ビアＶ１である。 FIG. 6C shows a state in which the first wiring parts WP10, WP11, and WP12 are formed on the first insulating film IF1 shown in FIG. 6B. In FIG. 7, one of the first wiring portions is represented as a first wiring portion "WP1". A portion of the first wiring portion formed in the opening AP1 is a first via V1.
　図６（Ｄ）は、第１配線部ＷＰ１０，ＷＰ１１，ＷＰ１２上に、第２絶縁膜ＩＦ２を形成し、その後、第２絶縁膜ＩＦ２にビア形成用の開口ＡＰ２を形成した状態を示す。 FIG. 6D shows a state in which the second insulating film IF2 is formed on the first wiring parts WP10, WP11, and WP12, and then the opening AP2 for via formation is formed in the second insulating film IF2.
　図６（Ｅ）は、第２絶縁膜ＩＦ２上に第２配線部ＷＰ２０，ＷＰ２１，ＷＰ２２を形成した状態を示す。図７においては、これら第２配線部の一つを代表して第２配線部“ＷＰ２”として表している。第２配線部のうち上記開口ＡＰ２に形成された部分が第２ビアＶ２である。 FIG. 6E shows a state in which the second wiring portions WP20, WP21, and WP22 are formed on the second insulating film IF2. In FIG. 7, one of the second wiring portions is represented as a second wiring portion "WP2". A portion of the second wiring portion formed in the opening AP2 is a second via V2.
　図６（Ｆ）は、第２配線部ＷＰ２上に、さらにめっき膜Ｍを形成した状態を示す。 FIG. 6F shows a state in which the plating film M is further formed on the second wiring portion WP2.
　図６（Ｇ）は、第２配線部ＷＰ２上およびめっき膜Ｍ上に、第３絶縁膜ＩＦ３を形成し、その後、めっき開口ＡＰ３を形成した状態を示す。このめっき開口ＡＰ３から露出するめっき膜Ｍの一部が外部接続端子Ｐ１，Ｐ２，Ｐ３，Ｐ４，Ｐ５，Ｐ６である。 FIG. 6G shows a state in which the third insulating film IF3 is formed on the second wiring portion WP2 and the plating film M, and then the plating opening AP3 is formed. Parts of the plating film M exposed from the plating opening AP3 are external connection terminals P1, P2, P3, P4, P5, and P6.
　図６（Ａ）に示す回路形成層のパターンは図１に示したとおりである。第１配線部のパターンは図４に示したとおりである。 The pattern of the circuit formation layer shown in FIG. 6A is as shown in FIG. The pattern of the first wiring portion is as shown in FIG.
　上述のとおり、第１ビアＶ１は過渡電圧抑制回路部ＳＣと第１配線部ＷＰ１とを所定位置で層間接続する。第２配線部ＷＰ２は、過渡電圧抑制回路部ＳＣを外部端子へ引き出すための配線である。第２ビアＶ２は第１配線部ＷＰ１と第２配線部ＷＰ２とを所定位置で層間接続する。めっき膜Ｍは第２配線部ＷＰ２の所定位置に形成される。めっき開口ＡＰ３は、外部接続端子となる部分で上記めっき膜を露出させるものである。 As described above, the first via V1 interlayer-connects the transient voltage suppression circuit SC and the first wiring portion WP1 at a predetermined position. The second wiring portion WP2 is a wiring for leading the transient voltage suppression circuit portion SC to the external terminal. The second via V2 interconnects the first wiring portion WP1 and the second wiring portion WP2 at predetermined positions. The plating film M is formed at a predetermined position of the second wiring portion WP2. The plating opening AP3 exposes the plating film at a portion to be an external connection terminal.
　図６に示す外部接続端子Ｐ１，Ｐ４は本発明に係る「第１外部接続端子」に相当し、外部接続端子Ｐ３，Ｐ６は本発明に係る「第２外部接続端子」に相当し、外部接続端子Ｐ２，Ｐ５は本発明に係る「第３外部接続端子」に相当する。グランドに接続される外部接続端子Ｐ２，Ｐ５は、半導体基板の主面に垂直な方向から視て、対称配置の基準線ＳＬＹ上に配置されている。後に示すように、外部接続端子Ｐ２，Ｐ５はグランドに接続される端子である。 The external connection terminals P1 and P4 shown in FIG. 6 correspond to the "first external connection terminal" according to the present invention, and the external connection terminals P3 and P6 correspond to the "second external connection terminal" according to the present invention. The terminals P2 and P5 correspond to the "third external connection terminal" according to the present invention. The external connection terminals P2 and P5 connected to the ground are arranged on the reference line SLY in a symmetrical arrangement as viewed from a direction perpendicular to the main surface of the semiconductor substrate. As described later, the external connection terminals P2 and P5 are terminals connected to the ground.
　本実施形態の過渡電圧抑制素子１０１の半導体基板１は互いに対向する第１辺Ｓ１および第２辺Ｓ２を有し、第１外部接続端子（Ｐ１，Ｐ４）は半導体基板１の第１辺Ｓ１の近傍に配置され、第２外部接続端子（Ｐ３，Ｐ６）は半導体基板１の第２辺Ｓ２の近傍に配置され、第１外部接続端子（Ｐ１，Ｐ４）と第２外部接続端子（Ｐ３，Ｐ６）との間に第３外部接続端子（Ｐ２，Ｐ５）が配置されている。 The semiconductor substrate 1 of the transient voltage suppression element 101 of the present embodiment has the first side S1 and the second side S2 facing each other, and the first external connection terminals (P1, P4) are on the first side S1 of the semiconductor substrate 1. The second external connection terminals P3 and P6 are disposed in the vicinity of the second side S2 of the semiconductor substrate 1, and the first external connection terminals P1 and P4 and the second external connection terminals P3 and P6 are disposed. And third external connection terminals (P2, P5).
　上記第１絶縁膜ＩＦ１はＳｉＮ膜、第１配線部ＷＰ１はパターン化されたＡｌ膜、第２絶縁膜ＩＦ２はエポキシ樹脂膜、第２配線部ＷＰ２はパターン化されたＣｕ膜である。めっき膜Ｍは下地をＮｉ膜、表面をＡｕ膜とするめっき膜である。第３絶縁膜ＩＦ３はエポキシ樹脂膜である。第２絶縁膜ＩＦ２以上の各層は再配線プロセスによって形成される。 The first insulating film IF1 is a SiN film, the first wiring portion WP1 is a patterned Al film, the second insulating film IF2 is an epoxy resin film, and the second wiring portion WP2 is a patterned Cu film. The plating film M is a plating film whose base is a Ni film and whose surface is an Au film. The third insulating film IF3 is an epoxy resin film. Each layer of the second insulating film IF2 or more is formed by the rewiring process.
　図８は本実施形態の過渡電圧抑制素子の回路図である。図９は、回路基板への過渡電圧抑制素子１０１の実装状態を示す図である。 FIG. 8 is a circuit diagram of the transient voltage suppression element of this embodiment. FIG. 9 is a diagram showing the mounting state of the transient voltage suppression element 101 on the circuit board.
　図６、図８に示すように、第１外部接続端子（Ｐ１，Ｐ４）と第２外部接続端子（Ｐ３，Ｐ６）とは第２配線部ＷＰ２０を介して接続されている。この過渡電圧抑制素子１０１は、第１外部接続端子（Ｐ１，Ｐ４）および第２外部接続端子（Ｐ３，Ｐ６）と第３外部接続端子（Ｐ２，Ｐ５）との間に過渡電圧抑制回路が接続された構造である。 As shown in FIGS. 6 and 8, the first external connection terminals (P1, P4) and the second external connection terminals (P3, P6) are connected via the second wiring portion WP20. The transient voltage suppression element 101 has a transient voltage suppression circuit connected between the first external connection terminal (P1, P4) and the second external connection terminals (P3, P6) and the third external connection terminal (P2, P5). Structure.
　図８、図９に示すように、第１外部接続端子（Ｐ１，Ｐ４）および第２外部接続端子（Ｐ３，Ｐ６）は信号ラインＳＬに接続される。また、第３外部接続端子（Ｐ２，Ｐ５）はグランド導体パターンＧＮＤに接続される。 As shown in FIGS. 8 and 9, the first external connection terminals (P1, P4) and the second external connection terminals (P3, P6) are connected to the signal line SL. The third external connection terminals (P2, P5) are connected to the ground conductor pattern GND.
　図９に表れているように、過渡電圧抑制素子１０１はグランド導体パターンＧＮＤを跨いで実装され、信号ラインＳＬと信号ラインＳＬとが過渡電圧抑制素子１０１を介して接続される。 As shown in FIG. 9, the transient voltage suppression element 101 is mounted across the ground conductor pattern GND, and the signal line SL and the signal line SL are connected via the transient voltage suppression element 101.
　本実施形態によれば、次のような効果を奏する。 According to the present embodiment, the following effects can be obtained.
（ａ）第１配線部ＷＰ１（ＷＰ１０，ＷＰ１１，ＷＰ１２）および第２配線部ＷＰ２（ＷＰ２０，ＷＰ２１，ＷＰ２２）は対称形であるので、配線部の寄生成分（寄生インダクタンスまたは寄生容量）の影響は、外部接続端子間で等しい。そのため、過渡電圧抑制素子の実装の向きに関わらず、等しい高周波特性が得られる。 (A) Since the first wiring portion WP1 (WP10, WP11, WP12) and the second wiring portion WP2 (WP20, WP21, WP22) are symmetrical, the influence of the parasitic component (parasitic inductance or parasitic capacitance) of the wiring portion is , Equal between external connection terminals. Therefore, the same high frequency characteristic can be obtained regardless of the mounting direction of the transient voltage suppression element.
（ｂ）静電気（ＥＳＤ）放電等によって過渡電圧抑制素子が破壊される主要因は、過渡電圧抑制素子に電流が流れて、この過渡電圧抑制素子の抵抗成分が発熱することであるが、本実施形態によれば、半導体基板１の全体に分散して電流が流れるので、発熱箇所が分散され、熱の放熱効率が高い。そのため、高いＥＳＤ放電特性、高いＥＳＤ耐量が得られる。 (B) The main factor that the transient voltage suppression element is destroyed by electrostatic discharge (ESD) or the like is that the current flows through the transient voltage suppression element and the resistance component of the transient voltage suppression element generates heat. According to the embodiment, since the current flows while being dispersed throughout the semiconductor substrate 1, the heat generation location is dispersed, and the heat radiation efficiency is high. Therefore, high ESD discharge characteristics and high ESD tolerance can be obtained.
（ｃ）外部接続端子Ｐ２，Ｐ５は、半導体基板１の主面に垂直な方向から視て、対称配置の基準線ＳＬＹ上に配置され、外部接続端子Ｐ２，Ｐ５にそれぞれ接続される配線部（第１配線部ＷＰ１または第２配線部ＷＰ２）の配線の経路長は等しくされている。そのため、配線部の寄生成分（寄生インダクタンスまたは寄生容量）の影響は、外部接続端子間で等しい。したがって、過渡電圧抑制素子の実装の向きに関わらず、等しい高周波特性が得られる。 (C) The external connection terminals P2 and P5 are arranged on the reference line SLY in a symmetrical arrangement when viewed from a direction perpendicular to the main surface of the semiconductor substrate 1, and are connected to the external connection terminals P2 and P5, respectively (wiring portions The path lengths of the wirings of the first wiring portion WP1 or the second wiring portion WP2) are made equal. Therefore, the influence of the parasitic component (parasitic inductance or parasitic capacitance) of the wiring portion is equal between the external connection terminals. Therefore, the same high frequency characteristics can be obtained regardless of the mounting direction of the transient voltage suppression element.
（ｄ）複数の外部接続端子のうち、基準線ＳＬＹ上に設けられている外部接続端子Ｐ２，Ｐ５はグランドに接続される端子であるので、つまり、共通の導体であるグランドに接続される外部接続端子が過渡電圧抑制素子の中央に配置されることになるので、複数の過渡電圧抑制回路部を容易に対称配置できる。 (D) Among the plurality of external connection terminals, the external connection terminals P2 and P5 provided on the reference line SLY are terminals connected to the ground, that is, the external connection connected to the ground which is a common conductor Since the connection terminal is disposed at the center of the transient voltage suppression element, the plurality of transient voltage suppression circuit portions can be easily arranged symmetrically.
（ｅ）第１過渡電圧抑制回路部および第２過渡電圧抑制回路部は、半導体基板１の主面に垂直な方向に電流経路が生じるように形成されているので、第１過渡電圧抑制回路部および第２過渡電圧抑制回路部の面積をそれぞれ小さくでき、半導体基板の限られた面積内に多数の第１過渡電圧抑制回路部および第２過渡電圧抑制回路部を配置できる。 (E) The first transient voltage suppression circuit unit and the second transient voltage suppression circuit unit are formed such that the current path is generated in the direction perpendicular to the main surface of the semiconductor substrate 1. The area of the second transient voltage suppression circuit unit can be reduced, and a large number of first transient voltage suppression circuit units and second transient voltage suppression circuit units can be disposed within the limited area of the semiconductor substrate.
（ｆ）第１過渡電圧抑制回路部は、仮想的な四角形の四つの頂点と、この四角形の中心（または中心近傍）とにそれぞれ配置され、第２過渡電圧抑制回路部は、四つの頂点のうち隣接する頂点の間にそれぞれ配置されるので、複数の第１過渡電圧抑制回路部と複数の第２過渡電圧抑制回路部とが互いに近接配置される。このことにより、配線部の配線を長く引き回すことなく、複数の第１過渡電圧抑制回路部と複数の第２過渡電圧抑制回路部とを備える過渡電圧抑制回路部が構成できる。 (F) The first transient voltage suppression circuit unit is disposed at each of four vertices of the virtual square and the center (or near the center) of the square, and the second transient voltage suppression circuit unit includes four vertexes. Among them, the plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units are disposed in proximity to each other because they are respectively disposed between adjacent apexes. As a result, it is possible to configure a transient voltage suppression circuit unit provided with a plurality of first transient voltage suppression circuit units and a plurality of second transient voltage suppression circuit units without extending the wiring of the wiring unit long.
（ｇ）複数の第１過渡電圧抑制回路部のうち、外部接続端子に接続されない不使用の第１過渡電圧抑制回路部を備え、また、複数の第２過渡電圧抑制回路部のうち、外部接続端子に接続されない不使用の第２過渡電圧抑制回路部を備えるので、必要な第１過渡電圧抑制回路部および第２過渡電圧抑制回路部を選択的に用いて、過渡電圧抑制特性や高周波特性の異なる多種の過渡電圧抑制素子を低コストで商品化できる。 (G) A plurality of first transient voltage suppression circuit units, including an unused first transient voltage suppression circuit unit not connected to the external connection terminal, and an external connection among the plurality of second transient voltage suppression circuit units Since the unused second transient voltage suppression circuit unit not connected to the terminal is provided, the required first transient voltage suppression circuit unit and the second transient voltage suppression circuit unit are selectively used to provide transient voltage suppression characteristics and high frequency characteristics. Various different transient voltage suppressors can be commercialized at low cost.
《第２の実施形態》
　第２の実施形態では、第１の実施形態で示した、特に第１配線部ＷＰ１のパターンを変更することにより、特性の異なる過渡電圧抑制素子を得る例について示す。 Second Embodiment
In the second embodiment, an example of obtaining a transient voltage suppression element having different characteristics by changing the pattern of the first wiring portion WP1 described in the first embodiment, in particular, will be described.
　図１０（Ａ）は、複数の過渡電圧抑制素子を接続する第１配線部のパターンを示す平面図であり、図１０（Ｂ）は第２配線部と外部接続端子のパターンを示す平面図である。図１０（Ｃ）は外部接続端子Ｐ２，Ｐ５へ流れる放電電流の経路を矢印で示す図である。図１０（Ａ）、図１０（Ｂ）、図１０（Ｃ）に示す構造は第１の実施形態で示した過渡電圧抑制素子１０１と同じである。 FIG. 10A is a plan view showing a pattern of a first wiring portion connecting a plurality of transient voltage suppression elements, and FIG. 10B is a plan view showing a pattern of a second wiring portion and an external connection terminal. is there. FIG. 10C is a diagram showing the path of the discharge current flowing to the external connection terminals P2 and P5 by arrows. The structures shown in FIG. 10A, FIG. 10B and FIG. 10C are the same as the transient voltage suppression element 101 shown in the first embodiment.
　図１１（Ａ）、図１１（Ｂ）、図１１（Ｃ）は第２の実施形態に係る過渡電圧抑制素子１０２について示す図である。図１１（Ａ）は第１配線部ＷＰ１（ＷＰ１０，ＷＰ１１，ＷＰ１３）のパターンを示す平面図であり、図１１（Ｂ）は、第２配線部ＷＰ２（ＷＰ２０，ＷＰ２１，ＷＰ２２）と外部接続端子Ｐ１，Ｐ２，Ｐ３，Ｐ４，Ｐ５，Ｐ６のパターンを示す平面図である。図１１（Ｃ）は外部接続端子Ｐ２へ流れる放電電流の経路を矢印で示す図である。過渡電圧抑制素子１０２と過渡電圧抑制素子１０１とは、第１配線部ＷＰ１のパターンだけが異なり、その他の構成は同じである。 FIG. 11A, FIG. 11B, and FIG. 11C are diagrams showing the transient voltage suppression element 102 according to the second embodiment. FIG. 11A is a plan view showing a pattern of the first wiring portion WP1 (WP10, WP11, WP13), and FIG. 11B shows a second wiring portion WP2 (WP20, WP21, WP22) and an external connection terminal. It is a top view which shows the pattern of P1, P2, P3, P4, P5, and P6. FIG. 11C is a diagram showing the path of the discharge current flowing to the external connection terminal P2 by an arrow. The transient voltage suppression element 102 and the transient voltage suppression element 101 are different only in the pattern of the first wiring portion WP1, and the other configurations are the same.
　図１１（Ａ）に示すように、第１配線部ＷＰ１０，ＷＰ１１，ＷＰ１３は基準線ＳＬＹに対して線対称形である。 As shown in FIG. 11A, the first wiring parts WP10, WP11, and WP13 have a linear symmetry with respect to the reference line SLY.
　図１１（Ａ）に示すように、第１配線部ＷＰ１３は第１過渡電圧抑制回路部ＳＣ１１と第２過渡電圧抑制回路部ＳＣ２１１とを接続する。図１１（Ａ）、図１１（Ｂ）、図１１（Ｃ）に示す過渡電圧抑制素子においては、外部接続端子Ｐ２に第１配線部ＷＰ１１，ＷＰ１３が導通するので、この外部接続端子Ｐ２には、第１過渡電圧抑制回路部ＳＣ１１，ＳＣ１２、第２過渡電圧抑制回路部ＳＣ２１１，ＳＣ２２１が接続される。また、外部接続端子Ｐ５はどの過渡電圧抑制素子にも接続されない。したがって、図１０（Ａ）、図１０（Ｂ）、図１０（Ｃ）に示す過渡電圧抑制素子と、図１１（Ａ）、図１１（Ｂ）、図１１（Ｃ）に示す過渡電圧抑制素子との回路は同じである。そのため、外部接続端子Ｐ１，Ｐ３，Ｐ４，Ｐ６と、外部接続端子Ｐ２との間の端子間容量は、図１０（Ｂ）、図１０（Ｃ）における外部接続端子Ｐ１，Ｐ３，Ｐ４，Ｐ６と外部接続端子Ｐ２，Ｐ５との間の端子間容量と同じである。 As shown in FIG. 11A, the first wiring portion WP13 connects the first transient voltage suppression circuit SC11 and the second transient voltage suppression circuit SC211. In the transient voltage suppressing elements shown in FIGS. 11A, 11B and 11C, since the first wiring portions WP11 and WP13 conduct to the external connection terminal P2, the external connection terminal P2 is The first transient voltage suppression circuit units SC11 and SC12 and the second transient voltage suppression circuit units SC211 and SC221 are connected. Also, the external connection terminal P5 is not connected to any transient voltage suppression element. Therefore, the transient voltage suppressor shown in FIGS. 10A, 10B and 10C, and the transient voltage suppressor shown in FIGS. 11A, 11B and 11C. The circuit with is the same. Therefore, the inter-terminal capacitance between the external connection terminals P1, P3, P4 and P6 and the external connection terminal P2 is the same as the external connection terminals P1, P3, P4 and P6 in FIG. 10 (B) and FIG. 10 (C). It is the same as the capacitance between the external connection terminals P2 and P5.
　図１２は二つの過渡電圧抑制素子１０２を差動線路に適用する場合の回路基板への実装状態を示す図である。第１信号ラインＳＬ１に接続される過渡電圧抑制素子１０２と第２信号ラインＳＬ２に接続される過渡電圧抑制素子１０２とは、外部接続端子Ｐ２が互いに隣接する向きに実装される。 FIG. 12 is a view showing a mounting state on a circuit board in the case of applying two transient voltage suppression elements 102 to a differential line. The transient voltage suppression element 102 connected to the first signal line SL1 and the transient voltage suppression element 102 connected to the second signal line SL2 are mounted such that the external connection terminals P2 are adjacent to each other.
　差動線路に二つの過渡電圧抑制素子を接続すると、回路基板上のグランド導体パターンＧＮＤを経由して二つの過渡電圧抑制素子が接続される構造となるので、差動線路はこのグランド導体パターンの寄生インダクタンスの影響を受ける。 When two transient voltage suppression elements are connected to the differential line, the two transient voltage suppression elements are connected via the ground conductor pattern GND on the circuit board. Affected by parasitic inductance.
　第１の実施形態の過渡電圧抑制素子１０１を回路基板に実装すると、回路基板上のグランド導体パターンＧＮＤに流れる電流経路は、外部接続端子Ｐ２同士を繋ぐ経路ＣＰ１と、外部接続端子Ｐ５同士を繋ぐ経路ＣＰ２が形成される。これに対し、第２の実施形態の過渡電圧抑制素子１０２を図１２に示すように実装すると、回路基板上のグランド導体パターンＧＮＤに流れる電流経路は外部接続端子Ｐ２同士を繋ぐ経路ＣＰ１だけとなる。そのため、過渡電圧抑制素子１０２を図１２に示すように実装することで、寄生インダクタンスが小さくなり、差動線の高周波特性の劣化が抑えられる。 When the transient voltage suppression element 101 according to the first embodiment is mounted on a circuit board, the current path flowing through the ground conductor pattern GND on the circuit board connects the external connection terminals P2 with the path CP1 connecting the external connection terminals P2 with each other. The route CP2 is formed. On the other hand, when the transient voltage suppressing element 102 of the second embodiment is mounted as shown in FIG. 12, the current path flowing through the ground conductor pattern GND on the circuit board is only the path CP1 connecting the external connection terminals P2. . Therefore, by mounting the transient voltage suppression element 102 as shown in FIG. 12, the parasitic inductance is reduced and deterioration of the high frequency characteristics of the differential line can be suppressed.
　本実施形態によれば、複数の第１過渡電圧抑制回路部と、複数の第２過渡電圧抑制回路部とを用い、配線部の接続構造を選ぶことで、過渡電圧抑制特性や高周波特性の異なる過渡電圧抑制素子が構成できる。 According to the present embodiment, the transient voltage suppression characteristics and the high frequency characteristics are different by selecting the connection structure of the wiring portion using the plurality of first transient voltage suppression circuit portions and the plurality of second transient voltage suppression circuit portions. A transient voltage suppression element can be configured.
《第３の実施形態》
　第３の実施形態では、過渡電圧抑制回路部の接続数を定めることで、特性の異なる過渡電圧抑制素子を構成する例について示す。 Third Embodiment
In the third embodiment, an example in which transient voltage suppression elements having different characteristics are configured by determining the number of connections of the transient voltage suppression circuit unit will be described.
　図１３（Ａ）は第３の実施形態の過渡電圧抑制素子１０３において、複数の過渡電圧抑制素子を接続する第１配線部のパターンを示す平面図である。 FIG. 13A is a plan view showing a pattern of a first wiring portion connecting a plurality of transient voltage suppression elements in the transient voltage suppression element 103 of the third embodiment.
　図１３（Ａ）に示すように、第１配線部ＷＰ１０は第１過渡電圧抑制回路部ＳＣ１０と第２過渡電圧抑制回路部ＳＣ２１４１，ＳＣ２１４２，ＳＣ２２３１，ＳＣ２２３２とを接続する。また、第１配線部ＷＰ１１は第１過渡電圧抑制回路部ＳＣ１２と第２過渡電圧抑制回路部ＳＣ２１１，ＳＣ２２１とを接続する。同様に、第１配線部ＷＰ１２は第１過渡電圧抑制回路部ＳＣ１４と第２過渡電圧抑制回路部ＳＣ２３１，ＳＣ２４１とを接続する。この第１配線部以外の構成は第１の実施形態で示したものと同じである。 As shown in FIG. 13A, the first wiring unit WP10 connects the first transient voltage suppression circuit unit SC10 and the second transient voltage suppression circuit units SC2141, SC2142, SC2231, and SC2232. The first wiring portion WP11 also connects the first transient voltage suppression circuit SC12 and the second transient voltage suppression circuit SC211 and SC221. Similarly, the first wiring unit WP12 connects the first transient voltage suppression circuit unit SC14 and the second transient voltage suppression circuit units SC231 and SC241. The configuration other than the first wiring portion is the same as that shown in the first embodiment.
　第１配線部ＷＰ１０，ＷＰ１１，ＷＰ１２は複数の過渡電圧抑制回路部形成領域の中心を中心とする点対称の形状（１８０度回転対称形）である。 The first wiring parts WP10, WP11, and WP12 are point-symmetrical shapes (180-degree rotational symmetry) centered on the centers of the plurality of transient voltage suppression circuit part formation regions.
　図１３（Ｂ）は第３の実施形態の過渡電圧抑制素子１０３の回路図である。第８に示した過渡電圧抑制素子１０１の回路とは、第２過渡電圧抑制回路部ＳＣ２３１，ＳＣ２１４２，ＳＣ２２３２，ＳＣ２１１が接続されている点で異なる。 FIG. 13B is a circuit diagram of the transient voltage suppression element 103 according to the third embodiment. The circuit differs from the circuit of transient voltage suppression element 101 shown in the eighth point in that second transient voltage suppression circuit units SC231, SC2142, SC2232, and SC211 are connected.
　本実施形態によれば、第２過渡電圧抑制回路部（第２ダイオード）の数が多くなって、第１の実施形態で示した過渡電圧抑制素子１０１より、更に高いＥＳＤ放電特性および高いＥＳＤ耐量が得られる。 According to the present embodiment, the number of second transient voltage suppression circuit parts (second diodes) is increased, and ESD discharge characteristics and ESD tolerance higher than those of the transient voltage suppression element 101 shown in the first embodiment are increased. Is obtained.
《第４の実施形態》
　第４の実施形態では、２チャンネル分の過渡電圧抑制回路を備える過渡電圧抑制素子の例について示す。 Fourth Embodiment
In the fourth embodiment, an example of a transient voltage suppression element provided with a transient voltage suppression circuit for two channels is shown.
　図１４は第４の実施形態に係る過渡電圧抑制素子１０４の第１配線部構成を示す平面図である。半導体基板に形成される複数の過渡電圧抑制回路部の構成は図１に示したものと同じである。 FIG. 14 is a plan view showing a first wiring portion configuration of the transient voltage suppression element 104 according to the fourth embodiment. The configuration of the plurality of transient voltage suppression circuits formed on the semiconductor substrate is the same as that shown in FIG.
　図１４に示す第１配線部ＷＰ１４は、第１過渡電圧抑制回路部ＳＣ１１，ＳＣ１４と、第２過渡電圧抑制回路部ＳＣ２１４２，ＳＣ２１１，ＳＣ２４１とを接続する。同様に、第１配線部ＷＰ１５は、第１過渡電圧抑制回路部ＳＣ１２，ＳＣ１３と、第２過渡電圧抑制回路部ＳＣ２２３２，ＳＣ２２１，ＳＣ２３１とを接続する。第１配線部ＷＰ１０については第１、第２の実施形態で示したものと同じである。 The first wiring portion WP14 shown in FIG. 14 connects the first transient voltage suppression circuit units SC11 and SC14 and the second transient voltage suppression circuit units SC2142, SC211 and SC241. Similarly, the first wiring unit WP15 connects the first transient voltage suppression circuit units SC12 and SC13 and the second transient voltage suppression circuit units SC2232, SC221, and SC231. The first wiring portion WP10 is the same as that shown in the first and second embodiments.
　図１５（Ａ）、図１５（Ｂ）、図１５（Ｃ）、図１５（Ｄ）、図１５（Ｅ）、図１５（Ｆ）、図１５（Ｇ）は過渡電圧抑制素子の半導体基板上の各層における各パターンを示す平面図である。 15 (A), 15 (B), 15 (C), 15 (D), 15 (E), 15 (F) and 15 (G) are on the semiconductor substrate of the transient voltage suppression element. It is a top view which shows each pattern in each layer of.
　回路形成層のパターンは図１に示したとおりである。第１配線部のパターンは図１４に示したとおりである。第１ビアは過渡電圧抑制回路部と第１配線部とを所定位置で層間接続する。第２配線部は、複数の過渡電圧抑制回路部を外部端子へ引き出すための配線である。第２ビアは第１配線部と第２配線部とを所定位置で層間接続する。めっき膜は第２配線部の所定位置に形成される。めっき開口は、外部接続端子となる部分で上記めっき膜を露出させるものである。第２配線部ＷＰ２３は第２ビアを介して第１配線部ＷＰ１０と導通する。第２配線部ＷＰ２４は第２ビアを介して第１配線部ＷＰ１４と導通する。同様に、第２配線部ＷＰ２５は第２ビアを介して第１配線部ＷＰ１５と導通する。 The pattern of the circuit formation layer is as shown in FIG. The pattern of the first wiring portion is as shown in FIG. The first via connects the transient voltage suppression circuit portion and the first wiring portion in an interlayer at a predetermined position. The second wiring portion is a wiring for leading the plurality of transient voltage suppression circuit portions to the external terminal. The second via interconnects the first wiring portion and the second wiring portion at a predetermined position. The plating film is formed at a predetermined position of the second wiring portion. The plating opening is for exposing the plating film at a portion to be an external connection terminal. The second wiring portion WP23 is electrically connected to the first wiring portion WP10 through the second via. The second wiring portion WP24 is electrically connected to the first wiring portion WP14 through the second via. Similarly, the second wiring portion WP25 is electrically connected to the first wiring portion WP15 via the second via.
　第１の実施形態において図６に示したものとは、第１ビア、第１配線部、第２ビア、第２配線部のパターンが異なる。その他は同じである。 The patterns of the first via, the first wiring portion, the second via, and the second wiring portion are different from those shown in FIG. 6 in the first embodiment. Others are the same.
　図１５に示す外部接続端子Ｐ１，Ｐ４は本発明に係る「第１外部接続端子」に相当し、外部接続端子Ｐ３，Ｐ６は本発明に係る「第２外部接続端子」に相当し、外部接続端子Ｐ２，Ｐ５は本発明に係る「第３外部接続端子」に相当する。これらは第１の実施形態で示した過渡電圧抑制素子１０１と同じである。 The external connection terminals P1 and P4 shown in FIG. 15 correspond to the "first external connection terminal" according to the present invention, and the external connection terminals P3 and P6 correspond to the "second external connection terminal" according to the present invention. The terminals P2 and P5 correspond to the "third external connection terminal" according to the present invention. These are the same as the transient voltage suppression element 101 shown in the first embodiment.
　図１６は本実施形態の過渡電圧抑制素子１０４の回路図である。図１７は、回路基板への過渡電圧抑制素子１０４の実装状態を示す図である。 FIG. 16 is a circuit diagram of the transient voltage suppression element 104 of this embodiment. FIG. 17 is a diagram showing the mounting state of the transient voltage suppression element 104 on the circuit board.
　この過渡電圧抑制素子１０４は、第１外部接続端子（Ｐ１，Ｐ４）と第３外部接続端子（Ｐ２，Ｐ５）との間に第１の過渡電圧抑制回路が接続され、第２外部接続端子（Ｐ３，Ｐ６）と第３外部接続端子（Ｐ２，Ｐ５）との間に第２の過渡電圧抑制回路が接続された構造である。 The transient voltage suppression element 104 has a first transient voltage suppression circuit connected between the first external connection terminal (P1, P4) and the third external connection terminal (P2, P5), and the second external connection terminal A second transient voltage suppression circuit is connected between P3 and P6) and the third external connection terminal (P2 and P5).
　図１７に示すように、第１外部接続端子（Ｐ１，Ｐ４）は第１信号ラインＳＬ１に接続される。同様に、第２外部接続端子（Ｐ３，Ｐ６）は第２信号ラインＳＬ２に接続される。また、第３外部接続端子（Ｐ２，Ｐ５）はグランド導体パターンＧＮＤに接続される。 As shown in FIG. 17, the first external connection terminals (P1, P4) are connected to the first signal line SL1. Similarly, the second external connection terminals (P3, P6) are connected to the second signal line SL2. The third external connection terminals (P2, P5) are connected to the ground conductor pattern GND.
　本実施形態によれば、２チャンネル分の過渡電圧抑制回路部を有する過渡電圧抑制素子として利用できる。図６に示した例と比較すれば明らかなように、同じ半導体基板を用いながら、配線部およびビアのパターンを変更するだけで、１チャンネルの過渡電圧抑制素子と２チャンネルの過渡電圧抑制素子とを選択的に製造することができる。 According to the present embodiment, it can be used as a transient voltage suppression element having a transient voltage suppression circuit unit for two channels. As apparent from comparison with the example shown in FIG. 6, the transient voltage suppression element for one channel and the transient voltage suppression element for two channels can be obtained simply by changing the wiring portion and via pattern while using the same semiconductor substrate. Can be selectively manufactured.
　また、複数の第１過渡電圧抑制回路部と、複数の第２過渡電圧抑制回路部とがそれぞれ対称配置されていて、第１配線部ＷＰ１０，ＷＰ１４，ＷＰ１５、第２配線部ＷＰ２３，ＷＰ２４，ＷＰ２５もそれぞれ対称形であるので、配線部の寄生成分（寄生インダクタンスまたは寄生容量）の影響は、二つのチャンネルについて等しい。そのため、チャンネル間での高周波特性を等しくできる。 In addition, the plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units are symmetrically disposed, and the first wiring portions WP10, WP14, WP15, and the second wiring portions WP23, WP24, WP25 Since each is also symmetrical, the influence of the parasitic component (parasitic inductance or parasitic capacitance) of the wiring part is equal for the two channels. Therefore, high frequency characteristics between channels can be equalized.
《第５の実施形態》
　図１８は第５の実施形態に係る過渡電圧抑制素子の、複数の過渡電圧抑制回路部の形状および配置を示す平面図である。これまでに示した各実施形態とは、第１過渡電圧抑制回路部ＳＣ１０Ａ，ＳＣ１０Ｂを備える点で異なる。この例では、全ての第１過渡電圧抑制回路部ＳＣ１０Ａ，ＳＣ１０Ｂ，ＳＣ１１，ＳＣ１２，ＳＣ１３，ＳＣ１４の平面積は同じである。第１過渡電圧抑制回路部ＳＣ１０Ａ，ＳＣ１０Ｂは基準線ＳＬＹに対して線対称に配置されている。 Fifth Embodiment
FIG. 18 is a plan view showing the shape and the arrangement of a plurality of transient voltage suppression circuits of the transient voltage suppression element according to the fifth embodiment. The embodiments are different from the embodiments described above in that first transient voltage suppression circuit units SC10A and SC10B are provided. In this example, the planar areas of all the first transient voltage suppression circuit units SC10A, SC10B, SC11, SC12, SC13, and SC14 are the same. The first transient voltage suppression circuit units SC10A and SC10B are disposed in line symmetry with respect to the reference line SLY.
　このように、複数の第１過渡電圧抑制回路部の全てが同一面積であってもよい。 Thus, all of the plurality of first transient voltage suppression circuit units may have the same area.
　最後に、上述の実施形態の説明は、すべての点で例示であって、制限的なものではない。当業者にとって変形および変更が適宜可能である。本発明の範囲は、上述の実施形態ではなく、特許請求の範囲によって示される。さらに、本発明の範囲には、特許請求の範囲内と均等の範囲内での実施形態からの変更が含まれる。 Finally, the description of the above embodiments is illustrative in all respects and not restrictive. Modifications and variations are possible as appropriate to those skilled in the art. The scope of the present invention is indicated not by the embodiments described above but by the claims. Furthermore, the scope of the present invention includes modifications from the embodiments within the scope of the claims and equivalents.
　例えば、半導体基板はＰ型に限らず、Ｎ型であってもよい。つまり、ツェナーダイオードＺＤ、第１ダイオード、第２ダイオードそれぞれは、各図に示したＰ型とＮ型が逆の関係であってもよい。 For example, the semiconductor substrate is not limited to P-type, and may be N-type. That is, in each of the Zener diode ZD, the first diode, and the second diode, the P-type and the N-type shown in the respective drawings may have an inverse relationship.
　また、外部接続端子は三つであってもよい。例えば、図１１（Ｂ）、図１１（Ｃ）に示した外部接続端子Ｐ１，Ｐ４を一つに纏め、外部接続端子Ｐ３，Ｐ６を一つに纏め、外部接続端子Ｐ２，Ｐ５を一つに纏めることによって、３端子の過渡電圧抑制素子を構成してもよい。 Also, three external connection terminals may be provided. For example, the external connection terminals P1 and P4 shown in FIGS. 11B and 11C are combined into one, the external connection terminals P3 and P6 are combined into one, and the external connection terminals P2 and P5 are combined into one. The three-terminal transient voltage suppression element may be configured by putting it together.
　また、サイズの異なる複数種の第１過渡電圧抑制回路部を備えてもよい。同様に、サイズの異なる複数種の第２過渡電圧抑制回路部を備えてもよい。 In addition, a plurality of types of first transient voltage suppression circuit units having different sizes may be provided. Similarly, a plurality of second transient voltage suppression circuit units of different sizes may be provided.
ＣＰ１，ＣＰ２…電流経路
ＧＮＤ…グランド導体パターン
ＨＳＤ…第１ダイオード
ＩＦ１…第１絶縁膜
ＩＦ２…第２絶縁膜
ＩＦ３…第３絶縁膜
ＬＳＤ…第２ダイオード
Ｐ１～Ｐ６…外部接続端子
Ｓ１…第１辺
Ｓ２…第２辺
ＳＣ１０，ＳＣ１０Ａ，ＳＣ１０Ｂ，ＳＣ１１，ＳＣ１２，ＳＣ１３，ＳＣ１４…第１過渡電圧抑制回路部
ＳＣ２１１，ＳＣ２１２，ＳＣ２１３，ＳＣ２２１，ＳＣ２２２，ＳＣ２２３，ＳＣ２３１，ＳＣ２３２，ＳＣ２３３，ＳＣ２４１，ＳＣ２４２，ＳＣ２４３，ＳＣ２１４１，ＳＣ２１４２，ＳＣ２２３１，ＳＣ２２３２…第２過渡電圧抑制回路部
ＳＬ…信号ライン
ＳＬ１…第１信号ライン
ＳＬ２…第２信号ライン
ＳＬＸ，ＳＬＹ…基準線
ＴＲ…トレンチ
ＷＰ１，ＷＰ１０～ＷＰ１５…第１配線部
ＷＰ２，ＷＰ２０～ＷＰ２５…第２配線部
ＺＤ…ツェナーダイオード
１…半導体基板
１０１～１０４…過渡電圧抑制素子 CP1, CP2 ... Current path GND ... Ground conductor pattern HSD ... First diode IF1 ... First insulating film IF2 ... Second insulating film IF3 ... Third insulating film LSD ... Second diodes P1 to P6 ... External connection terminal S1 ... First Side S2: second side SC10, SC10A, SC10B, SC11, SC13, SC14: first transient voltage suppression circuit unit SC211, SC212, SC213, SC221, SC222, SC223, SC231, SC232, SC233, SC241, SC242, SC243 , SC2141, SC2142, SC2231, SC2232 ... second transient voltage suppression circuit unit SL ... signal line SL1 ... first signal line SL2 ... second signal line SLX, SLY ... reference line TR ... trench WP1, WP10 to WP15 ... first wiring Department WP2, WP20 WP25 ... second wiring portion ZD ... Zener diode 1 ... semiconductor substrate 101-104 ... transient voltage suppression device

Claims (9)

  1. 　過渡電圧抑制回路部、配線部および外部接続端子が形成された半導体基板を有し、前記過渡電圧抑制回路部と前記配線部とによって過渡電圧抑制回路が構成された過渡電圧抑制素子であって、
    　前記外部接続端子は、前記半導体基板の主面に沿って配置された３つ以上の端子であり、
    　前記過渡電圧抑制回路部は、それぞれツェナーダイオードと第１ダイオードとの直列接続回路を有する複数の第１過渡電圧抑制回路部と、それぞれ第２ダイオードを有する複数の第２過渡電圧抑制回路部とを有し、
    　前記半導体基板の主面に垂直な方向から平面視して、前記複数の第１過渡電圧抑制回路部が前記複数の第２過渡電圧抑制回路部のうち少なくとも１つの前記第２過渡電圧抑制回路部を挟み、且つ前記複数の第２過渡電圧抑制回路部が前記複数の第１過渡電圧抑制回路部のうち少なくとも１つの前記第１過渡電圧抑制回路部を挟むように、前記複数の第１過渡電圧抑制回路部と前記複数の第２過渡電圧抑制回路部とが配置されており、
    　前記半導体基板の主面に垂直な方向から平面視して、前記複数の第１過渡電圧抑制回路部は少なくとも一部が対称配置されていて、前記複数の第２過渡電圧抑制回路部は少なくとも一部が対称配置されている、
    　過渡電圧抑制素子。     A transient voltage suppression element comprising: a semiconductor substrate on which a transient voltage suppression circuit portion, a wiring portion, and an external connection terminal are formed, wherein a transient voltage suppression circuit is configured by the transient voltage suppression circuit portion and the wiring portion.
    The external connection terminals are three or more terminals disposed along the main surface of the semiconductor substrate,
    The transient voltage suppression circuit unit includes a plurality of first transient voltage suppression circuit units each having a series connection circuit of a zener diode and a first diode, and a plurality of second transient voltage suppression circuit units each having a second diode. Have
    The plurality of first transient voltage suppression circuits are at least one of the plurality of second transient voltage suppression circuits, when viewed in a plan view from a direction perpendicular to the main surface of the semiconductor substrate. And the plurality of first transient voltages such that the plurality of second transient voltage suppression circuits sandwich the at least one first transient voltage suppression circuit among the plurality of first transient voltage suppression circuits. A suppression circuit unit and the plurality of second transient voltage suppression circuit units are disposed;
    At least a part of the plurality of first transient voltage suppression circuit portions are symmetrically arranged in plan view in a direction perpendicular to the main surface of the semiconductor substrate, and the plurality of second transient voltage suppression circuit portions are at least one The parts are arranged symmetrically,
    Transient voltage suppressor.
  2. 　前記半導体基板の主面に垂直な方向から平面視して、前記複数の第１過渡電圧抑制回路部は少なくとも一部が基準線を中心に線対称に配置されていて、前記第２過渡電圧抑制回路部は少なくとも一部が前記基準線を中心に線対称に配置されており、
    　前記外部接続端子の少なくとも１つは、前記半導体基板の主面に垂直な方向から視て、前記基準線上に配置されている、
    　請求項１に記載の過渡電圧抑制素子。     At least a part of the plurality of first transient voltage suppression circuits are disposed in line symmetry with respect to the reference line in plan view from a direction perpendicular to the main surface of the semiconductor substrate, and the second transient voltage suppression is performed. At least a part of the circuit portion is disposed in line symmetry with respect to the reference line,
    At least one of the external connection terminals is disposed on the reference line as viewed from a direction perpendicular to the main surface of the semiconductor substrate.
    The transient voltage suppression element according to claim 1.
  3. 　前記外部接続端子のうち、前記基準線上に設けられている外部接続端子はグランドに直接接続される、
    　請求項２に記載の過渡電圧抑制素子。     Among the external connection terminals, an external connection terminal provided on the reference line is directly connected to the ground,
    The transient voltage suppression element according to claim 2.
  4. 　前記複数の第１過渡電圧抑制回路部および前記複数の第２過渡電圧抑制回路部は、前記半導体基板の主面に垂直な方向に電流経路が生じるように形成されている、
    　請求項１から３のいずれかに記載の過渡電圧抑制素子。     The plurality of first transient voltage suppression circuit units and the plurality of second transient voltage suppression circuit units are formed such that current paths are generated in a direction perpendicular to the main surface of the semiconductor substrate.
    The transient voltage suppression element according to any one of claims 1 to 3.
  5. 　前記複数の第１過渡電圧抑制回路部は、四角形の四つの頂点と、前記四角形の内部とにそれぞれ配置され、前記複数の第２過渡電圧抑制回路部は、前記四つの頂点のうち隣接する頂点の間にそれぞれ配置された、
    　請求項１から４のいずれかに記載の過渡電圧抑制素子。     The plurality of first transient voltage suppression circuit units are respectively disposed at four corners of the square and the inside of the square, and the plurality of second transient voltage suppression circuit units are adjacent ones of the four vertices. Placed between
    The transient voltage suppression element according to any one of claims 1 to 4.
  6. 　前記半導体基板は互いに対向する第１辺および第２辺を有し、
    　前記外部接続端子は、第１外部接続端子、第２外部接続端子および第３外部接続端子を有し、
    　前記第１外部接続端子は前記半導体基板の第１辺の近傍に配置され、前記第２外部接続端子は前記半導体基板の第２辺の近傍に配置され、前記第１外部接続端子と前記第２外部接続端子との間に前記第３外部接続端子が配置され、
    　前記第１外部接続端子と前記第２外部接続端子とは前記配線部を介して接続され、
    　前記第１外部接続端子と前記第３外部接続端子との間、および前記第２外部接続端子と前記第３外部接続端子との間に前記過渡電圧抑制回路がそれぞれ接続され、
    　前記第１外部接続端子および前記第２外部接続端子は信号ラインにそれぞれ接続され、前記第３外部接続端子はグランドに接続される、
    　請求項１から５のいずれかに記載の過渡電圧抑制素子。     The semiconductor substrate has a first side and a second side facing each other,
    The external connection terminal includes a first external connection terminal, a second external connection terminal, and a third external connection terminal.
    The first external connection terminal is disposed near the first side of the semiconductor substrate, and the second external connection terminal is disposed near the second side of the semiconductor substrate, and the first external connection terminal and the second external connection terminal are disposed. The third external connection terminal is disposed between the external connection terminal and
    The first external connection terminal and the second external connection terminal are connected via the wiring portion,
    The transient voltage suppression circuit is connected between the first external connection terminal and the third external connection terminal, and between the second external connection terminal and the third external connection terminal.
    The first external connection terminal and the second external connection terminal are each connected to a signal line, and the third external connection terminal is connected to ground.
    The transient voltage suppression element according to any one of claims 1 to 5.
  7. 　前記半導体基板は互いに対向する第１辺および第２辺を有し、
    　前記外部接続端子は、第１外部接続端子、第２外部接続端子および第３外部接続端子を有し、
    　前記第１外部接続端子は前記半導体基板の第１辺の近傍に配置され、前記第２外部接続端子は前記半導体基板の第２辺の近傍に配置され、前記第１外部接続端子と前記第２外部接続端子との間に前記第３外部接続端子が配置され、
    　前記過渡電圧抑制回路は第１の過渡電圧抑制回路と第２の過渡電圧抑制回路とを含み、
    　前記第１外部接続端子と前記第３外部接続端子との間に前記第１の過渡電圧抑制回路が接続され、
    　前記第２外部接続端子と前記第３外部接続端子との間に前記第２の過渡電圧抑制回路が接続され、
    　前記第１外部接続端子は第１信号ラインに接続され、前記第２外部接続端子は第２信号ラインに接続され、前記第３外部接続端子はグランドに接続される、
    　請求項１から５のいずれかに記載の過渡電圧抑制素子。     The semiconductor substrate has a first side and a second side facing each other,
    The external connection terminal includes a first external connection terminal, a second external connection terminal, and a third external connection terminal.
    The first external connection terminal is disposed near the first side of the semiconductor substrate, and the second external connection terminal is disposed near the second side of the semiconductor substrate, and the first external connection terminal and the second external connection terminal are disposed. The third external connection terminal is disposed between the external connection terminal and
    The transient voltage suppression circuit includes a first transient voltage suppression circuit and a second transient voltage suppression circuit,
    The first transient voltage suppression circuit is connected between the first external connection terminal and the third external connection terminal,
    The second transient voltage suppression circuit is connected between the second external connection terminal and the third external connection terminal,
    The first external connection terminal is connected to a first signal line, the second external connection terminal is connected to a second signal line, and the third external connection terminal is connected to ground.
    The transient voltage suppression element according to any one of claims 1 to 5.
  8. 　前記複数の第１過渡電圧抑制回路部のうち、少なくとも一つの第１過渡電圧抑制回路は前記外部接続端子に接続されていない、
    　請求項１から７のいずれかに記載の過渡電圧抑制素子。     At least one first transient voltage suppression circuit among the plurality of first transient voltage suppression circuit units is not connected to the external connection terminal,
    The transient voltage suppression element according to any one of claims 1 to 7.
  9. 　前記複数の第２過渡電圧抑制回路部のうち、少なくとも一つの第２過渡電圧抑制回路は前記外部接続端子に接続されていない、
    　請求項１から８のいずれかに記載の過渡電圧抑制素子。     At least one second transient voltage suppression circuit among the plurality of second transient voltage suppression circuit units is not connected to the external connection terminal,
    The transient voltage suppression element according to any one of claims 1 to 8.
PCT/JP2018/034132 2018-01-19 2018-09-14 Transient voltage suppression element WO2019142394A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023058553A1 (en) * 2021-10-04 2023-04-13 株式会社村田製作所 Transient voltage absorption element

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101083001B1 (en) * 2010-12-23 2011-11-14 김진형 Semiconductor device for protection from static electricity and method for fabricating thereof
US20140319598A1 (en) * 2013-04-24 2014-10-30 Madhur Bobde Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)
JP2015126149A (en) * 2013-12-27 2015-07-06 パナソニックＩｐマネジメント株式会社 Low capacity semiconductor device and method of manufacturing the same
JP2015179776A (en) * 2014-03-19 2015-10-08 株式会社東芝 semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101083001B1 (en) * 2010-12-23 2011-11-14 김진형 Semiconductor device for protection from static electricity and method for fabricating thereof
US20140319598A1 (en) * 2013-04-24 2014-10-30 Madhur Bobde Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)
JP2015126149A (en) * 2013-12-27 2015-07-06 パナソニックＩｐマネジメント株式会社 Low capacity semiconductor device and method of manufacturing the same
JP2015179776A (en) * 2014-03-19 2015-10-08 株式会社東芝 semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023058553A1 (en) * 2021-10-04 2023-04-13 株式会社村田製作所 Transient voltage absorption element

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