CN209766397U - 瞬态电压抑制元件 - Google Patents

瞬态电压抑制元件 Download PDF

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Publication number
CN209766397U
CN209766397U CN201890000306.9U CN201890000306U CN209766397U CN 209766397 U CN209766397 U CN 209766397U CN 201890000306 U CN201890000306 U CN 201890000306U CN 209766397 U CN209766397 U CN 209766397U
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CN
China
Prior art keywords
transient voltage
voltage suppression
external connection
suppression circuit
connection terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201890000306.9U
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English (en)
Chinese (zh)
Inventor
植木纪行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
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Publication of CN209766397U publication Critical patent/CN209766397U/zh
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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201890000306.9U 2018-01-19 2018-09-14 瞬态电压抑制元件 Active CN209766397U (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2018-007154 2018-01-19
JP2018007154 2018-01-19
PCT/JP2018/034132 WO2019142394A1 (fr) 2018-01-19 2018-09-14 Élément de suppression de tension transitoire

Publications (1)

Publication Number Publication Date
CN209766397U true CN209766397U (zh) 2019-12-10

Family

ID=67301345

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201890000306.9U Active CN209766397U (zh) 2018-01-19 2018-09-14 瞬态电压抑制元件

Country Status (2)

Country Link
CN (1) CN209766397U (fr)
WO (1) WO2019142394A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2023058553A1 (fr) * 2021-10-04 2023-04-13

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8981425B2 (en) * 2013-04-24 2015-03-17 Alpha And Omega Semiconductor Incorporated Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)
KR101083001B1 (ko) * 2010-12-23 2011-11-14 김진형 정전기 보호용 반도체 소자 및 그 제조 방법
JP2015126149A (ja) * 2013-12-27 2015-07-06 パナソニックIpマネジメント株式会社 低容量半導体装置およびその製造方法
JP2015179776A (ja) * 2014-03-19 2015-10-08 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
WO2019142394A1 (fr) 2019-07-25

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