WO2019140941A1 - 一种扫描驱动电路、扫描驱动器及显示装置 - Google Patents

一种扫描驱动电路、扫描驱动器及显示装置 Download PDF

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Publication number
WO2019140941A1
WO2019140941A1 PCT/CN2018/106932 CN2018106932W WO2019140941A1 WO 2019140941 A1 WO2019140941 A1 WO 2019140941A1 CN 2018106932 W CN2018106932 W CN 2018106932W WO 2019140941 A1 WO2019140941 A1 WO 2019140941A1
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Prior art keywords
switching element
signal
path end
control
scan driving
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PCT/CN2018/106932
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English (en)
French (fr)
Inventor
吴剑龙
胡思明
朱晖
Original Assignee
昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to EP18900697.6A priority Critical patent/EP3614368A4/en
Priority to JP2019564150A priority patent/JP6923675B2/ja
Priority to KR1020197033213A priority patent/KR102259800B1/ko
Priority to US16/265,717 priority patent/US10839751B2/en
Publication of WO2019140941A1 publication Critical patent/WO2019140941A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms

Definitions

  • the present application belongs to the field of display technologies, and in particular, to a scan driving circuit, a scan driver, and a display device.
  • the organic light-emitting display device utilizes the recombination of electron-hole pairs in a specific material to emit light of a specific wavelength to display an image, and has the advantages of fast response, low power consumption, light weight, wide color gamut and the like.
  • a conventional organic light emitting display device includes a scan driver for sequentially supplying scan signals to scan lines, and a scan driver for sequentially applying scan signals to the pixel units.
  • the scan driving circuit in the scan driver is complicated and takes up a large space.
  • the present application provides a scan driving circuit, a scan driver, and a display device, which can simplify the scan driving circuit by reducing the number of switching elements used, thereby reducing the space occupied by the scan driving circuit and facilitating the narrowness of the display device.
  • the development trend of the border is a scan driving circuit, a scan driver, and a display device, which can simplify the scan driving circuit by reducing the number of switching elements used, thereby reducing the space occupied by the scan driving circuit and facilitating the narrowness of the display device.
  • an embodiment of the present application provides a scan driving circuit, where the scan driving circuit includes a first control module, a second control module, and an output module, wherein the output module includes a first switch unit, a second switch unit, and a scan a driving signal output end, the first switching unit and the second switching unit are connected in parallel and connected in common to the scan driving signal output end, the port of the first switching unit remote from the scan driving signal output end is for receiving the second clock signal, and the second switching unit is far away
  • the port of the scan driving signal output terminal is configured to receive the first reference signal;
  • the first control module is configured to receive the first clock signal and the start signal, and control the working state of the first switch unit according to the first clock signal and the start signal;
  • the second control module is configured to receive the second reference signal, and control the working state of the second switching unit according to the working state of the first control module and the second reference signal.
  • the first control module includes a first switching element, the first switching element includes a first control end, a first path end, and a second path end, and the first control end of the first switching element is configured to receive the first clock signal, a second path end of the first switching element is configured to receive the start signal;
  • the second control module includes a second switching element and a third switching element, wherein the second switching element includes a second control end, a third path end, and a fourth a second control end of the second switching element is connected to the first path end of the first switching element, a fourth path end of the second switching element is configured to receive the first clock signal, and a third control element includes a third control end a fifth path end and a sixth path end, the third control end of the third switching element is configured to receive the first clock signal, and the fifth path end of the third switching element is connected to the third path end of the second switching element, a sixth path end of the three switching element is for receiving the second reference signal;
  • a first switching unit of the output module includes a fourth
  • the first control module further includes a sixth switching element, the sixth switching element includes a sixth control end, an eleventh path end, and a twelfth path end, and the sixth control end of the sixth switching element is configured to receive the second The reference signal, the eleventh path end of the sixth switching element is connected to the second control end of the second switching element, and the twelfth path end of the sixth switching element is connected to the fourth control end of the fourth switching element.
  • the first reference signal is a reference high voltage signal
  • the second reference signal is a reference low voltage signal
  • the output module further includes a first conduction enhancing component, the seventh via end of the fourth switching component is connected to the fourth control terminal through the first conduction enhancement component, and the first conduction enhancement component is configured to reduce the fourth switching component The difficulty of conduction.
  • the first conduction enhancing element is a capacitive element.
  • the output module further includes a second conduction enhancement element, wherein the ninth path end of the fifth switching element is connected to the fifth control end of the fifth switching element through the second conduction enhancement element, and the second conduction enhancement element is used for The conduction difficulty of the fifth switching element is lowered.
  • the second conduction enhancing element is a capacitive element.
  • the second conduction enhancement element is a parasitic capacitance of the fifth switching element.
  • the start signal is a scan driving signal outputted by the scan driving circuit that differs by a preset number of stages.
  • the preset number of stages is one level
  • the start signal of the nth stage is the scan drive signal of the n-1th stage
  • n is an integer greater than 0.
  • At least one of the first to fifth switching elements is a PMOS transistor.
  • the first switching element is a double gate PMOS transistor.
  • first clock signal and the second clock signal have the same duty cycle and period, and the first clock signal and the low level of the second clock signal are interleaved with each other.
  • an embodiment of the present application further provides a scan driver, including the scan drive circuit mentioned in any of the above embodiments.
  • an embodiment of the present application further provides a display device, including the scan driver mentioned in the above embodiment.
  • the display device further includes a data driver, a emission control driver, and a pixel panel, and the pixel panel displays pixels of the image according to the scan driving signal of the scan driver, the emission control signal of the emission control driver, and the data signal of the data driver.
  • the present application provides a scan driving circuit, a scan driver and a display device, the scan driving circuit realizes the first control by means of the first reference signal, the second reference signal, the start signal, the first clock signal and the second clock signal
  • the scan driving circuit realizes the function of outputting the scan driving signal by the scan driving circuit by using fewer components, thereby simplifying the scan driving circuit and reducing
  • the space occupied by the scan driving circuit provides favorable conditions for the development of the narrow frame of the display device.
  • the function of outputting the scan driving signal is realized by means of the first switching element, the second switching element, the third switching element, the fourth switching element and the fifth switching element in the scan driving circuit. .
  • FIG. 1 is a schematic diagram showing the circuit structure of a scan driving circuit according to a first embodiment of the present application
  • FIG. 2 is a waveform diagram of a received signal and an output scan driving signal of the scan driving circuit of the first embodiment of the present application;
  • FIG. 3 is a schematic diagram showing the circuit structure of a scan driving circuit according to a second embodiment of the present application.
  • FIG. 4 is a block diagram of a scan driver of a third embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a display device according to a fourth embodiment of the present application.
  • the scan driving circuit includes a first control module, a second control module, and an output module, where the first control module and the second control module are used to control an output of the output module.
  • the output module includes a first switch unit, a second switch unit, and a scan drive signal output end. The first switch unit and the second switch unit are connected in parallel and are commonly connected to the scan drive signal output end, and the first switch unit is away from the scan drive signal.
  • the port of the output end is for receiving the second clock signal
  • the port of the second switch unit is remote from the output end of the scan driving signal for receiving the first reference signal
  • the first control module is configured to receive the first clock signal and the start signal, and according to the first The clock signal and the start signal control an operating state of the first switching unit
  • the second control module is configured to receive the second reference signal, and control an operating state of the second switching unit according to an operating state of the first control module and a second reference signal.
  • the operating states of the first switching unit and the second switching unit include both the on or off state of the switching unit and the path end state of the switching unit.
  • the scan driving circuit provided by the embodiment of the present application implements the first control module, the second control module, and the output module by means of the first reference signal, the second reference signal, the start signal, the first clock signal, and the second clock signal.
  • the interaction between the two, and the use of fewer components to integrate the scan drive circuit simplifies the structure of the existing scan drive circuit, and provides favorable conditions for the development of the narrow frame of the display device.
  • the first reference signal is a reference high voltage signal
  • the second reference signal is a reference low voltage signal
  • the first reference signal is a reference low voltage signal
  • the second reference signal is a reference high voltage signal. That is to say, the embodiment of the present application does not uniformly define this, as long as the first reference signal and the second reference signal can cooperate with driving the scan driving circuit to complete the function of outputting the scan driving signal.
  • FIG. 1 is a schematic diagram showing the circuit structure of a scan driving circuit according to a first embodiment of the present application
  • FIG. 2 is a waveform diagram of a received signal and an output scan driving signal of the scan driving circuit of the first embodiment of the present application.
  • FIG. 1 and FIG. 2 please refer to FIG. 1 and FIG. 2 at the same time.
  • a first embodiment of the present application provides a scan driving circuit, including a first control module 101 , a second control module 102 , and an output module 103 .
  • the first control module 101 includes a first switching element M1, and the first switching element M1 includes a first control end, a first path end, and a second path end.
  • the first control end of the first switching element M1 receives the first clock signal SCK1, the first path end of the first switching element M1 is connected to the second control end of the second switching element M2, and the second path end of the first switching element M1
  • the start signal SIN is received.
  • the first switching element M1 may be a dual-gate transistor (the transistor in the embodiment of the present application is a MOS transistor, also referred to as a metal-oxide-semiconductor field effect transistor) to reduce parasitic parameters and thereby improve Cut-off frequency.
  • the transistor in the embodiment of the present application is a MOS transistor, also referred to as a metal-oxide-semiconductor field effect transistor
  • the second control module 102 includes a second switching element M2 and a third switching element M3.
  • the second switching element M2 includes a second control end, a third path end and a fourth path end, and the second control end of the second switching element M2 is connected to the first path end of the first switching element M1, and the second switching element M2
  • the third path end is connected to the fifth control end of the fifth switching element M5 of the output module 103, and the fourth path end of the second switching element M2 receives the first clock signal SCK1.
  • the third switching element M3 includes a third control terminal, a fifth path end, and a sixth path end.
  • the third control terminal of the third switching element M3 receives the first clock signal SCK1, and the fifth path end of the third switching element M3
  • the third path end of the second switching element M2 is connected, and the sixth path end of the third switching element M3 receives the reference low voltage VGL.
  • the output module 103 includes a fourth switching element M4 and a fifth switching element M5 for outputting a scan driving signal SCANn.
  • the fourth switching element M4 includes a fourth control terminal, a seventh path end, and an eighth path end, and the fourth control end of the fourth switching element M4 and the first path of the first switching element M1 of the first control module 101
  • the terminal is connected (or the fourth control terminal is connected to the second control terminal of the second switching element M2)
  • the seventh path end of the fourth switching element M4 is connected to the tenth path end of the fifth switching element M5, and the fourth switching element M4
  • the eighth path end receives the second clock signal SCK2.
  • the fourth control end of the fourth switching element M4 is connected to the first path end of the first switching element M1 of the first control module 101 , and therefore, the fourth switching element M4 is controlled to be turned on by the first control module 101 or shut down.
  • the fifth switching element M5 includes a fifth control terminal, a ninth path end, and a tenth path end, and the fifth control end of the fifth switching element M5 is connected to the fifth path end of the third switching element M3 ( Or the fifth control terminal is connected to the third path end of the second switching element M2, the ninth path end of the fifth switching element M5 receives the reference high voltage VGH, and the tenth path end and the fourth switching element of the fifth switching element M5
  • the seventh path end of M4 is connected for outputting the nth stage scan driving signal SCANn, and n is an integer greater than zero.
  • the start signal SIN is a scan drive signal of the n-1th stage. That is to say, except for the scan driving circuit of the first stage, the start signal SIN is the scan drive signal SCAN(n-1) of the previous stage outputted by the scan drive circuit which is one step apart, which is not shown in FIG. Please refer to Figure 2). Further, since the first-stage scan driving circuit does not have the scan driving circuit which differs by one step, the start signal SIN of the first-stage scan driving circuit is to be externally supplied.
  • the fifth control terminal of the fifth switching element M5 is connected to the fifth path end of the third switching element M3 of the second control module 102, the fifth switching element M5 is controlled by the second control module 102. Pass or close.
  • the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 in the scan driving circuit provided by the embodiments of the present application are both P.
  • the transistor in the present embodiment, a P-type MOS transistor
  • the P-type transistor is a transistor that is turned on at a low level.
  • the first switching element M1 may be a dual gate P-type MOS transistor.
  • the double gate structure MOS transistor is a structure that reduces the parasitic parameter to increase the cutoff frequency. It can be grounded through the second gate AC to provide effective electrostatic shielding between the first gate and the drain, thereby greatly reducing the feedback capacitance between the gate and the drain. frequency.
  • FIG. 2 is a waveform diagram of a received signal and an output scan driving signal of the scan driving circuit of the first embodiment of the present application.
  • the first clock signal SCK1 may have the same duty cycle and period as the second clock signal SCK2, and the low levels of the first clock signal SCK1 and the second clock signal SCK2 are interleaved.
  • the duty ratio is the ratio of the low level (or high level) in the clock signal in one cycle (the duty ratio of the low level in this embodiment is twenty-five percent, but not This is limited to).
  • the low level of the first clock signal SCK1 and the second clock signal SCK2 are mutually interleaved, that is, when one of the clock signals is at a low level, the other clock signal cannot be at a low level, and it should be understood that When one of the clock signals is high, the other clock signal can be high at the same time.
  • the start signal SIN, the first clock signal SCK1, and the second clock signal SCK2 are divided into eight stages in one cycle. Among them, the conduction state of each switching element at each stage and the level of the output scan driving signal are as shown in Table 1:
  • the first clock signal SCK1 is at a low level, and since the first control terminal of the first switching element M1 receives the first clock signal SCK1 of the low level, the first switching element M1 and the third switching element M3 lead And because the second path end receiving start signal SIN of the first switching element M1 is also at a low level, the first path end of the first switching element M1 is pulled low, so that the second switching element M2 is turned on. .
  • the sixth path end of the third switching element M3 receives the reference low voltage VGL, so the fifth control end of the fifth switching element M5 passes The turned-on second switching element M2 and the turned-on third switching element M3 are pulled low, such that the fifth switching element M5 is turned on, and the tenth path end of the fifth switching element M5 is turned on by the turned-on fifth switching element M5.
  • the reference high voltage VGH is maintained at a high level, so that the output nth stage scan driving signal SCANn is also at a high level.
  • the fourth control terminal of the fourth switching element M4 is connected to the first path end of the first switching element M1, the fourth control terminal of the fourth switching element M4 is started by the turned-on first switching element M1.
  • the signal SIN is pulled low, so that the fourth switching element M4 is turned on, and since the second clock signal SCK2 is at a high level at this time, the output nth stage scan driving signal SCANn is also maintained at the same time by the second clock signal SCK2. Level.
  • the first clock signal SCK1 changes from a low level to a high level. Therefore, the first switching element M1 and the third switching element M3 are turned off, and the first path end of the first switching element M1 is maintained in the first stage. Passing low level, so the second switching element M2 continues to be turned on, and the third path end of the second switching element M2 is pulled high by the first clock signal SCK1 through the turned-on second switching element M2, so the fifth switching element M5 The fifth control terminal is pulled high and the fifth switching element M5 is turned off.
  • the fourth switching element M4 since the first path end of the first switching element M1 connected to the fourth control terminal of the fourth switching element M4 is at a low level, the fourth switching element M4 is turned on, and since the second clock signal SCK2 is high at this time The level, therefore, the nth stage scan driving signal SCANn is maintained at a high level by the second clock signal SCK2 through the turned-on fourth switching element M4.
  • the first clock signal SCK1 and the start start signal SIN are still at the same level as the second stage, but the second clock signal SCK2 is changed from the high level to the low level, and therefore, the first switching element M1
  • the third switching element M3 is still turned off, the second switching element M2 is still turned on, and the fourth switching element M4 is still turned on, and the fifth switching element M5 is turned off. Therefore, the nth-level scan driving signal SCANn is turned on.
  • the fourth switching element M4 is pulled low by the second clock signal SCK2.
  • the first clock signal SCK1 changes from a high level to a low level. Therefore, the first switching element M1 and the third switching element M3 are both turned on, and because the start signal SIN and the second clock signal SCK2 are both The second control terminal of the second switching element M2 and the fourth path end of the fourth switching element M4 are both pulled up by the start signal SIN through the turned-on first switching element M1, and the second switching element M2 and The fourth switching element M4 is turned off.
  • the third switching element M3 Since the third switching element M3 is turned on, and the fifth control terminal of the fifth switching element M5 is pulled low by the reference low voltage VGL through the turned-on third switching element M3, the fifth switching element M5 is turned on, so that the nth stage The scan driving signal SCANn is maintained at a high level by the reference high voltage VGL through the turned-on fifth switching element M5.
  • the first clock signal SCK1 changes from a low level to a high level, so that the first switching element M1 is turned off, and the first path end of the first switching element M1 maintains the high level of the fifth stage, so the second Both the switching element M2 and the fourth switching element M4 are kept in a closed state.
  • the first clock signal SCK1 is at a high level
  • the third switching element M3 is turned off, and the fifth path end of the third switching element M3 maintains the low level of the fifth stage, so the fifth switching element M5 remains guided.
  • the pass state is maintained while the nth scan drive signal SCANn is maintained at a high level.
  • the first clock signal SCK1 of the seventh and sixth stages is the same as the start signal SIN, and only the second clock signal SCK2 of the seventh stage is different from the second clock signal SCK2 of the sixth stage, and it can be seen from the sixth stage Since the fourth switching element M4 is turned off, the change of the second clock signal SCK2 has no influence on the nth-stage scan driving signal SCANn outputted at this time, so the output n-th scan driving signal SCANn is still maintained at this time. Level.
  • the first clock signal SCK1 of the eighth stage and the sixth stage is the same as the start signal SIN, and the second clock signal SCK2 of the eighth stage and the sixth stage are also the same, so the eighth stage and the sixth stage are identical, so this
  • the n-th scan drive signal SCANn outputted at the time is still maintained at a high level.
  • the scan driving circuit provided by the embodiment of the present application can be output only by the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 which are mutually coupled and connected.
  • the normal scan driving signal due to the use of fewer components, makes the space occupied by the scan driving circuit less, which is beneficial to the development trend of the narrow frame of the display device.
  • FIG. 3 is a schematic diagram showing the circuit structure of a scan driving circuit of a second embodiment of the present application.
  • the scan driving circuit of the embodiment is substantially the same as the scan driving circuit shown in FIG. 1 , except that the first control module 101 further includes: a sixth switching element M6, and the output module 103 further includes: a first capacitor C1 and second capacitor C2.
  • first switching element M1, the second switching element M2, and the third switching element M3 are referred to the first embodiment, and will not be further described herein.
  • the sixth switching element M6 includes a sixth control end, an eleventh path end, and a twelfth path end.
  • the sixth control end of the sixth switching element M6 receives the reference low voltage VGL, and the sixth switching element M6.
  • the eleventh path end is connected to the second control end of the second switching element M2, and the twelfth path end of the sixth switching element M6 is connected to the fourth control end of the fourth switching element M4.
  • the fourth switching element M4 includes a fourth control terminal, a seventh path end, and an eighth path end, and the fourth control end of the fourth switching element M4 is connected to the twelfth path end of the sixth switching element M6.
  • the seventh path end of the fourth switching element M4 can be connected to the fourth control terminal of the fourth switching element M4 through the first capacitor C1, and the eighth path end of the fourth switching element M4 receives the second clock signal SCK2.
  • the connection manner of the first capacitor C1 and the fourth switching element M4 is to improve the coupling effect of the first capacitor C1, thereby reducing the fourth control of the node QA, that is, the fourth switching element M4.
  • the voltage at the terminal achieves a pull-down effect, making the fourth switching element M4 more easily turned on.
  • the first capacitor C1 is the first conduction enhancement element of the output module for reducing the conduction difficulty of the fourth switching element.
  • the first conductive enhancement component may also include other components, which are not uniformly defined in this embodiment of the present application.
  • the fifth switching element M5 includes a fifth control end, a ninth path end, and a tenth path end, and the fifth control end of the fifth switching element M5 is connected to the fifth path end of the third switching element M3.
  • the ninth path end of the fifth switching element M5 receives the reference high voltage VGH, and the ninth path end of the fifth switching element M5 is further connected to the fifth control end of the fifth switching element M5 through the second capacitor C2, the fifth switching element
  • the tenth path end of the M5 is connected to the seventh path end of the fourth switching element for outputting the nth stage scan driving signal, and n is an integer greater than zero.
  • n is an integer greater than zero.
  • the scan driving circuit of the second embodiment of the present application has n stages, and the start signal SIN is the scan driving signal of the n-1th stage.
  • the ninth path end of the fifth switching element M5 receives the reference high voltage, and because the second switching element M2 and/or the third switching element M3 have the possibility of leakage, it may The charge of the fifth control terminal of the fifth switching element M5 is caused to be lost, so the second capacitor C2 is connected to the fifth switching element M5 in order to increase the amount of charge of the node QB, thereby maintaining the voltage of the node QB, so that the fifth switching element The voltage at the fifth control terminal of M5 is more stable, so that the fifth switching element M5 is more easily turned on.
  • the second capacitor C2 is the second conduction enhancement component of the output module for reducing the conduction difficulty of the fifth switching component.
  • the second conductive enhancement component may also include other components, which are not uniformly defined in this embodiment of the present application.
  • the second capacitor C2 may be a parasitic capacitance of the fifth switching element M5.
  • the start signal SIN, the first clock signal SCK1, and the second clock signal SCK2 are divided into eight stages in one cycle. Among them, the conduction state of each switching element at each stage and the output of the scan driving signal are as shown in Table 2:
  • the first clock signal SCK1 is at a low level, and since the first control terminal of the first switching element M1 receives the first clock signal SCK1 of the low level, the first switching element M1 and the third switching element M3 lead And because the start signal SIN received by the second path end of the first switching element M1 is also at a low level at this time, the first path end of the first switching element M1 is pulled low, so that the second switching element M2 leads through.
  • the sixth path end of the third switching element M3 receives the reference low voltage VGL, so the fifth control end of the fifth switching element M5 passes The turned-on second switching element M2 and the turned-on third switching element M3 are pulled low, such that the fifth switching element M5 is turned on, and the tenth path end of the fifth switching element M5 is turned on by the turned-on fifth switching element M5.
  • the reference high voltage VGH is maintained at a high level, so that the output nth stage scan driving signal SCANn is at a high level.
  • the sixth control terminal of the sixth switching element M6 receives the reference low voltage VGL is pulled low, so the sixth switching element M6 is turned on, because the eleventh path end of the sixth switching element M6 and the first switching element M1 are a path end is connected, so that the twelfth path end of the sixth switching element M6 is pulled low, so that the fourth control terminal of the fourth switching element M4 connected to the twelfth path end of the sixth switching element M6 is pulled low, so that The fourth switching element M4 is turned on, and since the second clock signal SCK2 is at a high level at this time, the nth-stage scan driving signal SCANn outputted at this time is also maintained at the high level by the second clock signal SCK2.
  • the first clock signal SCK1 and the start signal SIN are still the same as the second stage (high level), but the second clock signal SCK2 is changed from the high level to the low level, therefore, the first switch The element M1 and the third switching element M3 are turned off, and the first path end of the first switching element M1 maintains the low level of the first stage conduction, so the second switching element M2 continues to be turned on, and the third of the second switching element M2 The path end is pulled up by the first clock signal SCK1 through the turned-on second switching element M2, so the fifth control terminal of the fifth switching element M5 is pulled high, and the fifth switching element M5 is turned off.
  • the sixth switching element M6 since the control terminal of the sixth switching element M6 receives the reference low voltage VGL, the sixth switching element M6 is turned on, since the eleventh path end of the sixth switching element M6 is connected to the first path end of the first switching element M1. Therefore, the twelfth path end of the sixth switching element M6 is pulled low, so that the fourth control terminal of the fourth switching element M4 connected to the twelfth path end of the sixth switching element M6 is also pulled low, so that the fourth switch The component M4 is turned on, and since the second clock signal SCK2 is at a low level at this time, the n-th scan driving signal SCANn outputted at this time is pulled low by the second clock signal SCK2, and at this time, due to the fourth switching element M4 The seventh path terminal is connected to the fourth control terminal of the fourth switching element M4 through the first capacitor C1, which lowers the voltage of the node QA (ie, generates a kickback effect), so that the fourth switching element M4 is more easily turned on, so that
  • the sixth switching element M6 is located between the fourth control end of the fourth switching element M4 and the first path end of the first switching element M1, the first switching element M1 can be prevented from directly being low in voltage with the third stage.
  • the fourth control terminal of the fourth switching element M4 is connected such that the voltage of the first path end of the first switching element M1 is too low, causing damage to the first switching element M1 which is very important in the scan driving circuit provided in this embodiment. Thereby functioning as a protection circuit.
  • the scan driving circuit provided by the second embodiment of the present application includes a first switching element M1, a second switching element M2, a third switching element M3, a fourth switching element M4, a fifth switching element M5, and a sixth switching element M6,
  • a capacitor C1 and a second capacitor C2 can output a normal scan driving signal, and can be referred to as a 6T2C scan driving circuit, wherein the first capacitor C1 can make the fourth switching element M4 easier to conduct and cooperate with the sixth switch.
  • the element M6 can function as a circuit protection, and the second capacitor C2 can make the fifth switching element M5 easier to conduct. Therefore, both the first capacitor C1 and the second capacitor C2 can make the output n-th scan driving signal SCANn more stable. .
  • the number of components used in the scan driving circuit provided by the second embodiment of the present application is smaller than that of the existing scan driving circuit, and the scanning driving circuit provided by the embodiment of the present application also occupies relatively less space, which is more advantageous for display.
  • the development trend of the narrow frame of the device is smaller than that of the existing scan driving circuit, and the scanning driving circuit provided by the embodiment of the present application also occupies relatively less space, which is more advantageous for display.
  • FIG. 4 is a block diagram of a scan driver of a third embodiment of the present application.
  • the scan driver of the third embodiment of the present application please refer to FIG.
  • the third embodiment of the present application provides a scan driver including at least one scan drive circuit as shown in FIG. 1 or FIG. 3 , wherein the specific implementation and benefits of the scan drive circuit can be referred to the first embodiment and the first embodiment.
  • the second embodiment will not be described again here.
  • the scan driver includes an N-stage scan driving circuit (N ⁇ 3), and the scan driving circuit of the current stage is an nth-level driving circuit, wherein N-1 ⁇ n ⁇ 1, the current scanning
  • the driving circuit scan driving signal is SCANn
  • the upper-stage scanning driving signal outputted by the scanning driving circuit of the first-order difference level is SCAN(n-1)
  • the next-stage scanning driving signal outputted by the scanning driving circuit of the first-order difference is one step. Is SCAN(n+1).
  • the scan driver provided by the third embodiment of the present application includes a multi-stage scan driving circuit, and the scan signals of the other stages except the start signal SIN of the scan drive circuit of the first stage need to be externally provided.
  • the scan driving signal outputted by the scan driving circuit of the one step up phase difference is used as the start signal SIN.
  • the internal circuit structure of the scan driver provided by the embodiment of the present application is a multi-stage scan driving circuit provided by the present application. Since the scan driving circuit provided by the present application can output a normal scan driving signal by using fewer components, the present application The space occupied by the provided scan driving circuit is reduced, so that the volume of the scan driver is reduced, thereby facilitating the development trend of the narrow frame of the display device.
  • FIG. 5 is a schematic structural diagram of a display device according to a fourth embodiment of the present application.
  • a fourth embodiment of the present application provides a display device with a scan driver 1, a data driver 2, an emission control driver 3, and a pixel panel 4 provided by the present application.
  • a scan driver 1 for a specific implementation manner and beneficial effects of the scan driver 1, reference may be made to the third embodiment, and details are not described herein again.
  • the pixel panel 4 is capable of displaying a plurality of pixels PXn1, PXn2 of an image according to a scan driving signal supplied from the scan driver 1, a transmission control signal supplied from the emission control driver 3, and a data signal supplied from the data driver 2 (where n is greater than An integer of 0).
  • the pixel PX includes an Organic Light-Emitting Diode (OLED) for emitting light of a driving current corresponding to the data signal.
  • OLED Organic Light-Emitting Diode
  • the scan driver 1 sequentially supplies the multi-level scan signals to the scan lines S1 to Sn according to a control signal supplied from an external control circuit (for example, a timing controller), and then selects a certain row of pixels PXn1, PXn2 by the scan drive signal to correspond
  • the data signals supplied from the data lines D1 to Dm are received.
  • the pixels PXn1, PXn2 are charged (stored) with a voltage corresponding to the data signal and emit light having a luminance component corresponding to the voltage.
  • the emission control driver 3 supplies the emission control signals to the emission control lines E1 to En in order in accordance with a control signal supplied from an external control circuit (for example, a timing controller). Then, the light-emitting time of the pixels PXn1, PXn2 is controlled by transmitting a control signal.
  • an external control circuit for example, a timing controller
  • each pixel PX may form a red pixel that emits red light or a green pixel that emits green light or a blue pixel that emits blue. That is, in an embodiment, the pixel panel 4 includes red pixels, green pixels, and blue pixels. The adjacent at least one red pixel, the at least one green pixel, and the at least blue pixel constitute one pixel unit. Therefore, the pixel unit can emit light of a different color having a luminance corresponding to the driving current, thereby enabling the pixel panel 4 to realize display of a color image.
  • the scan driver 1 and the emission control driver 3 may be additionally mounted in the form of a chip, and/or embedded on the panel together with the pixel circuit elements in the pixel panel 4 to constitute an embedded circuit unit.
  • the display device provided by the embodiment of the present application internally uses the scan driver 1 provided by the above embodiment of the present application. That is to say, the present application achieves the purpose of reducing the frame of the display device by providing the scanning driver provided in the above embodiment in the display device, and further facilitates the development trend of the narrow frame of the display device.

Abstract

本申请提供一种扫描驱动电路、扫描驱动器及显示装置，该扫描驱动电路包括第一控制模块、第二控制模块和输出模块，输出模块包括第一开关单元、第二开关单元和扫描驱动信号输出端，第一开关单元和第二开关单元并行连接且共同连接至扫描驱动信号输出端，第一开关单元远离扫描驱动信号输出端的端口用于接收第二时钟信号，第二开关单元远离扫描驱动信号输出端的端口用于接收第一参考信号；第一控制模块用于根据接收的信号控制第一开关单元的工作状态；第二控制模块用于根据第一控制模块的工作状态和接收的信号控制第二开关单元的工作状态。本申请提供的扫描驱动电路利用较少的元器件实现了输出扫描驱动信号的功能，减少了扫描驱动电路占用的空间。

Description

一种扫描驱动电路、扫描驱动器及显示装置
本申请要求2018年01月19日提交的申请号为No.201810055643.4的中国申请的优先权，通过引用将其全部内容并入本文。
技术领域
本申请属于显示技术领域，尤其涉及一种扫描驱动电路、扫描驱动器及显示装置。
发明背景
近年，国内外开发出了众多类型的显示装置，例如液晶显示装置，等离子显示装置，电润湿显示装置，电泳显示装置，有机发光显示装置等。其中有机发光显示装置利用电子空穴对在特定材料中的复合，发出特定波长的光，来显示图像，具有快速响应，功耗低，轻薄，色域广等优点。
传统的有机发光显示装置包括扫描驱动器以及像素单元，其中，扫描驱动器用于将扫描信号按顺序提供给扫描线，并借助于扫描线将扫描信号按顺序施加到像素单元。然而，扫描驱动器中的扫描驱动电路较复杂，并且占用空间较大。
发明内容
有鉴于此，本申请提供一种扫描驱动电路、扫描驱动器及显示装置，通过减少了开关元件的使用数量，从而简化扫描驱动电路，进而能够减少扫描驱动电路占用的空间，有利于显示装置的窄边框的发展趋势。
本申请是这样实现的：
第一方面，本申请一实施例提供一种扫描驱动电路，该扫描驱动电路包括第一控制模块、第二控制模块和输出模块，其中，输出模块包括第一开关单元、第二开关单元和扫描驱动信号输出端，第一开关单元和第二开关单元并行连接且共同连接至扫描驱动信号输出端，第一开关单元远离扫描驱动信号输出端的端口用于接收第二时钟信号，第二开关单元远离扫描驱动信号输出端的端口用于接收第一参考信号；第一控制模块用于接收第一时钟信号和起始信号，并根据第一时钟信号和起始信号控制第一开关单元的工作状态；第二控制模块用于接收第二参考信号，并根据第一控制模块的工作状态和第二参考信号控制第二开关单元的工作状态。
进一步地，第一控制模块包括第一开关元件，第一开关元件包括第一控制端、第一通路端及第二通路端，第一开关元件的第一控制端用于接收第一时钟信号， 第一开关元件的第二通路端用于接收起始信号；第二控制模块包括第二开关元件和第三开关元件，其中，第二开关元件包括第二控制端、第三通路端及第四通路端，第二开关元件的第二控制端与第一开关元件的第一通路端相连，第二开关元件的第四通路端用于接收第一时钟信号；第三开关元件包括第三控制端、第五通路端及第六通路端，第三开关元件的第三控制端用于接收第一时钟信号，第三开关元件的第五通路端与第二开关元件的第三通路端相连，第三开关元件的第六通路端用于接收第二参考信号；输出模块的第一开关单元包括第四开关元件，输出模块的第二开关单元包括第五开关元件，其中，第四开关元件包括第四控制端、第七通路端及第八通路端，第四开关元件的第四控制端与第二开关元件的第二控制端相连，第四开关元件的第八通路端用于接收第二时钟信号；第五开关元件包括第五控制端、第九通路端及第十通路端，第五开关元件的第五控制端与第三开关元件的第五通路端相连，第五开关元件的第九通路端用于接收第一参考信号，第五开关元件的第十通路端与第四开关元件的第七通路端相连。
进一步地，第一控制模块还包括第六开关元件，第六开关元件包括第六控制端、第十一通路端及第十二通路端，第六开关元件的第六控制端用于接收第二参考信号，第六开关元件的第十一通路端与第二开关元件的第二控制端相连，第六开关元件的第十二通路端与第四开关元件的第四控制端相连。
进一步地，第一参考信号为参考高电压信号，第二参考信号为参考低电压信号。
进一步地，输出模块还包括第一导通增强元件，第四开关元件的第七通路端通过第一导通增强元件与第四控制端相连，第一导通增强元件用于降低第四开关元件的导通难度。
进一步地，第一导通增强元件为电容元件。
进一步地，输出模块还包括第二导通增强元件，第五开关元件的第九通路端通过第二导通增强元件与第五开关元件的第五控制端相连，第二导通增强元件用于降低第五开关元件的导通难度。
进一步地，第二导通增强元件为电容元件。
进一步地，第二导通增强元件为第五开关元件的寄生电容。
进一步地，起始信号为相差预设级数的扫描驱动电路输出的扫描驱动信号。
进一步地，预设级数为一级，第n级的起始信号为第n-1级的扫描驱动信号，n为大于0的整数。
进一步地，第一开关元件至第五开关元件中至少一个为PMOS管。
进一步地，第一开关元件为双栅极的PMOS管。
进一步地，第一时钟信号和第二时钟信号具有相同的占空比和周期，并且第一时钟信号与第二时钟信号的低电平相互交错。
第二方面，本申请一实施例还提供一种扫描驱动器，包括上述任一实施例所提及的扫描驱动电路。
第三方面，本申请一实施例还提供一种显示装置，包括上述实施例所提及的扫描驱动器。
进一步地，显示装置还包括数据驱动器、发射控制驱动器和像素面板，像素面板根据扫描驱动器的扫描驱动信号、发射控制驱动器的发射控制信号和所述数据驱动器的数据信号显示图像的像素。
本申请提供了一种扫描驱动电路、扫描驱动器及显示装置，该扫描驱动电路借助于第一参考信号、第二参考信号、起始信号、第一时钟信号和第二时钟信号实现了第一控制模块、第二控制模块和输出模块之间的相互配合联动，因此本申请提供的扫描驱动电路利用较少的元器件实现了扫描驱动电路输出扫描驱动信号的功能，从而简化了扫描驱动电路、减少了扫描驱动电路占用的空间，为显示装置的窄边框发展提供了有利条件。尤其是在本申请一实施例中，借助于扫描驱动电路中的第一开关元件、第二开关元件、第三开关元件、第四开关元件及第五开关元件就实现了输出扫描驱动信号的功能。
附图简要说明
图1是本申请第一实施例的扫描驱动电路的电路结构示意图；
图2是本申请第一实施例的扫描驱动电路的接收的信号与输出的扫描驱动信号的波形示意图；
图3是本申请第二实施例的扫描驱动电路的电路结构示意图；
图4是本申请第三实施例的扫描驱动器的模块示意图；
图5是本申请第四实施例提供的显示装置的结构示意图。
实施本发明的方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
尽管本申请使用第一、第二、第三等术语来描述不同的元件、信号、端口等，但是这些元件、信号、端口等并不受这些术语的限制。这些术语仅是用来将一个元件、信号、端口与另一个元件、信号、端口区分开来。在本申请中，一个元件、端口与另一个元件、端口“相连”、“连接”，可以理解为直接电性连接，或者也可 以理解为存在中间元件的间接电性连接。除非另有定义，否则本申请所使用的所有术语(包括技术术语和科学术语)具有与本申请所属领域的普通技术人员所通常理解的意思。
在本申请一实施例提供的扫描驱动电路中，该扫描驱动电路包括第一控制模块、第二控制模块和输出模块，第一控制模块和所述第二控制模块用于控制输出模块的输出，其中，输出模块包括第一开关单元、第二开关单元和扫描驱动信号输出端，第一开关单元和第二开关单元并行连接且共同连接至扫描驱动信号输出端，第一开关单元远离扫描驱动信号输出端的端口用于接收第二时钟信号，第二开关单元远离扫描驱动信号输出端的端口用于接收第一参考信号；第一控制模块用于接收第一时钟信号和起始信号，并根据第一时钟信号和起始信号控制第一开关单元的工作状态；第二控制模块用于接收第二参考信号，并根据第一控制模块的工作状态和第二参考信号控制第二开关单元的工作状态。
应当理解，第一开关单元和第二开关单元的工作状态既包括开关单元的导通或关闭状态，又包括开关单元的通路端状态。
本申请实施例提供的扫描驱动电路，借助于第一参考信号、第二参考信号、起始信号、第一时钟信号和第二时钟信号实现了第一控制模块、第二控制模块和输出模块之间的相互配合联动，进而利用较少的元器件集成了扫描驱动电路，简化了现有扫描驱动电路的结构，为显示装置的窄边框发展提供了有利条件。
优选地，第一参考信号为参考高电压信号，第二参考信号为参考低电压信号；亦或者第一参考信号为参考低电压信号，第二参考信号为参考高电压信号。也就是说，本申请实施例对此不进行统一限定，只要第一参考信号和第二参考信号能够配合驱动上述扫描驱动电路完成输出扫描驱动信号的功能即可。
下面结合附图对本申请实施例做进一步详述。
第一实施例：
图1是本申请第一实施例的扫描驱动电路的电路结构示意图，图2是本申请第一实施例的扫描驱动电路的接收的信号与输出的扫描驱动信号的波形示意图。为了清楚地描述本申请提供的扫描驱动电路，请同时参见图1和图2。
参见图1，本申请第一实施例提供了一种扫描驱动电路，包括第一控制模块101、第二控制模块102以及输出模块103。
其中，第一控制模块101包括第一开关元件M1，第一开关元件M1包括第一控制端、第一通路端及第二通路端。第一开关元件M1的第一控制端接收第一时钟信号SCK1，第一开关元件M1的第一通路端连接至第二开关元件M2的第二控制端，第一开关元件M1的第二通路端接收起始信号SIN。
在一实施方式中，第一开关元件M1可以为双栅极的晶体管(本申请实施例中晶体管为MOS管，又称金属-氧化物-半导体场效应晶体管)，以减小寄生参量、 从而提高截止频率。
其中，第二控制模块102包括第二开关元件M2和第三开关元件M3。第二开关元件M2包括第二控制端、第三通路端及第四通路端，第二开关元件M2的第二控制端与第一开关元件M1的第一通路端相连，第二开关元件M2的第三通路端连接至输出模块103的第五开关元件M5的第五控制端，第二开关元件M2的第四通路端接收第一时钟信号SCK1。第三开关元件M3包括第三控制端、第五通路端及第六通路端，第三开关元件M3的第三控制端接收第一时钟信号SCK1，第三开关元件M3的第五通路端与第二开关元件M2的第三通路端相连，第三开关元件M3的第六通路端接收参考低电压VGL。
参见图1，输出模块103包括第四开关元件M4和第五开关元件M5，用于输出扫描驱动信号SCANn。
具体地，第四开关元件M4包括第四控制端、第七通路端及第八通路端，第四开关元件M4的第四控制端与第一控制模块101的第一开关元件M1的第一通路端相连(或者第四控制端与第二开关元件M2的第二控制端相连)，第四开关元件M4的第七通路端与第五开关元件M5的第十通路端相连，第四开关元件M4的第八通路端接收第二时钟信号SCK2。
参见图1，第四开关元件M4的第四控制端与第一控制模块101的第一开关元件M1的第一通路端相连，因此，第四开关元件M4由第一控制模块101控制导通或关闭。
其中，参考图1，第五开关元件M5包括第五控制端、第九通路端及第十通路端，第五开关元件M5的第五控制端与第三开关元件M3的第五通路端相连(或者第五控制端与第二开关元件M2的第三通路端相连)，第五开关元件M5的第九通路端接收参考高电压VGH，第五开关元件M5的第十通路端与第四开关元件M4的第七通路端相连，用于输出第n级扫描驱动信号SCANn，且n为大于0的整数。
在一实施方式中，其中，当n大于1时，起始信号SIN为第n-1级的扫描驱动信号。也就是说，除第一级的扫描驱动电路外，起始信号SIN为向上相差一级的扫描驱动电路输出的上一级的扫描驱动信号SCAN(n-1)(图1中未示出，请参考图2)。此外，由于第一级扫描驱动电路没有向上相差一级的扫描驱动电路，所以第一级扫描驱动电路的起始信号SIN要由外部提供。
参见图1，由于第五开关元件M5的第五控制端与第二控制模块102的第三开关元件M3的第五通路端相连，因此，第五开关元件M5由第二控制模块102控制其导通或关闭。
在一实施方式中，本申请实施例提供的扫描驱动电路中的第一开关元件M1、第二开关元件M2、第三开关元件M3、第四开关元件M4、第五开关元件M5、均 为P型晶体管(本实施例中为P型MOS管)，P型晶体管为低电平导通的晶体管。在一实施方式中，第一开关元件M1可以为双栅极的P型MOS管。双栅极结构MOS管是通过减小寄生参量、以提高截止频率的一种结构。它可以通过第二个栅极交流接地，可在第一个栅极和漏极之间起到有效的静电屏蔽作用，从而使得栅极与漏极之间的反馈电容大大减小，则提高了频率。
参见图2，图2是本申请第一实施例的扫描驱动电路的接收的信号与输出的扫描驱动信号的波形示意图。如图2所示，第一时钟信号SCK1可以与第二时钟信号SCK2具有相同的占空比和周期，并且第一时钟信号SCK1与第二时钟信号SCK2的低电平相互交错。其中，占空比是一个周期中的时钟信号中的低电平(或高电平)所占的比例(本实施例中低电平的占空比为百分之二十五，但并不以此为限)。
其中，第一时钟信号SCK1与第二时钟信号SCK2的低电平相互交错，也就是说，当其中一个时钟信号处于低电平时，另一个时钟信号不能为低电平，且应当理解的是，当其中一个时钟信号处为高电平时，另一个时钟信号可以同时为高电平。
参见图2，在一个周期中将起始信号SIN、第一时钟信号SCK1和第二时钟信号SCK2分成了8个阶段。其中，在每一个阶段的各开关元件的导通情况及输出的扫描驱动信号的电平情况，如表1所示：
表1
Figure PCTCN2018106932-appb-000001
具体地：
第1阶段，第一时钟信号SCK1为低电平，由于第一开关元件M1的第一控制端接收低电平的第一时钟信号SCK1，因此，第一开关元件M1及第三开关元件M3导通，又因为第一开关元件M1的第二通路端接收起始信号SIN此时也为低电平，所以第一开关元件M1的第一通路端被拉低，这样第二开关元件M2导通。由于第二开关元件M2的第四通路端接收低电平的第一时钟信号SCK1，第三开关 元件M3的第六通路端接收参考低电压VGL，因此第五开关元件M5的第五控制端通过导通的第二开关元件M2及导通的第三开关元件M3被拉低，这样第五开关元件M5导通，第五开关元件M5的第十通路端通过导通的第五开关元件M5被参考高电压VGH维持在高电平，从而此时输出的第n级扫描驱动信号SCANn也为高电平。此外，由于第四开关元件M4的第四控制端与第一开关元件M1的第一通路端相连，因此，第四开关元件M4的第四控制端通过导通的第一开关元件M1被起始信号SIN拉低，这样第四开关元件M4导通，又由于第二时钟信号SCK2此时为高电平，故此时输出的第n级扫描驱动信号SCANn还同时被第二时钟信号SCK2维持在高电平。
第2阶段，第一时钟信号SCK1由低电平变为高电平，因此，第一开关元件M1及第三开关元件M3关闭，且第一开关元件M1的第一通路端保持第1阶段导通的低电平，所以第二开关元件M2继续导通，第二开关元件M2的第三通路端通过导通的第二开关元件M2被第一时钟信号SCK1拉高，所以第五开关元件M5的第五控制端被拉高，第五开关元件M5被关闭。此外，由于与第四开关元件M4的第四控制端相连的第一开关元件M1第一通路端为低电平，所以第四开关元件M4导通，且由于第二时钟信号SCK2此时为高电平，因此，第n级扫描驱动信号SCANn通过导通的第四开关元件M4被第二时钟信号SCK2维持在高电平。
第3阶段，第一时钟信号SCK1和起始起始信号SIN依然跟第2阶段一样为高电平，但第二时钟信号SCK2由高电平变为低电平，因此，第一开关元件M1与第三开关元件M3仍然关闭，第二开关元件M2仍然导通，且第四开关元件M4也依然被导通、第五开关元件M5关闭，因此，第n级扫描驱动信号SCANn通过导通的第四开关元件M4被第二时钟信号SCK2拉低。
第4阶段，因为第4阶段的第一时钟信号SCK1、起始信号SIN和第二时钟信号SCK2与第2阶段的第一时钟信号SCK1、起始信号SIN和第二时钟信号SCK2一致，所以此时的第一开关元件M1关闭、第二开关元件M2导通、第三开关元件M3关闭、第四开关元件M4导通、第五开关元件M5关闭，输出的第n级扫描驱动信号SCANn通过导通的第四开关元件M4被第二时钟信号SCK2拉高。
第5阶段，第一时钟信号SCK1由高电平变为低电平，因此，第一开关元件M1及第三开关元件M3均导通，又因为起始信号SIN及第二时钟信号SCK2均为高电平，所以第二开关元件M2的第二控制端及第四开关元件M4的第四通路端均通过导通的第一开关元件M1被起始信号SIN拉高，第二开关元件M2及第四开关元件M4均被关闭。由于第三开关元件M3导通，且第五开关元件M5的第五控制端通过导通的第三开关元件M3被参考低电压VGL拉低，所以第五开关元件M5导通，这样第n级扫描驱动信号SCANn通过导通的第五开关元件M5被参考高电压VGL维持在高电平。
第6阶段，第一时钟信号SCK1由低电平变为高电平，因此第一开关元件M1被关闭，第一开关元件M1的第一通路端保持第5阶段的高电平，所以第二开关元件M2及第四开关元件M4均保持关闭状态。但因为第一时钟信号SCK1为高电平，所以第三开关元件M3被关闭，且第三开关元件M3的第五通路端保持第5阶段的低电平，因此第五开关元件M5仍然保持导通状态，而将第n级扫描驱动信号SCANn维持在高电平。
第7阶段和第6阶段的第一时钟信号SCK1和起始信号SIN相同，且第7阶段仅第二时钟信号SCK2与第6阶段的第二时钟信号SCK2不同，并从第6阶段可以看出，由于第四开关元件M4被关闭，因此第二时钟信号SCK2的改变对此时输出的第n级扫描驱动信号SCANn并无影响，因此此时输出的第n级扫描驱动信号SCANn依然维持在高电平。
第8阶段和第6阶段的第一时钟信号SCK1和起始信号SIN相同，且第8阶段和第6阶段的第二时钟信号SCK2也相同，所以第8阶段和第6阶段完全相同，因此此时输出的第n级扫描驱动信号SCANn依然维持在高电平。
本申请实施例提供的扫描驱动电路，仅借助于相互配合连接的第一开关元件M1、第二开关元件M2、第三开关元件M3、第四开关元件M4及第五开关元件M5，就能够输出正常的扫描驱动信号，由于使用的元器件较少，使得该扫描驱动电路占用的空间减少，有利于显示装置的窄边框的发展趋势。
第二实施例：
图3是本申请第二实施例的扫描驱动电路的电路结构示意图。为了清楚的描述本申请第二实施例的扫描驱动电路，请同时参考图2和图3。本实施例的扫描驱动电路与如图1所示的扫描驱动电路基本相同，不同之处仅仅在于：第一控制模块101还包括：第六开关元件M6，且输出模块103还包括：第一电容C1和第二电容C2。
其中，在一实施方式中，第一开关元件M1、第二开关元件M2和第三开关元件M3的具体实施方式及有益效果参考第一实施例，在此将不再赘述。
其中，参考图3，第六开关元件M6包括第六控制端、第十一通路端及第十二通路端，第六开关元件M6的第六控制端接收参考低电压VGL，第六开关元件M6的第十一通路端与第二开关元件M2的第二控制端相连，第六开关元件M6的第十二通路端与第四开关元件M4的第四控制端相连。
其中，参见图3，第四开关元件M4包括第四控制端、第七通路端及第八通路端，第四开关元件M4的第四控制端与第六开关元件M6的第十二通路端相连，且第四开关元件M4的第七通路端可以通过第一电容C1与第四开关元件M4的第四控制端相连，第四开关元件M4的第八通路端接收第二时钟信号SCK2。当然，本领域的技术人员可以理解的是，第一电容C1与第四开关元件M4的连接方式是 为了提高第一电容C1的耦合效应，从而降低节点QA即第四开关元件M4的第四控制端的电压，实现拉低效果，使得第四开关元件M4更容易被导通。
也就是说，第一电容C1为输出模块的第一导通增强元件，用于降低第四开关元件的导通难度。应当理解，第一导通增强元件亦可以包括其它元器件，本申请实施例对此不进行统一限定。
其中，参见图3，第五开关元件M5包括第五控制端、第九通路端及第十通路端，第五开关元件M5的第五控制端与第三开关元件M3的第五通路端相连，第五开关元件M5的第九通路端接收参考高电压VGH，并且第五开关元件M5的第九通路端还通过第二电容C2与第五开关元件M5的第五控制端相连，第五开关元件M5的第十通路端与第四开关元件的第七通路端相连，用于输出第n级扫描驱动信号，且n为大于0的整数。其中，当n大于1时，本申请第二实施例的扫描驱动电路有n级，起始信号SIN为第n-1级的扫描驱动信号。
当然本领域的技术人员可以理解的是，由于第五开关元件M5的第九通路端接收参考高电压，并且由于第二开关元件M2和/或第三开关元件M3有漏电的可能，因此可能会引起第五开关元件M5的第五控制端的电荷流失，所以第二电容C2与第五开关元件M5的连接方式是为了增大节点QB的电荷量，从而保持节点QB的电压，使第五开关元件M5的第五控制端处的电压更稳定，从而使得第五开关元件M5更容易被导通。
也就是说，第二电容C2为输出模块的第二导通增强元件，用于降低第五开关元件的导通难度。应当理解，第二导通增强元件亦可以包括其它元器件，本申请实施例对此不进行统一限定。
在一实施方式中，第二电容C2可以是第五开关元件M5的寄生电容。
具体地，多级扫描驱动电路中每一级扫描驱动电路输出的扫描驱动信号SCANn、第一时钟信号SCK1和第二时钟信号SCK2的具体实施方式参考第一实施例，在此将不再赘述。
同样参考图2，在一个周期中将起始信号SIN、第一时钟信号SCK1、第二时钟信号SCK2分成8个阶段。其中，在每一个阶段的各开关元件的导通情况及输出的扫描驱动信号情况，如表2所示：
表2
Figure PCTCN2018106932-appb-000002
具体地：
第1阶段，第一时钟信号SCK1为低电平，由于第一开关元件M1的第一控制端接收低电平的第一时钟信号SCK1，因此，第一开关元件M1及第三开关元件M3导通，又因为第一开关元件M1的第二通路端接收的起始信号SIN此时也为低电平，所以第一开关元件M1的第一通路端被拉低，这样第二开关元件M2导通。由于第二开关元件M2的第四通路端接收低电平的第一时钟信号SCK1，第三开关元件M3的第六通路端接收参考低电压VGL，因此第五开关元件M5的第五控制端通过导通的第二开关元件M2及导通的第三开关元件M3被拉低，这样第五开关元件M5导通，第五开关元件M5的第十通路端通过导通的第五开关元件M5被参考高电压VGH维持在高电平，从而此时输出的第n级扫描驱动信号SCANn为高电平。此外，第六开关元件M6的第六控制端接收参考低电压VGL被拉低，所以第六开关元件M6导通，由于第六开关元件M6的第十一通路端与第一开关元件M1的第一通路端相连，因此第六开关元件M6的第十二通路端被拉低，从而使连接第六开关元件M6的第十二通路端的第四开关元件M4的第四控制端被拉低，这样第四开关元件M4导通，又由于第二时钟信号SCK2此时为高电平，故此时输出的第n级扫描驱动信号SCANn还同时被第二时钟信号SCK2维持在高电平。
以下的第2-8阶段的分析方式，参考第一实施例和本实施例第1阶段的分析方式，其中第六开关元件M6仅在第3阶段关闭，在第2阶段、第4-8阶段均为导通，因此对第2阶段、第4-8阶段的各开关元件的导通情况和输出的扫描驱动信号的情况参考第一实施例和本实施例第1阶段的分析方式，在此将不再赘述。
其中，第3阶段，第一时钟信号SCK1和起始信号SIN依然跟第2阶段一样(为高电平)，但第二时钟信号SCK2由高电平变为低电平，因此，第一开关元件M1与第三开关元件M3关闭，且第一开关元件M1的第一通路端保持第1阶段导 通的低电平，所以第二开关元件M2继续导通，第二开关元件M2的第三通路端通过导通的第二开关元件M2被第一时钟信号SCK1拉高，所以第五开关元件M5的第五控制端被拉高，第五开关元件M5被关闭。此外，由于第六开关元件M6的控制端接收参考低电压VGL，所以第六开关元件M6导通，由于第六开关元件M6的第十一通路端与第一开关元件M1的第一通路端相连，因此第六开关元件M6的第十二通路端被拉低，从而使连接第六开关元件M6的第十二通路端的第四开关元件M4的第四控制端也被拉低，这样第四开关元件M4导通，又由于第二时钟信号SCK2此时为低电平，故此时输出的第n级扫描驱动信号SCANn被第二时钟信号SCK2拉低，且此时由于第四开关元件M4的第七通路端通过第一电容C1与第四开关元件M4的第四控制端相连，会拉低节点QA的电压(即产生回踢效应)，使得第四开关元件M4更容易导通，这样就能使输出的第n级扫描驱动信号SCANn的低电平更稳定。
但由于第一电容C1的存在会产生回踢效应，拉低了节点QA的电压，会使得第六开关元件M6的第十二通路端的电压比第六开关元件M6的第六控制端的电压还要低，会导致第六开关元件M6等同于关闭状态，所以当输出的第n级的扫描驱动信号SCANn维持低电平时，第六开关元件M6一直处于等同于被关闭的状态。
其中，由于第六开关元件M6位于第四开关元件M4的第四控制端与第一开关元件M1的第一通路端之间，因此能避免第一开关元件M1直接与第3阶段电压很低的第四开关元件M4的第四控制端连接，使得第一开关元件M1的第一通路端的电压过低，对本实施例提供的扫描驱动电路中非常重要的第一开关元件M1造成损坏的情况发生，从而起到保护电路的作用。
本申请第二实施例提供的扫描驱动电路，包括第一开关元件M1、第二开关元件M2、第三开关元件M3、第四开关元件M4、第五开关元件M5、第六开关元件M6、第一电容C1和第二电容C2，就可以输出正常的扫描驱动信号，且可以称为6T2C的扫描驱动电路，其中第一电容C1能够使第四开关元件M4更容易导通，并配合第六开关元件M6能够起到电路保护的作用，第二电容C2能够使第五开关元件M5更容易导通，因此第一电容C1和第二电容C2均能够使输出的第n级扫描驱动信号SCANn更稳定。此外，本申请第二实施例提供的扫描驱动电路所使用的元件数量少于现有的扫描驱动电路，并且，本申请实施例提供的扫描驱动电路占用的空间也相对较少，更有利于显示装置窄边框的发展趋势。
第三实施例：
图4是本申请第三实施例的扫描驱动器的模块示意图。为了清楚地描述本申请第三实施例的扫描驱动器，请参见图4。
本申请第三实施例提供了一种扫描驱动器，包括至少一级如图1或图3所示 的扫描驱动电路，其中，扫描驱动电路的具体实施方式和有益效果可以参考第一实施例和第二实施例，在此将不再赘述。
参见图4，在一实施方式中，假设扫描驱动器包括N级扫描驱动电路(N≥3),本级扫描驱动电路是第n级驱动电路，其中，N-1≥n≥1，本级扫描驱动电路扫描驱动信号为SCANn，则向上相差一级的扫描驱动电路输出的上一级扫描驱动信号为SCAN(n-1)，向下相差一级的扫描驱动电路输出的下一级扫描驱动信号为SCAN(n+1)。
参见图4，具体地，本申请第三实施例提供的扫描驱动器包括多级扫描驱动电路，且除第1级的扫描驱动电路的起始信号SIN需要由外部提供以外，其余各级扫描驱动电路由向上相差一级的扫描驱动电路输出的扫描驱动信号作为起始信号SIN。
本申请实施例提供的扫描驱动器，其内部电路结构为本申请提供的多级扫描驱动电路，由于本申请提供的扫描驱动电路利用较少的元器件就能够输出正常的扫描驱动信号，因此本申请提供的扫描驱动电路占用的空间减少，从而使得扫描驱动器的体积减小，进而有利于显示装置的窄边框的发展趋势。
第四实施例：
图5是本申请第四实施例提供的显示装置的结构示意图。
参见图5，本申请第四实施例提供了一种显示装置，其内部安装有本申请提供的扫描驱动器1、数据驱动器2、发射控制驱动器3及像素面板4。其中，扫描驱动器1的具体实施方式及有益效果可以参考第三实施例，在此将不再赘述。
具体地，像素面板4能够根据扫描驱动器1供应的扫描驱动信号、发射控制驱动器3供应的发射控制信号和数据驱动器2供应的数据信号来显示图像的多个像素PXn1、PXn2(其中，n为大于0的整数)。像素PX包括有机发光二极管(Organic Light-Emitting Diode，OLED)，有机发光二极管用于发射与数据信号对应的驱动电流的光。
扫描驱动器1根据从外部控制电路(例如，时序控制器)提供的控制信号将多级扫描信号按顺序对应提供到扫描线S1至Sn，然后，通过扫描驱动信号选择某一行像素PXn1、PXn2以对应接收数据线D1至Dm提供的数据信号。然后，像素PXn1、PXn2充入(存储)与数据信号对应的电压并发射具有与该电压对应的亮度分量的光。
发射控制驱动器3根据外部控制电路(例如，时序控制器)供应的控制信号将发射控制信号按顺序供应到发射控制线E1至En。然后，通过发射控制信号来控制像素PXn1、PXn2的发光时间。
在一实施方式中，每个像素PX可以形成发射红光的红色像素或发射绿光的绿色像素或发射蓝色的蓝色像素。即，在一实施方式中，像素面板4中包括红色 像素、绿色像素和蓝色像素。相邻的至少一个红色像素、至少一个绿色像素和至少蓝色像素构成一个像素单元。因此，像素单元能够发射具有与驱动电流对应的亮度的不同颜色的光，从而能够使像素面板4实现彩色图像的显示。
在一实施方式中，扫描驱动器1和发射控制驱动器3可以以芯片的形式额外地安装，和/或与像素面板4中的像素电路元件一起嵌入在面板上以构成嵌入式电路单元。
应当理解，本申请实施例提供的显示装置，其内部使用了本申请上述实施例提供的扫描驱动器1。也就是说，本申请通过在显示装置中设置上述实施例提供的扫描驱动器的方式，实现了缩小显示装置的边框的目的，进而更有利于显示装置窄边框的发展趋势。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换或改进等，均应包含在本申请的保护范围之内。

Claims (17)

  1. 一种扫描驱动电路，包括第一控制模块、第二控制模块和输出模块，其中
    所述输出模块包括第一开关单元、第二开关单元和扫描驱动信号输出端，所述第一开关单元和所述第二开关单元并行连接且共同连接至所述扫描驱动信号输出端，所述第一开关单元远离所述扫描驱动信号输出端的端口用于接收第二时钟信号，所述第二开关单元远离所述扫描驱动信号输出端的端口用于接收第一参考信号；
    所述第一控制模块用于接收第一时钟信号和起始信号，并根据所述第一时钟信号和所述起始信号控制所述第一开关单元的工作状态；
    所述第二控制模块用于接收第二参考信号，并根据所述第一控制模块的工作状态和所述第二参考信号控制所述第二开关单元的工作状态。
  2. 如权利要求1所述的扫描驱动电路，其中
    所述第一控制模块包括第一开关元件，所述第一开关元件包括第一控制端、第一通路端及第二通路端，所述第一开关元件的所述第一控制端用于接收所述第一时钟信号，所述第一开关元件的所述第二通路端用于接收所述起始信号；
    所述第二控制模块包括第二开关元件和第三开关元件，其中，所述第二开关元件包括第二控制端、第三通路端及第四通路端，所述第二开关元件的所述第二控制端与所述第一开关元件的所述第一通路端相连，所述第二开关元件的所述第四通路端用于接收所述第一时钟信号；所述第三开关元件包括第三控制端、第五通路端及第六通路端，所述第三开关元件的所述第三控制端用于接收所述第一时钟信号，所述第三开关元件的所述第五通路端与所述第二开关元件的所述第三通路端相连，所述第三开关元件的所述第六通路端用于接收所述第二参考信号；
    所述输出模块的所述第一开关单元包括第四开关元件，所述输出模块的所述第二开关单元包括第五开关元件，其中，所述第四开关元件包括第四控制端、第七通路端及第八通路端，所述第四开关元件的所述第四控制端与所述第二开关元件的所述第二控制端相连，所述第四开关元件的所述第八通路端用于接收所述第二时钟信号；所述第五开关元件包括第五控制端、第九通路端及第十通路端，所述第五开关元件的所述第五控制端与所述第三开关元件的所述第五通路端相连，所述第五开关元件的所述第九通路端用于接收所述第一参考信号，所述第五开关元件的所述第十通路端与所述第四开关元件的所述第七通路端相连。
  3. 如权利要求2所述的扫描驱动电路，其中，所述第一控制模块还包括第六开关元件，所述第六开关元件包括第六控制端、第十一通路端及第十二通路端，所述第六开关元件的所述第六控制端用于接收所述第二参考信号，所述第六开关 元件的所述第十一通路端与所述第二开关元件的所述第二控制端相连，所述第六开关元件的所述第十二通路端与所述第四开关元件的所述第四控制端相连。
  4. 如权利要求1至3任一所述的扫描驱动电路，其中，所述第一参考信号为参考高电压信号，所述第二参考信号为参考低电压信号。
  5. 如权利要求2或3所述的扫描驱动电路，其中，所述输出模块还包括第一导通增强元件，所述第四开关元件的所述第七通路端通过所述第一导通增强元件与所述第四控制端相连，所述第一导通增强元件用于降低所述第四开关元件的导通难度。
  6. 如权利要求5所述的扫描驱动电路，其中，所述第一导通增强元件为电容元件。
  7. 如权利要求2或3所述的扫描驱动电路，其中，所述输出模块还包括第二导通增强元件，所述第五开关元件的所述第九通路端通过所述第二导通增强元件与所述第五开关元件的所述第五控制端相连，所述第二导通增强元件用于降低所述第五开关元件的导通难度。
  8. 如权利要求7所述的扫描驱动电路，其中，所述第二导通增强元件为电容元件。
  9. 如权利要求8所述的扫描驱动电路，其特征在于，所述第二导通增强元件为所述第五开关元件的寄生电容。
  10. 如权利要求1所述的扫描驱动电路，其中，
    所述起始信号为相差预设级数的所述扫描驱动电路输出的扫描驱动信号。
  11. 如权利要求10所述的扫描驱动电路，其中，
    所述预设级数为一级，第n级的所述起始信号为第n-1级的扫描驱动信号，n为大于0的整数。
  12. 如权利要求2所述的扫描驱动电路，其中，所述第一开关元件至所述第五开关元件中至少一个为PMOS管。
  13. 如权利要求12所述的扫描驱动电路，其中，所述第一开关元件为双栅极的PMOS管。
  14. 如权利要求1至3任一所述的扫描驱动电路，其特征在于，所述第一时钟信号和所述第二时钟信号具有相同的占空比和周期，并且所述第一时钟信号与所述第二时钟信号的低电平相互交错。
  15. 一种扫描驱动器，包括如权利要求1至14任一所述的扫描驱动电路。
  16. 一种显示装置，包括如权利要求15所述的扫描驱动器。
  17. 如权利要求16所述的显示装置，其中，所述显示装置还包括数据驱动器、发射控制驱动器和像素面板，所述像素面板根据所述扫描驱动器的扫描驱动信号、所述发射控制驱动器的发射控制信号和所述数据驱动器的数据信号显示图像的像 素。
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