WO2019137117A1 - 半导体器件及用于半导体器件的引线框 - Google Patents

半导体器件及用于半导体器件的引线框 Download PDF

Info

Publication number
WO2019137117A1
WO2019137117A1 PCT/CN2018/119175 CN2018119175W WO2019137117A1 WO 2019137117 A1 WO2019137117 A1 WO 2019137117A1 CN 2018119175 W CN2018119175 W CN 2018119175W WO 2019137117 A1 WO2019137117 A1 WO 2019137117A1
Authority
WO
WIPO (PCT)
Prior art keywords
die pad
horizontal direction
lead
proximal end
lead fingers
Prior art date
Application number
PCT/CN2018/119175
Other languages
English (en)
French (fr)
Inventor
陈萌奇
陈晨
Original Assignee
陈萌奇
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201810016866.XA external-priority patent/CN108022902B/zh
Application filed by 陈萌奇 filed Critical 陈萌奇
Publication of WO2019137117A1 publication Critical patent/WO2019137117A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to integrated circuits and packaged integrated circuits, and more particularly to a semiconductor device and a leadframe for packaging integrated circuits.
  • An integrated circuit (IC) die is a small device formed on a semiconductor wafer such as a silicon wafer. Typically, such a die is cut from the wafer and packaged using a leadframe.
  • a leadframe is a metal frame, typically formed of copper or a nickel alloy that supports an integrated circuit die and provides an external electrical connection for the chip of the package.
  • Leadframes typically include a flag or die pad and lead fingers. Bond pads on the die are electrically connected to the leads of the leadframe via wire bonds.
  • the die and bond wires are encapsulated with a protective material to form a package.
  • the leads project either outwardly from the envelope, or at least flush with the envelope, such that they can serve as terminals, allowing the integrated circuit to be electrically connected to other devices or printed circuit boards (PCBs).
  • PCBs printed circuit boards
  • Device 100 includes a semiconductor die 102 that is attached to die pad 104 and electrically connected to lead fingers 106. Die 102, die pad 104, and a portion of lead fingers 106 are covered by a mold compound 108 that protects the electrical connections of die 102 and lead fingers 106 from damage. Lead fingers 106 protrude from the mold compound 108 and are later bent into a gull-wing shape to provide an external electrical connection to the die 102.
  • QFP quad flat package
  • FIG. 2 an enlarged cross-sectional view of a conventional die pad exposed square flat leadless package (QFN) semiconductor device 200 is shown.
  • Device 200 is substantially similar to device 100 except that the die pad 204 to which die 202 is attached is exposed to the bottom of device 200.
  • lead fingers 206 and die pads 204 are typically formed from a substantially flat, sheet-like leadframe that is substantially coplanar with die pad 204 and thus also exposed to the bottom of device 200, Die 202 provides an external electrical connection.
  • the semiconductor device 200 has a heat dissipation effect by providing exposed die pads 204 to provide heat transfer to the die 202 from the outside.
  • the die 202 of the device 200 is susceptible to damage in the collision of the device 200 with the exterior as compared to the device 100.
  • the bottom surface of the die pad 204 is completely free of the encapsulation of the mold compound 208, separation due to weak adhesion between the top surface of the die pad 204 and the mold compound 208 is easily caused.
  • a semiconductor device comprising: a die pad, wherein the die pad extends in a wave shape in a first horizontal direction, comprising a plurality of first planes a first strip, a plurality of second strips located in a second plane different from the first plane, and staggered with the plurality of first strips in the first horizontal direction, and a plurality of joining the plurality of strips a first belt and a transition strip of the adjacent second belt, wherein each of the first belt, the second belt, and the transition belt respectively extend in a second horizontal direction different from the first horizontal direction; a first lead finger spaced apart from the first side of the die pad extending in the first horizontal direction and extending outwardly, wherein the first lead finger has a proximity to the die pad a proximal end and a distal end remote from the die pad, and wherein the proximal end of the first lead finger is in the first plane and respectively located in the second horizontal direction of the first strap Upper extension line; a plurality of
  • the present invention further provides a lead frame for a semiconductor device, comprising: a die pad, wherein the die pad extends in a wave shape in a first horizontal direction, including a plurality of first ones located in a first plane a plurality of strips, a plurality of second strips located in a second plane different from the first plane, and staggered with the plurality of first strips in the first horizontal direction, and a plurality of joining the plurality of first strips a transition strip with the adjacent second strip, wherein each of the first strip, the second strip, and the transition strip respectively extend in a second horizontal direction different from the first horizontal direction; a plurality of first a lead finger spaced apart from the first side of the die pad extending in the first horizontal direction and extending outwardly, wherein the first lead finger has a proximal end proximate to the die pad And a distal end remote from the die pad, and wherein the proximal end of the first lead finger is in the first plane and respectively located in the second horizontal direction of the first band
  • the present invention provides a method of packaging a semiconductor die, comprising the steps of: providing a conductive metal sheet; forming a die pad region in the conductive metal sheet; forming a plurality of the conductive metal sheets Lead fingers, wherein the plurality of lead fingers extend from a tie bar surrounding the die pad region to the die pad region, and the plurality of lead fingers have a proximal end proximate to the die pad And a distal end remote from the die pad; bending the die pad region into a die pad extending in a wave shape in a first horizontal direction, the die pad including a plurality of a first strip of a plane, a plurality of second strips located in a second plane different from the first plane, and staggered with the plurality of first strips in the first horizontal direction, and a plurality of joints a transition strip of the plurality of first strips and the adjacent second strips; a lead of the plurality of lead fingers spaced apart from a first side extending in a first horizontal direction of the die pad Means
  • a semiconductor device comprising: a die pad, wherein the die pad extends in a wave shape in a first horizontal direction, including a plurality of locations on a first plane a first strip, a plurality of second strips located in a second plane different from the first plane, and staggered with the plurality of first strips in the first horizontal direction, and a plurality of joints a first strip and a transition strip of the adjacent second strip, wherein each of the first strip, the second strip, and the transition strip respectively extend in a second horizontal direction different from the first horizontal direction; First lead fingers spaced apart from the first side of the die pad extending in the first horizontal direction and extending outwardly, wherein the first lead fingers have proximity to the die pad a proximal end and a distal end remote from the die pad, and wherein the proximal end of the first lead finger is in the first plane and respectively located at the second level An extension line in the direction; a plurality of second lead fingers, and the die pad.
  • QFP quad flat package
  • FIG. 2 is an enlarged cross-sectional view of a conventional die pad exposed square flat leadless package (QFN) semiconductor device
  • FIG. 3 is a bottom plan view of a packaged semiconductor device in accordance with one embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of the semiconductor device of FIG. 3 on line A-A, in accordance with one embodiment of the present invention
  • Figure 5 is a front elevational view of the semiconductor device of Figure 3, in accordance with one embodiment of the present invention.
  • Figure 6 is a cross-sectional view of the semiconductor device of Figure 3 on a fold line B-B, in accordance with one embodiment of the present invention.
  • Figure 7 is a top plan view of a raw lead frame in accordance with one embodiment of the present invention.
  • Figure 8 is a top plan view of the processed lead frame of the unprocessed lead frame of Figure 7 in accordance with one embodiment of the present invention.
  • FIG. 9 is a top plan view of a partially packaged semiconductor device in accordance with one embodiment of the present invention.
  • Figure 10 is a bottom plan view of a packaged semiconductor device in accordance with another embodiment of the present invention.
  • FIG. 11 is a cross-sectional view of the semiconductor device of FIG. 10 on line C-C, in accordance with another embodiment of the present invention.
  • Figure 12 is a top plan view of a lead frame in accordance with still another embodiment of the present invention.
  • Figure 13 is a bottom plan view of a semiconductor device packaged with the lead frame of Figure 12, in accordance with yet another embodiment of the present invention.
  • Figure 14 is a front elevational view of the semiconductor device of Figure 13 in accordance with yet another embodiment of the present invention.
  • Figure 15 is a cross-sectional view of the semiconductor device of Figure 13 on a fold line D-D, in accordance with yet another embodiment of the present invention.
  • FIG. 3 a bottom plan view of a packaged semiconductor device 300 in accordance with one embodiment of the present invention is shown. 4, 5, and 6 respectively show a cross-sectional view, a front view, and a cross-sectional view on line B-B of the semiconductor device 300 of FIG. 3 on line A-A, in accordance with one embodiment of the present invention.
  • the semiconductor device 300 includes a die pad 302 that extends in a wave shape in a first horizontal direction 304, including a plurality of first strips 308 located in a first plane 306, a plurality of A second strip 312 that is different from the second plane 310 of the first plane 306.
  • the second strip 312 and the plurality of first strips 308 are staggered in a first horizontal direction 304.
  • the die pad 302 also includes a plurality of transition strips 314 that join the first strip 308 and the adjacent second strip 312.
  • Each of the first belt 308, the second belt 312, and the transition belt 314 extend in a second horizontal direction 316 that is different from the first horizontal direction 304, respectively.
  • the second side 320 of the die pad 302 adjacent to the first side 318 extending in the first horizontal direction 304 is the first strip 308 located in the first plane 306 so as not to increase the semiconductor device
  • the die pad 302 is provided with a larger upper surface to attach the semiconductor die.
  • the die pad 302 extends in a wedge wave in the first horizontal direction 304.
  • the semiconductor device 300 further includes a plurality of first lead fingers 322 and a second lead finger 324 staggered in a first horizontal direction 304 with the first lead fingers 322.
  • the first and second lead fingers 322 and 324 are spaced apart from the first side 318 of the die pad 302 and extend outward.
  • Each first lead finger 322 has a proximal end 326 proximate to the die pad and a distal end 328 remote from the die pad 302.
  • the proximal end 326 of the first lead finger 322 is in the first plane 306 and is located on an extension line of the first strip 308 in the second horizontal direction 316.
  • the second lead finger 324 has a proximal end 330 proximate to the die pad 302 and a distal end 332 remote from the die pad 302.
  • the proximal end 330 of the second lead finger 324 is in the second plane 310 and is located on an extension line of the second strip 312 in the second horizontal direction 316.
  • the semiconductor device 300 additionally includes a semiconductor die 334 attached to the first strip 308 of the die pad 302 electrically coupled to the proximal ends 326 and 330 of the first and second lead fingers 322 and 324 by bond wires 336. And an encapsulation material 338 that surrounds at least a portion of the die pad 302, the semiconductor die 334, and the proximal ends 326 and 330 of the first and second lead fingers 322 and 324. Wherein the distal end 328 of the first lead finger 322 projects outwardly from the encapsulation material 338, the bottom surface of the proximal end 330 of the second lead finger 324 and the bottom surface of the second strip 312 of the die pad 302 are exposed from the encapsulation material 338. .
  • the entire second lead finger 324 is in the second plane 310, and the bottom surface and the distal end 332 are exposed from the encapsulation material 338, respectively exposed to the bottom surface and the side surface of the semiconductor device 300.
  • the encapsulation material 338 wraps the bottom of the first strip 308 of the die pad 302, thereby providing better protection to the semiconductor die 334, also The separation between the upper surface of the die pad 302 and the encapsulation material 338 is prevented, while the bottom surface of the second strip 312 of the die pad 302 is again exposed from the encapsulation material 338, thereby providing a very good semiconductor die 334. Good cooling function.
  • first and second lead fingers 322 and 324 distributed along the first horizontal direction 304 are staggered in the first and second planes such that the spacing of adjacent first and second lead fingers 322 and 324 It can be further reduced without introducing a risk of short circuit, thereby further reducing the size of the semiconductor device 300 without reducing the input and output terminals of the semiconductor device 300.
  • semiconductor device 300 further includes a plurality of third lead fingers 340 spaced apart from and extending outwardly from second side 320 of die pad 302 and having proximity to die pad 302 The proximal end 342 and the distal end 344 remote from the die pad 302, wherein the proximal end 342 is in the second plane 310.
  • the proximal end 342 of the third lead finger 340 on the second plane 310 can be closer to the tube in the first horizontal direction 304
  • the second side 320 of the core pad 302 reduces the width of the semiconductor device 300 on the first horizontal warp direction 304 without reducing the number of input and output terminals.
  • the bottom and distal ends 344 of the third lead fingers 340 are exposed from the encapsulation material 338 and are exposed to the bottom and sides of the semiconductor device 300, respectively.
  • FIG. 7 is a top plan view of a raw leadframe 400 in accordance with one embodiment of the present invention.
  • the unprocessed leadframe 400 is formed by stamping or cutting a conductive metal sheet.
  • the unprocessed leadframe 400 includes a die pad region 402 that includes a plurality of first straps 404, a plurality of second straps 406 that are staggered with the first straps 404 in a first horizontal direction 304, and a tie phase A transition zone 408 of the first zone 404 and the second zone 406 is adjacent.
  • the two opposing second sides of the die pad region 402 adjacent the first side extending in the first horizontal direction 304 are the first straps 404.
  • the unprocessed leadframe 400 also includes a plurality of first and second lead fingers 410 and 412 that are spaced apart from and extend outwardly from a first side of the die pad region 402 that extends in the first horizontal direction 304.
  • first lead fingers 410 and the second lead fingers 412 are staggered in the first horizontal direction 304, and the first lead fingers 410 are respectively located on the extension line of the first strip 404 in the second horizontal direction 316, and the second lead fingers 412 are respectively located on extension lines of the second strip 406 in the second horizontal direction 316.
  • the unprocessed leadframe 400 further includes a plurality of third lead fingers 414 spaced apart from the second side of the die pad region 402 and extending outwardly.
  • First lead fingers 410, second lead fingers 412, third lead fingers 414, and die pad regions 402 are joined together by tie bars 416.
  • FIG. 8 is a top plan view of the processed leadframe 500 of the unprocessed leadframe 400 of Figure 7 in accordance with one embodiment of the present invention.
  • the processed lead frame 500 includes a die pad 502 that extends in a wave shape in a first horizontal direction 304, wherein the first strip 404 is in a first plane and the second strip 406 is in a second plane 310 that is different from the first plane 306.
  • the transition zone 408 joins the adjacent first belt 404 and second belt 406 located in different planes.
  • the die pad 502 extends in a square wave or a wedge wave in the first horizontal direction.
  • the first lead fingers 410 are located in a first plane 306 and the second lead fingers 412 are located in a second plane 310, the connecting strips 416 extending correspondingly in a wave shape in the first horizontal direction 304.
  • the third lead finger 414 is located in the second plane 310.
  • Semiconductor device 600 includes a leadframe 500, and a semiconductor die 334 attached to die pad 502 of wireframe 500 that is electrically coupled to first, second, and third lead fingers 410, 412, and 414 by bond wires 336 . Subsequently, by encapsulating the semiconductor die 334, the lead frame 500, and the bonding wires 336 with the encapsulating material 338, the connecting strips 416 are removed such that the respective lead fingers and the die pads 502 are independent, and the first lead fingers 410 are bent to form FIG.
  • encapsulation material 338 is a mold compound.
  • FIG. 10 is a bottom plan view of a packaged semiconductor device 700 in accordance with another embodiment of the present invention
  • FIG. 11 is an enlarged cross-sectional view of the semiconductor device 700 of FIG. 10 on line C-C, in accordance with another embodiment of the present invention.
  • the semiconductor device 700 is substantially similar to the semiconductor device 300 of FIGS. 3-6 except that the die pad 702 extends in a square wave in the first horizontal direction 304.
  • Figure 12 is a top plan view of a leadframe 800 in accordance with yet another embodiment of the present invention.
  • the leadframe 800 is substantially similar to the leadframe 500 of FIG. 8, except that the first lead fingers 802 are in a second plane and the second lead fingers 804 are in a first plane so as to be vertically offset from the first and second strips 404 and 406, respectively. Thereby, the first side 318 of the die pad 502 can be brought closer, so that the size of the semiconductor device can be further reduced without reducing the number of input and output terminals.
  • Figure 13 is a bottom plan view of a semiconductor device 900 packaged with the leadframe 800 of Figure 12, and Figure 14 is a front elevational view of the semiconductor device 900 of Figure 13 in accordance with yet another embodiment of the present invention, in accordance with yet another embodiment of the present invention.
  • Figure 15 is a cross-sectional view of the semiconductor device 900 of Figure 13 on a fold line DD, in accordance with yet another embodiment of the present invention.
  • the semiconductor device 900 is substantially similar to the semiconductor device 300 shown in FIGS.
  • first and second straps 404 and 406 are vertically offset such that the proximal ends of the first and second lead fingers 802 and 804 can be closer to the first side of the die pad 502, so that without reducing the number of input and output terminals, further Reduce the size of semiconductor devices.

Abstract

一种半导体器件（600），具有在第一水平方向（304）上呈波浪形延伸的管芯焊盘（502），其包括位于第一平面（306）的多个第一带（404），位于第二平面（310）且与所述第一带（404）在第一水平方向（304）上交错安排的多个第二带（406），以及连结第一带（404）与相邻的第二带（406）的多个过渡带（408）。所述半导体器件（600）还具有多个第一引线指（410），其近端处于第一平面（306）中，以及多个第二引线指（412），其与第一引线指（410）在第一水平方向（304）上交错安排，其中所述第二引线指（412）的近端处于第二平面（310）中。所述第一和第二引线指（410、412）分别位于所述多个第一带（404）或第二带（406）的延伸线上。第一引线指（410）的远端从用于包封附接于所述管芯焊盘（502）的第一带（404）上的半导体管芯（334）的包封材料（338）向外凸出，第二引线指（412）的底面和所述管芯焊盘（502）的第二带（406）的底面从所述包封材料（338）露出。

Description

半导体器件及用于半导体器件的引线框 技术领域
本发明涉及集成电路以及封装的集成电路，并且更具体地，涉及一种半导体器件以及用于封装集成电路的引线框。
背景技术
集成电路(IC)管芯(die)是一种形成在半导体晶片(诸如，硅晶片)上的小型器件。典型地，将这种管芯从晶片切下，并利用引线框将其封装。引线框是一种金属框架，通常由铜或镍合金形成，其支撑集成电路管芯并提供用于封装的芯片的外部电连接。引线框通常包括标志(flag)或管芯焊盘(die pad)以及引线指(lead fingers)。管芯上的接合焊盘(bond pad)经由导线接合电连接到引线框的引线。利用保护性材料包封管芯和接合线以形成封装。引线或者从所述包封向外凸出，或者至少与所述包封齐平，因而它们可以作端子，允许集成电路电连接到其他器件或印刷电路板(PCB)。
参考图1，示出了常规的方形扁平封装(QFP)的半导体器件100的放大横截面图。器件100包括半导体管芯102，其附接到管芯焊盘104并电连接到引线指106。管芯102、管芯焊盘104和部分引线指106被模化合物(mold compound)108覆盖，所述模化合物108保护管芯102和引线指106的电连接不受损害。引线指106从模化合物108凸出，并在后期被弯折成鸥翼(gull-wing)状，从而给管芯102提供外部电连接。
参考图2，示出了常规的管芯焊盘暴露的方形扁平无引脚封装(QFN)的半导体器件200的放大横截面图。器件200与器件100基本相似，除了其上附接有管芯202的管芯焊盘204的暴露于器件200的底部。此外，引线指206与管芯焊盘204通常是从一个基本扁平呈片状的引线框形成的，引线指206与管芯焊盘204基本位于同一平面，从而也暴露于器件200的底部，给管芯202提供外部电连接。相比于图1的半导体器件100，半导体器件200由于具有暴露的管芯焊盘204，从而为管芯202提供与外部 的热传递，起到散热作用。然而，由于管芯202底部与外界仅隔有一层管芯焊盘204，相比于器件100，器件200的管芯202容易在器件200与外部的碰撞中受到损伤。此外，由于管芯焊盘204的底面完全没有模化合物208的包裹，因此很容易造成管芯焊盘204的顶面与模化合物208之间粘合不牢固而引起的分离。
另外，如何在同样或更小尺寸的封装中使半导体器件装配有更多的提供输入输出的电连接的引线指同时仍维持或降低封装成本，一直是业界的改进方向。
因此，能够提供一种既能使管芯获得更多的保护，又能给管芯提供散热功能，且在不增大尺寸的前提下，具有更多的输入输出端的半导体器件将是有利的。
发明内容
根据本发明的一个实施例，本发明提供了一种半导体器件，包括：管芯焊盘，其中所述管芯焊盘在第一水平方向上呈波浪形延伸，包括多个位于第一平面的第一带，多个位于不同于第一平面的第二平面的，且与所述多个第一带在所述第一水平方向上交错安排的第二带，以及多个连结所述多个第一带与相邻的所述第二带的过渡带，其中每个所述第一带、第二带、以及过渡带分别在不同于第一水平方向的第二水平方向上延伸；多个第一引线指，其与所述管芯焊盘在所述第一水平方向上延伸的第一侧间隔开并向外延伸，其中所述第一引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第一引线指的所述近端处于所述第一平面中，且分别位于所述第一带在所述第二水平方向上的延伸线上；多个第二引线指，其与所述管芯焊盘的所述第一侧间隔开并向外延伸并与所述多个第一引线指在所述第一水平方向上交错安排，其中所述第二引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第二引线指的所述近端处于所述第二平面中，且分别位于所述第二带在所述第二水平方向上的延伸线上；附接到所述管芯焊盘的所述第一带上的半导体管芯，其中所述半导体管芯通过接合线电连接到所述第一和第二引线指的近端；以及包封材料，其至少围绕所述管芯焊盘的部分、所述半导体管芯、以及所述多个第一和第二引线指的近端，其中所述第一引线指的远端从所述包封材料向外凸出，所述第二引线指的所述近端的底面以及所述管芯焊盘的所述第二带的底面从所述包封材料露出。
本发明进一步提供了一种用于半导体器件的引线框，包括：管芯焊盘，其中所述管芯焊盘在第一水平方向上呈波浪形延伸，包括多个位于第一平面的第一带，多个位于不同于第一平面的第二平面的，且与所述多个第一带在所述第一水平方向上交错安排的第二带，以及多个连结所述多个第一带与相邻的所述第二带的过渡带，其中每个所述第一带、第二带、以及过渡带分别在不同于第一水平方向的第二水平方向上延伸；多个第一引线指，其与所述管芯焊盘在所述第一水平方向上延伸的第一侧间隔开并向外延伸，其中所述第一引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第一引线指的所述近端处于所述第一平面中，且分别位于所述第一带在所述第二水平方向上的延伸线上；多个第二引线指，其与所述管芯焊盘的所述第一侧间隔开并向外延伸并与所述多个第一引线指在所述第一水平方向上交错安排，其中所述第二引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第二引线指的所述近端处于所述第二平面中，且分别位于所述第二带在所述第二水平方向上的延伸线上；以及环绕所述管芯焊盘的连接条，所述连接条将所述多个第一引线指和所述多个第二引线指与所述管芯焊盘连结。
更进一步的，本发明提供了一种封装半导体管芯的方法，包括如下步骤：提供导电金属片；在所述导电金属片中形成管芯焊盘区域；在所述导电金属片中形成多个引线指，其中所述多个引线指从环绕所述管芯焊盘区域的连接条向所述管芯焊盘区域延伸，并且所述多个引线指具有接近所述管芯焊盘的近端和远离所述管芯焊盘的远端；将所述管芯焊盘区域弯折成在第一水平方向上呈波浪形延伸的管芯焊盘，所述管芯焊盘包括多个位于第一平面的第一带，多个位于不同于第一平面的第二平面的，且与所述多个第一带在所述第一水平方向上交错安排的第二带，以及多个连结所述多个第一带与相邻的所述第二带的过渡带；将所述多个引线指中位于与所述管芯焊盘在第一水平方向上延伸的第一侧间隔开的引线指分成多个第一引线指和与所述多个第一引线指在所述第一水平方向上交错安排的多个第二引线指；弯折所述连接条，使所述第一引线指的所述近端处于所述第一平面中，且分别位于所述第一带在所述第二水平方向上的延伸线上，以及使所述第二引线指的所述近端处于所述第二平面中，且分别位于所述第二带在所述第二水平方向上的延伸线上；将半导体管芯附接到所述管芯焊盘的第一带上；将所述半导体管芯与所述多个引线指的近端通过接合线电连接；利用模化合物至少包封所述半导体管芯、所述管芯焊盘部分和所述多 个引线指的近端，其中所述第一引线指的所述远端从所述模化合物向外凸出，所述管芯焊盘的所述第二带的底面和所述第二引线指的所述近端的底面从所述模化合物露出；以及去除所述连接条，使所述多个引线指，以及所述管芯焊盘彼此独立。
根据本发明的另一个实施例，本发明提供了一种半导体器件，包括：管芯焊盘，其中所述管芯焊盘在第一水平方向上呈波浪形延伸，包括多个位于第一平面的第一带，多个位于不同于第一平面的第二平面的，且与所述多个第一带在所述第一水平方向上交错安排的第二带，以及多个连结所述多个第一带与相邻的所述第二带的过渡带，其中每个所述第一带、第二带、以及过渡带分别在不同于第一水平方向的第二水平方向上延伸；多个第一引线指，其与所述管芯焊盘在所述第一水平方向上延伸的第一侧间隔开并向外延伸，其中所述第一引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第一引线指的所述近端处于所述第一平面中，且分别位于所述第二带在所述第二水平方向上的延伸线上；多个第二引线指，其与所述管芯焊盘的所述第一侧间隔开并向外延伸并与所述多个第一引线指在所述第一水平方向上交错安排，其中所述第二引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第二引线指的所述近端处于所述第二平面中，且分别位于所述第一带在所述第二水平方向上的延伸线上；附接到所述管芯焊盘的所述第一带上的半导体管芯，其中所述半导体管芯通过接合线电连接到所述第一和第二引线指的近端；以及包封材料，其至少围绕所述管芯焊盘的部分、所述半导体管芯、以及所述多个第一和第二引线指的近端，其中所述第一引线指的远端从所述包封材料向外凸出，所述第二引线指的所述近端的底面以及所述管芯焊盘的所述第二带的底面从所述包封材料露出。
附图说明
前述发明内容以及下面的本发明优选实施例的详细说明，在结合附图阅读时可以得到更好的理解。为了说明本发明，在附图中示出了当前优选的实施例。然而，应当理解，本发明不限于所示的精确的布置和手段。在附图中：
图1是常规的方形扁平封装(QFP)的半导体器件的放大横截面图；
图2是常规的管芯焊盘暴露的方形扁平无引脚封装(QFN)的半导体器件的放大横截面图；
图3是根据本发明一个实施例的封装的半导体器件的底部平面图；
图4是根据本发明一个实施例的图3的半导体器件在线A-A上的横截面图；
图5是根据本发明一个实施例的图3的半导体器件的正面视图；
图6是根据本发明一个实施例的图3的半导体器件在折线B-B上的横截面图；
图7是根据本发明一个实施例的未加工的引线框的顶部平面图；
图8是根据本发明一个实施例的图7的未加工的引线框在加工后的引线框顶部平面图；
图9是根据本发明一个实施例的被部分封装的半导体器件的顶部平面图；
图10是根据本发明另一个实施例的封装的半导体器件的底部平面图；
图11是根据本发明另一个实施例的图10的半导体器件在线C-C上的横截面图；
图12是根据本发明的又一个实施例的引线框的顶部平面图；
图13是根据本发明的又一个实施例的封装有图12的引线框的半导体器件的底部平面图；
图14是根据本发明的又一个实施例的图13的半导体器件的正面视图；以及
图15是根据本发明的又一个实施例的图13的半导体器件在折线D-D上的横截面图。
具体实施方式
下面的结合附图阐述的详细说明意图作为对本发明的当前优选的实施例的描述，并且并不意图表示可以实践本发明的仅有的形式。应当理解，可以通过不同的实施例实现相同或等效的功能，并意图将这些实施例涵盖在本发明的精神和范围内。如本领域技术人员将理解的，本发明可以应用于多种封装和封装类型。
附图中的某些特征已经被放大以便于图示，并且附图及其要素并不必然成正确的比例。在附图中，相同的数字被用于表示相同的要素。
现在参考图3，示出了根据本发明一个实施例的封装的半导体器件300的底部平面图。图4、图5和图6分别示出了根据本发明一个实施例图3的半导体器件300在线A-A上的横截面图、正面视图和在折线B-B上的横截面图。
如图3至图6所示，半导体器件300包括管芯焊盘302，其在第一水平方向304上呈波浪形延伸，包括了多个位于第一平面306的第一带308，多个位于不同于第一平面306的第二平面310的第二带312。第二带312与所述多个第一带308在第一水平方向304上交错安排。管芯焊盘302还包括多个连结第一带308与相邻第二带312的过渡带314。每个第一带308、第二带312和过渡带314分别在不同于第一水平方向304的第二水平方向316上延伸。优选的，其中管芯焊盘302的与其在第一水平方向304上延伸的第一侧318相邻的第二侧320是位于第一平面306的第一带308，从而在不增大半导体器件300的尺寸的前提下，为管芯焊盘302提供一个面积更大的上表面来附接半导体管芯。优选地，管芯焊盘302在所述第一水平方向304上呈楔形波延伸。
半导体器件300还包括多个第一引线指322和与第一引线指322在第一水平方向304上交错安排第二引线指324。第一和第二引线指322和324与管芯焊盘302的第一侧318间隔开并向外延伸。每个第一引线指322具有接近于所述管芯焊盘的近端326和远离管芯焊盘302的远端328。第一引线指322的近端326处于第一平面306中，且位于第一带308在第二水平方向316上的延伸线上。第二引线指324具有接近于管芯焊盘302的近端330和远离管芯焊盘302的远端332。第二引线指324的近端330处于第二平面310中，且位于第二带312在第二水平方向316上的延伸线上。
半导体器件300另外还包括附接到管芯焊盘302的第一带308上的半导体管芯334，其通过接合线336电连接到第一和第二引线指322和324的近端326和330，以及至少围绕管芯焊盘302的部分、半导体管芯334、以及第一和第二引线指322和324的近端326和330的包封材料338。其中第一引线指322的远端328从包封材料338向外凸出，第二引线指324的近端330的底面以及管芯焊盘302的第二带312的底面从包封材料338露出。优选地，如图6所示，整个第二引线指324处于第二平面310中，其底面及远端332从包封材料338露出，分别暴露于半导体器件300的底面和侧面。由于管芯焊盘302在第一水平方向上成波浪形延伸，包封材料338包裹了管芯焊盘302的第一带308的底部，从而给半导体管芯334提供了更好的保护，也防止了管芯焊盘302上表面与包封材料338之间的分离，同时管芯焊盘302的第二带312的 底面又从包封材料338暴露出，从而为半导体管芯334提供了很好的散热功能。此外，沿着第一水平方向304分布的第一和第二引线指322和324的近端交错的位于第一和第二平面，从而相邻的第一和第二引线指322和324的间距可以进一步缩小，而不会带来短路风险，从而在不减少半导体器件300的输入输出端的情况下，进一步的缩小半导体器件300的尺寸。
根据本发明的一个优选实施例，半导体器件300还包括多个第三引线指340，其与管芯焊盘302的第二侧320间隔开并向外延伸，并具有接近于管芯焊盘302的近端342和远离管芯焊盘302的远端344，其中近端342处于第二平面310中。由于管芯焊盘302的第二侧320是处于第一平面306的第一带308，因此位于第二平面310的第三引线指340的近端342可以在第一水平方向304上更加接近管芯焊盘302的第二侧320，从而在不减少输入输出端数的前提下，减小半导体器件300在第一水平防向304上的宽度。优选地，第三引线指340的的底面和远端344从包封材料338露出，分别暴露于半导体器件300的底面和侧面。
图7是根据本发明一个实施例的未加工的引线框400的顶部平面图。根据本发明的一个优选实施例，所述未加工的引线框400是通过对一导电金属片进行冲压或切割形成的。所述未加工的引线框400包括管芯焊盘区域402，其包括多个第一带404，与第一带404在第一水平方向304上交错安排的多个第二带406，以及连结相邻第一带404和第二带406的过渡带408。优选地，管芯焊盘区域402中与在第一水平方向304上延伸的第一侧相邻的两个相对的第二侧都是第一带404。
所述未加工的引线框400还包括多个第一和第二引线指410和412，其与管芯焊盘区域402在第一水平方向304上延伸的第一侧间隔开并向外延伸。其中第一引线指410与第二引线指412在第一水平方向304上交错安排，并且第一引线指410分别位于第一带404在第二水平方向316上的延伸线上，第二引线指412分别位于第二带406在第二水平方向316上的延伸线上。根据本发明的一个优选实施例，所述未加工的引线框400还包括多个第三引线指414，其与管芯焊盘区域402的第二侧间隔开并向外延伸。第一引线指410，第二引线指412，第三引线指414，以及管芯焊盘区域402通过连接条416连结在一起。
图8是根据本发明一个实施例的图7中的未加工的引线框400在加工后的引线框500的顶部平面图。根据本发明的一个优选实施例，通过对未加工的引线框400按照图7中用虚线表示的山折线和用点划线表示的谷折线进行弯折或模压，可以很简捷方便的形成图8中的加工后的引线框500。引线框500包括一个在第一水平方向304上呈波浪形延伸的管芯焊盘502，其中第一带404位于第一平面，第二带406位于不同于第一平面306的第二平面310，过渡带408连结相邻的位于不同平面的第一带404和第二带406。优选地，管芯焊盘502在所述第一水平方向上呈方波或楔形波延伸。在本发明的一个实施例中，第一引线指410位于第一平面306，第二引线指412位于第二平面310，连接条416在第一水平方向304上相应的呈波浪形延伸。优选地，第三引线指414位于第二平面310。
图9是根据本发明一个实施例的被部分封装的半导体器件600的顶部平面图。半导体器件600包括引线框500，和附接于线框500的管芯焊盘502的半导体管芯334，其通过接合线336与第一、第二和第三引线指410、412和414电连接。随后通过用包封材料338包封半导体管芯334、引线框500和接合线336，去除连接条416使得各引线指和管芯焊盘502各自独立，弯折第一引线指410，形成图3-6中所示的半导体器件300，其中管芯焊盘502的第二带406的底面，第二和第三引线指412和414的底面从包封材料338暴露出。优选地，包封材料338是一种模化合物。
图10是根据本发明另一个实施例的封装的半导体器件700的底部平面图，图11是根据本发明另一个实施例的图10中的半导体器件700在线C-C上的放大横截面图。半导体器件700与图3-6中的半导体器件300基本相似，除了管芯焊盘702在所述第一水平方向304上呈方形波延伸。
图12是根据本发明的又一个实施例的引线框800的顶部平面图。引线框800与图8中的引线框500基本相似，除了第一引线指802位于第二平面，第二引线指804位于第一平面，从而分别与第一和第二带404和406垂直错开，从而可以更加接近管芯焊盘502的第一侧318，使得在不减少输入输出端数的前提下，进一步缩小半导体器件的尺寸。
图13是根据本发明的又一个实施例的封装有图12的引线框800的半导体器件900的底部平面图，图14是根据本发明的又一个实施例的图13中的半导体器件900的正面视图，以及图15是根据本发明的又一个实施例的图13中的半导体器件900在折线D-D上的横截面图。半导体器件900与图3-图6中所示的半导体器件300基本相似，除了第一引线指802的近端位于第二平面，第二引线指804的近端位于第一平面，从而分别与第一和第二带404和406垂直错开，从而第一和第二引线指802和804的近端可以更加接近管芯焊盘502的第一侧，使得在不减少输入输出端数的前提下，进一步缩小半导体器件的尺寸。
陈述本发明优选实施例的说明书是为了说明及描述的目的，而不旨在详细说明或限制本发明为所公开的形式。本领域所属技术人员将了解，在不脱离其宽泛的发明构思的情况下，可以对上述实施例做出改变。因此，应了解，本发明并不限于公开的特定实施例，而是覆盖了由所附权利要求所定义的本发明的精神及范围内的修改。

Claims (10)

  1. 一种半导体器件，包括：
    管芯焊盘，其中所述管芯焊盘在第一水平方向上呈波浪形延伸，包括多个位于第一平面的第一带，多个位于不同于第一平面的第二平面的，且与所述多个第一带在所述第一水平方向上交错安排的第二带，以及多个连结所述多个第一带与相邻的所述第二带的过渡带，其中每个所述第一带、第二带、以及过渡带分别在不同于第一水平方向的第二水平方向上延伸；
    多个第一引线指，其与所述管芯焊盘在所述第一水平方向上延伸的第一侧间隔开并向外延伸，其中所述第一引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第一引线指的所述近端处于所述第一平面中，且分别位于所述第一带在所述第二水平方向上的延伸线上；
    多个第二引线指，其与所述管芯焊盘的所述第一侧间隔开并向外延伸并与所述多个第一引线指在所述第一水平方向上交错安排，其中所述第二引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第二引线指的所述近端处于所述第二平面中，且分别位于所述第二带在所述第二水平方向上的延伸线上；
    附接到所述管芯焊盘的所述第一带上的半导体管芯，其中所述半导体管芯通过接合线电连接到所述第一和第二引线指的近端；以及
    包封材料，其至少围绕所述管芯焊盘的部分、所述半导体管芯、以及所述多个第一和第二引线指的近端，其中所述第一引线指的远端从所述包封材料向外凸出，所述第二引线指的所述近端的底面以及所述管芯焊盘的所述第二带的底面从所述包封材料露出。
  2. 如权利要求1所述的半导体器件，其中所述管芯焊盘在所述第一水平方向上呈方波或楔形波延伸。
  3. 如权利要求1所述的半导体器件，其中所述管芯焊盘与所述第一侧相邻的第二侧是所述第一带。
  4. 如权利要求3所述的半导体器件，还包括多个第三引线指，其与所述管芯焊盘的所述第二侧间隔开并向外延伸，其中所述第三引线指具有接近于所述管芯焊盘的近端和远 离所述管芯焊盘的远端，其中所述第三引线指的所述近端处于所述第二平面中，且所述近端的底面和所述远端从所述包封材料露出。
  5. 一种用于半导体器件的引线框，包括：
    管芯焊盘，其中所述管芯焊盘在第一水平方向上呈波浪形延伸，包括多个位于第一平面的第一带，多个位于不同于第一平面的第二平面的，且与所述多个第一带在所述第一水平方向上交错安排的第二带，以及多个连结所述多个第一带与相邻的所述第二带的过渡带，其中每个所述第一带、第二带、以及过渡带分别在不同于第一水平方向的第二水平方向上延伸；
    多个第一引线指，其与所述管芯焊盘在所述第一水平方向上延伸的第一侧间隔开并向外延伸，其中所述第一引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第一引线指的所述近端处于所述第一平面中，且分别位于所述第一带在所述第二水平方向上的延伸线上；
    多个第二引线指，其与所述管芯焊盘的所述第一侧间隔开并向外延伸并与所述多个第一引线指在所述第一水平方向上交错安排，其中所述第二引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第二引线指的所述近端处于所述第二平面中，且分别位于所述第二带在所述第二水平方向上的延伸线上；以及
    环绕所述管芯焊盘的连接条，所述连接条将所述多个第一引线指和所述多个第二引线指与所述管芯焊盘连结。
  6. 如权利要求5所述的引线框，其中所述管芯焊盘在所述第一水平方向上呈方波或楔形波延伸。
  7. 如权利要求5所述的引线框，其中所述管芯焊盘与所述第一侧相邻的第二侧是所述第一带。
  8. 如权利要求7所述的引线框，还包括多个第三引线指，其与所述管芯焊盘的所述第二侧间隔开并向外延伸，其中所述第三引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，其中所述第三引线指的所述近端处于所述第二平面中。
  9. 一种封装半导体管芯的方法，包括：
    提供导电金属片；
    在所述导电金属片中形成管芯焊盘区域；
    在所述导电金属片中形成多个引线指，其中所述多个引线指从环绕所述管芯焊盘区域的连接条向所述管芯焊盘区域延伸，并且所述多个引线指具有接近所述管芯焊盘的近端和远离所述管芯焊盘的远端；
    将所述管芯焊盘区域弯折成在第一水平方向上呈波浪形延伸的管芯焊盘，所述管芯焊盘包括多个位于第一平面的第一带，多个位于不同于第一平面的第二平面的，且与所述多个第一带在所述第一水平方向上交错安排的第二带，以及多个连结所述多个第一带与相邻的所述第二带的过渡带；
    将所述多个引线指中位于与所述管芯焊盘在第一水平方向上延伸的第一侧间隔开的引线指分成多个第一引线指和与所述多个第一引线指在所述第一水平方向上交错安排的多个第二引线指；
    弯折所述连接条，使所述第一引线指的所述近端处于所述第一平面中，且分别位于所述第一带在所述第二水平方向上的延伸线上，以及使所述第二引线指的所述近端处于所述第二平面中，且分别位于所述第二带在所述第二水平方向上的延伸线上；
    将半导体管芯附接到所述管芯焊盘的第一带上；
    将所述半导体管芯与所述多个引线指的近端通过接合线电连接；
    利用模化合物至少包封所述半导体管芯、所述管芯焊盘部分和所述多个引线指的近端，其中所述第一引线指的所述远端从所述模化合物向外凸出，所述管芯焊盘的所述第二带的底面和所述第二引线指的所述近端的底面从所述模化合物露出；以及
    去除所述连接条，使所述多个引线指，以及所述管芯焊盘彼此独立。
  10. 一种半导体器件，包括：
    管芯焊盘，其中所述管芯焊盘在第一水平方向上呈波浪形延伸，包括多个位于第一平面的第一带，多个位于不同于第一平面的第二平面的，且与所述多个第一带在所述第一水平方向上交错安排的第二带，以及多个连结所述多个第一带与相邻的所述第二带的过渡 带，其中每个所述第一带、第二带、以及过渡带分别在不同于第一水平方向的第二水平方向上延伸；
    多个第一引线指，其与所述管芯焊盘在所述第一水平方向上延伸的第一侧间隔开并向外延伸，其中所述第一引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第一引线指的所述近端处于所述第一平面中，且分别位于所述第二带在所述第二水平方向上的延伸线上；
    多个第二引线指，其与所述管芯焊盘的所述第一侧间隔开并向外延伸并与所述多个第一引线指在所述第一水平方向上交错安排，其中所述第二引线指具有接近于所述管芯焊盘的近端和远离所述管芯焊盘的远端，并且其中所述第二引线指的所述近端处于所述第二平面中，且分别位于所述第一带在所述第二水平方向上的延伸线上；
    附接到所述管芯焊盘的所述第一带上的半导体管芯，其中所述半导体管芯通过接合线电连接到所述第一和第二引线指的近端；以及
    包封材料，其至少围绕所述管芯焊盘的部分、所述半导体管芯、以及所述多个第一和第二引线指的近端，其中所述第一引线指的远端从所述包封材料向外凸出，所述第二引线指的所述近端的底面以及所述管芯焊盘的所述第二带的底面从所述包封材料露出。
PCT/CN2018/119175 2018-01-09 2018-12-04 半导体器件及用于半导体器件的引线框 WO2019137117A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810016866.XA CN108022902B (zh) 2018-01-09 半导体器件及用于半导体器件的引线框
CN201810016866.X 2018-01-09

Publications (1)

Publication Number Publication Date
WO2019137117A1 true WO2019137117A1 (zh) 2019-07-18

Family

ID=62071351

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/119175 WO2019137117A1 (zh) 2018-01-09 2018-12-04 半导体器件及用于半导体器件的引线框

Country Status (1)

Country Link
WO (1) WO2019137117A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6348726B1 (en) * 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
CN102403298A (zh) * 2010-09-07 2012-04-04 飞思卡尔半导体公司 用于半导体器件的引线框
CN108022902A (zh) * 2018-01-09 2018-05-11 陈萌奇 半导体器件及用于半导体器件的引线框
CN207896084U (zh) * 2018-01-09 2018-09-21 陈萌奇 半导体器件及用于半导体器件的引线框

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6348726B1 (en) * 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
CN102403298A (zh) * 2010-09-07 2012-04-04 飞思卡尔半导体公司 用于半导体器件的引线框
CN108022902A (zh) * 2018-01-09 2018-05-11 陈萌奇 半导体器件及用于半导体器件的引线框
CN207896084U (zh) * 2018-01-09 2018-09-21 陈萌奇 半导体器件及用于半导体器件的引线框

Also Published As

Publication number Publication date
CN108022902A (zh) 2018-05-11

Similar Documents

Publication Publication Date Title
US9991213B2 (en) Resin-encapsulated semiconductor device and its manufacturing method
US6437429B1 (en) Semiconductor package with metal pads
US5172214A (en) Leadless semiconductor device and method for making the same
US6157074A (en) Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same
US7482679B2 (en) Leadframe for a semiconductor device
JPS6344749A (ja) 半導体装置及びこれに用いるリードフレーム
US5299091A (en) Packaged semiconductor device having heat dissipation/electrical connection bumps and method of manufacturing same
WO2007018473A1 (en) Leadframe and semiconductor package
CN108140630A (zh) 具有垂直连接器的集成电路芯片
US7619307B1 (en) Leadframe-based semiconductor package having arched bend in a supporting bar and leadframe for the package
WO2019137117A1 (zh) 半导体器件及用于半导体器件的引线框
JP3075617B2 (ja) 半導体集積回路装置
CN109427698B (zh) 组装qfp型半导体器件的方法
TWI301316B (en) Chip package and manufacturing method threrof
JP4252563B2 (ja) 半導体装置
CN208538842U (zh) 半导体器件及用于半导体器件的引线框
CN108022902B (zh) 半导体器件及用于半导体器件的引线框
TWI792588B (zh) 半導體封裝
KR100891649B1 (ko) 반도체 패키지 제조방법
TWI405316B (zh) 導線架及晶片封裝體
TW201309126A (zh) 小基板記憶卡封裝構造
US7951651B2 (en) Dual flat non-leaded semiconductor package
JPS63160262A (ja) リ−ドフレ−ムおよびそれを用いた半導体装置
JPH02180061A (ja) リードフレームおよび半導体装置
JPS59115551A (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18900461

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18900461

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 06/04/2021)