WO2019125348A1 - Dispositifs à points quantiques avec réseaux de points quantiques verticaux - Google Patents

Dispositifs à points quantiques avec réseaux de points quantiques verticaux Download PDF

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Publication number
WO2019125348A1
WO2019125348A1 PCT/US2017/066916 US2017066916W WO2019125348A1 WO 2019125348 A1 WO2019125348 A1 WO 2019125348A1 US 2017066916 W US2017066916 W US 2017066916W WO 2019125348 A1 WO2019125348 A1 WO 2019125348A1
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WIPO (PCT)
Prior art keywords
gate
quantum
quantum dot
stack
layer
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PCT/US2017/066916
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English (en)
Inventor
Zachary R. YOSCOVITS
Hubert C. GEORGE
Nicole K. THOMAS
Ravi Pillarisetty
Jeanette M. Roberts
Roman CAUDILLO
Lester LAMPERT
David J. Michalak
Kanwaljit SINGH
James S. Clarke
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Intel Corporation
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Priority to PCT/US2017/066916 priority Critical patent/WO2019125348A1/fr
Publication of WO2019125348A1 publication Critical patent/WO2019125348A1/fr

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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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Definitions

  • This disclosure relates generally to the field of quantum computing, and more specifically, to quantum dot devices for use in quantum circuits.
  • Quantum computing refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. These quantum-mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.
  • Quantum computers use so-called quantum bits, referred to as qubits (both terms “bits” and “qubits” often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states - a uniquely quantum-mechanical phenomenon.
  • Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.
  • FIG. 1 provides various views of a single-sided quantum dot device, in accordance with some embodiments of the present disclosure.
  • FIGS. 2A-2B illustrate various exemplary biasing schemes for a quantum dot device in accordance with various embodiments of the present disclosure.
  • FIG. 3 provides various views of a double-sided quantum dot device, in accordance with some embodiments of the present disclosure.
  • FIGS. 4A-4E illustrate various embodiments of a quantum well stack that may be included in a quantum dot device, in accordance with various embodiments.
  • FIGS. 5A-5B provide a flow chart of a method for fabricating quantum dot devices as described herein, according to some embodiments of the present disclosure.
  • FIGS. 6A-6K are cross-sections illustrating various exemplary stages in the manufacture of a quantum dot device using the method of FIGS. 5A-5B, in accordance with some embodiments of the present disclosure.
  • FIGS. 7A and 7B are top views of a wafer and dies that may include any of the quantum dot devices disclosed herein.
  • FIG. 8 is a cross-sectional side view of a device assembly that may include any of the quantum dot devices disclosed herein.
  • FIG. 9 is a block diagram of an example quantum computing device that may include any of the quantum dot devices disclosed herein, in accordance with various embodiments.
  • quantum computing or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data.
  • quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states.
  • Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole.
  • quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).
  • Embodiments of the present disclosure provide improved layout designs for quantum dot devices employing quantum dot qubits.
  • various quantum dot devices, and related systems and methods, are disclosed herein.
  • the quantum dot devices disclosed herein may enable the formation of quantum dots to serve as quantum bits ("qubits") in a quantum computing device, as well as the control of these quantum dots to perform quantum logic operations.
  • a quantum dot device may include a substrate, a quantum well stack provided over the substrate, and at least one gate stack, but preferably a plurality of gate stacks.
  • the quantum well stack may include a plurality of planar layers, wherein planes of the quantum well layers are substantially perpendicular to the substrate (i.e., if the substrate is considered to be horizontal, then the quantum well layers are vertical).
  • the layers of the quantum well stack are stacked in a direction substantially parallel to the substrate, or, phrased differently, a normal to the planes of the layers of the quantum well stack is substantially parallel to the substrate.
  • the at least one gate stack is adjacent to a portion of first layer of the quantum well layers. When multiple gate stacks are employed, such gate stacks are adjacent to different portions of the first layer of the quantum well layers, where some of the different portions could be at different distances from the substrate.
  • quantum dots which will form during operation of the quantum dot device will be in a plane perpendicular to the substrate, i.e. the array of the resulting quantum dots will be vertical (i.e. the plane of the array of such quantum dots will be perpendicular to the plane of the substrate).
  • quantum dot arrays which are all horizontal (i.e. conventionally, the plane of the array of quantum dots is parallel to the plane of the substrate).
  • quantum dot devices may provide strong spatial localization of the quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.
  • the phrase “A and/or B” means (A), (B), or (A and B).
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
  • the notation "A/B/C” means (A), (B), and/or (C).
  • the terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature at which the qubits are typically operated.
  • techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-10 GFIz, e.g. in 3-8 GFIz, range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering.
  • qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.
  • Quantum dot devices with vertical quantum well layers Quantum dot devices with vertical quantum well layers
  • FIG. 1 provides various views of a quantum dot device 100 with quantum well layers perpendicular to the substrate (i.e. vertical), in accordance with some embodiments of the present disclosure.
  • FIG. 1 illustrates a top down view (the view shown in the upper left portion of FIG. 1) of the y-x plane of the coordinate system illustrated in some of the present FIGS., a first cross- sectional view (the view shown in the lower left portion of FIG. 1) along the y-z plane, and a second cross-sectional view (the view shown in the lower right portion of FIG. 1) along the x-z plane.
  • the top down view shown in FIG. 1 may be the view looking down from a plane indicted in FIG. 1 as a plane AA
  • the first cross-sectional view may be a cross-section along a plane indicted in FIG.
  • the second cross-sectional view may be a cross-section along a plane indicted in FIG. 1 as a plane CC (each of the planes AA, BB, and CC is shown in FIG. 1 with a dashed line intended to illustrate a plane perpendicular to the page of the drawing and containing said dashed line).
  • the top down view of a portion of the quantum dot device 100 is shown in FIG. 1 with some of the materials removed so that gate contact metal 118 to quantum dot (QD) gates and barrier gates, described below, are visible.
  • QD quantum dot
  • FIG. 1 with the interlayer dielectric (ILD) 116 removed so that the gate dielectric 110 is visible below the gate metal portions 108 of each of the gate stacks 106.
  • a legend provided within a dashed box at the bottom of FIG. 1 illustrates patterns used to indicate some of the elements shown in FIG. 1, so that FIG. 1 is not cluttered by too many reference numerals. These considerations are also applicable to FIGS. 2A-2B, FIG. 3, and FIGS. 6A-6K, showing views similar to those shown in FIG. 1, and using a similar/same notation. In all of the present FIGS., same reference numerals refer to the same or analogous elements/materials shown.
  • the quantum dot device 100 may include a substrate 102, a quantum well stack 104 provided over the substrate 102, and a plurality of gate stacks 106 provided in contact with the quantum well stack 104.
  • the substrate 102 may be any substrate which may serve as a foundation for housing quantum circuits.
  • the substrate 102 may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof.
  • the substrate 102 may be non-crystalline.
  • any material that provides sufficient advantages e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques
  • to outweigh the possible disadvantages e.g. negative effects of various defects
  • Additional examples of substrates which may serve as the substrate 102 on which the quantum dot devices as described herein may be fabricated include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.
  • SOI silicon-on-insulator
  • the quantum well stack 104 may include a plurality of layers, each of which is provided substantially perpendicular to the substrate 102, i.e. if the substrate 102 is considered to be horizontal, then each of the layers of the quantum well stack 104 is a vertical layer, illustrated with exemplary vertical lines shown within the quantum well stack 104 in the upper left and lower left illustrations of FIG. 1.
  • the individual layers of the quantum well stack 104 are stacked in a direction substantially parallel to the plane of the substrate 102 (which direction is illustrated in FIG. 1 with an arrow 108), or, phrased differently, a normal to the planes of the layers of the quantum well stack 104 (which normal is also in the direction 112) is substantially parallel to the substrate 102.
  • a quantum well stack 104 may include at least one quantum well layer 152 (not specifically shown in FIG. 1, but discussed below) in which quantum dots may be localized during operation of the quantum dot device 100; examples of quantum well stacks 104 are discussed below with reference to FIG. 3.
  • Each of the gate stacks 106 is a stack of a gate metal 110 and a gate dielectric 112. Only two of the gate stacks 106 are specifically labeled in FIG. 1 in order to not clutter the drawing, but an exemplary 4x6 array of the gate stacks 106 (i.e. 24 gate stacks in total) is illustrated in the lower right portion view of FIG. 1.
  • the quantum dot device 100 may include any other number of such gate stacks 106.
  • each of the gate stacks 106 may include an individual gate dielectric 112, e.g. the gate dielectric 112 of each of the gate stacks 106 may include a dielectric material provided only between the gate metal 110 and the portion of the quantum well stack 104.
  • the gate dielectric 112 may be in contact with the quantum well stack 104, and, for each of the gate stacks 106, the gate dielectric 112 is between the respective gate metal 110 and the respective portion of the quantum well stack 104.
  • each of the gate metals 110 may be provided as a strip of a suitable conductive or superconductive material.
  • a strip of the gate metal 110 may have a width (i.e. a dimension measured along the x-axis shown in FIG. 1) between about 10 and 500 nanometers (nm), including all values and ranges therein, e.g. between about 20 and 100 nm, or between about 30 and 50 nm, and a thickness (i.e. a dimension measured along the z-axis shown in FIG. 1) between about 10 and 500 nm, including all values and ranges therein, e.g. between about 20 and 100 nm, or between about 30 and 50 nm.
  • the individual strips of the gate metal 110 may be stacked above one another in a step-like manner, as can be seen in the lower left illustration of FIG. 1, electrically insulated from one another with an insulating spacer 114, to form a column 120 of the gate metals 110 (4 such columns are shown in the exemplary embodiment of the quantum dot device 100 of FIG. 1, indicated as columns 120-1 through 120-4).
  • individual gate stacks of the plurality of gate stacks may be aligned along a single line substantially perpendicular to the substrate 102.
  • quantum dots may be formed in the portions of the quantum well stack 104 behind the gate metals 110 for the gate stacks biased to function as quantum dot gates, as described in greater detail below (i.e. the resulting quantum dots may also be arranged in columns, i.e. along a line perpendicular to the substrate, at a distance from one another).
  • the individual strips of the gate metal 110 may further be arranged in rows (6 such rows are shown in the exemplary embodiment of the quantum dot device 100 of FIG. 1, indicated as rows 122-1 through 122-6).
  • the individual strips of the gate metal 110 may have different lengths (i.e.
  • the lengths of the gate metals 110 may be between about 50 and 500,000 nm, including all values and ranges therein, e.g. between about 500 and 100,000 nm, or between about 1000 and 50,000.
  • the lengths of any pair of individual gate metals 110 closest to one another i.e. one "step” of the gate metal 110 and the next “step” of the gate metal 110
  • various gate stacks 106 are provided at different distances from the substrate.
  • the gate stacks 106 of the upper most row 122-1 (i.e. the shortest "step” of the step-like arrangement shown in FIG. 1) of the vertical array of gate stacks are provided at a distance to the substrate 102 than the gate stacks 106 of the lowest row 122-6 (i.e. the longest "step” of the step-like arrangement shown in FIG. 1).
  • the spacer 114 separating the different layers of the gate metals 110 may have a thickness (i.e. a dimension measured along the z-axis shown in FIG. 1) between about 1 and 500 nm, including all values and ranges therein, e.g. between about 5 and 100 nm, or between about 10 and 50 nm.
  • the pairs of two closest different columns of the gate metals 110 e.g. each pair of the two closest columns of the 4 columns shown in the exemplary embodiment of FIG. 1 may be separated by a distance (i.e. a dimension measured along the x-axis shown in FIG. 1) between about 5 and 500 nm, including all values and ranges therein, e.g.
  • the plurality of gate stacks 106 may have a pitch (i.e. center-to-center distance) between about 10 and 500 nm, including all values and ranges therein, e.g. between about 20 and 200 nm, or between about 35 and 50 nm.
  • each of the gate stacks 106 may be provided by means of gate contact metal 118, e.g. provided in vias as shown in FIG. 1, electrically connected to the respective gate metal 110.
  • the gate contact metals 118 for the individual gate stacks 106 are electrically isolated from one another by the ILD 116. Because of the step-like arrangement of the gate metals 110 of different gate stacks 106 within each column 120, contacts 118 to individual gate metals 110 of a given column 120 may be seen as electrically conductive vias arranged along a single plane substantially perpendicular to the substrate 120, e.g. illustrated in the upper left view of FIG. 1 as a plane shown with a dotted line 124.
  • the array of gate contacts 118 allows different ones of the gates 106 to be separately electrically controlled.
  • the vertical positioning of the quantum well stack 104, and the step-like arrangement of the gate metals 110 may be particularly advantageous for providing easier control of the individual gates 106, i.e. easier control of the individual quantum dots formed in the vicinity of those gates as a result of the gate operation.
  • some of the gate stacks 106 may form quantum dot gates, while other gate stacks 106 may form barrier gates, depending on the biases (e.g. voltages) applied to the individual gates 106. Still other gate stacks 106 may act as
  • quantum dot gate (also sometimes interchangeably referred to as a “plunger gate”) is used to describe a gate under which an electrostatic quantum dot is formed during operation of the quantum dot device, e.g. the quantum dot device 100.
  • the electric field in the quantum well stack adjacent to that gate can be modulated/changed to create an energy valley (assuming electron-based quantum dot qubits) between the tunnel barriers created by the barrier gates.
  • electrical signals may be provided to a quantum dot gate (and neighboring gates) to cause a quantum dot (e.g., an electron spin-based quantum dot) to form in the portion of the quantum well stack 104 adjacent to the quantum dot gate.
  • a quantum dot e.g., an electron spin-based quantum dot
  • the term "barrier gate” is used to describe a gate used to set a tunnel barrier (i.e. a potential barrier) between either two quantum dot gates (i.e. controlling tunneling of charge carrier(s), e.g. electrons, from one quantum dot to an adjacent quantum dot) or a quantum dot gate and an accumulation gate.
  • a tunnel barrier i.e. a potential barrier
  • the control logic of the quantum dot device changes the voltage applied to a barrier gate, it changes the height of the tunnel barrier.
  • the barrier gate may be used to transfer charge carriers between quantum dots that may be formed in areas of the quantum well adjacent to these quantum dot gates.
  • the barrier gate When a barrier gate is used to set a tunnel barrier between a quantum dot gate and an accumulation gate, the barrier gate may be used to transfer charge carriers in and out of the quantum dot array via the accumulation gate.
  • electrical signals e.g., voltages, RF, and/or microwave signals
  • a barrier gate may be provided between each pair of quantum dot gates, as explained below.
  • accumulation gate (also referred to as “accumulation region”) is used to describe a gate used to form a two-dimensional electron gas (2DEG) in an area that is between the area where the quantum dots may be formed and a charge carrier reservoir.
  • 2DEG two-dimensional electron gas
  • Changing the voltage applied to the accumulation gate allows the control logic of the quantum dot device to control the number of charge carriers in the area under the accumulation gate.
  • changing the voltage applied to the accumulation gate allows reducing the number of charge carriers in the area under the gate so that single charge carriers can be transferred from the reservoir into the quantum dot array, and vice versa.
  • Accumulation regions may be electrically coupled to the quantum well layer of the quantum well stack 104.
  • the accumulation regions may be regions in which carriers accumulate (e.g., due to doping, or due to the presence of large electrodes that pull carriers into the quantum well layer), and may serve as reservoirs of carriers that can be selectively drawn into the areas of the quantum well layer under the quantum dot gates (e.g., by controlling the voltages on the quantum dot gates and the barrier gates) to form carrier-based quantum dots (e.g., electron or hole quantum dots).
  • a quantum dot device 100 may not include lateral accumulation regions, but may instead include doped layers within the quantum well stack 104. These doped layers may provide the carriers to the quantum well layer. Any combination of accumulation regions (e.g., doped or non-doped) or doped layers in a quantum well stack 104 may be used in any of the embodiments of the quantum dot devices 100 disclosed herein.
  • FIG. 2A One exemplary biasing scheme which may be used to set which gate stacks 106 act as barrier gates and which act as quantum dot gates is shown in FIG. 2A, illustrating a view of a quantum dot device 200A similar to the quantum dot device 100 shown in the lower right portion of FIG. 1, but with a different number of rows and columns of the gate metals 110.
  • each of the squares 240 illustrate a different gate, e.g. a different gate stack 106.
  • the squares 240 shown in black illustrate gates biased to act as quantum dot gates (i.e., during operation, quantum dots would form in the portion of the quantum well stack 104 that is behind (in the view of FIG. 2A) the gate dielectric 112 behind the black squares), the squares 240 shown with a brick pattern illustrate gates biased to act as barrier gates, while the squares 240 shown in white illustrate gates biased to act as accumulation gates. This creates a two-dimensional rectangular, i.e. an array of quantum dots with each pair of quantum dots separated by a barrier gate.
  • FIG. 2B Another exemplary biasing scheme which may be used to set which gate stacks 106 act as barrier gates and which act as quantum dot gates is shown in FIG. 2B, illustrating a view of a quantum dot device 200B similar to the quantum dot device 100 shown in the lower right portion of FIG. 1, but with a different number of rows and columns of the gate metals 110.
  • the squares 240 shown in black illustrate gates biased to act as quantum dot gates
  • the squares 240 shown with a brick pattern illustrate gates biased to act as barrier gates
  • the squares 240 shown in white illustrate gates biased to act as accumulation gate.
  • the accumulation regions between neighboring accumulation gates can merge, creating a single accumulation region. This creates columns which each containing a single quantum dot with an accumulation region above and below.
  • any of the gate metals 110 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride.
  • the gate dielectric 112 may be any suitable material.
  • the gate dielectric 112 may be silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide.
  • the gate dielectric 112 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • Examples of materials that may be used in the gate dielectric 112 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric 112 to improve the quality of the gate dielectric 112.
  • the gate dielectric 112 may be a multilayer gate dielectric, with the layers stacked up in the direction of the arrow 108 shown in FIG. 1.
  • the spacer materials e.g., the spacer material 114 may be any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride).
  • the insulating materials 116 may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride, for example.
  • the gate contact metal 118 may include any suitable conductive or superconductive material, such as e.g.
  • the quantum dot device 100 may include a set of magnets above some or all of the quantum dot gates such that the quantum dot gates are disposed between corresponding magnets and the quantum well stack 104.
  • each magnet along a quantum dot gate may have a different associated frequency. This frequency may be engineered to take a particular value, or different magnets may have different frequencies due to process variations.
  • any suitable magnets may be used, and each magnet may thus act as an "antenna” for directing energy of a matching frequency to the quantum dot associated with the magnet.
  • a microwave pulse e.g., in the gigahertz range
  • the frequency of the microwave pulse may allow the quantum dot p to be selected by the field gradient of the associated magnet, and thus the microwave pulse may change only the state of the quantum dot p (and not other quantum dots disposed below the same quantum dot gate).
  • the voltages on the other quantum dot gates may remain fixed, and the voltages on the barrier gates may also remain fixed to confine the Pauli gate operation to the quantum dot p.
  • FIG. 1 illustrates a particular number of gate stacks 106, columns 120, and rows 122, this is simply for illustrative purposes, and any number of gate stacks 106, columns 120, and rows 122 may be included in a quantum dot device 100.
  • Electrical interconnects e.g., vias and conductive lines
  • FIG. 3 is a cross-sectional view of a double-sided quantum dot device 300, in accordance with various embodiments.
  • the quantum dot device 300 of FIG. 3 may be formed by fabricating the quantum dot device discussed with reference to FIG. 1 on both sides of the quantum well stack 104, e.g. as described below with reference to FIGS. 6A-6K.
  • the quantum well stack 104 may itself include two quantum well layers, one in which quantum dots may be formed by the gates on the corresponding side of the quantum well stack 104, and the other in which quantum dots may be formed by the gates on the other, corresponding side of the quantum well stack 104.
  • the two such quantum well layers are schematically illustrated in the example of FIG. 3 as quantum well layers 324-1 and 324-2 within each of which some exemplary quantum dots shown as white circles.
  • Respective gate dielectrics 112 of the gate stacks on each side of the quantum well stack 104 are shown in FIG. 3 as a first gate dielectric 112-1 and a second gate dielectric 112-2.
  • the quantum dots formed in one of the quantum well layers may act as the "active" quantum dots in the quantum dot device 100, and the quantum dots formed in the other of the quantum well layers may act as the "read” quantum dots, sensing the state of the active quantum dots for readout (e.g., through the corresponding gates and other interconnects).
  • Similar double sided quantum dot devices may be formed using the alternative arrangements of the quantum dot device as e.g. shown in FIGS. 2A-2B, all of which being within the scope of the present disclosure.
  • FIGS. 4A-4E illustrate various examples of quantum well stacks 104 that may provide the quantum well stacks 104 of any of the embodiments of the quantum dot devices 100, 200, and 300disclosed herein.
  • FIGS. 4A-4E illustrate the quantum well stacks in a horizontal position in order to show the order of the layers, but within various quantum dot devices 100, 200, and 300 each of such quantum well stacks would be rotated by 90 degrees to be in a vertical position (i.e.
  • the layers of the quantum well stacks 104 may be grown by epitaxy.
  • the quantum well stacks 104 illustrated in FIG. 4 each include two quantum well layers 152 (e.g., as appropriate for a double-sided device, as discussed above with reference to FIG. 3)
  • the quantum well stack 104 included in any of the quantum dot devices 100, 200, and 300 may include one quantum well layer 152 or more than two quantum well layers 152; elements may be omitted from the quantum well stacks 104, or added to the quantum well stacks 104, to achieve various embodiments, as appropriate.
  • Layers other than the quantum well layer(s) 152 in a quantum well stack 104 may have higher threshold voltages for conduction than the quantum well layer(s) 152 so that when the quantum well layer(s) 152 are biased at their threshold voltages, the quantum well layer(s) 152 conduct and the other layers of the quantum well stack 104 do not. This may avoid parallel conduction in both the quantum well layer(s) 152 and the other layers, and thus avoid compromising the strong mobility of the quantum well layer(s) 152 with conduction in layers having inferior mobility.
  • FIG. 4A is a cross-sectional view of a quantum well stack 104 including only a quantum well layer 152-1, a barrier layer 154, and a quantum well layer 152-2.
  • the quantum well layers 152 of FIG. 4A may be formed of intrinsic silicon, and the gate dielectrics 112 may be formed of silicon oxide; in such an arrangement, during use of the quantum dot device 100, a 2DEG may form in the intrinsic silicon at the interface between the intrinsic silicon and the proximate silicon oxide.
  • the quantum well layers 152 of FIG. 4A are formed of intrinsic silicon may be particularly advantageous for electron-type quantum dot devices 100, 200, and 300.
  • the quantum well layers 152 of FIG. 4A may be formed of intrinsic germanium, and the gate dielectrics 112 may be formed of germanium oxide; in such an
  • a 2DEG may form in the intrinsic germanium at the interface between the intrinsic germanium and the proximate germanium oxide. Such embodiments may be particularly advantageous for hole-type quantum dot devices 100, 200, and 300.
  • the quantum well layers 152 may be strained, while in other embodiments, the quantum well layers 152 may not be strained.
  • the barrier layer 154 of FIG. 4A may provide a potential barrier between the quantum well layer 152-1 and the quantum well layer 152-2.
  • the barrier layer 154 may be formed of silicon
  • germanium The germanium content of this silicon germanium may be about 20-80% (e.g., about 30%).
  • the barrier layer 154 may be formed of silicon germanium (with a germanium content of about 20-80% (e.g., about 70%)).
  • the thicknesses (i.e., dimensions measure along the y-axis of the coordinate systems shown in FIGS. 1-3) of the layers in the quantum well stack 104 of FIG. 4A may take any suitable values.
  • the thickness of the barrier layer 154 e.g., silicon germanium
  • the thickness of the barrier layer 154 may be between about 0 and 400 nm, including all values and ranges therein, e.g. below about 100 nm.
  • the thickness of the quantum well layers 152 may be between about 5 and 30 nm, including all values and ranges therein.
  • FIG. 4B is a cross-sectional view of a quantum well stack 104 including quantum well layers 152-1 and 152-2, a barrier layer 154-2 disposed between the quantum well layers 152-1 and 152-2, and additional barrier layers 154-1 and 154-3.
  • the barrier layer 154-1 may be disposed between the quantum well layer 152-1 and the first gate dielectric 112-1
  • the barrier layer 154-3 may be disposed between the quantum well layer 152- 2 and the second gate dielectric 112-2.
  • the barrier layer 154-3 may be formed of a material (e.g., silicon germanium), and when the quantum well stack 104 is being grown, the barrier layer 154-3 may include a buffer region of that material.
  • This buffer region may trap defects that form in this material as it is grown, and in some embodiments, the buffer region may be grown under different conditions (e.g., deposition temperature or growth rate) from the rest of the barrier layer 154-3. In particular, the rest of the barrier layer 154-3 may be grown under conditions that achieve fewer defects than the buffer region. In some embodiments, the buffer region may be lattice mismatched with the quantum well layer(s) 152 in a quantum well stack 104, imparting biaxial strain to the quantum well layer(s) 152.
  • the barrier layers 154-1 and 154-3 may provide potential energy barriers around the quantum well layers 152-1 and 152-2, respectively, and the barrier layer 154-1 may take the form of any of the embodiments of the barrier layer 154-3 discussed herein.
  • the barrier layer 154-1 may have a similar form as the barrier layer 154-3, but may not include a "buffer region" as discussed above; in the quantum dot device 100, the barrier layer 154-3 and the barrier layer 154-1 may have substantially the same structure.
  • the barrier layer 154-2 may take the form of any of the embodiments of the barrier layer 154 discussed above with reference to FIG. 4A.
  • the thickness of the barrier layers 154-1 and 154-3 (e.g., silicon germanium) in the quantum dot device 100 may be between about 0 and 400 nm.
  • the thickness of the quantum well layers 152 e.g., silicon or germanium
  • the thickness of the barrier layer 154-2 e.g., silicon germanium
  • the thickness of the barrier layer 154-2 may be between about 25 and 75 nm (e.g., about 32 nm).
  • FIGS. 4C-4D illustrate examples of quantum well stacks 104 including doped layer(s) 137.
  • doped layer(s) 137 may be included in a quantum well stack 104 instead of or in addition to an accumulation region 162.
  • FIG. 4C is a cross-sectional view of a quantum well stack 104 including a buffer layer 176, a barrier layer 155-2, a quantum well layer 152-2, a barrier layer 154-2, a doped layer 137, a barrier layer 154-1, a quantum well layer 152-1, and a barrier layer 155-1.
  • the buffer layer 176 may be formed of the same material as the barrier layer 155-2, and may be present to trap defects that form in this material as it is grown. In some embodiments, the buffer layer 176 may be grown under different conditions (e.g., deposition temperature or growth rate) from the barrier layer 155-2. In particular, the barrier layer 155-2 may be grown under conditions that achieve fewer defects than the buffer layer 176.
  • the silicon germanium of the buffer layer 176 may have a germanium content that varies to the barrier layer 155-2; for example, the silicon germanium of the buffer layer 176 may have a germanium content that varies from zero percent to a non-zero percent (e.g., about 30%) at the barrier layer 155-2.
  • the buffer layer 176 may be grown beyond its critical layer thickness such that it is substantially free of stress from the underlying base (and thus may be referred to as "relaxed").
  • the thickness of the buffer layer 176 e.g., silicon germanium
  • the buffer layer 176 may be lattice mismatched with the quantum well layer(s) 152 in a quantum well stack 104, imparting biaxial strain to the quantum well layer(s) 152.
  • the barrier layer 155-2 may provide a potential energy barrier proximate to the quantum well layer 152-2.
  • the barrier layer 155-2 may be formed of any suitable materials.
  • the quantum well layer 152 may be formed of silicon or germanium.
  • the thickness of the barrier layer 155-2 may be between about 0 and 400 nm (e.g., between about 25 and 75 nm).
  • the quantum well layer 152-2 may be formed of a different material than the barrier layer 155-2.
  • a quantum well layer 152 may be formed of a material such that, during operation of the quantum dot devices 100, 200, and 300, a 2DEG may form in the quantum well layer 152.
  • Embodiments in which the quantum well layer 152 is formed of intrinsic silicon may be particularly advantageous for electron-type quantum dot devices 100, 200, and 300.
  • Embodiments in which a quantum well layer 152 is formed of intrinsic germanium may be particularly advantageous for hole- type quantum dot devices 100, 200, and 300.
  • a quantum well layer 152 may be strained, while in other embodiments, a quantum well layer 152 may not be strained.
  • the thickness of a quantum well layer 152 may take any suitable values; in some embodiments, a quantum well layer 152 may have a thickness between about 5 and 30 nm.
  • the doped layer 137 may be "shared" by the two quantum well layers 152 in the quantum well stack 104, in that the doped layer 137 provides carriers to the quantum well layer 152-1 and the quantum well layer 152-2 during use.
  • the quantum well layer 152-1 may be disposed between the doped layer 137 and the first gate dielectric 112-1
  • the quantum well layer 152-2 may be disposed between the doped layer 137 and the second gate dielectric 112-2.
  • the doping concentration of the doped layer 137 may be between about 10 17 /cm 3 and 10 20 /cm 3 (e.g., between about 10 17 /cm 3 and 10 18 /cm 3 ).
  • the thickness (i.e., z-height) of the doped layer 137 may depend on the doping concentration, among other factors, and in some embodiments, may be between about 5 and 50 nm (e.g., between about 20 and 30 nm).
  • a doped layer 137 may be formed using any of a number of techniques.
  • a doped layer 137 may be formed of an undoped base material (e.g., silicon germanium) that is doped in situ during growth of the base material by epitaxy.
  • a doped layer 137 may initially be fully formed of an undoped base material (e.g., silicon germanium), then a layer of dopant may be deposited on this base material (e.g., a monolayer of the desired dopant), and an annealing process may be performed to drive the dopant into the base material.
  • a doped layer 137 may initially be fully formed of an undoped base material (e.g., silicon germanium), and the dopant may be implanted into the lattice (and, in some embodiments, may be subsequently annealed).
  • a doped layer 137 may be provided by a silicon germanium layer (e.g., with about 90% germanium content) doped with an n-type dopant. In general, any suitable technique may be used to form a doped layer 137.
  • the barrier layer 154-2 may not be doped, and thus may provide a barrier to prevent impurities in the doped layer 137 from diffusing into the quantum well layer 152-2 and forming recombination sites or other defects that may reduce channel conduction and thereby impede performance of the quantum dot devices 100, 200, and 300.
  • the doped layer 137 may include a same material as the barrier layer 154- 2, but the barrier layer 154-2 may not be doped.
  • the doped layer 137 and the barrier layer 154-2 may both be silicon germanium.
  • the barrier layer 154-2 may be formed of silicon germanium.
  • the germanium content of this silicon germanium may be about 20-80% (e.g., about 30%).
  • the barrier layer 154-2 may be formed of silicon germanium (with a germanium content of about 20- 80% (e.g., about 70%)).
  • the thickness of the barrier layer 154-2 may depend on the doping concentration of the doped layer 137, among other factors discussed below, and in some embodiments, may be between about 5 and 50 nm (e.g., between about 20 and 30 nm).
  • the barrier layer 154-1 may provide a barrier to prevent impurities in the doped layer 137 from diffusing into the quantum well layer 152-1, and may take any of the forms described herein for the barrier layer 154-2.
  • the quantum well layer 152-1 may take any of the forms described herein for the quantum well layer 152-2.
  • the barrier layer 155-1 may provide a potential energy barrier proximate to the quantum well layer 152-1 (as discussed above with reference to the barrier layer 155-2 and the quantum well layer 152-2), and may take any of the forms described herein for the barrier layer 155-2.
  • the thickness of a barrier layer 154 may impact the ease with which carriers in the doped layer 137 can move into a quantum well layer 152 disposed on the other side of the barrier layer 154.
  • the thicker the barrier layer 154 the more difficult it may be for carriers to move into the quantum well layer 152; at the same time, the thicker the barrier layer 154, the more effective it may be at preventing impurities from the doped layer 137 from moving into the quantum well layer 152.
  • the diffusion of impurities may depend on the temperature at which the quantum dot devices 100, 200, and 300 operate.
  • the thickness of the barrier layer 154 may be adjusted to achieve a desired energy barrier and impurity screening effect between the doped layer 137 and the quantum well layer 152 during expected operating conditions.
  • quantum well stack 104 of FIG. 4C e.g., those included in "single-sided" quantum dot devices described herein, e.g. quantum dot device 100
  • only a single quantum well layer 152 may be included.
  • the layers 154-1 and 152-1 may be omitted, and gates may be formed proximate to the barrier layer 155-1 such that the quantum well layer 152- 1 is disposed between the gates and the doped layer 137.
  • the layers 154-1, 152-1, and 155-2 may be omitted, and gates may be formed proximate to the doped layer 137.
  • the buffer layer 176 and/or the barrier layer 155-2 may be omitted from the quantum well stack 104 of FIG. 4C.
  • FIG. 4D is a cross-sectional view of a quantum well stack 104 that is similar to the quantum well stack 104 of FIG. 4C, except that in the place of the single doped layer 137 shared by two quantum well layers 152, the quantum well stack 104 of FIG. 4D includes two different doped layers 137-2 and 137-1 (spaced apart by a barrier layer 155-3).
  • the doped layer 137-2 may provide a source of carriers for the quantum well layer 152-2
  • the doped layer 137-1 may provide a source of carriers for the quantum well layer 152-1.
  • the barrier layer 155-3 may provide a potential barrier between the two doped layers 137, and may take any suitable form.
  • the elements of the quantum well stack 104 of FIG. 4D may take the form of any of the corresponding elements of the quantum well stack 104 of FIG. 4C.
  • 2 may have the same geometry and material composition, or may have different geometries and/or material compositions.
  • FIG. 4E is a cross-sectional view of a quantum well stack 104 in which two doped layers 137-
  • the quantum well layer 152-2 is disposed between the doped layer 137-2 and the quantum well layer 152-1, and the quantum well layer 152-1 is disposed between the doped layer 137-1 and the quantum well layer 152-2.
  • the doped layer 137-1 may be disposed between the quantum well layer 152-1 and the first gate dielectric 112-1, while the doped layer 137-
  • a barrier layer 155-3 provides a potential barrier between the quantum well layers 152-1 and 152-2 (rather than between the doped layers 137-1 and 137-2, as illustrated in the quantum well stack 104 of FIG. 4D).
  • the elements of the quantum well stack 104 of FIG. 4E may take the form of any of the corresponding elements of the quantum well stack 104 of FIGS. 4A-D.
  • the quantum well stack 104 may include a silicon base, a buffer layer 176 of silicon germanium (e.g., with 30% germanium content), then a doped layer 137 formed of silicon germanium doped with an n-type dopant, a thin barrier layer 154 formed of silicon germanium (e.g., silicon germanium with 70% germanium content), a silicon quantum well layer 152, and a barrier layer 155 formed of silicon germanium (e.g., with 30% germanium content); in such an embodiment, the gates may be disposed on the barrier layer 155.
  • the quantum well stack 104 may include a silicon base, a doped layer 137 formed of silicon doped with an n-type dopant, a thin barrier layer 154 formed of silicon germanium, and a silicon quantum well layer 152; in such an embodiment, the gates may be disposed on the silicon quantum well layer 152.
  • FIGS. 5A-5B provide a flow chart of one exemplary method 500 for fabricating quantum dot devices with vertical quantum well layers as described herein, according to some embodiments of the present disclosure. While the method 500 is particularly adapted for fabricating a double-sided quantum dot device, e.g. as the one shown in FIG. 3, this method is also applicable for fabricating single-sided quantum dot devices, possibly with minor modifications.
  • one or more operations may be performed in parallel to manufacture multiple quantum circuit assemblies as described herein substantially simultaneously.
  • the operations may be performed in a different order to reflect the architecture of a particular quantum circuit component in which one or more quantum circuit assemblies with vertical quantum well layers fabricated according to the method 500 are to be included.
  • the exemplary manufacturing method 500 may include other operations not specifically shown in FIGS. 5A-5B, such as e.g. various cleaning or planarization operations as known in the art.
  • the substrate may be cleaned prior to or/and after any of the processes of the method 500 described herein, e.g. to remove oxides, surface-bound organic and metallic contaminants, as well as subsurface contamination.
  • cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using hydrofluoric acid (HF)).
  • planarization may be carried out using either wet or dry planarization processes, e.g. planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.
  • CMP chemical mechanical planarization
  • FIGS. 6A-6K are cross-sections illustrating various example stages in the manufacture of a quantum circuit assembly using the method of FIGS. 5A-5B in accordance with some embodiments of the present disclosure.
  • FIGS. 6A-6K illustrates a top down view and two cross-sectional views similar to FIGS. 1 and 3.
  • the method 500 may begin with providing, over a substrate, a stack of gate metal layers separated by spacer dielectric layers (process 502 shown in FIG. 5A, a result of which is illustrated with an assembly 602 shown in FIG. 6A).
  • the assembly 602 illustrates the substrate 102, with pairs of a spacer dielectric, e.g. the spacer 114, and gate metal, e.g. the gate metal 110, layers stacked over one another, forming a stack 630.
  • the first gate metal layer may be provided over the substrate 102 without the spacer 114 in between.
  • the number of gate metal layers provided in the process 502 will define the number of staircase "steps" (i.e. the number of rows 122) of the future gate stack array.
  • any suitable deposition techniques may be used for providing the stack of gate metal layers separated by spacer dielectric layers in the process 502.
  • deposition techniques for depositing layers of electrically conductive gate metal layers include atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g. evaporative deposition, magnetron sputtering, or e-beam deposition), chemical vapor deposition (CVD), or electroplating.
  • deposition techniques for depositing layers of dielectric spacer layers include ALD, PVD, CVD, spin-coating, or dip-coating.
  • the layers may include materials and have thicknesses as described above with reference to the gate metals 110 and the spacer 114.
  • the method 500 may then proceed with patterning the stack of gate metal layers separated by spacer dielectric layers to form strips of gate metals (process 504 shown in FIG. 5A, a result of which is illustrated with an assembly 604 shown in FIG. 6B).
  • the assembly 604 illustrates the stack 630 patterned to create openings 632 extending through the stack to the substrate 102, thus defining gate metal strips and forming the columns 120 of the future gate stack array as described above.
  • any suitable patterning techniques may be used for forming openings 632 in the stack 630 in the process 504.
  • suitable patterning techniques include photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with a dry etch, such as e.g. RF reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE, to pattern the stack 630 of continuous layers into columns of specified geometries for a given implementation.
  • RIE reactive ion etch
  • ICP inductively coupled plasma
  • the method 500 may then proceed with filling the openings between the gate metal columns with a dielectric material (process 506 shown in FIG. 5A, a result of which is illustrated with an assembly 606 shown in FIG. 6C).
  • the assembly 606 illustrates that the spacer 114 may be deposited in between and above the columns 120.
  • a dielectric material different from the spacer 114 may be provided in the process 506, e.g. the ILD 116 as described above, or any other dielectric material that is able to be deposited into the openings 632 and which can serve to provide electrical isolation between the different columns 120.
  • any suitable deposition techniques for filling in dielectric materials may be used for filling the openings 632 with the dielectric material in the process 506.
  • Examples of such techniques include ALD, PVD, CVD, spin-coating, or dip-coating.
  • an opening for the future quantum well stack and gate dielectric of a quantum dot device may be created within the stack 630 patterned into columns 120 (process 508 shown in FIG. 5A, a result of which is illustrated with an assembly 608 shown in FIG. 6D).
  • the assembly 608 illustrates that an opening 634 extending through the stack 630 to the substrate 102 may be created, e.g. in the center of the stack 630 (center along the y-axis). In other embodiments, the opening 634 does not have to be in the center.
  • the assembly 608 further illustrates sidewalls 636 and a bottom 638 of the opening 634.
  • any suitable patterning techniques may be used for forming the openings 634 in the process 508, such as e.g. those described above with reference to the process 504.
  • Dimensions of the opening 634 may be such as to allow providing the gate dielectric 112 and the quantum well stack 104, both as described above, within the opening 634.
  • At least the sidewalls of the opening for the future quantum well stack and gate dielectric of a quantum dot device may then be lined with a gate dielectric material (process 510 shown in FIG. 5A, a result of which is illustrated with an assembly 610 shown in FIG. 6E).
  • the assembly 610 illustrates that the sidewalls 636 and the bottom 638 of the opening 634 may be lined with the gate dielectric 112.
  • the volume of the opening 634 is reduced but there still remains a smaller opening, as indicated in FIG. 6E with a smaller opening 640.
  • the gate dielectric 112 may be deposited not only within the opening 634, but also over upper surfaces 642 of the stack 630. Such a layer over the upper surfaces 642 may subsequently be removed, e.g. using a suitable
  • any suitable deposition techniques for conformally depositing materials onto selected surfaces may be used to line the opening 634 with the dielectric material in the process 510.
  • Examples of such techniques include ALD, CVD, plasma enhanced CVD (PECVD), or/and PVD processes. Thickness of the gate dielectric liner deposited in the process 510 is described above with reference to the gate dielectric 112.
  • the method 500 may then proceed with removing the gate dielectric material from the bottom of the opening, thereby exposing the underlying substrate (process 512 shown in FIG. 5A, a result of which is illustrated with an assembly 612 shown in FIG. 6F).
  • the assembly 612 illustrates that the gate dielectric 112 is removed to expose the substrate 102 at the bottom 638 of the opening 640.
  • the gate dielectric 112 is separated into the first gate dielectric 112-1 on one of the sidewalls 636 of the opening 634 and the second gate dielectric 112-2 on the other sidewall, and the opening 640 is transformed into an opening 644, as also shown in the assembly 612.
  • any suitable techniques for recessing dielectric materials may be used to remove the gate dielectric 112 from the bottom 638 of the opening 640 in the process 512.
  • Examples of such techniques include various RIE processes.
  • the method 500 may proceed with filling at least a portion of the opening resulting from performing the process 512 with a quantum well stack (process 514 shown in FIG. 5B, a result of which is illustrated with an assembly 614 shown in FIG. 6G).
  • the assembly 614 illustrates the quantum well stack 104 provided within the opening 644.
  • the quantum well stack 104 may include any suitable stack of materials as described above, and may be provided using various deposition techniques, such as e.g. epitaxial growth.
  • the columns 120 of the stack 630 may be patterned to create the staircase profile where the gate metal elements at different distances from the substrate have different lengths (process 516 shown in FIG. 5B, a result of which is illustrated with an assembly 616 shown in FIG.
  • any suitable patterning techniques may be used for forming the steps of the gate metals 110 in the process 516, such as e.g. those described above with reference to the process 504. Lengths of the gate metals 110 in different rows 122 may be as described above.
  • the method 500 may then proceed with filling the openings which may be created as a result of forming the staircase profile with a dielectric material (process 518 shown in FIG. 5B, a result of which is illustrated with an assembly 618 shown in FIG. 61).
  • the assembly 618 illustrates that the ILD 116 may be deposited in the process 518.
  • a dielectric material different from the ILD 116 may be provided in the process 518, e.g. the spacer 114 as described above, or any other suitable dielectric material.
  • any suitable deposition techniques for filling in dielectric materials may be used for filling the dielectric material in the process 518.
  • Examples of such techniques include ALD, PVD, CVD, spin-coating, or dip-coating.
  • opening for the future gate contacts to the gate metals of a quantum dot device may be created (process 520 shown in FIG. 5B, a result of which is illustrated with an assembly 620 shown in FIG. 6J).
  • the assembly 620 illustrates that openings 646, e.g. via openings, extending through the stack 630 to respective steps of the gate metals 110 may be created in the process 520.
  • any suitable patterning techniques may be used for forming the via openings 646 in the process 520, such as e.g. those described above with reference to the process 504. Dimensions of the openings 646 may be such as to allow providing suitable electrical conductive materials within the openings 646 in order to create gate contacts 118 as described above.
  • the method 500 may finish with providing electrically conductive gate contact materials within the via openings formed in the process 520 (process 522 shown in FIG. 5B, a result of which is illustrated with an assembly 622 shown in FIG. 6K).
  • the assembly 622 illustrates that the openings 646 are filled with the gate contact material 118, however, in other embodiments, the gate contact material 118 may be provided only on the sidewalls of the openings 646 and the center of the openings 646 may be either left void or filled with a different material, which material could then be either conductive (e.g. a conductive but not superconductive material) or a dielectric material (e.g. a ceramic).
  • any suitable deposition techniques for providing electrically conductive materials within via openings may be used to fill the opening 646 with the gate contact material 118 in the process 522.
  • suitable deposition techniques include ALD, CVD, plasma enhanced CVD (PECVD), or/and PVD processes.
  • processes may be performed in a different order.
  • the staircase profile may be created right after the continuous layers of the stack 630 are patterned into columns 120, or right after any other one of the processes shown in FIG. 5A.
  • the method 500 may also be applicable for fabricating single-sided quantum dot devices, with suitable differences to produce gates on only one side.
  • Quantum dot devices with vertical quantum well layers as described above may be included in any kind of qubit device assemblies or quantum processing devices/structures. Some examples of such devices/structures are illustrated in FIGS. 7A-7B, 8, and 9.
  • FIGS. 7A-7B are top views of a wafer 1100 and dies 1102 that may be formed from the wafer 1100, according to some embodiments of the present disclosure.
  • the die 1102 may include any of the quantum dot devices 100, 200, or/and 300 disclosed herein.
  • the wafer 1100 may include semiconductor material and may include one or more dies 1102 having conventional and quantum circuit device elements formed on a surface of the wafer 1100.
  • Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device.
  • the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product.
  • a die 1102 may include one or more quantum circuit assemblies with vertical quantum well layers in accordance with any of the designs described herein, as well as other 1C components.
  • the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102.
  • a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 2002 of FIG. 9) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • FIG. 8 is a cross-sectional side view of a device assembly 1200 that may include any of the quantum dot devices 100, 200, or/and 300 described herein.
  • the device assembly 1200 includes a number of components disposed on a circuit board 1202.
  • the device assembly 1200 may include components disposed on a first face 1240 of the circuit board 1202 and an opposing second face 1242 of the circuit board 1202; generally, components may be disposed on one or both faces 1240 and 1242.
  • the circuit board 1202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1202. Signal transfer between components or layer may happen with both low resistance DC connections or by either in-plane or out-of-plane capacitive connections.
  • the circuit board 1202 may be a package substrate or flexible board.
  • the 1C device assembly 1200 illustrated in FIG. 8 may include a package-on-interposer structure 1236 coupled to the first face 1240 of the circuit board 1202 by coupling components 1216.
  • the coupling components 1216 may electrically and mechanically couple the package-on- interposer structure 1236 to the circuit board 1202, and may include solder balls (as shown in FIG.
  • the coupling components 1216 may include other forms of electrical connections that may have no mechanical contact, such as parallel- plate capacitors or inductors, which can allow high-frequency connection between components without mechanical or DC connection.
  • the package-on-interposer structure 1236 may include a package 1220 coupled to an interposer 1204 by coupling components 1218.
  • the coupling components 1218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1216. Although a single package 1220 is shown in FIG. 8, multiple packages may be coupled to the interposer 1204; indeed, additional interposers may be coupled to the interposer 1204.
  • the interposer 1204 may provide an intervening substrate used to bridge the circuit board 1202 and the package 1220.
  • the package 1220 may be a quantum circuit device package as described herein, e.g. a package including one or more dies with any of the quantum dot devices 100, 200, or/and 300 described herein.
  • the package 1220 may be a conventional 1C package with non-quantum circuit assemblies.
  • the interposer 1204 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 1204 may couple the package 1220 (e.g., a die) to a ball grid array (BGA) of the coupling components 1216 for coupling to the circuit board 1202.
  • BGA ball grid array
  • the package 1220 and the circuit board 1202 are attached to opposing sides of the interposer 1204; in other embodiments, the package 1220 and the circuit board 1202 may be attached to a same side of the interposer 1204.
  • three or more components may be interconnected by way of the interposer 1204.
  • the interposer 1204 may be formed of a crystalline material, such as silicon, germanium, or other semiconductors, an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer 1204 may include metal interconnects 1210 and vias 1208, including but not limited to through-silicon vias (TSVs) 1206.
  • TSVs through-silicon vias
  • the interposer 1204 may further include embedded devices 1214, including both passive and active devices.
  • Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and
  • M EMS microelectromechanical systems
  • the device assembly 1200 may include a package 1224 coupled to the first face 1240 of the circuit board 1202 by coupling components 1222.
  • the coupling components 1222 may take the form of any of the embodiments discussed above with reference to the coupling components 1216
  • the package 1224 may take the form of any of the embodiments discussed above with reference to the package 1220.
  • the package 1224 may be a package including any of the quantum dot devices 100, 200, or/and 300 described herein or may be a conventional 1C package, for example.
  • the device assembly 1200 illustrated in FIG. 8 includes a package-on-package structure 1234 coupled to the second face 1242 of the circuit board 1202 by coupling components 1228.
  • the package-on-package structure 1234 may include a package 1226 and a package 1232 coupled together by coupling components 1230 such that the package 1226 is disposed between the circuit board 1202 and the package 1232.
  • the coupling components 1228 and 1230 may take the form of any of the embodiments of the coupling components 1216 discussed above, and the packages 1226 and 1232 may take the form of any of the embodiments of the package 1220 discussed above.
  • Each of the packages 1226 and 1232 may be a qubit device package with any of the quantum dot devices 100, 200, or/and 300 as described herein or may be a conventional 1C package, for example.
  • FIG. 9 is a block diagram of an exemplary quantum computing device 2000 that may include one or more of quantum circuit assemblies with any of the quantum dot devices 100, 200, or/and 300 in accordance with any of the configurations described herein, according to some embodiments of the present disclosure.
  • a number of components are illustrated in FIG. 9 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application.
  • some or all of the components included in the quantum computing device 2000 may be attached to one or more PCBs (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with any of the quantum circuit assemblies described herein.
  • PCBs e.g., a motherboard
  • various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die.
  • the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 9, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components.
  • the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled.
  • the quantum computing device 2000 may not include an audio input device 2018 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2018 or audio output device 2008 may be coupled.
  • the quantum computing device 2000 may include a microwave input device or a microwave output device (not specifically shown in FIG. 9), or may include microwave input or output device interface circuitry (e.g., connectors and supporting circuitry) to which a microwave input device or microwave output device may be coupled.
  • the quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices).
  • processing device e.g., one or more processing devices
  • the term "processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices).
  • the quantum processing device 2026 may include one or more of any of the quantum dot devices 100, 200, or/and 300 arranged in accordance with various embodiments described herein, and may perform data processing by performing operations on the quantum dots that may be generated in these quantum circuit assemblies, and monitoring the result of those operations. For example, different quantum dots may be allowed to interact, the quantum states of different quantum dots may be set or transformed, and the quantum states of different quantum dots may be read.
  • the quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc.
  • the quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.
  • the processing device 2002 may include a non-quantum processing device 2028.
  • the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026.
  • the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc.
  • the non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026.
  • the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components.
  • the non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
  • DSPs digital signal processors
  • ASICs application-specific ICs
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute cryptographic algorithms within hardware
  • server processors or any other suitable processing devices.
  • the quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid-state memory
  • solid-state memory solid-state memory
  • hard drive solid-state memory
  • the states of quantum dots in the quantum processing device 2026 may be read and stored in the memory 2004.
  • the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-M RAM).
  • eDRAM embedded dynamic random access memory
  • STT-M RAM spin transfer torque magnetic random access memory
  • the quantum computing device 2000 may include a cooling apparatus 2024.
  • the cooling apparatus 2024 may maintain the quantum processing device 2026, in particular the quantum dot devices 100, 200, or/and 300 as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2026.
  • This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less.
  • the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature.
  • the cooling apparatus 2024 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.
  • the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips).
  • the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
  • IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for
  • Microwave Access which is a certification mark for products that pass conformity
  • the communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • HSPA High Speed Packet Access
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • the communication chip 2012 may operate in accordance with other wireless protocols in other embodiments.
  • the quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless
  • the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet).
  • the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless
  • the quantum computing device 2000 may include battery/power circuitry 2014.
  • the battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).
  • the quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above).
  • the display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
  • LCD liquid crystal display
  • the quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above).
  • the audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
  • the quantum computing device 2000 may include an audio input device 2018 (or corresponding interface circuitry, as discussed above).
  • the audio input device 2018 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
  • MIDI musical instrument digital interface
  • the quantum computing device 2000 may include a GPS device 2016 (or corresponding interface circuitry, as discussed above).
  • the GPS device 2016 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.
  • the quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above).
  • Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
  • the quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above).
  • Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • RFID radio frequency identification
  • the quantum computing device 2000 may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
  • a hand-held or mobile computing device e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.
  • PDA personal digital assistant
  • a desktop computing device e.g., a
  • Example 1 provides a quantum dot device that includes a substrate, a quantum well stack provided over the substrate, and at least one gate stack, preferably a plurality of gate stacks.
  • the quantum well stack includes a plurality of planar layers, where planes of the plurality of layers are substantially perpendicular to the substrate (in other words, the layers of the quantum well stack are stacked in a direction substantially parallel to the substrate, or, phrased differently, a normal to the planes of the layers of the quantum well stack is substantially parallel to the substrate).
  • the at least one gate stack is adjacent to a portion of a first layer of the plurality of layers of the quantum well stack (such a "first layer" is the layer closest to the gate dielectric as described herein). In case a plurality of gate stacks are used, the gate stacks are adjacent to different portions of the first layer of the plurality of layers of the quantum well stack, where some of the different portions could be at different distances from the substrate.
  • Example 2 provides the quantum dot device according to Example 1, where the at least one gate stack includes a gate dielectric adjacent to the portion of the first layer and a gate metal, and where the gate dielectric is between the portion of the first layer and the gate metal.
  • Example 3 provides the quantum dot device according to Examples 1 or 2, where at least one gate stack is at least one first gate stack, and the quantum dot device further includes at least one second gate stack adjacent to the quantum well stack opposite the at least one first gate stack.
  • the quantum dot device could be a double-sided device having gate stacks on both sides of the quantum well stack.
  • Example 4 provides the quantum dot device according to any one Examples 1-3, where at least one gate stack includes a plurality of gate stacks adjacent to different portions of the first layer, where individual gate stacks of the plurality of gate stacks are provided at different distances from the substrate.
  • the plurality of gate stacks may be seen as arranged in a vertical array along a plane that is substantially perpendicular to the plane of the substrate and is substantially parallel to the planes of the plurality of layers of the quantum well stack.
  • Example 5 provides the quantum dot device according to Example 1, where at least one gate stack includes a plurality of gate stacks adjacent to different portions of the first layer, with individual gate stacks of the plurality of gate stacks being aligned along a line substantially perpendicular to the substrate.
  • the individual gate stacks may be stacked above one another, so that, in operation, quantum dots formed in portions of the quantum well stacks adjacent to at least some of such gate stacks are arranged substantially vertically with respect to the substrate (i.e. quantum dots are arranged along a line perpendicular to the substrate, at a distance from one another).
  • Vertical quantum dot arrays may allow for easier control of individual gates/quantum dots, especially when an arrangement described herein as a "step-like" arrangement is used.
  • Example 6 provides the quantum dot device according to Example 5, where each gate stack of the plurality of gate stacks includes a gate dielectric and a gate metal, and where the gate metals of different gate stacks of the plurality of gate stacks extend away from the first layer by different lengths.
  • Example 7 provides the quantum dot device according to Example 5, where each gate stack of the plurality of gate stacks includes a gate dielectric and a gate metal, and where the gate metals of different gate stacks are arranged over the substrate above one another as steps (i.e. in a step-like arrangement).
  • Example 8 provides the quantum dot device according to Example 5, where each gate stack of the plurality of gate stacks includes a gate dielectric and a gate metal, and where contacts to individual gate metals of the plurality of gate stacks include electrically conductive vias arranged along a single plane substantially perpendicular to the substrate.
  • Example 9 provides the quantum dot device according to any one of Examples 6-8, where the gate metals of different gate stacks are electrically isolated from one another, e.g. using a spacer material, which could be any suitable dielectric material.
  • Example 10 provides the quantum dot device according to any one of Examples 6-9, where the gate dielectric is adjacent to the first layer, and is between the first layer and the gate metal.
  • the materials of the gate stacks namely, the gate dielectric and the gate metal
  • the quantum well stack which includes a stack of layers provided substantially perpendicular to the substrate
  • gate dielectrics are provided adjacent to different portions of the first layer of the stack of layers
  • gate metals are provided so that, for each of the gate stacks, at least a portion of the gate dielectric is between the first layer of the quantum well stack and the corresponding gate metal.
  • the gate metals of different gate stacks are electrically isolated from one another.
  • Example 11 provides the quantum dot device according to any one of Examples 6-10, where the gate dielectrics of different gate stacks are parts of a substantially continuous layer of a dielectric material adjacent the first layer of the quantum well stack.
  • the gate dielectric may continuously extend between the gate metal of different gate stacks and the quantum well stack.
  • Example 12 provides the quantum dot device according to Example 1, where at least one gate stack includes a plurality of gate stacks aligned with (or, phrased differently, arranged as) points of an NxM array (i.e. aligned with points where different lines of an NxM grid of lines intersect one another), where each of N and M is an integer, and at least one of them is greater than 1, and where a plane of the NxM array is substantially parallel to the planes of the plurality of layers of the quantum well stack and is substantially perpendicular to the substrate.
  • quantum dots will be formed within the quantum well layer in an array that is substantially perpendicular to the substrate, thus forming a vertical quantum dot array.
  • Example 13 provides the quantum dot device according to Example 12, where an individual gate stack of the plurality of gate stacks includes a gate dielectric and a gate metal.
  • Example 14 provides the quantum dot device according to Example 13, where the gate metals of different individual gate stacks are electrically isolated from one another, e.g. using a spacer material.
  • Example 15 provides the quantum dot device according to Examples 13 or 14, where the gate dielectric of the individual gate stack is adjacent to the first layer, and is between the first layer and the corresponding gate metal.
  • the gate dielectric may continuously extend between the gate metal of different gate stacks and the quantum well stack.
  • Example 16 provides the quantum dot device according to any one of Examples 4-15, where the plurality of gate stacks includes a plurality of quantum dot gates and a plurality of barrier gates.
  • Example 17 provides the quantum dot device according to Example 16, where a quantum dot gate is between each nearest neighbor pair of barrier gates.
  • Example 18 provides the quantum dot device according to any one of Examples 4-17, where the plurality of gate stacks have a pitch between about 10 and 500 nm, including all values and ranges therein, e.g. between about 20 and 200 nm, or between about 35 and 50 nm.
  • Example 19 provides a method for forming a quantum dot device.
  • the method includes providing a stack of alternating layers of electrically conductive and dielectric materials over a substrate; patterning the stack to form two or more columns of the alternating layers of electrically conductive and dielectric materials, where each two nearest columns are separated by a respective opening; patterning the stack to create a staircase profile where alternating layers further away from the substrate are shorter than alternating layers closer to the substrate; providing electrical connections to at least some of the layers of the electrically conductive material; providing an opening within the stack; providing a gate dielectric on sidewalls of the opening; providing a quantum well stack within the opening with the gate dielectric so that layers of the quantum well stack are substantially perpendicular to the substrate.
  • Example 20 provides the method according to Example 19, where providing the gate dielectric on the sidewalls of the opening includes conformally depositing the gate dielectric on the sidewalls and bottom of the opening, followed by removal of the gate dielectric deposited on the bottom of the opening.
  • Example 21 provides the method according to Examples 19 or 20, further including depositing a dielectric material into the respective openings between each two nearest columns.
  • Example 22 provides a quantum computing device that includes a quantum processing device that includes a quantum dot device and a memory device to store data generated during operation of the quantum processing device.
  • the quantum dot device includes a quantum well stack provided over a substrate and including a plurality of layers, where planes of the plurality of layers are substantially perpendicular to the substrate, and a plurality of gate stacks adjacent to different portions of a first layer of the plurality of layers of the quantum well stack.
  • Example 23 provides the quantum computing device according to Example 22, further including a cooling apparatus configured to maintain the temperature of the quantum processing device below 5 degrees Kelvin.
  • Example 24 provides the quantum computing device according to any of Examples 22-23, where the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
  • Example 25 provides the quantum computing device according to any of Examples 22-24, further including a non-quantum processing device coupled to the quantum processing device.
  • the quantum dot device of the quantum processing device according to any one of Examples 22-25 may be Example provides the quantum dot device according to any one of the preceding Examples (e.g. Example provides the quantum dot device according to any one of Examples 1-18).

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Abstract

La présente invention concerne des dispositifs à points quantiques et des systèmes et procédés associés. Un dispositif à points quantiques donné à titre d'exemple peut comprendre un substrat logeant un empilement de puits quantiques ayant une pluralité de couches, et une pluralité d'empilements de grille adjacents à différentes parties d'une première couche de l'empilement de puits quantiques. Les couches de puits quantiques sont empilées dans une direction parallèle au substrat de telle sorte que chacune des couches est sensiblement perpendiculaire au substrat, c'est-à-dire que les couches sont verticales. Par conséquent, des points quantiques qui se forment dans la pile de puits quantiques pendant le fonctionnement du dispositif peuvent être vus comme étant agencés dans un réseau vertical. Les dispositifs à points quantiques décrits ici fournissent une forte localisation spatiale des points quantiques, une bonne variabilité dimensionnelle dans le nombre de points quantiques inclus dans le dispositif, et/ou une flexibilité de conception dans la réalisation de connexions électriques aux dispositifs à points quantiques.
PCT/US2017/066916 2017-12-18 2017-12-18 Dispositifs à points quantiques avec réseaux de points quantiques verticaux WO2019125348A1 (fr)

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US11417755B2 (en) 2018-01-08 2022-08-16 Intel Corporation Differentially strained quantum dot devices
US11417765B2 (en) 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US11335778B2 (en) 2018-06-26 2022-05-17 Intel Corporation Quantum dot devices with overlapping gates
US10910488B2 (en) 2018-06-26 2021-02-02 Intel Corporation Quantum dot devices with fins and partially wrapped gates
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US11749721B2 (en) 2018-09-28 2023-09-05 Intel Corporation Gate walls for quantum dot devices
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