WO2019125498A1 - Intégration à l'échelle de tranche de jonctions josephson à base de semi-conducteur - Google Patents

Intégration à l'échelle de tranche de jonctions josephson à base de semi-conducteur Download PDF

Info

Publication number
WO2019125498A1
WO2019125498A1 PCT/US2017/068366 US2017068366W WO2019125498A1 WO 2019125498 A1 WO2019125498 A1 WO 2019125498A1 US 2017068366 W US2017068366 W US 2017068366W WO 2019125498 A1 WO2019125498 A1 WO 2019125498A1
Authority
WO
WIPO (PCT)
Prior art keywords
quantum
trench
substrate
semiconductor
qubit
Prior art date
Application number
PCT/US2017/068366
Other languages
English (en)
Inventor
Ravi Pillarisetty
Nicole K. THOMAS
Roman CAUDILLO
James S. Clarke
Kanwaljit SINGH
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/068366 priority Critical patent/WO2019125498A1/fr
Publication of WO2019125498A1 publication Critical patent/WO2019125498A1/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H10N60/12—Josephson-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate

Definitions

  • This disclosure relates generally to the field of quantum computing, and more specifically, to Josephson Junctions for use in quantum circuits and to methods of fabrication thereof.
  • Quantum computing refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. These quantum-mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing.
  • Quantum computers use so-called quantum bits, referred to as qubits (both terms “bits” and “qubits” often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states - a uniquely quantum-mechanical phenomenon.
  • Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.
  • FIG. 1 provides a schematic illustration of an exemplary superconducting quantum circuit, according to some embodiments of the present disclosure.
  • FIGS. 2A-2B provides various views of a semiconductor-based Josephson Junction, in accordance with different exemplary embodiments of the present disclosure.
  • FIG. 3 provides a flow chart of an ART method for fabricating semiconductor-based
  • FIGS. 4A-4D are various views illustrating different exemplary stages in the manufacture of a quantum circuit assembly using the ART method of FIG. 3, in accordance with some embodiments of the present disclosure.
  • FIGS. 5A-5D are various views illustrating different exemplary stages in forming a trench opening during the manufacture of a quantum circuit assembly using the ART method of FIG. 3, in accordance with some embodiments of the present disclosure.
  • FIGS. 6A-6C are various views illustrating different exemplary stages in forming a trench opening during the manufacture of a quantum circuit assembly using the ART method of FIG. 3, in accordance with other embodiments of the present disclosure.
  • FIGS. 7A and 7B are top views of a wafer and dies that may include one or more of quantum circuit assemblies disclosed herein.
  • FIG. 8 is a cross-sectional side view of a device assembly that may include one or more of quantum circuit assemblies disclosed herein.
  • FIG. 9 is a block diagram of an exemplary quantum computing device that may include one or more of quantum circuit assemblies disclosed herein, in accordance with various embodiments.
  • quantum computing or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data.
  • quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states.
  • Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole.
  • superconducting qubits are promising candidates for building a quantum computer. All of superconducting qubits operate based on the Josephson effect, which refers to a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a device known as a Josephson Junction.
  • a Josephson Junction includes two superconductors (typically referred to as “electrodes” or “superconductors” of a Josephson Junction) coupled by a so-called “weak link” element that weakens the superconductivity in terms of the tunneling current between the two superconductors (the weak link element typically referred to as a “barrier” or a “tunnel barrier” of a Josephson Junction).
  • Josephson Junctions provide non-linear inductive elements for the quantum circuit and allow the qubit to become an anharmonic oscillator. In turn, the anharmonicity is what allows the state of the qubit to be controlled to a high level of fidelity.
  • One way to form a weak link of a Josephson Junction in a quantum circuit is to provide a semiconductor nanowire (i.e. an elongated element, a "wire," of a semiconductor material, the wire having a cross-sectional dimension on the order of a few nanometers) between two superconductor electrodes of the Junction. Due to the use of semiconductor materials for forming the weak link, such Josephson Junctions are typically referred to as “semiconductor-based" Josephson Junctions. A choice of a particular semiconductor material may be based on the required minimum critical current in the final Josephson Junction, where the term "critical current” refers to the highest current that can tunnel through the weak link before the superconducting state of the electrodes of the Josephson Junction is destroyed.
  • a conventional approach to fabricating semiconductor-based Josephson Junctions for quantum circuits includes growing nanowires of a suitable semiconductor material separately from the substrate on which a quantum circuit is to be provided (such a substrate referred to herein as a "qubit substrate"), and then transferring the nanowires, e.g. in a mixture of a fluid in which nanowires are suspended, to the qubit substrate, with the hope that some of the nanowires will end up in places on the qubit substrate where they are supposed to be - namely, between the two superconductor electrodes. While such an approach may be adequate for fabricating qubit devices with Josephson Junctions in a lab environment, it has a very low yield and is not consistent with wafer-scale manufacturing techniques used in the semiconductor industry.
  • Josephson Junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits. Therefore, improvements with respect to fabricating Josephson Junctions for use in quantum circuit assemblies are always desirable. In particular, it would be desirable to have methods for fabricating semiconductor-based Josephson Junctions that have adequate performance and can be manufactured using wafer-scale, e.g. very-large-scale-integration (VLSI), techniques.
  • VLSI very-large-scale-integration
  • Embodiments of the present disclosure propose methods of fabricating quantum circuit assemblies that include semiconductor-based Josephson Junctions, as well as qubit devices comprising such Junctions.
  • a method of fabricating a quantum circuit assembly with at least one semiconductor-based Josephson Junction is disclosed. The method is based on providing a semiconductor tunnel barrier element of a Josephson Junction by directly growing the semiconductor on the qubit substrate, e.g. using epitaxial growth. Epitaxially growing group lll-V or group IV compound semiconductors on silicon substrates is not an easy task due to the relatively large lattice mismatch between crystal lattices of such compound
  • the method described herein uses a phenomenon of aspect ratio trapping (ART) by growing a desired semiconductor within a relatively high-aspect ratio (AR) opening in or over a substrate made of a different semiconductor, where the lattice constant of the semiconductor being grown is different from the lattice constant of the semiconductor of the substrate (i.e. the two semiconductors are lattice mismatched), where the growth in the high-AR opening allows trapping a significant portion of defects due to the lattice mismatch in a region at the bottom of the opening.
  • ART aspect ratio trapping
  • an ART technique is used, where a semiconductor material that will form the tunnel barrier of a Josephson Junction (which material may include one or more semiconductor materials) is epitaxially grown in a trench formed over a semiconductor qubit substrate. Epitaxial growth within a trench could advantageously keep most of the crystalline defects contained at the bottom of the trench.
  • the semiconductor material that is closer/closest to the surface of the trench may be a material with sufficiently high crystallinity, as well as suitable dimensions (due to the growth of this material being restricted by the dimensions of the trench), so that it can serve as a semiconductor tunnel barrier of a Josephson Junction.
  • Such a method may be efficiently used in wafer-scale integration, providing a substantial improvement, e.g. in terms of atomic-level control and manufacturability, with respect to conventional approaches, such as e.g. the one described above, which include fabrications steps which are not suitable for implementing with larger wafer sizes used by leading edge device manufactures.
  • a method may lead to an improved yield because the growth process of semiconductor tunnel barriers can intentionally be initiated exactly in locations where the final Josephson Junctions need to be.
  • Some embodiments of such a method may also advantageously help decrease amount of spurious (i.e. unintentional and undesirable) two- level systems (TLS's), thought to be the dominant source of superconducting qubit decoherence, in the vicinity of Josephson Junctions.
  • TLS's two- level systems
  • the term "aspect ratio" is used to describe a ratio between a depth and a width of an opening.
  • An opening may be said to have a relatively high-AR, if the AR of the opening is e.g. above about 2, including all values and ranges therein, e.g. above about 3 or above about 5.
  • the opening in which the semiconductor material for forming the semiconductor tunnel barrier of a Josephson Junction is grown can be trench-like, i.e. the opening can extend in the direction substantially parallel to the plane of the qubit substrate.
  • some or all of the electrically conductive portions of various quantum circuit elements described herein may be made from one or more superconductive materials, i.e. superconductors.
  • these electrically conductive portions could be made from electrically conductive materials which are not
  • any material described herein as a "superconductive/superconducting material” or as a “superconductor” may refer to one or more materials, including alloys of materials, which exhibit superconducting behavior at typical qubit operating conditions (e.g. materials which exhibit superconducting behavior at very low temperatures at which qubits typically operate), but which may not exhibit such behavior at higher temperatures (e.g. at room temperatures).
  • Examples of such materials include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), niobium titanium nitride (NbTiN), indium (In), and molybdenum rhenium (MoRe), all of which are particular types of superconductors at qubit operating temperatures, as well as their alloys.
  • the phrase “A and/or B” means (A), (B), or (A and B).
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
  • the notation "A/B/C” means (A), (B), and/or (C).
  • the terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are typically operated at.
  • techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-10 GFIz, e.g. in 4-10 GFIz, range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering.
  • qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.
  • FIG. 1 provides a schematic illustration of an exemplary superconducting quantum circuit 100 that may include any of the quantum circuit assemblies described herein.
  • an exemplary superconducting quantum circuit 100 may include two or more qubits 102 (reference numerals following after a dash, such as e.g. qubit 102-1 and 102-2 indicate different instances of the same or analogous element).
  • Each of the superconducting qubits 102 may include one or more Josephson Junctions 104 electrically connected to one or more other circuit elements 106, which, in combination with the Josephson Junction(s) 104, form a non-linear circuit providing a unique two-level quantum state for the qubit.
  • a frequency of the qubit cannot be changed substantially beyond what is defined by the design unless one of the qubit capacitive elements is tunable.
  • SQUID superconducting quantum interference device
  • superconducting qubit includes a pair of Josephson Junctions and a loop of a conductive, typically superconductive material (i.e. a superconducting loop), connecting a pair of Josephson Junctions.
  • Applying a net magnetic field in a certain orientation to the SQUID loop of a superconducting qubit allows controlling the frequency of the qubit.
  • applying magnetic field to the SQUID region of a superconducting qubit is generally referred to as a "flux control" of a qubit, and the magnetic field is generated by providing direct current (DC) or a pulse of current through an electrically conductive or superconductive line generally referred to as a "flux bias line” (also known as a "flux line” or a “flux coil line”).
  • the one or more Josephson Junctions 104 may be directly electrically connected to one or more other circuit elements 106, which, in combination with the Josephson Junction(s) 104, form a non-linear oscillator circuit providing multi-level quantum system where the first two to three levels define the qubit under normal operation.
  • the circuit elements 106 could be e.g.
  • shunt capacitors superconducting loops of a SQUID, electrodes for setting an overall capacitance of a qubit, or/and ports for capacitively coupling the qubit to one or more of a readout resonator, a coupling resonator, and a direct microwave drive line, or electromagnetically coupling the qubit to a flux bias line.
  • an exemplary quantum circuit 100 typically includes a plurality of non-resonant transmission lines 108, and a plurality of resonators 110.
  • the non-resonant transmission lines 108 are typically used for providing microwave signals to different quantum circuit elements and components, such as e.g. various control lines for various qubits, and may be considered to implement external control of qubits.
  • examples of the non-resonant transmission lines 108 include flux bias lines, microwave lines, and readout lines.
  • the resonators 110 may be viewed as implementing internal control lines for qubit.
  • examples of the resonators 110 include coupling and readout resonators.
  • a resonator 110 of a quantum circuit differs from a non-resonant microwave transmission line 108 in that a resonator is deliberately designed to support resonant oscillations (i.e. resonance), under certain conditions.
  • non-resonant transmission lines may be similar to conventional microwave transmission lines in that they are designed to avoid resonances, especially resonances at frequencies/wavelengths close to the resonant frequencies/wavelengths of any resonant object used in the quantum computing circuits, e.g., qubits, bus resonators, or readout resonators in the proximity of such non-resonant lines.
  • non-resonant transmission lines Once non-resonant transmission lines are manufactured, some of them may inadvertently support some resonances, but, during its design, efforts are taken to minimize resonances, standing waves, and reflected signals as much as possible, so that all of the signals can be transmitted through these lines without, or with as little resonance as possible.
  • On-chip capacitive coupling between quantum or control elements can be achieved either through use of coupling components such as a coupling component on a neighboring qubit, a lumped element capacitor, a lumped element resonator, or a transmission line segment.
  • a transmission line segment is a resonator that is made by employing fixed boundary conditions, and these boundary conditions control the frequencies/wavelengths which will resonate within a given transmission line segment used to implement a resonator.
  • each end of a transmission line segment resonator can be either a node, if it is shorted to ground (e.g.
  • resonators 110 differ from non-resonant microwave transmission lines 108 in how these lines are terminated at the relevant ends.
  • a line used to route a signal on a substrate i.e. one of the non-resonant transmission lines 108, typically extends from a specific source, e.g. a bonding pad or another type of electrical connection to a source, to a specific load (e.g. a short circuit proximate to SQUID loop, a quantum dot device, another bonding pad, or another electrical connection to a load).
  • non-resonant transmission lines 108 terminate with direct electrical connections to sources, ground sinks, and/or loads.
  • a transmission line resonator is typically composed of a piece of transmission line terminated with either two open circuits (in case of a half-wavelength resonator) or an open and a short circuit (in case of a quarter-wavelength resonator).
  • transmission line length may e.g. be a multiple of a microwave wavelength divided by 2 or 4, respectively.
  • other terminations are possible, for example capacitive or inductive, and in this case the required line length to support resonance will be different from that identified above.
  • capacitive terminations may be used for resonators which are coupled to qubits, to a feedline, line, or to another resonator by a capacitive interaction.
  • transmission line segments of the resonators 110 need to be of a specific length that can support such oscillations. That is why, often times, resonators 110 may be laid out on a substrate longer than the actual distance would require (i.e. a non-resonant transmission line would typically be laid out to cover the distance in the most compact manner possible, e.g. without any curves, wiggles, or excess length, while a resonator may need to have curves, wiggles, and be longer than the shortest distance between the two elements the resonator is supposed to couple in order to be sufficiently long to support resonance).
  • Coupled resonators also known as “bus resonators”
  • bus resonators allow one method to couple different qubits together in order to realize quantum logic gates.
  • These types of resonators are analogous in concept and have analogous underlying physics as readout resonators, except that a coupling or "bus" resonator involves only capacitive couplings between two or more qubits whereas a readout resonator involves capacitive coupling between two or more qubits and a feedline.
  • a coupling resonator may be implemented as a microwave transmission line segment that includes capacitive or inductive connections to ground on both sides (e.g.
  • each side of a coupling resonator is coupled, either capacitively or inductively, to a respective (i.e. different) qubit by being in the appropriate location and sufficient proximity to the qubit. Because different regions of a coupling resonator have coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator.
  • coupling resonators may be employed for implementing logic gates.
  • resonators 110 used with superconducting qubits are so-called “readout resonators,” which may be used to read the state(s) of qubits.
  • readout resonators may be used to read the state(s) of qubits.
  • a readout resonator similar to the bus coupling resonator, is a transmission line segment. On one end it may have an open circuit connection to ground as well as any capacitively or inductively coupled connections to other quantum elements or a non-resonant microwave feedline. On the other end, a readout resonator may either have a capacitive connection to ground (for a half-wavelength resonator) or may have a short circuit to the ground (for a quarter-wavelength resonator), which also results in oscillations within the transmission line, with the resonant frequency of the oscillations being close to the frequency of the qubit.
  • a readout resonator is coupled to a qubit by being in the appropriate location and sufficient proximity to the qubit, again, either through capacitive or inductive coupling. Due to a coupling between a readout resonator and a qubit, changes in the state of the qubit result in changes of the resonant frequency of the readout resonator. In turn, changes in the resonant frequency of the readout resonator can be read externally via connections which lead to external electronics e.g. wire or solder bonding pads.
  • the qubit frequency may be controlled in order to bring the frequency either closer to or further away from another resonant item, for example a coupling resonator or a coupled neighbor qubit, to implement multi-qubit interactions, as may be desired in a particular setting.
  • another resonant item for example a coupling resonator or a coupled neighbor qubit
  • both qubits 102 may need to be tuned to be at nearly the same frequency or a detuning equal, or nearly equal, to the anharmonicity.
  • One way in which such two qubits could interact is that, if the frequency of the first qubit 102-1 is tuned very close to the resonant frequency of the coupling resonator, the first qubit can, when in the excited state, relax back down to the ground state by emitting a photon (similar to how an excited atom would relax) that would resonate within the coupling resonator. If the second qubit 102-2 is also at this energy (i.e. if the frequency of the second qubit is also tuned very close to the resonant frequency of the coupling resonator), then it can absorb the photon emitted from the first qubit, via the coupling resonator coupling these two qubits, and be excited from its ground state to an excited state.
  • the two qubits interact, or are entangled, in that a state of one qubit is controlled by the state of another qubit.
  • two qubits could interact via exchange of virtual photons, where the qubits do not have to be tuned to be at the same frequency with one another.
  • two or more qubits could be configured to interact with one another by tuning their frequencies to specific values or ranges.
  • two qubits coupled by a coupling resonator do not interact, i.e. the qubits are independent.
  • magnetic flux by means of controlling the current in the appropriate flux bias line, to one qubit it is possible to cause the frequency of the qubit to change enough so that the photon it could emit no longer has the right frequency to resonate on the coupling resonator or on the neighboring qubit via a virtual photon transfer through the bus. If there is nowhere for such a frequency-detuned photon to go, the qubit will be better isolated from its surroundings and will live longer in its current state.
  • two or more qubits could be configured to reduce interactions with one another by tuning their frequencies to specific values or ranges.
  • each qubit 102 may be read by way of its corresponding readout resonator of the resonators 110. As explained below, the state of qubit 102 induces a shift in the resonant frequency in the associated readout resonator. This shift in resonant frequency can then be read out using its coupling to a feedline. To that end, an individual readout resonator may be provided for each qubit.
  • a readout resonator may be a transmission line segment that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side (for a quarter-wavelength resonator) or has a capacitive connection to ground (for a half wavelength resonator), which results in oscillations within the transmission line (resonance) that depends upon the state of a proximal qubit.
  • a readout resonator may be coupled to its
  • corresponding qubit 102 by being in an appropriate location and sufficient proximity to the qubit, more specifically in an appropriate location and sufficient proximity to a first element (or "island) of the qubit 102 that capacitively couples to the readout resonator, when the qubit is implemented as a transmon. Due to a coupling between the readout resonator and the qubit, changes in the state of the qubit result in changes of the resonant frequency of the readout resonator. In turn, by ensuring that the readout resonator is in sufficient proximity to a corresponding microwave feedline, changes in the resonant frequency of the readout resonator induce changes in the transmission coefficients of the microwave feedline, detected externally.
  • a coupling resonator allows coupling different qubits together, e.g. as described above, in order to realize quantum logic gates.
  • a coupling component could be comprised of a coupling component on a neighboring qubit, a lumped element capacitor, a lumped element resonator, or a coupling transmission line segment.
  • a coupling transmission line segment (e.g., coupling resonator or bus resonator) is similar to a readout resonator in that it is a transmission line segment that includes capacitive connections to various objects (e.g., qubits, ground, etc.) on both sides (i.e.
  • Each side/end of a coupling component is coupled (again, either capacitively or inductively) to a respective qubit by being in appropriate location and sufficient proximity to the qubit, namely in sufficient proximity to a first element (or "island") of the qubit that capacitively couples to the coupling component, when the qubit is implemented as a transmon. Because each side of a given coupling component has coupling with a respective different qubit, the two qubits are coupled together through the coupling component.
  • coupling components may be employed in order to implement multi-qubit interactions.
  • a microwave line may be used to not only readout the state of the qubits as described above, but also to control the state of the qubits.
  • the line operates in a half-duplex mode where, at some times, it is configured to readout the state of the qubits, and, at other times, it is configured to control the state of the qubits.
  • microwave lines may be used to only readout the state of the qubits as described above, while separate drive lines, may be used to control the state of the qubits.
  • microwave lines used for readout may be referred to as readout lines
  • microwave lines used for controlling the state of the qubits may be referred to as drive lines.
  • Drive lines may control the state of their respective qubits 102 by providing to the qubits a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the states of the qubit. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the states of the qubit.
  • Flux bias lines, microwave lines, readout lines, drive lines, coupling components, and readout resonators such as e.g. those described above, together form interconnects for supporting propagation of microwave signals. Further, any other connections for providing direct electrical interconnection between different quantum circuit elements and components, such as e.g.
  • interconnects may also be used to refer to elements providing electrical interconnections between quantum circuit elements and components and non quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit.
  • non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog to digital converters, mixers, multiplexers, amplifiers, etc.
  • various conductive circuit elements of supporting circuitry included in a quantum circuit could have different shapes and layouts.
  • the term "line" as used herein in context of signal lines or transmission lines does not imply straight lines, unless specifically stated so.
  • some resonant or non-resonant transmission lines or parts thereof e.g. conductor strips of resonant or non-resonant transmission lines
  • At least some of the Josephson Junctions 104 included within the qubits 102 shown in FIG.1 may be fabricated according to various embodiments of the improved method described herein.
  • the qubits 102, the non-resonant transmission lines 108, and the resonators 110 of the quantum circuit 100 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 1).
  • the substrate may be any substrate suitable for realizing quantum circuit assemblies described herein.
  • the substrate may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof.
  • the substrate may be non-crystalline.
  • any material that provides sufficient advantages e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g.
  • substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.
  • quantum circuits such as the one shown in FIG. 1 may be used to implement components associated with a quantum integrated circuit (1C).
  • Such components may include those that are mounted on or embedded in a quantum 1C, or those connected to a quantum 1C.
  • the quantum 1C may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the 1C.
  • the 1C may be employed as part of a chipset for executing one or more related functions in a quantum system. Exemplary Josephson Junctions fabricated using ART method
  • FIGS. 2A-2B provides various views of a quantum circuit assembly 200 with a semiconductor-based Josephson Junction, in accordance with different exemplary embodiments of the present disclosure.
  • each of FIGS. 2A-2B illustrates a top down view (the view shown in the lower left portion of FIG. 2) of the y-x plane of the coordinate system illustrated in some of the present FIGS., a first cross-sectional view (the view shown in the upper left portion of FIG. 2) along the y-z plane, and a second cross-sectional view (the view shown in the upper right portion of FIG. 2) along the x-z plane.
  • the top down view shown in FIG. 2 may be the view looking down from a plane indicted in FIG. 2 as a plane AA
  • the first cross-sectional view may be a cross-section along a plane indicted in FIG.
  • FIG. 2 A legend provided within a dashed box at the bottom of FIG. 2 illustrates patterns used to indicate some of the elements shown in FIG. 2, so that FIG. 2 is not cluttered by too many reference numerals.
  • the quantum circuit assembly 200A may include a substrate 202, a dielectric material 204 provided over the substrate 202, one or more semiconductor materials 206 provided within a trench opening formed in the dielectric material 204 over the substrate 202, and two electrodes 208 for a Josephson Junction.
  • the substrate 202 may include a substrate 202, a dielectric material 204 provided over the substrate 202, one or more semiconductor materials 206 provided within a trench opening formed in the dielectric material 204 over the substrate 202, and two electrodes 208 for a Josephson Junction.
  • Josephson Junction of the quantum circuit assembly 200A may be viewed as having a tunnel barrier formed by the one or more semiconductor materials 206, the tunnel barrier extending between the two electrodes 208.
  • the substrate 202 may be any substrate which may serve as a foundation for housing quantum circuits, such as e.g. any of the substrates described above.
  • the dielectric material 204 may be any suitable dielectric material used in semiconductor processing, including but not limited to elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • low-k materials that may be used as the dielectric material 204 may include, but are not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, spin-on organic polymeric dielectrics such as e.g. polyimide, polynorbornenes, benzocyclobutene, and polytetrafluoroethylene (PTFE), or spin-on silicon-based polymeric dielectric such as e.g.
  • the dielectric material 204 may be any material that may be used as interlayer dielectric (ILD), or any material that may be used as a shallow trench insulator (STI) in semiconductor manufacturing.
  • ILD interlayer dielectric
  • STI shallow trench insulator
  • the one or more semiconductor materials 206 may be any materials different from the semiconductor material of the substrate 202, namely, having lattice constant(s) different from that of the semiconductor material of the substrate 202.
  • the substrate 202 is a silicon substrate
  • the one or more semiconductor materials 206 may include lll-V compound semiconductors, group IV compound semiconductors, or elemental semiconductors different from silicon).
  • the term "compound semiconductor” is used to describe a semiconductor compound composed of elements of at least two different species.
  • the term “lll-V compound semiconductor” (or, simply, “lll-V semiconductor”) is used to describe semiconductor compounds having one or more elements which belong to group III of the periodic table of elements (e.g. arsenic, nitrogen, etc.) in combination with one or more elements which belong to group V of the periodic table (e.g. gallium, indium, etc.).
  • lll-V semiconductors include indium arsenide (InAs), gallium arsenide (GaAs), as well as ternary alloys (i.e. lll-V semiconductors combining three elements) such as e.g.
  • Group IV compound semiconductor is used to describe semiconductor compounds having two or more different species/elements which belong to group IV of the periodic table of elements, such as e.g. silicon- germanium (SiGe).
  • the term “elemental semiconductor” is used to describe a semiconductor element, such as e.g. Si or Ge, which is not intentionally combined with any other elements (of course a low level of other elements as unintentional or unavoidable impurities may be present).
  • FIG. 2A illustrates an exemplary embodiment where the one or more semiconductor materials 206 include three different semiconductor materials, labeled in FIG. 2A as a first semiconductor material 206-1, a second semiconductor material 206-2, and a third semiconductor material 206-3.
  • first semiconductor material 206-1 labeled in FIG. 2A
  • second semiconductor material 206-2 labeled in FIG. 2A
  • third semiconductor material 206-3 labeled in FIG. 2A.
  • descriptions provided herein are equally applicable to any other number of layers of different semiconductor materials 206, such as e.g. only one semiconductor material 206, two semiconductor materials 206, or more than four different semiconductor materials 206.
  • Providing more than one layer of different semiconductor materials 206 in a trench within the dielectric 204 may have the benefit of being able to fill the trench by, first, growing the first semiconductor material 206-1 having less of a lattice mismatch with the semiconductor material of the substrate 202, and then grow the second semiconductor material 206-2 having a greater lattice mismatch with the semiconductor material of the substrate 202 compared to the first semiconductor material 206-1, which may allow reducing the amount and the extent of defects in the trench. Further semiconductor layers provided in the trench may have successively greater lattice mismatch with the semiconductor material of the substrate 202.
  • the third semiconductor material 206-3 may have the greatest lattice mismatch with the semiconductor material of the substrate 202, compared to the first and second semiconductors 206-1 and 206-2.
  • the first semiconductor material 206-1 may be or include GaAs
  • the second semiconductor material 206-2 may be or include InGaAs
  • the third semiconductor material 206-3 may be or include InAs.
  • the one or more semiconductors 206 fill a trench 210 extending between the first and second electrodes 208 (labeled in FIG. 2A as a first electrode 208-1 and a second electrode 208-2).
  • the first and second electrodes 208 are in contact with different regions of the one or more semiconductors 206 so that, during operation of the Josephson Junction, the tunneling current can flow between the first and second electrodes 208 via the tunnel barrier of the one or more semiconductors 206.
  • the one or more semiconductors 206 may be said to form a "nanowire," where the term nanowire does not necessarily imply a circular transverse cross-sectional profile.
  • the nanowire of the one or more semiconductors 206 in various embodiments of the present disclosure may have a substantially quadrilateral (e.g. substantially rectangular or trapezoid) cross-sectional profile, as shown in the views of the x-z plane of the various embodiments of the present disclosure, e.g. as shown in the cross-section of the x-z plane shown in FIG. 2A.
  • the thickness (i.e. a dimension measured along the z-axis of the coordinate system shown in FIG. 2A) of the first semiconductor 206-1 may be between about 2 and 200 nanometers (nm), including all values and ranges therein, e.g. between about 10 and 100 nm, or between about 20 and 50 nm, e.g. about 25 nm.
  • the thickness (again, a dimension measured along the z-axis of the coordinate system shown in FIG. 2A) of the second semiconductor 206-2 may be between about the same as the thickness of the first semiconductor 206-1.
  • the thickness of the third semiconductor 206-2 may be between about 2 and 200 nm, including all values and ranges therein, e.g. between about 10 and 150 nm, or between about 25 and 50 nm.
  • the depth of the trench 210 may be seen as a sum of thicknesses of the one or more semiconductors 206, e.g. the sum of the thicknesses described above.
  • the width (i.e. a dimension measured along the x-axis of the coordinate system shown in FIG. 2A) of the trench 210 may be between about 20 and 300 nm, including all values and ranges therein, e.g. between about 80 and 120 nm, e.g. about 100 nm, while the length (i.e. a dimension measured along the y-axis of the coordinate system shown in FIG. 2A) of the trench 210 may be between about 50 and 10,000 nm, including all values and ranges therein, e.g. between about 1,000 and 3,000 nm (i.e. 1 to 3 micron).
  • the trench 210 may be a high-AR trench, e.g. having an AR greater than 2, preferably having an AR between about 3 and 10.
  • the nature of the ART growth of the one or more semiconductor materials 206 is such that defects, e.g. threading dislocations or other defects due to epitaxially growing a semiconductor material having a crystalline lattice with a particular lattice constant on a
  • the semiconductor material having a crystalline lattice with a different lattice constant are concentrated mainly at the bottom of the trench, i.e. at the region of the trench closest to the substrate 202. This allows the semiconductor material 206 closer to the surface of the device, i.e. in the region of the trench farthest away from the substrate 202, to have a limited number of defects so that the material has sufficiently good quality to serve as a tunnel barrier of a Josephson Junction in a quantum circuit.
  • an amount of defects measured e.g.
  • the amount of defects in the first region may be greater than about 10 9 defects per square centimeter (cm 2 ), including all values and ranges therein, e.g.
  • the first and second regions may, but do not have to correspond to the first, second, and so forth, semiconductor material layers 206.
  • the first region may correspond to the first semiconductor material 206-1 and the second region may correspond to the second semiconductor material 206-2, but, in general, the correspondence may not be there but the amount of defects still reduces from the bottom to the top of the trench.
  • the amount of defects may still reduce as described above, from the first to the second region.
  • the electrodes 208 of the Josephson Junction may be formed of any suitable electrically conductive, preferably superconductive materials, e.g. any of the exemplary superconductors described above, such as e.g. Al, Nb, NbN, NbTiN, TiN, MoRe, etc., or any alloy of two or more superconducting/conducting materials. While the quantum circuit assembly 200A illustrates the electrodes 208 to be substantially aligned with edges of the trench 210, such an alignment is not necessary. In various other embodiments, the electrodes 208 may be provided at any locations so that the tunneling effect through the one or more semiconductors 206 may take place between the electrodes 208, in order to realize the Josephson effect in the quantum circuit.
  • Josephson Junctions as described herein e.g. one or more of the Josephson Junctions as shown in the quantum circuit assemblies 200, could be included in a superconducting qubit, e.g. included in a charge qubit, in particular included in a transmon, or included in a flux qubit.
  • the qubit substrate 202 may further include a second Josephson Junction similar to the Josephson Junction shown in FIG. 2A. Two such Josephson Junctions may be connected by a superconducting loop to form a SQUID, as described above.
  • the quantum circuit assembly 200A may be included in a quantum 1C package which may include a qubit die with a substrate, e.g. the substrate 202, and at least one qubit device that includes one or more Josephson Junctions as described with reference to FIG. 2A.
  • a quantum 1C package may further include a further 1C element such as e.g. an interposer, a circuit board, a flexible board, or a package substrate, where the qubit die is coupled to the further 1C element by one or more first-level interconnects.
  • the qubit die may include a plurality of qubit devices, e.g. a plurality of superconducting qubits as described above with reference to FIG. 1.
  • FIG. 2B showing a quantum circuit assembly 200B
  • the exemplary embodiment shown in FIG. 2B is different from that shown in FIG. 2A in the extent of the substrate 202 relative to the trench 210 in which the one or more semiconductors 206 are grown.
  • the one or more semiconductors 206 are grown on the semiconductor material of the substrate 202, but, while in the embodiment of FIG. 2A the trench 210 includes a fin formed of the semiconductor material of the substrate 202 at the bottom, in the embodiment of FIG. 2B the trench 210 is formed in a layer of the dielectric material 204 above the substrate 202 (i.e. in the embodiment of FIG. 2B there is substantially no semiconductor material of the substrate 202 extending into the trench).
  • Such a difference may arise due to differences in forming a trench in a dielectric material, as described in greater detail below with references to FIGS. 5A-5D and FIGS. 6A- 6C.
  • Other discussions provided with respect to FIG. 2A are applicable to FIG. 2B and, therefore, in the interests of brevity, are not repeated.
  • FIG. 3 provides a flow chart of an ART method 300 for fabricating semiconductor-based Josephson Junctions in quantum circuits, according to some embodiments of the present disclosure, such as e.g. for fabricating Josephson Junctions as shown in FIG. 2A or FIG. 2B.
  • one or more operations may be performed in parallel to manufacture multiple quantum circuit assemblies as described herein, or multiple Josephson Junctions of such assemblies, substantially simultaneously.
  • the operations may be performed in a different order to reflect the architecture of a particular quantum circuit component in which one or more quantum circuit assemblies with Josephson Junctions fabricated according to the method 300 are to be included.
  • the exemplary manufacturing method 300 may include other operations not specifically shown in FIG. 3, such as e.g. various cleaning or planarization operations as known in the art.
  • the substrate may be cleaned prior to or/and after any of the processes of the method 300 described herein, e.g. to remove oxides, surface-bound organic and metallic contaminants, as well as subsurface contamination.
  • cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using hydrofluoric acid (HF)).
  • a chemical solutions such as peroxide
  • UV radiation ultraviolet
  • oxidizing the surface e.g., using thermal oxidation
  • HF hydrofluoric acid
  • planarization may be carried out using either wet or dry planarization processes, e.g. planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.
  • CMP chemical mechanical planarization
  • FIGS. 4, 5, and 6 are different views illustrating various example stages in the manufacture of a quantum circuit assembly using the method of FIG. 3 in accordance with some embodiments of the present disclosure.
  • FIGS. 4, 5, and 6 illustrates a top down view and two cross-sectional views similar to FIGS. 2A-2B, except that the scale of FIGS. 5 and 6 is somewhat smaller than that of FIGS. 2 and 4, in order to have sufficient space on the page of the drawings to show larger portions of the substrate 202.
  • the method 300 may begin with providing, within a layer of a dielectric (cover) material over a substrate, an opening, e.g. a trench opening, in which semiconductor materials of a tunnel barrier of a future Josephson Junction will be grown (process 302 shown in FIG. 3, a result of which according to some embodiments is illustrated with a quantum circuit assembly 302 shown in FIG.
  • the assembly 402 illustrates the substrate 202, the dielectric material 204, and the trench 210 as described above, except that the trench 210 is not yet filled with semiconductor material(s) suitable for forming the tunnel barrier of a semiconductor-based Josephson Junction.
  • the trench 210 may be seen as having a portion of the substrate 202 within the trench, at its' bottom (if the trench is viewed as what is surrounded by the dielectric material 204).
  • the method 300 is equally applicable to embodiments where the trench 210 extends through the dielectric material 204 all the way to the substrate 202 so that the semiconductor material of the substrate 202 forms the bottom of the trench but does not extend into the trench, as e.g. shown in FIG. 2B.
  • Such differences may arise due to different manners in forming the trench in which semiconductor materials are to be grown using ART, as shown with the two examples of FIG. 5 and FIG. 6, respectively, described below.
  • FIG. 5 illustrates that a trench may be formed by, starting with a substrate as shown in FIG. 5A with an assembly 502, forming a fin 503 in the upper portion of the substrate 202, as shown in FIG. 5B with an assembly 504, then enclosing the sidewalls of the fin 503 with the dielectric material 204, as shown in FIG. 5C with an assembly 506, and, finally, recessing at least a portion of the fin 503 to form the trench 210, as shown in FIG. 5D with an assembly 508.
  • the fin 503 may have dimensions such that, when at least a portion of the fin 503 is recessed within the dielectric material 204, a trench of suitable dimensions for growing the one or more semiconductors 204 using the ART process is formed, such as e.g. the trench of dimensions as described above.
  • FIG. 2A may be seen as illustrating the portion of the assembly 508 above the dotted line (i.e. the base portion of the substrate 202 from which the fin 503 originally extended is not specifically shown in FIG. 2A). While FIGS. 2A and 5D illustrate that a portion of the fin 503 remain to be enclosed in between the dielectric material 204, in other embodiments, the fin 503 in the assembly 508 may be recessed further, e.g. to the dotted line shown in FIG. 5D, so that there is no semiconductor material of the substrate 202 that used to form the fin 503 remains enclosed by the dielectric material 204.
  • any suitable patterning techniques may be used to form the fin 503 while forming a trench in a manner shown in FIG. 5.
  • Examples of such techniques include photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with a dry etch, such as e.g. radio frequency (RF) reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE, to pattern the substrate 202 to form the fin 503 extending away from a base 505, the fin 503 being of a specified geometry for a given implementation.
  • RF radio frequency
  • RIE reactive ion etch
  • ICP inductively coupled plasma
  • Any suitable deposition technique may then be used to enclose the sidewalls of the fin 503 with the dielectric material 204.
  • deposition techniques for depositing layers of dielectric materials include atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), spin-coating, or dip-coating.
  • a planarization process may then be applied to remove the excess dielectric material 204 from the top of the assembly 506 so that substantially only the sidewalls of the fin 503 are enclosed with the dielectric material 204.
  • the fin 503 may be recessed using a suitable technique for removing the material(s) of the substrate 202, such as e.g. a suitable etching technique.
  • the dielectric material 204 may include any material that has sufficient etch selectivity with respect to the material(s) of the substrate 202, in order for an etch process used in a later stage to remove some or all of the fin 503 to not etch significantly into the dielectric material 204.
  • two materials are said to have "sufficient etch selectivity" when etchants used to etch one material do not substantially etch the other, enabling selective etching of one material but not the other.
  • some other considerations in selecting a suitable material for the dielectric material 204 may include e.g. possibilities of smooth film formation, low shrinkage and outgassing, and good dielectric properties (such as e.g. low electrical leakage, suitable value of a dielectric constant, and thermal stability).
  • FIG. 6 illustrates an alternative manner for forming a trench where, starting with a substrate as shown in FIG. 6A with an assembly 602, a layer of the dielectric material 204 is provided over the substrate, as shown in FIG. 6B with an assembly 604, and then a trench opening 210 is formed in the dielectric material 204, the opening extending all the way to the substrate 202, as shown in FIG. 6C with an assembly 606.
  • Any suitable deposition techniques may be used to deposit the layer of the dielectric material 204 as shown in the assembly 604 and to form an opening in the dielectric material 204 as shown in the assembly 606, e.g. any of the deposition and patterning techniques described above with reference to FIG. 5.
  • the method 300 may proceed with providing one or more semiconductor materials within the trench (process 304 shown in FIG. 3, a result of which according to some embodiments is illustrated with a quantum circuit assembly 304 shown in FIG. 4B).
  • the assembly 404 illustrates the multiple layers of the
  • semiconductor materials 206 grown within the trench 210 as described above. Any suitable techniques may be used to successively grow the one or more semiconductor materials 206 within the trench 210 in the process 304, such as e.g. epitaxial growth as known in the art.
  • the ART technique typically will allow threading dislocations to propagate and terminate on the oxide sidewall of the trench. Therefore the top surface of the device will have a much lower defect density than lower portions of the trench.
  • the method 300 may proceed with providing the electrodes for the Josephson Junction (process 306 shown in FIG. 3, a result of which according to some embodiments is illustrated with a quantum circuit assembly 306 shown in FIG. 4C).
  • the assembly 406 illustrates the first and second electrodes 208-1 and 208-2 provided over the semiconductor materials 206 grown within the trench 210, as described above.
  • any suitable deposition techniques may be used to provide the electrodes 208 in the process 306, such as e.g. PVD techniques such as e.g. evaporative deposition, magnetron sputtering, or e-beam deposition), ALD, CVD, or electroplating.
  • PVD techniques such as e.g. evaporative deposition, magnetron sputtering, or e-beam deposition
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • electroplating electroplating
  • the dielectric material 204 may be removed.
  • the assembly 408 illustrates that, in some embodiments, the dielectric material 204 may be recessed in the upper areas 410 of the Josephson Junction.
  • Such embodiments of removing portions of dielectric material(s) in the vicinity of the Josephson Junction(s) have the potential of advantageously reducing the amount of spurious TLS's surrounding the Josephson Junction(s), which may improve coherence time of qubits with such Josephson Junction(s).
  • removal of the dielectric material 204 in the process 308 may be carried out by e.g. etching the dielectric material 204 using an appropriate etchant, provided that the material of the dielectric material 204 has sufficient etch selectivity with respect to the semiconductor materials 206 within the trench 210 and with respect to the substrate 202.
  • ART method can be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to conventional approaches for fabricating semiconductor-based Josephson Junctions, such as e.g. the method described above, which may include fabrications steps that are not suitable for implementing with larger wafer sizes used by device manufacturers.
  • the ART method described herein advantageously enables atomic control of the tunnel junction barrier due to formation of such a barrier using epitaxial growth in an opening of specified location and dimensions.
  • Quantum circuit assemblies/structures with Josephson Junctions as described above may be included in any kind of qubit devices or quantum processing devices/structures. Some examples of such devices/structures are illustrated in FIGS. 7A-7B, 7, and 8.
  • FIGS. 7A-7B are top views of a wafer 1100 and dies 1102 that may be formed from the wafer 1100, according to some embodiments of the present disclosure.
  • the dies 1102 may include any of the quantum circuits disclosed herein, e.g., the quantum circuit 100, and may include any of the quantum circuit assemblies described herein, such as e.g. the quantum circuit assemblies 200A or 200B, or any further embodiments of such circuits and assemblies as described herein, and may include one or more Josephson Junctions fabricated using the ART method described herein.
  • the wafer 1100 may include semiconductor material and may include one or more dies 1102 having conventional and quantum circuit device elements formed on a surface of the wafer 1100.
  • Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device. After the fabrication of the semiconductor product is complete, the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product.
  • a die 1102 may include one or more quantum circuits 100, including any Josephson Junctions fabricated using the ART method described herein, as well as any other 1C components.
  • the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element.
  • SRAM static random access memory
  • logic device e.g., AND, OR, NAND, or NOR gate
  • a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 2002 of FIG. 9) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • FIG. 8 is a cross-sectional side view of a device assembly 1200 that may include any of the embodiments of the quantum circuit assemblies disclosed herein.
  • the device assembly 1200 includes a number of components disposed on a circuit board 1202.
  • the device assembly 1200 may include components disposed on a first face 1240 of the circuit board 1202 and an opposing second face 1242 of the circuit board 1202; generally, components may be disposed on one or both faces 1240 and 1242.
  • the circuit board 1202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1202. Signal transfer between components or layer may happen with both low resistance DC connections or by either in-plane or out-of-plane capacitive connections.
  • the circuit board 1202 may be a package substrate or flexible board.
  • the 1C device assembly 1200 illustrated in FIG. 8 may include a package-on-interposer structure 1236 coupled to the first face 1240 of the circuit board 1202 by coupling components 1216.
  • the coupling components 1216 may electrically and mechanically couple the package-on- interposer structure 1236 to the circuit board 1202, and may include solder balls (as shown in FIG.
  • the coupling components 1216 may include other forms of electrical connections that may have no mechanical contact, such as parallel plate capacitors or inductors, which can allow high-frequency connection between components without mechanical or DC connections.
  • the package-on-interposer structure 1236 may include a package 1220 coupled to an interposer 1204 by coupling components 1218.
  • the coupling components 1218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1216. Although a single package 1220 is shown in FIG. 8, multiple packages may be coupled to the interposer 1204; indeed, additional interposers may be coupled to the interposer 1204.
  • the interposer 1204 may provide an intervening substrate used to bridge the circuit board 1202 and the package 1220.
  • the package 1220 may be a quantum circuit device package as described herein, e.g.
  • the interposer 1204 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 1204 may couple the package 1220 (e.g., a die) to a ball grid array (BGA) of the coupling components 1216 for coupling to the circuit board 1202.
  • BGA ball grid array
  • the package 1220 and the circuit board 1202 are attached to opposing sides of the interposer 1204; in other embodiments, the package 1220 and the circuit board 1202 may be attached to a same side of the interposer 1204.
  • three or more components may be interconnected by way of the interposer 1204.
  • the interposer 1204 may be formed of a crystalline material, such as silicon, germanium, or other semiconductors, an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer 1204 may include metal interconnects 1210 and vias 1208, including but not limited to through-silicon vias (TSVs) 1206.
  • TSVs through-silicon vias
  • the interposer 1204 may further include embedded devices 1214, including both passive and active devices.
  • Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and
  • MEMS microelectromechanical systems
  • the package-on-interposer structure 1236 may take the form of any of the package-on-interposer structures known in the art.
  • the device assembly 1200 may include a package 1224 coupled to the first face 1240 of the circuit board 1202 by coupling components 1222.
  • the coupling components 1222 may take the form of any of the embodiments discussed above with reference to the coupling components 1216
  • the package 1224 may take the form of any of the embodiments discussed above with reference to the package 1220.
  • the package 1224 may be a package including one or more quantum circuits with Josephson Junctions fabricated using the ART method as described herein, e.g. the quantum circuit 100, and may include any of the quantum circuit assemblies described herein, such as e.g. the quantum circuit assemblies 200A or 200B, or any further embodiments of such circuits and assemblies, or may be a conventional 1C package, for example.
  • the package 1224 may take the form of any of the embodiments of the quantum circuit 100 with any of the quantum circuit assemblies described herein.
  • the device assembly 1200 illustrated in FIG. 8 includes a package-on-package structure 1234 coupled to the second face 1242 of the circuit board 1202 by coupling components 1228.
  • the package-on-package structure 1234 may include a package 1226 and a package 1232 coupled together by coupling components 1230 such that the package 1226 is disposed between the circuit board 1202 and the package 1232.
  • the coupling components 1228 and 1230 may take the form of any of the embodiments of the coupling components 1216 discussed above, and the packages 1226 and 1232 may take the form of any of the embodiments of the package 1220 discussed above.
  • Each of the packages 1226 and 1232 may be a qubit device package as described herein or may be a conventional 1C package, for example.
  • one or both of the packages 1226 and 1232 may take the form of any of the embodiments of the quantum circuit 100 with any of the quantum circuit assemblies described herein, or a combination thereof.
  • FIG. 9 is a block diagram of an exemplary quantum computing device 2000 that may include any of the quantum circuits with any of the quantum circuit assemblies disclosed herein.
  • a number of components are illustrated in FIG. 9 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application.
  • some or all of the components included in the quantum computing device 2000 may be attached to one or more PCBs (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with any of the quantum circuit assemblies described herein.
  • various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die.
  • SoC system-on-a-chip
  • the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 9, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components.
  • the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled.
  • the quantum computing device 2000 may not include an audio input device 2018 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2018 or audio output device 2008 may be coupled.
  • the quantum computing device 2000 may include a microwave input device or a microwave output device (not specifically shown in FIG.
  • the quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices).
  • processing device e.g., one or more processing devices.
  • the term "processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices).
  • the quantum processing device 2026 may include any of the quantum circuits disclosed herein, e.g., the quantum circuit 100, and may include any of the quantum circuit assemblies described herein, such as e.g. the quantum circuit assemblies 200A or 200B, or any further embodiments of such circuits and assemblies as described herein, and may include one or more Josephson Junctions fabricated using the ART method described herein, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuits as described herein, and monitoring the result of those operations. For example, as discussed above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of different qubits may be read.
  • the quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms.
  • the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc.
  • the quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.
  • the processing device 2002 may include a non-quantum processing device 2028.
  • the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026.
  • the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc.
  • the non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026.
  • the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components.
  • the non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
  • DSPs digital signal processors
  • ASICs application-specific ICs
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute cryptographic algorithms within hardware
  • server processors or any other suitable processing devices.
  • the quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid-state memory
  • solid-state memory solid-state memory
  • hard drive solid-state memory
  • the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004.
  • the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
  • eDRAM embedded dynamic random access memory
  • STT-MRAM spin transfer torque magnetic random access memory
  • the quantum computing device 2000 may include a cooling apparatus 2024.
  • the cooling apparatus 2024 may maintain the quantum processing device 2026, in particular the quantum circuits with Josephson Junctions as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2026.
  • This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less.
  • the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature.
  • the cooling apparatus 2024 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.
  • the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips).
  • the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
  • IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for
  • Microwave Access which is a certification mark for products that pass conformity
  • the communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • HSPA High Speed Packet Access
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • the communication chip 2012 may operate in accordance with other wireless protocols in other embodiments.
  • the quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless
  • the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet).
  • the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless
  • a second communication chip 2012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
  • GPS global positioning system
  • EDGE EDGE
  • GPRS global positioning system
  • CDMA Code Division Multiple Access
  • WiMAX Long Term Evolution
  • LTE Long Term Evolution
  • EV-DO EV-DO
  • a first communication chip 2012 may be dedicated to wireless communications
  • a second communication chip 2012 may be dedicated to wired communications.
  • the quantum computing device 2000 may include battery/power circuitry 2014.
  • the battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).
  • the quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above).
  • the display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
  • the quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above).
  • the audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
  • the quantum computing device 2000 may include an audio input device 2018 (or corresponding interface circuitry, as discussed above).
  • the audio input device 2018 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
  • MIDI musical instrument digital interface
  • the quantum computing device 2000 may include a GPS device 2016 (or corresponding interface circuitry, as discussed above).
  • the GPS device 2016 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.
  • the quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above).
  • Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
  • the quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above).
  • Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • RFID radio frequency identification
  • the quantum computing device 2000 may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
  • a hand-held or mobile computing device e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.
  • PDA personal digital assistant
  • Example 1 provides a quantum circuit assembly that includes a substrate and at least one qubit device including at least one Josephson Junction.
  • Each such Josephson Junction may include a first electrode and a second electrode provided over or at least partially in the substrate, and a tunnel barrier including one or more semiconductor materials provided in a trench in a layer of a cover material provided over the substrate, the trench extending between the first electrode and the second electrode.
  • Example 2 provides the quantum circuit assembly according to Example 1, where the tunnel barrier is formed as a nanowire of the one or more semiconductor materials, the nanowire extending between the first electrode and the second electrode.
  • Example 3 provides the quantum circuit assembly according to Example 2, where a transverse cross-sectional profile of the nanowire is substantially quadrilateral (e.g. substantially rectangular or trapezoid).
  • Example 4 provides the quantum circuit assembly according to any one of the preceding Examples, where the one or more semiconductor materials include at least a first semiconductor material and a second semiconductor material, the first semiconductor material is between the second semiconductor material and the substrate (i.e. the first semiconductor material is closer to the substrate than the second semiconductor material), and a lattice mismatch (e.g. measured as the difference in lattice constants of two crystalline lattices) between the crystalline lattice of the second semiconductor material and the crystalline lattice of the substrate is greater than a lattice mismatch between the crystalline lattice of the first semiconductor material and the crystalline lattice of the substrate.
  • the one or more semiconductor materials include at least a first semiconductor material and a second semiconductor material
  • the first semiconductor material is between the second semiconductor material and the substrate (i.e. the first semiconductor material is closer to the substrate than the second semiconductor material)
  • a lattice mismatch e.g. measured as the difference in lattice constants of two crystalline
  • Example 5 provides the quantum circuit assembly according to Example 4, where a thickness (i.e. a dimension measured along the z-axis of the coordinate system shown in the FIGS.) of the first semiconductor material is between about 2 and 200 nm, including all values and ranges therein, e.g. between about 10 and 100 nm, or between about 20 and 50 nm, e.g. about 25 nm.
  • a thickness i.e. a dimension measured along the z-axis of the coordinate system shown in the FIGS.
  • Example 6 provides the quantum circuit assembly according to Examples 4 or 5, where a thickness (again, a dimension measured along the z-axis of the coordinate system shown in the FIGS.) of the second semiconductor material is between about 2 and 200 nm, including all values and ranges therein, e.g. between about 10 and 100 nm, or between about 20 and 50 nm, e.g. about 25 nm.
  • Example 7 provides the quantum circuit assembly according to any one of the preceding Examples, where an amount of defects (measured e.g. as areal defect density quantifying the number of defects per unit area) in a crystalline structure of the one or more semiconductor materials in a first region of the trench is substantially greater, e.g. at least 10 3 times greater or at least 10 6 greater, than an amount of defects in a crystalline structure of the one or more semiconductor materials in a second region of the trench, where the first region is between the second region and the substrate (i.e. the first region of the trench is the region closer to the substrate than the second region).
  • an amount of defects measured e.g. as areal defect density quantifying the number of defects per unit area
  • Example 8 provides the quantum circuit assembly according to Example 7, where the amount of defects in the first region is greater than about 10 9 cm 2 , including all values and ranges therein, e.g. greater than about 10 11 cm 2 or greater than about 10 12 cm 2 .
  • Example 9 provides the quantum circuit assembly according to Examples 7 or 8, where the amount of defects in the second region is less than about 10 8 0cm 2 , including all values and ranges therein, e.g. less than about 10 6 cm 2 or less than about 10 3 cm 2 .
  • Example 10 provides the quantum circuit assembly according to any one of the preceding Examples, where the one or more semiconductor materials include one or more lll-V semiconductor materials, such as e.g. semiconductor materials including indium and arsenic (e.g. InAs),
  • semiconductor materials including indium, gallium, and arsenic (e.g. InGaAs), or/and semiconductor materials including gallium and arsenic (e.g. GaAs).
  • Example 11 provides the quantum circuit assembly according to any one of the preceding Examples, where the one or more semiconductor materials include one or more group-IV semiconductor materials, such as e.g. semiconductor materials including germanium (e.g. Ge), or/and semiconductor materials including silicon and germanium (e.g. SiGe), where atomic percentage of germanium may vary from just below 100% to just above 0%.
  • group-IV semiconductor materials such as e.g. semiconductor materials including germanium (e.g. Ge), or/and semiconductor materials including silicon and germanium (e.g. SiGe), where atomic percentage of germanium may vary from just below 100% to just above 0%.
  • Example 12 provides the quantum circuit assembly according to any one of the preceding Examples, where the at least one Josephson Junction includes two Josephson Junctions.
  • the two Josephson Junctions may form a SQUID.
  • Example 13 provides a quantum 1C package that includes a qubit die including a substrate and at least one qubit device and a further 1C element, where the qubit die is coupled to the further 1C element by one or more first-level interconnects.
  • the at least one qubit device may include at least one Josephson Junction including a first electrode and a second electrode provided over or at least partially in the substrate, and a semiconductor nanowire between the first electrode and the second electrode having a substantially quadrilateral (e.g. substantially rectangular or trapezoid) transverse cross-sectional profile.
  • Example 14 provides the quantum 1C package according to Example 13, where the further 1C element is one of an interposer, a circuit board, a flexible board, or a package substrate.
  • Example 15 provides the quantum 1C package according to Examples 13 or 14, where the at least one qubit device is a plurality of superconducting qubit devices, and where at least of a first and a second of the plurality of superconducting qubit devices are coupled by a coupling resonator.
  • the qubit die of the quantum 1C package according to any one of Examples 13-15 may be a qubit die of a quantum circuit assembly, such as e.g. Example provides the quantum circuit assembly according to any one of the preceding Examples (e.g. Example provides the quantum circuit assembly according to any one of Examples 1-12).
  • Example 16 provides a method of fabricating a quantum circuit assembly.
  • the method may include providing a first and a second qubit devices, where each qubit device includes at least one Josephson Junction, and where an individual Josephson Junction is provided by forming a trench in a dielectric material provided over a crystalline substrate, and depositing one or more semiconductor materials within the trench.
  • the method may further include providing a first and a second electrodes in contact with the one or more semiconductor materials at opposite ends of the trench, and providing at least one resonator coupled to each of the first and the second qubit devices.
  • Example 17 provides the method according to Example 16, where the trench has an aspect ratio (i.e. a ratio between the depth of the trench and the width of the trench) greater than about 2, including all values and ranges therein, e.g. greater than about 3, e.g. between about 3 and 10.
  • aspect ratio i.e. a ratio between the depth of the trench and the width of the trench
  • Example 18 provides the method according to Examples 16 or 17, where a portion of the substrate forms a bottom of the trench (i.e. the trench in the dielectric material extends to the semiconductor material of the substrate).
  • Example 19 provides the method according to any one of Examples 16-18, where depositing the one or more semiconductor materials within the trench includes epitaxially growing the one or more semiconductor materials.
  • Example provides the method according to any one of Examples 16-19, where forming the trench includes patterning the substrate to form a fin extending away from a base, encompassing at least sidewalls of (enclosing, or covering on the sides) the fin with the dielectric material, and recessing a portion of the fin to form the trench.
  • Example 21 provides a quantum computing device that includes a quantum processing device that includes a quantum circuit assembly including at least one qubit device with at least one Josephson Junction provided over or at least partially in a substrate, and a memory device configured to store data generated during operation of the quantum processing device.
  • the at least one Josephson Junction may include a first electrode and a second electrode provided over or at least partially in the substrate, and a trench in a layer of a cover material provided over the substrate, the trench extending between the first electrode and the second electrode and filled with one or more semiconductor materials different from a semiconductor material of the substrate.
  • Example 22 provides the quantum computing device according to Example 21, where the one or more semiconductor materials include one or more lll-V semiconductor materials or/and one or more semiconductor materials which include germanium.
  • Example 23 provides the quantum computing device according to Examples 21 or 22, where an amount of defects (measured e.g. as areal defect density quantifying the number of defects per unit area) in a crystalline structure of the one or more semiconductor materials in a first region of the trench is substantially greater than an amount of defects in a crystalline structure of the one or more semiconductor materials in a second region of the trench, where the first region is between the second region and the substrate (i.e. the first region of the trench is the region closer to the substrate than the second region), e.g. at least 10 3 times greater or at least 10 6 greater.
  • Example 24 provides the quantum computing device according to any one of Examples 21- 23, further including a cooling apparatus configured to maintain the temperature of the quantum processing device below 5 degrees Kelvin.
  • Example 25 provides the quantum computing device according to any of Examples 21-24, where the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
  • Example 26 provides the quantum computing device according to any of Examples 21-25, further including a non-quantum processing device coupled to the quantum processing device.
  • the quantum circuit assembly of the quantum processing device according to any one of Examples 21-26 may be Example provides the quantum circuit assembly according to any one of the preceding Examples (e.g. Example provides the quantum circuit assembly according to any one of Examples 1-12).
  • Example 27 provides a quantum circuit assembly that includes a substrate, and at least one qubit device including at least one Josephson Junction.
  • the at least one Josephson Junction may include a first electrode and a second electrode provided over or at least partially in the substrate, a first semiconductor material between the first electrode and the second electrode, and a second semiconductor material, where the first semiconductor material is between the second
  • the first semiconductor material is closer to the substrate than the second semiconductor material
  • a lattice mismatch between the crystalline lattice of the second semiconductor material and the crystalline lattice of the substrate is greater than a lattice mismatch between the crystalline lattice of the first semiconductor material and the crystalline lattice of the substrate.
  • Example 28 provides the quantum circuit assembly according to Example 27, where a thickness (i.e. a dimension measured along the z-axis of the coordinate system shown in the FIGS.) of the first semiconductor material is between c
  • Example 29 provides the quantum circuit assembly according to Examples 27 or 28, where a thickness (i.e. a dimension measured along the z-axis of the coordinate system shown in the FIGS.) of the second semiconductor material is between 2 and 200 nm.
  • Example 30 provides the quantum circuit assembly according to any one of Examples 27-29, where an amount of defects (measured e.g. as areal defect density quantifying the number of defects per unit area) in a crystalline structure of the first semiconductor material is substantially greater, e.g. at least 10 3 times greater or at least 10 6 greater, than an amount of defects in a crystalline structure of the second semiconductor material.
  • Example 31 provides the quantum circuit assembly according to Example 30, where the amount of defects in the first semiconductor material is greater than about 10 9 cm 2 , including all values and ranges therein, e.g. greater than about 10 11 cm 2 or greater than about 10 12 cm 2 .
  • Example 32 provides the quantum circuit assembly according to Examples 30 or 31, where the amount of defects in the second semiconductor material is less than about 10 8 cm 2 , including all values and ranges therein, e.g. less than about 10 6 cm 2 or less than about 10 3 cm 2 .
  • Example 33 provides the quantum circuit assembly according to any one of Examples 27-32, where the at least one Josephson Junction includes two Josephson Junctions.
  • Example 34 provides the quantum circuit assembly according to Example 33, where the two Josephson Junctions form a SQUID.
  • Example 35 provides a quantum circuit assembly that includes a substrate and at least one qubit device including at least one Josephson Junction.
  • the at least one Josephson Junction may include a first electrode and a second electrode provided over or at least partially in the substrate, and a semiconductor nanowire between the first electrode and the second electrode, where the semiconductor nanowire has a substantially quadrilateral (e.g. substantially rectangular or trapezoid) transverse cross-sectional profile.
  • Example 36 provides the quantum circuit assembly according to Example 35, where the at least one Josephson Junction includes two Josephson Junctions.
  • Example 37 provides the quantum circuit assembly according to Example 36, where the two Josephson Junctions form a SQUID.
  • Example 38 provides a quantum circuit assembly that includes a substrate and at least one qubit device including at least one Josephson Junction.
  • the at least one Josephson Junction may include a first electrode and a second electrode provided over or at least partially in the substrate, and a trench in a layer of a cover material provided over the substrate, the trench extending between the first electrode and the second electrode and filled with one or more semiconductor materials, where an amount of defects (measured e.g.
  • a defect density quantifying the number of defects per unit area) in a crystalline structure of the one or more semiconductor materials in a first region of the trench is substantially greater than an amount of defects in a crystalline structure of the one or more semiconductor materials in a second region of the trench, where the first region is between the second region and the substrate (i.e. the first region of the trench is the region closer to the substrate than the second region), e.g. at least 10 3 times greater or at least 10 6 greater.
  • Example 39 provides the quantum circuit assembly according to Example 38, where the amount of defects in the first region is greater than about 10 9 cm 2 , including all values and ranges therein, e.g. greater than about 10 11 cm 2 or greater than about 10 12 cm 2 .
  • Example 40 provides the quantum circuit assembly according to Examples 38 or 39, where the amount of defects in the second region is less than about 10 8 cm 2 , including all values and ranges therein, e.g. less than about 10 6 cm 2 or less than about 10 3 cm 2 .
  • Example 41 provides the quantum circuit assembly according to any one of Examples 38-40, where the at least one Josephson Junction includes two Josephson Junctions.
  • Example 42 provides the quantum circuit assembly according to Example 41, where the two Josephson Junctions form a SQUID.
  • Example provides the quantum circuit assembly according to any one of Examples 27-42 may be included within a quantum 1C package where the quantum circuit assembly is provided over a qubit die coupled to a further 1C element by one or more first-level interconnects.
  • the further 1C element may be one of an interposer, a circuit board, a flexible board, or a package substrate, and said Josephson Junction may be a part of a superconducting qubit.
  • Example provides the quantum circuit assembly according to any one of Examples 27-42 may be included within a quantum processing device of a quantum computing device.
  • the quantum computing device may further include one or more of a memory device configured to store data generated during operation of the quantum processing device and/or configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device, a cooling apparatus configured to maintain the temperature of the quantum processing device below 5 degrees Kelvin, and a non quantum processing device coupled to the quantum processing device.
  • a memory device configured to store data generated during operation of the quantum processing device and/or configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device
  • a cooling apparatus configured to maintain the temperature of the quantum processing device below 5 degrees Kelvin
  • a non quantum processing device coupled to the quantum processing device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

Un aspect de la présente invention concerne un procédé de fabrication de jonctions Josephson à base de semi-conducteur dans des ensembles de circuits quantiques. Le procédé est basé sur la fourniture d'un élément barrière tunnel semi-conducteur d'une jonction Josephson par croissance d'un ou plusieurs semi-conducteurs, lequel semi-conducteur (s) formera ultérieurement un élément barrière tunnel d'une jonction Josephson, directement sur un substrat de bits quantiques, par exemple à l'aide d'une croissance épitaxiale. Le procédé utilise un phénomène de piégeage selon le rapport d'aspect (ART) par croissance du semi-conducteur souhaité (s) dans une ouverture de tranchée à rapport d'aspect relativement élevé dans ou sur le substrat de bits quantiques. La croissance épitaxiale à l'intérieur d'une telle tranchée peut avantageusement maintenir la majorité des défauts cristallins dans l'élément barrière à effet tunnel formé au fond de la tranchée et peut favoriser l'intégration à l'échelle de tranche de jonctions Josephson à base de semi-conducteur pour des bits quantiques.
PCT/US2017/068366 2017-12-23 2017-12-23 Intégration à l'échelle de tranche de jonctions josephson à base de semi-conducteur WO2019125498A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2017/068366 WO2019125498A1 (fr) 2017-12-23 2017-12-23 Intégration à l'échelle de tranche de jonctions josephson à base de semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2017/068366 WO2019125498A1 (fr) 2017-12-23 2017-12-23 Intégration à l'échelle de tranche de jonctions josephson à base de semi-conducteur

Publications (1)

Publication Number Publication Date
WO2019125498A1 true WO2019125498A1 (fr) 2019-06-27

Family

ID=66993700

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2017/068366 WO2019125498A1 (fr) 2017-12-23 2017-12-23 Intégration à l'échelle de tranche de jonctions josephson à base de semi-conducteur

Country Status (1)

Country Link
WO (1) WO2019125498A1 (fr)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879446B2 (en) 2018-08-14 2020-12-29 Intel Corporation Vertical flux bias lines coupled to vertical squid loops in superconducting qubits
US10910488B2 (en) 2018-06-26 2021-02-02 Intel Corporation Quantum dot devices with fins and partially wrapped gates
US11011693B2 (en) 2019-06-24 2021-05-18 Intel Corporation Integrated quantum circuit assemblies for cooling apparatus
US11335778B2 (en) 2018-06-26 2022-05-17 Intel Corporation Quantum dot devices with overlapping gates
US11417765B2 (en) 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US11417755B2 (en) 2018-01-08 2022-08-16 Intel Corporation Differentially strained quantum dot devices
US11424324B2 (en) 2018-09-27 2022-08-23 Intel Corporation Multi-spacers for quantum dot device gates
US11450765B2 (en) 2018-09-27 2022-09-20 Intel Corporation Quantum dot devices with diodes for electrostatic discharge protection
CN115423110A (zh) * 2021-05-31 2022-12-02 合肥本源量子计算科技有限责任公司 量子比特的量子态读取确定方法、系统及量子计算机
US11522116B2 (en) 2020-04-13 2022-12-06 International Business Machines Corporation Vertical AL/EPI SI/AL, and also AL/AL oxide/AL, josephson junction devices for qubits
US11658212B2 (en) 2019-02-13 2023-05-23 Intel Corporation Quantum dot devices with conductive liners
CN116193974A (zh) * 2022-12-14 2023-05-30 中国人民解放军战略支援部队信息工程大学 利用N空位缺陷调控NbN/AlN/NbN约瑟夫森结电输运性质的方法
US11749721B2 (en) 2018-09-28 2023-09-05 Intel Corporation Gate walls for quantum dot devices
US11957066B2 (en) 2019-09-04 2024-04-09 Intel Corporation Stackable in-line filter modules for quantum computing

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020190249A1 (en) * 2001-05-30 2002-12-19 Williams David Arfon Quantum computer
US20110147714A1 (en) * 2009-12-21 2011-06-23 Samsung Electronics Co., Ltd. Field-effect transistor and sensor based on the same
US20140357493A1 (en) * 2011-11-11 2014-12-04 Northrop Grumman Systems Corporation Quantum bits and methods of forming the same
WO2017046151A1 (fr) * 2015-09-15 2017-03-23 Technische Universität München Procédé de fabrication d'une nanostructure
WO2017217961A1 (fr) * 2016-06-13 2017-12-21 Intel Corporation Jonctions josephson constituées de métaux réfractaires et nobles

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020190249A1 (en) * 2001-05-30 2002-12-19 Williams David Arfon Quantum computer
US20110147714A1 (en) * 2009-12-21 2011-06-23 Samsung Electronics Co., Ltd. Field-effect transistor and sensor based on the same
US20140357493A1 (en) * 2011-11-11 2014-12-04 Northrop Grumman Systems Corporation Quantum bits and methods of forming the same
WO2017046151A1 (fr) * 2015-09-15 2017-03-23 Technische Universität München Procédé de fabrication d'une nanostructure
WO2017217961A1 (fr) * 2016-06-13 2017-12-21 Intel Corporation Jonctions josephson constituées de métaux réfractaires et nobles

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11417755B2 (en) 2018-01-08 2022-08-16 Intel Corporation Differentially strained quantum dot devices
US11417765B2 (en) 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US10910488B2 (en) 2018-06-26 2021-02-02 Intel Corporation Quantum dot devices with fins and partially wrapped gates
US11335778B2 (en) 2018-06-26 2022-05-17 Intel Corporation Quantum dot devices with overlapping gates
US10879446B2 (en) 2018-08-14 2020-12-29 Intel Corporation Vertical flux bias lines coupled to vertical squid loops in superconducting qubits
US11450765B2 (en) 2018-09-27 2022-09-20 Intel Corporation Quantum dot devices with diodes for electrostatic discharge protection
US11424324B2 (en) 2018-09-27 2022-08-23 Intel Corporation Multi-spacers for quantum dot device gates
US11749721B2 (en) 2018-09-28 2023-09-05 Intel Corporation Gate walls for quantum dot devices
US11658212B2 (en) 2019-02-13 2023-05-23 Intel Corporation Quantum dot devices with conductive liners
US11011693B2 (en) 2019-06-24 2021-05-18 Intel Corporation Integrated quantum circuit assemblies for cooling apparatus
US11957066B2 (en) 2019-09-04 2024-04-09 Intel Corporation Stackable in-line filter modules for quantum computing
US11522116B2 (en) 2020-04-13 2022-12-06 International Business Machines Corporation Vertical AL/EPI SI/AL, and also AL/AL oxide/AL, josephson junction devices for qubits
CN115423110A (zh) * 2021-05-31 2022-12-02 合肥本源量子计算科技有限责任公司 量子比特的量子态读取确定方法、系统及量子计算机
CN115423110B (zh) * 2021-05-31 2024-04-05 本源量子计算科技（合肥）股份有限公司 量子比特的量子态读取确定方法、系统及量子计算机
CN116193974A (zh) * 2022-12-14 2023-05-30 中国人民解放军战略支援部队信息工程大学 利用N空位缺陷调控NbN/AlN/NbN约瑟夫森结电输运性质的方法
CN116193974B (zh) * 2022-12-14 2024-05-03 中国人民解放军战略支援部队信息工程大学 利用N空位缺陷调控NbN/AlN/NbN约瑟夫森结电输运性质的方法

Similar Documents

Publication Publication Date Title
US10686007B2 (en) Quantum circuit assemblies with at least partially buried transmission lines and capacitors
US10803396B2 (en) Quantum circuit assemblies with Josephson junctions utilizing resistive switching materials
US10665769B2 (en) Quantum circuit assemblies with vertically-stacked parallel-plate capacitors
US11177912B2 (en) Quantum circuit assemblies with on-chip demultiplexers
WO2019125498A1 (fr) Intégration à l'échelle de tranche de jonctions josephson à base de semi-conducteur
US10879446B2 (en) Vertical flux bias lines coupled to vertical squid loops in superconducting qubits
US10468578B2 (en) Package substrates with top superconductor layers for qubit devices
US20200265334A1 (en) Improved qubit designs for quantum circuits
US10847705B2 (en) Reducing crosstalk from flux bias lines in qubit devices
WO2019117975A1 (fr) Intégration de trou d'interconnexion traversant le silicium pour circuits quantiques
US10256206B2 (en) Qubit die attachment using preforms
TWI767926B (zh) 量子電路組件、量子計算裝置及用於形成量子電路組件的方法
AU2018282484B2 (en) Wafer-scale integration of dopant atoms for donor- or acceptor-based spin qubits
US10565515B2 (en) Quantum circuit assemblies with triaxial cables
WO2019117973A1 (fr) Ligne de transmission verticale à bits quantiques avec deux plans de masse parallèles
WO2019117972A1 (fr) Ligne de transmission verticale de bits quantiques avec des trous d'interconnexion de masse entourant une ligne de signal
WO2019117974A1 (fr) Ligne de transmission verticale à bits quantiques avec une structure de mise à la terre entourant une ligne de signal
US10347834B2 (en) Wafer-scale integration of vacancy centers for spin qubits
WO2019117883A1 (fr) Dispositifs à bits quantiques à jonctions josephson fabriquées à l'aide d'un pont aérien ou d'un porte-à-faux
WO2019117929A1 (fr) Fabrication à l'échelle de tranche de jonctions josephson pour bits quantiques
WO2019032114A1 (fr) Dispositifs à bits quantiques ayant des éléments de circuit conducteur à contre-dépouille
US20200373351A1 (en) Substrate engineering for qubits
WO2019032115A1 (fr) Dispositifs à bits quantiques à jonctions josephson connectées en dessous de circuits de support
WO2018182584A1 (fr) Dispositifs à bits quantiques avec résonateurs à ondes lentes
WO2018182571A1 (fr) Lignes de polarisation de flux de courant commandé dans des dispositifs à bits quantiques

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17935554

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17935554

Country of ref document: EP

Kind code of ref document: A1