WO2019117975A1 - Intégration de trou d'interconnexion traversant le silicium pour circuits quantiques - Google Patents

Intégration de trou d'interconnexion traversant le silicium pour circuits quantiques Download PDF

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WO2019117975A1
WO2019117975A1 PCT/US2017/066891 US2017066891W WO2019117975A1 WO 2019117975 A1 WO2019117975 A1 WO 2019117975A1 US 2017066891 W US2017066891 W US 2017066891W WO 2019117975 A1 WO2019117975 A1 WO 2019117975A1
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face
layer
substrate
quantum
qubit
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Lester LAMPERT
Jeanette M. Roberts
Roman CAUDILLO
Zachary R. YOSCOVITS
David J. Michalak
James S. Clarke
Hubert C. GEORGE
Ravi Pillarisetty
Nicole K. THOMAS
Kanwaljit SINGH
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Intel Corporation
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53285—Conductive materials containing superconducting materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies

Definitions

  • This disclosure relates generally to the field of quantum computing, and more specifically, to through-silicon via (TSV) structures for use in quantum circuit assemblies and to methods of fabrication thereof.
  • TSV through-silicon via
  • Quantum computing refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. These quantum-mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.
  • Quantum computers use so-called quantum bits, referred to as qubits (both terms “bits” and “qubits” often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states - a uniquely quantum-mechanical phenomenon.
  • Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.
  • FIG. 1 provides a schematic illustration of an exemplary physical layout of a superconducting quantum circuit according to some embodiments of the present disclosure.
  • FIG. 2 illustrates an exemplary quantum circuit assembly with TSVs according to some embodiments of the present disclosure.
  • FIGS. 3A-3B provide a flow diagram of an illustrative method of manufacturing a quantum circuit assembly with one or more TSVs in accordance with various embodiments of the present disclosure.
  • FIGS. 4A-4M illustrate various stages in the manufacture of a quantum circuit assembly with one or more TSVs using the method shown in FIGS. 3A-3B in accordance with some embodiments of the present disclosure.
  • FIGS. 5A and 5B are top views of a wafer and dies that may include one or more quantum circuit assemblies with TSVs in accordance with various embodiments of the present disclosure.
  • FIG. 6 is a cross-sectional side view of a device assembly that may include one or more quantum circuit assemblies with TSVs in accordance with various embodiments of the present disclosure.
  • FIG. 7 is a block diagram of an example quantum computing device that may include one or more quantum circuit assemblies with TSVs in accordance with various embodiments of the present disclosure.
  • quantum computing or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data.
  • quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states.
  • Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole.
  • quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).
  • transitions include transitions (e.g., spin qubits and charge qubits), photon polarization qubits, single trapped ion qubits, etc.
  • quantum dots e.g., spin qubits and charge qubits
  • photon polarization qubits single trapped ion qubits, etc.
  • superconducting qubits are promising candidates for building a quantum computer, where, in general, superconducting qubits refer to qubit devices that operate based on Josephson effect which is a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a non-linear inductive device known as a Josephson Junction.
  • Josephson effect is a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a non-linear inductive device known as a Josephson Junction.
  • One challenge with qubits in general, and superconducting qubits in particular remains in protecting qubits from decoherence (i.e. loss of state, and, therefore loss of information that a qubit is supposed to hold).
  • Embodiments of the present disclosure propose a new approach to integrating TSVs into substrates on which qubits devices will later be formed.
  • the described approach is based on providing over the qubit side of the substrate (i.e. the side over which qubits will later be provided) an etch-stop layer for etching of the substrate (e.g. for deep reactive ion etching (DRIE) of the substrate), and then performing the necessary processing to form the TSVs from the backside of the substrate (i.e. the side opposite to the qubit side).
  • DRIE deep reactive ion etching
  • an etch is performed on the backside of the substrate to form via openings extending through the substrate and stopping at the etch-stop layer, and, following the etch, a superconductive material is conformally deposited into the via openings using a suitable conformal deposition technique, thus lining the sidewalls of the via openings and supported at the bottom of the via openings by the etch-stop layer.
  • the remaining volume of the via openings may then be filled with a fill material (which deposition is also performed from the backside of the substrate), where the fill material may be a superconductive material (e.g. electroplated indium), a conductive but not superconductive material (e.g. copper), or a dielectric (e.g. a ceramic material).
  • the etch-stop layer may be removed so that subsequent processes for providing one or more qubits devices on the qubit side of the substrate may be carried out.
  • Using an etch-stop layer on the qubit side of the substrate during the formation of TSVs advantageously allows forming the TSVs starting from the backside, may eliminate or at least reduce the need for polishing exposure to the qubit side, and may also serve to protect the qubit side from intrinsic silicon contamination. As a result, the qubit side on which qubit devices will later be formed may be kept cleaner and/or flatter compared to prior approaches, potentially reducing the amount of spurious TLS's and improving on qubit decoherence issues.
  • some or all of the electrically conductive portions of quantum circuit assemblies described herein may be made from one or more superconductive materials. However, some or all of these electrically conductive portions could be made from electrically conductive materials which are not superconductive. In the following, unless specified otherwise, reference to an electrically conductive material implies that a superconductive material can be used, and vice versa.
  • materials described herein as "superconductive materials" may refer to materials, including alloys of materials, which exhibit superconducting behavior at typical qubit operating conditions (e.g. materials which exhibit superconducting behavior at very low temperatures at which qubits typically operate), but which may or may not exhibit such behavior at higher temperatures (e.g.
  • Examples of such materials include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), niobium titanium nitride (NbTiN), indium (In), and molybdenum rhenium (MoRe), all of which are particular types of superconductors at qubit operating
  • the phrase “A and/or B” means (A), (B), or (A and B).
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
  • the notation "A/B/C” means (A), (B), and/or (C).
  • the terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are typically operated at.
  • techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-30 GFIz, e.g. in 3-10 GFIz range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering.
  • qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.
  • a quantum circuit may be viewed as comprising a plurality of qubits provided over a first face of a substrate, i.e. the qubit side of the substrate, and a plurality of various microwave transmission lines for providing microwave connectivity to, from, and between the qubits.
  • the qubits may be implemented as any of the suitable qubits, such as e.g. superconducting qubits (e.g. transmons), quantum dot qubits, etc.
  • Various microwave transmission lines may be either resonant or non-resonant, as explained in the following paragraphs. At various locations on such a substrate TSVs may be provided in order to reduce substrate resonant modes, microwave slot modes, and/or crosstalk between neighboring microwave elements.
  • FIG. 1 provides a schematic illustration of an exemplary physical layout of a superconducting quantum circuit 100, more specifically - a transmon circuit, according to some embodiments of the present disclosure.
  • the quantum circuit 100 may include one or more qubits, shown in FIG. 1 as qubits 102; at least one flux bias line provided for each qubit, shown in FIG. 1 as flux bias lines 104; a drive line provided for each qubit, shown in FIG. 1 as drive lines 106; a feedline (also sometimes referred to as a "microwave line” or a "readout line”), shown in FIG. 1 as a feedline 108; at least one readout resonator for each qubit, shown in FIG.
  • the quantum circuit 100 may further include various conductive contacts, shown in FIG. 1 as black circles illustrating conductive contacts 114 for the flux bias lines 104, conductive contacts 116 for the drive lines 106, and conductive contacts 118 for the feedline 108. Still further, the quantum circuit 100 may include a plurality of TSVs 120 shown in FIG. 1 as white circles.
  • each of the qubits 102 may include one or more non-linear inductive elements such as e.g. Josephson Junctions.
  • Josephson Junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits.
  • a non-linear inductive element such as e.g. Josephson Junctions.
  • Josephson Junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits.
  • a non-linear inductive elements such as e.g. Josephson Junctions.
  • Josephson Junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits.
  • Josephson Junction includes two superconductors coupled by a so-called "weak link” that weakens the superconductivity between the two superconductors.
  • a weak link of a Josephson Junction may e.g. be implemented by providing a thin layer of an insulating material, a conductive but not superconductive metal, or a semiconducting material, typically referred to as a "barrier” or a “tunnel barrier,” sandwiched, in a stack-like arrangement, between two layers of superconductor, which two superconductors server as a first and a second electrode of a Josephson Junction.
  • the Josephson Junction provides a non-linear inductive element to the circuit and allows the qubit to become an anharmonic oscillator.
  • the anharmonicity is determined by the ratio of the charging energy, which stems from the total capacitance between a first and second element of the qubit, and the Josephson energy of the non-linear inductive element (e.g., Josephson Junction).
  • the anharmonicity is what allows the state of the qubit to be controlled to a high level of fidelity.
  • the charging and Josephson energies also control the qubit frequency.
  • a frequency of the qubit cannot be changed substantially beyond what is defined by the design unless one of the qubit capacitive elements is tunable.
  • SQUID superconducting quantum interference device
  • superconducting qubit includes a pair of Josephson Junctions and a loop of a conductive, typically superconductive material (i.e. a superconducting loop), connecting a pair of Josephson Junctions.
  • Applying a net magnetic field in a certain orientation to the SQUID loop of a superconducting qubit allows controlling the frequency of the qubit.
  • applying magnetic field to the SQUID region of a superconducting qubit is generally referred to as a "flux control" of a qubit, and the magnetic field is generated by providing direct -current (DC) or a pulse of current through an electrically conductive or superconductive line generally referred to as a "flux bias line” (also known as a “flux line” or a “flux coil line”), e.g. the flux bias line 104 for each qubit 102 shown in FIG. 1.
  • a flux bias line also known as a "flux line” or a “flux coil line”
  • FIG. 1 a SQUID loop is illustrated as a small square in each of the qubits 102 near the corresponding flux bias line 104.
  • the one or more Josephson Junctions may be directly electrically connected to one or more other circuit elements, which, in combination with the Josephson Junction(s), form a non-linear oscillator circuit providing multi-level quantum system where the first two to three levels define the qubit under normal operation.
  • the circuit elements could be e.g. capacitors in transmons or superconducting loops in flux qubits. Since FIG. 1 provides an exemplary illustration of a transmon circuit, such circuit elements are schematically illustrated as interdigitated capacitors within each of the qubits 102, the capacitors connected to the respective SQUID loops.
  • the flux bias lines 104, microwave drive lines 106, and feedline 108 are examples of non resonant transmission lines, while the readout resonators 110 and coupling resonators 112 are examples of resonators of a typical superconducting quantum circuit.
  • the non-resonant transmission lines are typically used for providing microwave signals to different quantum circuit elements and components, which elements and components include e.g. readout resonators for various qubits, and may be considered to implement external readout and/or control of qubits.
  • the resonators may be viewed as implementing internal control lines for the qubits.
  • a resonator of a quantum circuit differs from a non-resonant microwave transmission line in that a resonator is deliberately designed to support resonant oscillations (i.e. resonance), under certain conditions.
  • non-resonant transmission lines may be similar to conventional microwave transmission lines in that they are designed to avoid resonances, especially resonances at frequencies/wavelengths close to the resonant frequencies/wavelengths of any resonant object used in the quantum computing circuits, e.g., qubits, bus resonators, or readout resonators in the proximity of such non-resonant lines.
  • non-resonant transmission lines Once non-resonant transmission lines are manufactured, some of them may inadvertently support some resonances, but, during its design, efforts are taken to minimize resonances, standing waves, and reflected signals as much as possible, so that all of the signals can be transmitted through these lines without, or with as little resonance as possible.
  • a resonator is a transmission line segment that is made by employing fixed boundary conditions, and these boundary conditions control the frequencies/wavelengths which will resonate within a given transmission line segment used to implement a resonator.
  • each end of a transmission line segment resonator can be either a node, if it is shorted to ground (e.g. where one end of the transmission line segment structure is electrically connected to a ground plane), or an antinode, if it is capacitively or inductively coupled to ground or to another quantum circuit element.
  • resonators differ from non-resonant microwave transmission lines in how these lines are terminated at the relevant ends.
  • a line used to route a signal on a substrate i.e.
  • a transmission line resonator is typically composed of a piece of transmission line terminated with either two open circuits (in case of a half-wavelength resonator) or an open and a short circuit (in case of a quarter-wavelength resonator).
  • transmission line length may e.g. be a multiple of a microwave wavelength divided by 2 or 4, respectively.
  • capacitive terminations may be used for resonators which are coupled to qubits, to a feedline, line, or to another resonator by a capacitive interaction.
  • transmission line segments of the resonators need to be of a specific length that can support such oscillations. That is why, often times, resonators may be laid out on a substrate longer than the actual distance would require (i.e. a non-resonant transmission line would typically be laid out to cover the distance in the most compact manner possible, e.g. without any curves, wiggles, or excess length, while a resonator may need to have curves, wiggles, and be longer than the shortest distance between the two elements the resonator is supposed to couple in order to be sufficiently long to support resonance, as is illustrated in FIG.
  • Readout resonators employed with superconducting qubits are used to read the state(s) of the qubits.
  • a corresponding readout resonator may be provided for each qubit, as is shown in FIG. 1 with a corresponding readout resonator 110 provided for the each qubit 102.
  • a readout resonator is a transmission line segment. On one end it may have an open circuit connection to ground as well as any capacitively or inductively coupled connections to other quantum elements or a non-resonant microwave feedline.
  • a readout resonator may either have a capacitive connection to ground (for a half-wavelength resonator) or may have a short circuit to the ground (for a quarter-wavelength resonator), which also results in oscillations within the transmission line, with the resonant frequency of the oscillations being close to the frequency of the qubit.
  • a readout resonator is coupled to a qubit by being in the appropriate location and sufficient proximity to the qubit, again, either through capacitive or inductive coupling. Due to a coupling between a readout resonator and a qubit, changes in the state of the qubit result in changes of the resonant frequency of the readout resonator. In turn, changes in the resonant frequency of the readout resonator can be read externally via connections which lead to external electronics e.g. wire or solder bonding pads.
  • Coupling resonators also known as “bus resonators” provide one manner for coupling different qubits together in order to realize quantum logic gates. These types of resonators are analogous in concept, and have analogous underlying physics, as readout resonators, except that a coupling or "bus" resonator involves only capacitive couplings between two or more qubits, as is shown in FIG. 1 with a coupling resonator 112 between two qubits 102, whereas a readout resonator involves capacitive coupling between two or more qubits and a feedline.
  • a coupling resonator may be implemented as a microwave transmission line segment that includes capacitive or inductive connections to ground on both sides (e.g.
  • each side of a coupling resonator is coupled, either capacitively or inductively, to a respective (i.e. different) qubit by being in the appropriate location and sufficient proximity to the qubit. Because different regions of a coupling resonator have coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator.
  • coupling resonators may be employed for implementing logic gates.
  • the qubit frequency may be controlled in order to bring the frequency either closer to or further away from another resonant item, for example a coupling resonator or a coupled neighbor qubit, to implement multi-qubit interactions, as may be desired in a particular setting.
  • another resonant item for example a coupling resonator or a coupled neighbor qubit
  • both qubits 102 may need to be tuned to be at nearly the same frequency or a detuning equal, or nearly equal, to the anharmonicity.
  • One way in which such two qubits could interact is that, if the frequency of the first qubit 102 is tuned very close to the resonant frequency of the coupling resonator 112, the first qubit can, when in the excited state, relax back down to the ground state by emitting a photon (similar to how an excited atom would relax) that would resonate within the coupling resonator 112. If the second qubit 102 is also at this energy (i.e. if the frequency of the second qubit is also tuned very close to the resonant frequency of the coupling resonator 112), then it can absorb the photon emitted from the first qubit, via the coupling resonator 112 coupling these two qubits, and be excited from its ground state to an excited state.
  • the two qubits 102 interact, or are entangled, in that a state of one qubit is controlled by the state of another qubit.
  • two qubits could interact via exchange of virtual photons, where these three elements do not have to be tuned to be at the same frequency with one another.
  • two or more qubits could be configured to interact with one another by tuning their frequencies to specific values or ranges.
  • two qubits coupled by a coupling resonator do not interact, i.e. the qubits are independent.
  • magnetic flux by means of controlling the current in the appropriate flux bias line 104, to one qubit it is possible to cause the frequency of the qubit to change enough so that the photon it could emit no longer has the right frequency to resonate on the coupling resonator 112 or on the neighboring qubit via a virtual photon transfer through the bus. If there is nowhere for such a frequency-detuned photon to go, the qubit will be better isolated from its surroundings and will live longer in its current state.
  • two or more qubits could be configured to reduce interactions with one another by tuning their frequencies to specific values or ranges.
  • each qubit 102 may be read by way of its corresponding readout resonator 110.
  • the state of qubit 102 induces a shift in the resonant frequency in the associated readout resonator 110.
  • This shift in resonant frequency can then be read out using its coupling to a feedline, e.g. the feedline 108.
  • an individual readout resonator 110 may be provided for each qubit 102.
  • a readout resonator may be a transmission line segment that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side (for a quarter-wavelength resonator) or has a capacitive connection to ground (for a half-wavelength resonator), which results in oscillations within the transmission line (resonance) that depends upon the state of a proximal qubit.
  • a readout resonator may be coupled to its corresponding qubit 102 by being in an appropriate location and sufficient proximity to the qubit, more specifically in an appropriate location and sufficient proximity to a superconductive element such as e.g.
  • a capacitor of the qubit 102 that capacitively couples to the readout resonator 110, when the qubit is implemented as a transmon. Due to a coupling between the readout resonator 110 and the qubit 102, changes in the state of the qubit result in changes of the resonant frequency of the readout resonator. In turn, by ensuring that the readout resonator is in sufficient proximity to a corresponding microwave feedline 108, changes in the resonant frequency of the readout resonator induce changes in the transmission coefficients of the microwave feedline, detected externally.
  • a microwave line such as the feedline 108 shown in FIG. 1 may be used to not only readout the state of the qubits as described above, but also to control the state of the qubits.
  • the line operates in a half-duplex mode where, at some times, it is configured to readout the state of the qubits 102, and, at other times, it is configured to control the state of the qubits.
  • such microwave lines may be used to only readout the state of the qubits as described above, while separate drive lines, shown in FIG. 1 as drive lines 106, may be used to control the state of the qubits.
  • microwave lines used for readout may be referred to as readout lines
  • microwave lines used for controlling the state of the qubits may be referred to as drive lines.
  • Drive lines 106 may control the state of their respective qubits 102 by providing to the qubits a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the states of the qubit. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the states of the qubit.
  • FIG. 1 further illustrates TSVs 120, or, viewed differently elements 120 represent the conductive contacts on the qubit surface for such TSVs, which conductive contacts may e.g. be connected to an interposer substrate via first-level interconnects such as e.g. solder bumps.
  • the TSVs 120 may e.g. be connected to the ground potential or some other reference potential.
  • such TSVs are typically used when a substrate supports propagation of microwave signals, where the TSVs serve to e.g. suppress microwave parallel plate modes, cross-coupling between circuital blocks, and substrate resonant modes.
  • providing such TSVs implementing ground pathways may improve signal quality, enable fast pulse excitation and improve the isolation between the different lines.
  • FIG. 1 Only two TSVs 120 are labeled in FIG. 1 with the reference numeral 120, but all white circle shown throughout the substrate on which the quantum circuit 100 is provided are intended to illustrate exemplary locations of such TSVs.
  • the illustration of the location and the number of the TSVs 120 in FIG. 1 is purely illustrative and, in various embodiments, the TSVs 120 may be provided at different places, as known in microwave engineering.
  • FIG. 1 illustrates an example of a quantum circuit comprising only two qubits 102, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure.
  • FIG. 1 illustrates an example of a quantum circuit comprising only two qubits 102, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure.
  • FIG. 1 illustrates an example of a quantum circuit comprising only two qubits 102, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure.
  • FIG. 1 illustrates an example of
  • FIG. 2 illustrates an exemplary quantum circuit assembly 200 with TSVs 202 according to some embodiments of the present disclosure.
  • Some of the elements referred to in the description of FIG. 2 with reference numerals are indicated in FIG. 2 with different patterns, with a legend showing the correspondence between the reference numerals and patterns being provided at the bottom of FIG. 2, and are not labeled in FIG. 2 with arrows pointing to them in order to not clutter the drawing.
  • the legend illustrates that FIG. 2 uses different patterns to show a substrate 204, a superconductive liner material 212, a fill material 214, etc.
  • the assembly 200 may be a result of carrying out the fabrication method shown in FIGS.
  • FIG. 2 illustrates an example of a quantum circuit assembly comprising three TSVs 202 located at certain positions within the substrate 204, the illustration of the location and the number of the TSVs 202 in FIG. 2 is purely illustrative and, in various embodiments, the TSVs 202 may be provided at different places in a substrate, as known in microwave engineering, all of which embodiments being within the scope of the present disclosure.
  • the TSVs 202 are provided within the substrate 204.
  • the substrate 204 may include any substrate which may serve as a foundation for fabricating a quantum circuit with plurality of qubits and TSVs as described herein.
  • the substrate 204 may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof.
  • the substrate 204 may be non-crystalline.
  • any material that provides sufficient advantages e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g.
  • substrates which may serve as the substrate 204 include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.
  • SOI silicon-on-insulator
  • the substrate 204 may include a layer that is particularly low-loss in terms of spurious TLS's, as an upper layer of the substrate over which qubits will be provided.
  • a layer may include e.g. an epitaxially grown silicon, preferably substantially intrinsic (and, hence, high resistivity) silicon, or any other highly crystalline dielectric material with as little defects as possible because such materials are believed to be low-loss in terms of TLS's.
  • the substrate 204 may have a first face 206 and an opposing second face 208. Over the first face 206 one or more qubits may be provided, schematically shown in FIG. 2 as a qubit 210, where, in various embodiments, number, location, and relative size of the qubits 210 may be different from what is shown in FIG. 2.
  • the one of more qubits 210 may e.g. be a plurality of superconducting qubits as described above with reference to FIG. 1, where at least of a first and a second of the plurality of superconducting qubits 210 may be coupled by a coupling resonator as described above.
  • the TSVs 202 extend between the first face 206 and the second face 208. More specifically, each of the TSVs 202 may be viewed as a via opening in the substrate 204, the opening extending between the first face 206 and the second face 208, filled with at least two different materials.
  • One material within the via opening of each of the TSVs 202 is a superconductive material 212 provided as a liner within the via opening and, as such, is present at least within the via opening at the first face 206 of the substrate 202 (i.e. the superconductive liner 212 is present at a portion of the via opening that is closest to the first face 206 of the substrate and interfaces whatever material is provided on the first face of the substrate).
  • the superconductive liner 212 may also be present at least on portions, but likely on all, sidewalls of the via openings for the TSVs 202, as shown in FIG. 2.
  • the second material within the via opening of each of the TSVs 202 is a fill material 214, filling the remainder of the via openings lined with the superconductive liner 212.
  • the fill material 214 is between the superconductive liner 212.
  • the fill material 214 may be a superconductive material different from that of the superconductive liner 212, e.g. the superconductive liner 212 may include TiN, while the fill material 214 may include a different superconductor.
  • the fill material 214 may be a conductive material that is not superconductive, e.g. a metal comprising copper.
  • the fill material 214 could be any other electrically conductive, but not superconductive, material, such as e.g.
  • the fill material 214 could be any non-superconductive, non-magnetic material that can be electroplated. Still in other embodiments, the fill material 214 may be a dielectric material such as e.g. a polymer or a ceramic material.
  • the via openings for the TSVs 202 may have aspect ratios (i.e. a ratio between the height and the width of a given opening) greater than about 3, including all values and ranges therein, e.g. greater than about 5, or greater than about 9.
  • the height of the openings i.e. a dimension measured along the z-axis of the coordinate system shown in FIG. 2
  • the width of the openings i.e. dimension measured along the y-axis of the coordinate system shown in FIG.
  • the thickness of the superconductive liner 212 may be between about 1 and 1000 nanometers (nm), including all values and ranges therein, e.g. between about 3 and 250 nm, or between about 5 and 100 nm.
  • the remaining space of the via openings may be occupied by the fill material 214, or at least some of it may be left unoccupied, either deliberately, or accidentally (e.g. due to imperfections during the process of filling small openings with the fill material 214).
  • the quantum circuit assembly 200 may include a first layer 216 of an electrically conductive, preferably superconductive, material provided over the first face 206 of the substrate 204, so that at least one or more portions of the one or more qubit devices 210 are provided over the first layer 216.
  • the material of the first layer 216 may interface the superconductive liner 212.
  • the material of the first layer 216 may include any suitable superconductive material, or a combination of one or more such materials.
  • the electrically conductive material of the first layer 216 could be the same as the superconductive material of the
  • the electrically conductive material of the first layer 216 could be seen as extending into the portion/end of the via opening that is closest to the first face 206 of the substrate.
  • the materials of the first layer 216 and of the superconductive liner 212 within the via openings could be different materials.
  • the first layer 216 may have a thickness between about 1 and 5000 nm, including all values and ranges therein, e.g. between about 25 and 1000 nm, or between about 50 and 500 nm.
  • the quantum circuit assembly 200 may further include a second layer 218 of an electrically conductive, preferably superconductive, material provided over the second face 208 of the substrate 204.
  • the fill material 214 within the via openings may interface the second layer 218.
  • the electrically conductive material of the second layer 218 could be the same as the superconductive material of the superconductive liner 212 within the via openings of the TSVs 202, or/and the material of the first layer 218.
  • the materials of the second layer 218 and of the superconductive liner 212 within the via openings or of the first layer 216 could be different materials.
  • the second layer 218 may have a thickness between about 1 and 5000 nm, including all values and ranges therein, e.g. between about 25 and 1000 nm, or between about 50 and 500 nm.
  • the quantum circuit assembly 200 may be a part of a quantum integrated circuit (1C) package where the qubit substrate 204 is coupled to a further 1C element by interconnects, e.g. first-level interconnects such as e.g. solder bumps, between the further 1C element and the electrically conductive materials of the via openings forming the TSVs 202.
  • the further 1C element may include an interposer, a circuit board, a flexible board, or a package substrate, as e.g. described below with reference to FIG. 6.
  • the quantum circuit assembly 200 may be a die 1220 coupled to an interposer 1204 shown in FIG.
  • such a further 1C element may be coupled to the second side 208 of the substrate.
  • such a further 1C element may be coupled to the first (i.e. the qubit) side 206 of the substrate, in a flip-chip configuration, e.g. using first-level interconnects in the form of flip-chip or controlled collapse chip connection ("C4") bumps disposed initially over the qubit substrate 204 or on the further 1C element.
  • any types of first-level interconnects may be used, all of which being within the scope of the present disclosure. How electrical connections are made for various conductive contacts on a qubit substrate and on a package substrate is well known in the art of packaging and, therefore, in the interests of brevity, not described here in detail.
  • FIGS. 3A-3B provide a flow diagram of an illustrative method 300 of manufacturing a quantum circuit assembly with one or more TSVs in accordance with various embodiments of the present disclosure, e.g. the quantum circuit assembly 200 as shown in FIG. 2.
  • Device assemblies in various example stages during the manufacture using the method 300 are illustrated in FIGS. 4A-4M, in accordance with some embodiments of the present disclosure.
  • each of FIGS. 4A-4M illustrates a cross-sectional view of the assembly, which is a view in the y-z plane of the exemplary x- y-z coordinate system shown at the bottom of each of FIGS. 4A-4M. Similar to FIG. 2, a number of elements referred to in the description of FIGS.
  • FIGS. 4A-4M with reference numerals are indicated in these FIGS with different patterns in order to not clutter the drawings, with a legend at the bottom of FIGS. 4A-4M showing the correspondence between the reference numerals and the patterns.
  • the same reference numerals used in FIG. 2 and FIGS. 4A-4M are intended to illustrate the same or analogous elements, so that, unless specified otherwise, descriptions of a given element provided with respect to one FIG. is applicable to other FIGS.
  • FIGS. 3A-3B once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture multiple TSVs as described herein substantially
  • the operations may be performed in a different order to reflect the architecture of a particular quantum circuit component that may include one or more TSVs according to any of the embodiments of the present disclosure.
  • the manufacturing method 300 may include other operations, not specifically shown in FIGS. 3A-3B, such as e.g. various cleaning and/or planarization operations as known in the art.
  • the substrate 204 and other portions of the assembly at any given stage of processing may be cleaned prior to or/and after any of the processes of providing the TSV as described herein, e.g. to remove oxide, surface-bound organic and metallic contaminants, as well as subsurface contamination.
  • cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g.
  • the quantum circuit assemblies as described herein may be planarized prior to or/and after any of the processes of providing the TSV as described herein, e.g. to remove the overburden of the materials deposited on the surfaces and to expose certain underlying elements.
  • planarization may be carried out using a polishing process such as e.g. chemical mechanical planarization (CMP), using a suitable slurry formulation and mechanical polishing process to remove unwanted materials from a wafer/structure, achieving a relatively smooth upper surface upon which further components of the quantum circuit assembly may be built.
  • CMP chemical mechanical planarization
  • the method 300 may begin with a process 302 that includes depositing an etch-stop layer over the side of a substrate over which qubits will later be provided.
  • etch-stop layer 432 is provided over the face 206 of the substrate 204.
  • the etch-stop layer 432 may be referred to as a "cover” layer because it serves to cover and protect the qubit surface of the substrate 204 during the fabrication of TSVs, and may also be referred to as a "sacrificial" layer because some or all of it will be removed in a later process, after the material has served its' purpose.
  • a material of an etch-stop layer 432 may include any material that has sufficient etch selectivity with respect to the material of the substrate 204, in order for an etch process used in a later stage to provide openings in the substrate 204 to not substantially etch into the etch-stop layer 432.
  • two materials are said to have "sufficient etch selectivity" when etchants used to etch one material do not substantially etch the other, enabling selective etching of one material but not the other.
  • some other considerations in selecting a suitable material for the etch-stop layer 432 may include e.g. possibilities of smooth film formation, low shrinkage and outgassing, and good dielectric properties (such as e.g. low electrical leakage, suitable value of a dielectric constant, and thermal stability).
  • the material of the etch-stop layer 432 may be a sacrificial dielectric material, such as e.g. any of the low-k or high-k dielectric materials used in semiconductor processing, including but not limited to elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • a sacrificial dielectric material such as e.g. any of the low-k or high-k dielectric materials used in semiconductor processing, including but not limited to elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • low-k materials that may be used as the etch-stop layer 432 may include, but are not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, spin-on organic polymeric dielectrics such as e.g. polyimide, polynorbornenes, benzocyclobutene, and polytetrafluoroethylene (PTFE), or spin-on silicon-based polymeric dielectric such as e.g.
  • any suitable deposition techniques may be used to deposit the etch-stop layer 432 over the face 206 of the substrate 204 in the process 302.
  • techniques such as e.g. spin-coating, dip-coating, atomic layer deposition (ALD), chemical vapor deposition (CVD), or plasma enhanced CVD (PECVD) may be used to deposit the etch-stop layer 432
  • patterning may include any suitable patterning technique(s), e.g. photolithographic or electron-beam patterning, possibly in combination with using a mask.
  • the etch-stop layer 432 deposited in the process 302 may have a thickness (i.e.
  • a dimension measured along the z-axis of the coordinate system shown in FIG. 4A may be between about 50 and 3000 nm, including all values and ranges therein, e.g. between about 500 and 2500 nm, or between about 750 and 2000 nm.
  • the method 300 may then proceed with a process 304 that includes turning the substrate 204 over, so that subsequent processing may be performed on the backside.
  • An exemplary result of the process 304 is illustrated with a quantum circuit assembly 404 shown in FIG. 4B, showing that the etch-stop layer 432 provided over the face 206 of the substrate 204 is now at the bottom and the backside face 208 of the substrate 204 is facing up.
  • a patterned mask may be provided over the backside of the substrate, the mask defining locations and dimensions of the future TSVs.
  • An exemplary result of the process 306 is illustrated with a quantum circuit assembly 406 shown in FIG. 4C, showing that a patterned mask 434 is provided over the backside 208 of the substrate 204, where openings 436 in the mask 434 define locations and dimensions for the future TSVs.
  • the assembly 406 illustrates 3 openings 436, in order to form 3 TSVs as shown in FIG. 2, but, as described with respect to FIG. 2, in other embodiments, any other number and other locations of such TSVs other than shown in FIGS are also possible. Any conventional techniques for providing a patterned mask may be used in the process 306 to provide the mask 434.
  • the method 300 may then proceed with a process 308 that includes, starting from the backside of the substrate, etching through the substrate via the mask openings and stopping at the etch-stop layer.
  • An exemplary result of the process 308 is illustrated with a quantum circuit assembly 408 shown in FIG. 4D, showing that openings 438 are formed as a result of etching the substrate 204 through the openings 436 in the mask 434.
  • the etch begins at the backside 208 of the substrate, and ends at the etch-stop layer 432 at the qubit face 206 of the substrate 204.
  • the openings 438 may be created in the process 308 using any suitable technique for removing desired portions of the material(s) of the substrate 204, such as e.g.
  • Forming the via opening 438 in the process 308 may include performing an etch using one or more etchants for which a rate of etching the substrate 204 is sufficiently higher than a rate of etching the etch-stop layer 432 (i.e. the etch-stop layer 432 is substantially etch-resistant when using the one or more etchants selected to etch the substrate 204 in the process 308).
  • the method 300 may then proceed with a process 310 that includes removing the etch mask used to define locations and dimensions of the openings etched through the substrate.
  • An exemplary result of the process 310 is illustrated with a quantum circuit assembly 410 shown in FIG. 4E, showing that the mask 434 is removed, exposing the backside 208 of the substrate in which the openings 438 have been formed.
  • Any conventional techniques for removing masks may be used in the process 310 to remove the mask 434, such as e.g. ashing, wet chemistry based stripping, or gentle polishing.
  • the method 300 may proceed with a process 312 that includes depositing a conductive, preferably superconductive, material on sidewalls and bottom of the openings provided in the substrate.
  • a process 312 that includes depositing a conductive, preferably superconductive, material on sidewalls and bottom of the openings provided in the substrate.
  • An exemplary result of the process 312 is illustrated with a quantum circuit assembly 412 shown in FIG. 4F, showing that the superconductive material 212 is provided as a conformal liner on the inner surfaces of the openings 438 in the substrate 204.
  • a liner of the superconductive material 212 may be deposited on sidewalls and bottom of the openings 438 in the process 312 using any suitable techniques for conformally depositing conductive materials onto selected surfaces, such as e.g. ALD, CVD, PECVD, or/and physical vapor deposition (PVD) processes such as e.g.
  • PVD physical vapor deposition
  • the superconductive liner 212 As a result of depositing the superconductive material 212 as a liner within the openings 438, the volume of the openings 438 is reduced but there still remain smaller openings, as indicated in FIG. 4F with smaller openings 440. Exemplary dimensions and materials for the superconductive liner 212 are described above with reference to FIG. 2.
  • the method 300 may proceed with a process 314 that includes filling the remaining empty volume of the lined openings 440 with a fill material.
  • An exemplary result of the process 314 is illustrated with a quantum circuit assembly 414 shown in FIG. 4G, showing that the openings 440 of the assembly 412 shown in the previous FIG. are now filled with the fill material 214.
  • Any suitable deposition techniques may be used to fill the openings 440 with the fill material 214 in the process 314, such as e.g. ALD, CVD, PECVD, PDV, electroplating, electroless deposition in combination with electroplating, spin-coating, or dip-coating. Exemplary materials used for the fill material 214 are described above with reference to FIG. 2.
  • the method 300 may include a process 316 in which the excess portions of the fill material are removed.
  • An exemplary result of the process 316 is illustrated with a quantum circuit assembly 416 shown in FIG. 4H, showing the excess portions 442 of the fill material 214 are removed so that the fill material fills the openings 440 but the upper portion of the fill material 214 is aligned with the upper portions of the superconductive liner 212, forming a continuous surface 444.
  • Any suitable techniques for removing an overburden of a material may be used to remove the excess portions 442 of the fill material 214 in the process 316, such as e.g. a CMP with an appropriate slurry, or chemical and plasma etches.
  • the method 300 may then proceed with a process 318 that includes depositing and possibly patterning a backside conductive, preferably superconductive, material over the upper surface of the assembly with filled TSV openings.
  • An exemplary result of the process 318 is illustrated with a quantum circuit assembly 418 shown in FIG. 41, showing that a layer of the electrically conductive, preferably superconductive material referred to in FIG. 2 as the second layer 218 is provided over the surface 444 of the assembly 416 of FIG. 4H.
  • Any suitable deposition and patterning techniques may be used to deposit and pattern the second layer 218 over the surface 444 in the process 318, such as e.g. exemplary deposition and patterning techniques described above. Exemplary dimensions and materials used for the second layer 218 are also described above, with reference to FIG. 2.
  • the method 300 may then proceed with a process 320 that includes turning the substrate 204 over, so that subsequent processing may be performed on the qubit side again.
  • An exemplary result of the process 320 is illustrated with a quantum circuit assembly 420 shown in FIG. 4J, showing that the etch-stop layer 432 provided over the face 206 of the substrate 204 is now again at the top of the assembly (as it was in the assembly 402 right after the deposition of the etch-stop layer 432) and the backside face 208 of the substrate 204 with the second layer 218 on it is facing down.
  • the method 300 may then proceed with a process 322 that includes removing the etch-stop layer.
  • FIG. 4K An exemplary result of the process 322 is illustrated with a quantum circuit assembly 422 shown in FIG. 4K, showing that the etch-stop layer 432 is removed, exposing the qubit side 206 of the substrate and the upper surfaces 446 of the superconductive liner 212 that was provided within the TSV openings.
  • Any conventional techniques for removing materials may be used in the process 322 to remove the etch-stop layer 432, such as e.g. etching, ashing or gentle polishing.
  • removing the etch-stop layer 432 covering the qubit side 206 of the substrate may include performing an etch using one or more etchants for which a rate of etching the etch-stop layer 432 is sufficiently higher than a rate of etching the substrate 204 and a rate of etching the superconductive liner 212 (i.e. the substrate 204 and the material of the superconductive liner 212 within the via opening are substantially etch-resistant when using the one or more etchants selected to remove the etch-stop layer 432).
  • the method 300 may then proceed with a process 324 that includes depositing and possibly patterning a qubit side conductive, preferably superconductive, material over the surface that was revealed as a result of removing the etch-stop layer.
  • An exemplary result of the process 324 is illustrated with a quantum circuit assembly 424 shown in FIG. 4L, showing that a layer of the electrically conductive, preferably superconductive material referred to in FIG. 2 as the first layer 216 is provided over the upper surface of the assembly 422 of FIG. 4K.
  • Any suitable deposition and patterning techniques may be used to deposit and pattern the first layer 216 in the process 324, such as e.g. exemplary deposition and patterning techniques described above. Exemplary dimensions and materials used for the first layer 216 are also described above, with reference to FIG. 2.
  • the method 300 may end with a process 326 in which one or more qubit devices are provided over the assembly with the first layer 216.
  • An exemplary result of the process 326 is illustrated with a quantum circuit assembly 426 shown in FIG. 4M, which is the same as the assembly 200 shown in FIG. 2.
  • Fabrication processes used to provide qubit devices 210 would depend on the type of the qubit device and are known in the art and, therefore, are not described here.
  • the method may further include a process in which the conductive/superconductive portions of the TSV are connected to the respective bias/signal sources - e.g. the superconductive liner 212 of the TSVs may be connected to a ground potential/bias or any other reference potential/bias. Such connections may be made in a plane at the bottom of the TSVs, in a plane at the top of the TSV, or as a combination.
  • Quantum circuit assemblies/structures incorporating TSVs as described above may be included in any kind of qubit devices or quantum processing devices/structures. Some examples of such devices/structures are illustrated in FIGS. 5A-5B, 6, and 7.
  • FIGS. 5A-5B are top views of a wafer 1100 and dies 1102 that may be formed from the wafer 1100, according to some embodiments of the present disclosure.
  • the dies 1102 may include any of the quantum circuit assemblies disclosed herein, e.g., quantum circuit assemblies comprising superconducting qubits, spin qubits, or any combination of various types of qubits, and may include any of the TSVs described herein, such as e.g. the TSVs shown in FIG. 2 (which may be implemented according to e.g. method shown in FIGS. 3A-3B), or any further embodiments of the TSVs as described herein.
  • the wafer 1100 may be any the form of the qubit substrates as described herein, and may further include one or more dies 1102 having conventional and quantum circuit device elements formed on a surface of the wafer 1100.
  • Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device.
  • the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product.
  • a die 1102 may include one or more quantum circuits with TSVs as described herein, such as e.g. quantum circuits such as the quantum circuit 100, as well as any other 1C components.
  • the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 2002 of FIG. 7) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • a memory device e.g., a static random access memory (SRAM) device
  • a logic device e.g., AND, OR, NAND, or NOR gate
  • FIG. 6 is a cross-sectional side view of a device assembly 1200 that may include any of the TSVs disclosed herein, such as e.g. the TSVs shown in FIG. 2 or any further embodiments of the TSVs as described herein.
  • the device assembly 1200 includes a number of components disposed on a circuit board 1202.
  • the device assembly 1200 may include components disposed on a first face 1240 of the circuit board 1202 and an opposing second face 1242 of the circuit board 1202; generally, components may be disposed on one or both faces 1240 and 1242.
  • the circuit board 1202 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1202.
  • the circuit board 1202 may be a package substrate or flexible board.
  • the 1C device assembly 1200 illustrated in FIG. 6 may include a package-on-interposer structure 1236 coupled to the first face 1240 of the circuit board 1202 by coupling components 1216.
  • the coupling components 1216 may electrically and mechanically couple the package-on- interposer structure 1236 to the circuit board 1202, and may include solder balls (as shown in FIG.
  • male and female portions of a socket an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
  • the package-on-interposer structure 1236 may include a package 1220 coupled to an interposer 1204 by coupling components 1218.
  • the coupling components 1218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1216. Although a single package 1220 is shown in FIG. 6, multiple packages may be coupled to the interposer 1204; indeed, additional interposers may be coupled to the interposer 1204.
  • the interposer 1204 may provide an intervening substrate used to bridge the circuit board 1202 and the package 1220.
  • the package 1220 may be a quantum circuit device package as described herein, e.g.
  • the package 1220 is a quantum circuit device package including at least one quantum circuit assembly with any of the TSVs described herein, the TSVs therein may be electrically connected to the interposer 1204 by the coupling components 1218.
  • the interposer 1204 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 1204 may couple the package 1220 (e.g., a die) to a ball grid array (BGA) of the coupling components 1216 for coupling to the circuit board 1202.
  • BGA ball grid array
  • the package 1220 and the circuit board 1202 are attached to opposing sides of the interposer 1204; in other embodiments, the package 1220 and the circuit board 1202 may be attached to a same side of the interposer 1204. In some embodiments, three or more components may be interconnected by way of the interposer 1204.
  • the interposer 1204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer 1204 may include metal interconnects 1208 and vias 1210, including but not limited to TSVs 1206, where each of TSVs 1206 may also be implemented as any TSVs described herein, such as e.g. the TSVs shown in FIG. 2 or any further embodiments of the TSVs as described herein.
  • the interposer 1204 may further include embedded devices 1214, including both passive and active devices.
  • embedded devices 1214 may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and
  • M EMS microelectromechanical systems
  • the device assembly 1200 may include a package 1224 coupled to the first face 1240 of the circuit board 1202 by coupling components 1222.
  • the coupling components 1222 may take the form of any of the embodiments discussed above with reference to the coupling components 1216
  • the package 1224 may take the form of any of the embodiments discussed above with reference to the package 1220.
  • the package 1224 may be a package including one or more quantum circuits with qubits as described herein or may be a conventional 1C package, for example. In some embodiments, the package 1224 may take the form of any of the embodiments of the quantum circuit with any of the quantum circuit assemblies described herein.
  • the device assembly 1200 illustrated in FIG. 6 includes a package-on-package structure 1234 coupled to the second face 1242 of the circuit board 1202 by coupling components 1228.
  • the package-on-package structure 1234 may include a package 1226 and a package 1232 coupled together by coupling components 1230 such that the package 1226 is disposed between the circuit board 1202 and the package 1232.
  • the coupling components 1228 and 1230 may take the form of any of the embodiments of the coupling components 1216 discussed above, and the packages 1226 and 1232 may take the form of any of the embodiments of the package 1220 discussed above.
  • Each of the packages 1226 and 1232 may be a qubit device package as described herein, e.g. by including the qubit substrates as described herein, or may be a conventional 1C package, for example.
  • FIG. 7 is a block diagram of an exemplary quantum computing device 2000 that may include any of the quantum circuit assemblies with TSVs as disclosed herein, such as e.g. the TSVs shown in FIG. 2 or any further embodiments of the TSVs as described herein.
  • a number of components are illustrated in FIG. 7 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application.
  • some or all of the components included in the quantum computing device 2000 may be attached to one or more PCBs (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with any of the quantum circuit assemblies described herein.
  • PCBs e.g., a motherboard
  • various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die.
  • the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 7, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components.
  • the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled.
  • the quantum computing device 2000 may not include an audio input device 2018 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2018 or audio output device 2008 may be coupled.
  • audio input or output device interface circuitry e.g., connectors and supporting circuitry
  • the quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices).
  • processing device e.g., one or more processing devices.
  • the term "processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices).
  • the quantum processing device 2026 may include one or more quantum circuit assemblies including any of the TSVs disclosed herein and quantum circuits with such TSVs, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuit assemblies with any of the TSVs disclosed herein, and monitoring the result of those operations. For example, as described above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of different qubits may be read.
  • the quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms.
  • the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc.
  • the quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.
  • the processing device 2002 may include a non-quantum processing device 2028.
  • the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026.
  • the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc.
  • the non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026.
  • the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed herein, the display device 2006 discussed herein, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components.
  • the non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
  • DSPs digital signal processors
  • ASICs application-specific ICs
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute cryptographic algorithms within hardware
  • server processors or any other suitable processing devices.
  • the quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid-state memory
  • solid-state memory solid-state memory
  • hard drive solid-state memory
  • the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004.
  • the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
  • eDRAM embedded dynamic random access memory
  • STT-MRAM spin transfer torque magnetic random access memory
  • the quantum computing device 2000 may include a cooling apparatus 2024.
  • the cooling apparatus 2024 may maintain the quantum processing device 2026, in particular the quantum circuits with any of the TSVs as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2026.
  • This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less.
  • the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature.
  • the cooling apparatus 2024 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.
  • the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips).
  • the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
  • IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for
  • Microwave Access which is a certification mark for products that pass conformity
  • the communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • HSPA High Speed Packet Access
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • the communication chip 2012 may operate in accordance with other wireless protocols in other embodiments.
  • the quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless
  • the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet).
  • the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless
  • a second communication chip 2012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
  • GPS global positioning system
  • EDGE EDGE
  • GPRS global positioning system
  • CDMA Code Division Multiple Access
  • WiMAX Long Term Evolution
  • LTE Long Term Evolution
  • EV-DO EV-DO
  • a first communication chip 2012 may be dedicated to wireless communications
  • a second communication chip 2012 may be dedicated to wired communications.
  • the quantum computing device 2000 may include battery/power circuitry 2014.
  • the battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).
  • the quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above).
  • the display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
  • LCD liquid crystal display
  • the quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above).
  • the audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
  • the quantum computing device 2000 may include an audio input device 2018 (or corresponding interface circuitry, as discussed above).
  • the audio input device 2018 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
  • MIDI musical instrument digital interface
  • the quantum computing device 2000 may include a GPS device 2016 (or corresponding interface circuitry, as discussed above).
  • the GPS device 2016 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.
  • the quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above).
  • Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
  • the quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above).
  • Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • RFID radio frequency identification
  • the quantum computing device 2000 may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
  • a hand-held or mobile computing device e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.
  • PDA personal digital assistant
  • Example 1 provides a quantum circuit assembly that includes a substrate and one or more qubit devices provided over the substrate.
  • the substrate includes a first face, a second face opposite the first face, and a via opening extending between the first face and the second face.
  • the one or more qubit devices are provided over the first face (i.e. the first face is what is referred to herein as a "qubit side" of the substrate, and the second face is then referred to as a "backside").
  • the via opening includes a liner layer including a first material at the first face (i.e. at a portion of the via opening that is closest to the first face of the substrate and interfaces whatever material is provided on the first face of the substrate).
  • the via opening further includes a second material filling remaining empty volume of the via opening with said layer (i.e. the second materials is between the layer including the first material and where the second face of the substrate would be if it was not for the via opening removing such second face), where the first material is a superconductive material and is different from the second material.
  • Example 2 provides the quantum circuit assembly according to Example 1, where the layer including the first material extends to at least portions of one or more sidewalls of the via opening.
  • Example 3 provides the quantum circuit assembly according to any one of the preceding Examples, where the layer including the first material extends as a substantially continuous conformal liner on all sidewalls of the via opening and on the top/bottom part of the via opening that is closest to the first face.
  • Example 4 provides the quantum circuit assembly according to any one of the preceding Examples, where the layer including the first material has a thickness between about 1 and 1000 nm, including all values and ranges therein, e.g. between about 3 and 250 nm, or between about 5 and 100 nm.
  • Example 5 provides the quantum circuit assembly according to any one of the preceding Examples, where the via opening has an aspect ratio (i.e. a ratio between the height and the width of the via opening) greater than about 3, including all values and ranges therein, e.g. greater than about 5, or greater than about 9.
  • Example 6 provides the quantum circuit assembly according to any one of the preceding Examples, where the first material is a metal including titanium and nitrogen (e.g. TiN). In other embodiments, the first material could be one or more of other superconductive materials.
  • Example 7 provides the quantum circuit assembly according to any one of Examples 1-6, where the second material is an electrically conductive non-superconductive material, e.g. a metal including copper.
  • the second material could be any other electrically conductive, but not superconductive, material, such as e.g. one or more of indium, gold, silver, tin, solder, cadmium, palladium, zinc, rhodium.
  • the second material could be any non-superconductive, non-magnetic material that can be electroplated.
  • Example 8 provides the quantum circuit assembly according to any one of Examples 1-6, where the second material is a dielectric material, such as e.g. a polymer or a ceramic material.
  • Example 9 provides the quantum circuit assembly according to any one of the preceding Examples, further including a first layer including an electrically conductive, preferably
  • Example 10 provides the quantum circuit assembly according to Example 9, where the layer including the first material interfaces the first layer.
  • Example 11 provides the quantum circuit assembly according to Examples 9 or 10, where the first layer has a thickness between about 1 and 5000 nm, including all values and ranges therein, e.g. between about 25 and 1000 nm, or between about 50 and 500 nm.
  • Example 12 provides the quantum circuit assembly according to any one of the preceding Examples, further including a second layer including an electrically conductive, preferably superconductive, material provided over the second face.
  • Example 13 provides the quantum circuit assembly according to Example 12, where the second material within the via opening interfaces the second layer.
  • Example 14 provides the quantum circuit assembly according to Examples 12 or 13, where the second layer has a thickness between about 1 and 5000 nm, including all values and ranges therein, e.g. between about 25 and 1000 nm, or between about 50 and 500 nm.
  • Example 15 provides a quantum 1C package that includes a qubit die and a further 1C element.
  • the qubit die includes a substrate including a first face, a second face opposite the first face, and a via opening extending between the first face and the second face, and one or more qubit devices provided over the first face, where the via opening includes a liner layer including a first material at the first face, the first material being a superconductive material, and where the via opening further includes a second material, different from the first material, between the layer including the first material and the second face.
  • the further 1C element is coupled to the qubit die by an interconnect between the further 1C element and the first or second materials of the via opening extending to the second face of the substrate of the qubit die.
  • Example 16 provides the quantum 1C package according to Example 15, where the further 1C element is one of an interposer, a circuit board, a flexible board, or a package substrate.
  • Example 17 provides the quantum 1C package according to Examples 15 or 16, where the one or more qubits include a plurality of superconducting qubits and at least of a first and a second of the plurality of superconducting qubits are coupled by a coupling resonator.
  • Example 18 provides a method of fabricating a quantum circuit assembly.
  • the method includes providing a layer of a cover material over a first face of a substrate, the substrate further having a second face opposite the first face; providing, over the second face of the substrate, a mask defining a location of a via opening to be formed in the substrate; forming a via opening from the second face to the cover material at the first face using the mask; depositing a layer of a first material on sidewalls and bottom of the via opening, where the first material is an electrically conductive, preferably superconductive, material; filling the via opening having the layer of the first material with a second material, the second material different from the first material; removing the cover material from the first face of the substrate; and after removing the cover material, providing one or more qubit devices over the first face of the substrate.
  • Example 19 provides the method according to Example 18, where forming the via opening includes performing an etch using one or more etchants for which a rate of etching the substrate is much higher than a rate of etching the cover material (i.e. the cover material is substantially etch- resistant when using the one or more etchants selected to etch the substrate).
  • Example 20 provides the method according to Examples 18 or 19, further including removing the mask prior to depositing the layer of the first material on the sidewalls and the bottom of the via opening.
  • Example 21 provides the method according to any one of Examples 18-20, where depositing the layer of the first material includes performing ALD to conformally deposit the first material on the sidewalls and the bottom of the via opening.
  • Example 22 provides the method according to any one of Examples 18-21, where filling the via opening with the second material includes depositing the second material within the via opening using electroplating, electroless deposition in combination with electroplating, spin-coating, or dip coating.
  • Example 23 provides the method according to any one of Examples 18-22, further including removing excess of the second material to expose the second face of the substrate, e.g. using CMP with an appropriate slurry, or using chemical and plasma etches.
  • Example 24 provides the method according to any one of Examples 18-23, where removing the cover material includes performing an etch using one or more etchants for which a rate of etching the cover material is much higher than a rate of etching the substrate and a rate of etching the first material (i.e. the substrate and the first material within the via opening are substantially etch-resistant when using the one or more etchants selected to remove the cover material).
  • Example 25 provides the method according to any one of Examples 18-24, further including, after filling the via opening with the second material, providing a layer of an electrically conductive, preferably superconductive, material over the second face of the substrate.
  • such a layer may have a thickness between about 1 and 5000 nm, including all values and ranges therein, e.g. between about 25 and 1000 nm, or between about 50 and 500 nm.
  • Example 26 provides the method according to any one of Examples 18-25, further including, after removing the cover material, providing a layer of an electrically conductive, preferably superconductive, material over the first face of the substrate, where at least portions of the one or more qubit devices are provided over said layer of conductive material over the first face of the substrate.
  • a layer may have a thickness between about 1 and 5000 nm, including all values and ranges therein, e.g. between about 25 and 1000 nm, or between about 50 and 500 nm.
  • Example 27 provides a quantum computing device that includes a quantum processing device that includes a plurality of qubits included in one or more quantum circuit assemblies according to any one of Examples 1-14 or/and one or more quantum 1C packages according to any one of Examples 15-17; and a memory device configured to store data generated by the plurality of qubits during operation of the quantum processing device.
  • Example 28 provides the quantum computing device according to Example 27, further including a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
  • Example 29 provides the quantum computing device according to Examples 27 or 28, where the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
  • Example 30 provides the quantum computing device according to any one of Examples 27- 29, further including a non-quantum processing device coupled to the quantum processing device.

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Abstract

Des modes de réalisation de la présente invention proposent une approche pour intégrer des TSV dans des substrats sur lesquels des circuits quantiques sont construits. L'approche est basée sur la fourniture d'une couche d'arrêt de gravure sur le côté bit quantique d'un substrat, afin de protéger le côté bit quantique, et la réalisation du traitement nécessaire pour former les TSV à partir de la face arrière du substrat. A savoir, une gravure est effectuée sur la face arrière du substrat pour former des ouvertures de trou d'interconnexion s'étendant à travers le substrat et s'arrêtant au niveau de la couche d'arrêt de gravure, et, après la gravure, un matériau supraconducteur est déposé de manière conforme dans les ouvertures, recouvrant ainsi les parois latérales des ouvertures et supporté au fond des ouvertures par la couche d'arrêt de gravure. Le volume restant des ouvertures peut ensuite être rempli d'un matériau de remplissage. Après cela, la couche d'arrêt de gravure peut être retirée et des dispositifs quantiques peuvent être prévus sur le côté bit quantique du substrat.
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