WO2019117972A1 - Ligne de transmission verticale de bits quantiques avec des trous d'interconnexion de masse entourant une ligne de signal - Google Patents

Ligne de transmission verticale de bits quantiques avec des trous d'interconnexion de masse entourant une ligne de signal Download PDF

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WO2019117972A1
WO2019117972A1 PCT/US2017/066888 US2017066888W WO2019117972A1 WO 2019117972 A1 WO2019117972 A1 WO 2019117972A1 US 2017066888 W US2017066888 W US 2017066888W WO 2019117972 A1 WO2019117972 A1 WO 2019117972A1
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signal line
quantum
vertical transmission
qubit
substrate
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PCT/US2017/066888
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English (en)
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Hubert C. GEORGE
James S. Clarke
Ravi Pillarisetty
Zachary R. YOSCOVITS
Nicole K. THOMAS
Jeanette M. Roberts
Roman CAUDILLO
Kanwaljit SINGH
David J. Michalak
Lester LAMPERT
Adel A. ELSHERBINI
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Intel Corporation
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Priority to PCT/US2017/066888 priority Critical patent/WO2019117972A1/fr
Publication of WO2019117972A1 publication Critical patent/WO2019117972A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/413—Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53285—Conductive materials containing superconducting materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
    • H01P5/022—Transitions between lines of the same kind and shape, but with different dimensions
    • H01P5/028—Transitions between lines of the same kind and shape, but with different dimensions between strip lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/805—Constructional details for Josephson-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66977—Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/7613—Single electron transistors; Coulomb blockade devices

Definitions

  • This disclosure relates generally to the field of quantum computing, and more specifically, to vertical transmission line structures for use in quantum circuit assemblies and to methods of fabrication thereof.
  • Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.
  • Quantum computers use so-called quantum bits, referred to as qubits (both terms “bits” and “qubits” often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states - a uniquely quantum-mechanical phenomenon.
  • Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.
  • FIGS. 1A-1E illustrate various quantum circuit assemblies with vertical transmission lines in accordance with various embodiments of the present disclosure.
  • FIG. 2 is a flow diagram of an illustrative method of manufacturing a vertical transmission line in accordance with various embodiments of the present disclosure.
  • FIGS. 3A-3E illustrate various stages in the manufacture of a vertical transmission line using the method shown in FIG. 2 in accordance with some embodiments of the present disclosure.
  • FIGS. 4A-4D illustrate coupling of other quantum circuit components to a vertical transmission line in accordance with various embodiments of the present disclosure.
  • FIGS. 5A and 5B are top views of a wafer and dies that may include one or more quantum circuit assemblies with vertical transmission lines in accordance with various embodiments of the present disclosure.
  • FIG. 6 is a cross-sectional side view of a device assembly that may include one or more quantum circuit assemblies with vertical transmission lines in accordance with various embodiments of the present disclosure.
  • FIG. 7 is a block diagram of an example quantum computing device that may include one or more quantum circuit assemblies with vertical transmission lines in accordance with various embodiments of the present disclosure.
  • quantum computing or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data.
  • quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states.
  • Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole.
  • quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).
  • transitions include transitions (e.g., spin qubits and charge qubits), photon polarization qubits, single trapped ion qubits, etc.
  • quantum dots e.g., spin qubits and charge qubits
  • photon polarization qubits single trapped ion qubits, etc.
  • Quantum circuits based on various physical systems for implementing qubits use microwaves to control the qubits, for example to initialize, manipulate (e.g. couple), and readout the qubits.
  • the microwaves are generally delivered and supported using transmission line structures.
  • microwave transmission lines used in quantum circuits can be either resonant (sometimes referred to as “resonators”) or non-resonant, sometimes referred to, together, as "microwave elements.”
  • resonators sometimes referred to as "resonators”
  • microwave elements In order to provide substantially lossless connectivity to, from, and between the qubits, electrically conductive portions of such microwave elements are typically made from
  • microwave transmission lines in quantum circuits have been implemented as coplanar waveguides (CPWs) provided in the plane of qubits, i.e. horizontally.
  • CPWs coplanar waveguides
  • Embodiments of the present disclosure propose a new transmission line structure for use as resonators, as well as for use as non-resonant transmission line interconnects, in quantum circuits. Fabrication techniques for forming such a structure are also disclosed.
  • a proposed quantum circuit assembly includes at least one qubit provided over or at least partially in a qubit substrate, and a vertical transmission line for providing microwave connectivity for said at least one qubit.
  • the vertical transmission line includes a signal line and a ground structure, where the signal line is an electrically conductive, preferably superconductive, elongated element provided substantially perpendicular to the plane of the substrate and where at least a portion of the ground structure includes a plurality of electrically conductive, preferably superconductive, ground vias surrounding the signal line along at least a portion of a length of the signal line and separated from the signal line by a gap (i.e. an opening which may include vacuum, air, or some other gas or combination of gasses).
  • a gap i.e. an opening which may include vacuum, air, or some other gas or combination of gasses.
  • such vertical transmission lines may keep losses which lead to qubit decoherence sufficiently low due to the presence of the gap, e.g. a substantially vacuum gap, an air gap, or a gap filled with some other gas or combination of gasses, between the ground structure and the signal line.
  • the gap e.g. a substantially vacuum gap, an air gap, or a gap filled with some other gas or combination of gasses
  • presence of an open gap between the signal line and the ground structure of a vertical transmission line may allow reducing spurious (i.e. unintentional and undesirable) two-level systems (TLSs), thought to be a dominant source of qubit decoherence, where, in general, as used in quantum mechanics, a two-level (also referred to as "two-state”) system is a system that can exist in any quantum superposition of two independent and physically distinguishable quantum states.
  • transmission line structures with surrounding ground vias as proposed herein could be used for providing microwave connectivity to, from, or/and between the qubits, or to set the frequencies that address individual qubits, and may be implemented as non-resonant or resonant transmission lines.
  • some or all of the electrically conductive portions of qubit devices/assemblies proposed herein may be made from one or more superconductive materials.
  • some or all of these electrically conductive portions could be made from electrically conductive materials which are not superconductive.
  • reference to an electrically conductive material implies that a superconductive material can be used, and vice versa.
  • materials described herein as "superconductive materials” may refer to materials, including alloys of materials, which exhibit superconducting behavior at typical qubit operating conditions (e.g.
  • materials which exhibit superconducting behavior at very low temperatures at which qubits typically operate but which may or may not exhibit such behavior at higher temperatures (e.g. at room temperatures).
  • examples of such materials include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), niobium titanium nitride (NbTiN), indium (In), and molybdenum rhenium (MoRe), all of which are particular types of superconductors at qubit operating temperatures, as well as their alloys.
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
  • the notation “A/B/C” means (A), (B), and/or (C).
  • the terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are typically operated at.
  • techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-30 GFIz, e.g. in 3-10 GFIz range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering.
  • qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.
  • a quantum circuit may be viewed as comprising a plurality of qubits and a plurality of transmission lines for providing microwave connectivity to, from, and between the qubits.
  • the qubits may be implemented as any of the suitable qubits, such as e.g. superconducting qubits (e.g. transmons), quantum dot qubits, etc.
  • Various transmission lines may be either resonant or non-resonant, as explained in the following paragraphs.
  • Substantially non-resonant transmission lines may be used in quantum circuits for providing microwave signals to different quantum circuit elements and components, such as e.g. various control lines for various qubits.
  • examples of the non resonant transmission lines include flux bias lines, microwave lines (also sometimes referred to as "microwave feed lines"), and drive lines.
  • examples of the non-resonant transmission lines include lines that may control microwave pulses applied to gates and/or the doped regions of quantum dot device(s) in order to control spins of charge carriers in quantum dots formed in such device(s) or microwave pulses transmitted over a conductive pathway to induce a magnetic field in magnet line(s) of quantum dot devices.
  • the quantum circuit may also include a plurality of resonant transmission lines, which are resonant microwave elements commonly referred to as "resonators" (e.g. coupling and readout resonators used in quantum circuits which employ superconducting qubits).
  • resonators e.g. coupling and readout resonators used in quantum circuits which employ superconducting qubits.
  • a resonator of a quantum circuit differs from a non-resonant microwave transmission line in that a resonator is deliberately designed to support resonant oscillations (i.e. resonance) within the line, under certain conditions.
  • non-resonant transmission lines may be similar to conventional microwave transmission lines in that they are designed to avoid resonances, especially resonances at frequencies/wavelengths close to the resonant
  • any resonant object used in the quantum computing circuits e.g., qubits, bus resonators, or readout resonators in the proximity of such non-resonant lines.
  • resonant transmission lines may inadvertently support some resonances, but, during its design, efforts are taken to minimize resonances, standing waves, and reflected signals as much as possible, so that all of the signals can be transmitted through these lines without, or with as little resonance as possible.
  • a resonator is a transmission line segment that is made by employing fixed boundary conditions, and these boundary conditions control the frequencies/wavelengths which will resonate within a given transmission line segment used to implement a resonator.
  • each end of a transmission line segment resonator can be either a node, if it is shorted to ground (e.g. where one end of the transmission line segment structure is electrically connected to a ground plane), or an antinode, if it is capacitively or inductively coupled to ground or to another quantum circuit element.
  • resonators differ from non-resonant microwave transmission lines in how these lines are terminated at the relevant ends.
  • a line used to route a signal on a substrate i.e.
  • one of the non-resonant transmission lines typically extends from a specific source, e.g. a bonding pad or another type of electrical connection to a source, to a specific load (e.g. a short circuit proximate to a superconducting quantum interference device (SQUID) loop, a quantum dot device, another bonding pad, or another electrical connection to a load).
  • a specific source e.g. a bonding pad or another type of electrical connection to a source
  • a specific load e.g. a short circuit proximate to a superconducting quantum interference device (SQUID) loop, a quantum dot device, another bonding pad, or another electrical connection to a load.
  • SQUID superconducting quantum interference device
  • a resonator is typically composed of a piece of transmission line terminated with either two open circuits (in case of a half-wavelength resonator) or an open and a short circuit (in case of a quarter-wavelength resonator
  • transmission line length may e.g. be a multiple of a microwave wavelength divided by 2 or 4, respectively.
  • other terminations are possible, for example capacitive or inductive, and in this case the required line length to support resonance will be different from that identified above.
  • capacitive terminations may be used for resonators which are coupled to qubits, to a feedline, line, or to another resonator by a capacitive interaction.
  • transmission line segments of the resonators need to be of a specific length that can support such oscillations. That is why, often times, resonators may be laid out on a substrate longer than the actual distance would require (i.e. a non-resonant transmission line would typically be laid out to cover the distance in the most compact manner possible, e.g. without any curves, wiggles, or excess length, while a resonator may need to have curves, wiggles, and be longer than the shortest distance between the two elements the resonator is supposed to couple in order to be sufficiently long to support resonance).
  • a coupling resonator may be implemented as a microwave transmission line segment that includes capacitive or inductive connections to ground on both sides (e.g.
  • each side of a coupling resonator is coupled, either capacitively or inductively, to a respective (i.e. different) qubit by being in the appropriate location and sufficient proximity to the qubit. Because different regions of a coupling resonator have coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator.
  • coupling resonators may be employed for implementing logic gates.
  • resonators used with superconducting qubits are so-called readout resonators, which may be used to read the state(s) of qubits.
  • readout resonators may be used to read the state(s) of qubits.
  • a readout resonator similar to the bus coupling resonator, is a transmission line segment. On one end it may have an open circuit connection to ground as well as any capacitively or inductively coupled connections to other quantum elements or a non-resonant microwave feedline. On the other end, a readout resonator may either have a capacitive connection to ground (for a half-wavelength resonator) or may have a short circuit to the ground (for a quarter-wavelength resonator), which also results in oscillations within the transmission line, with the resonant frequency of the oscillations being close to the frequency of the qubit.
  • a readout resonator is coupled to a qubit by being in the appropriate location and sufficient proximity to the qubit, again, either through capacitive or inductive coupling. Due to a coupling between a readout resonator and a qubit, changes in the state of the qubit result in changes of the resonant frequency of the readout resonator. In turn, changes in the resonant frequency of the readout resonator can be read externally via connections which lead to external electronics e.g. wire or solder bonding pads.
  • Coupling resonators and readout resonators, as well as non-resonant transmission lines may be considered as being included within a broad category of interconnects for supporting propagation of microwave signals in a quantum circuit.
  • any other connections for providing microwave or other electrical signals to different quantum circuit elements and components such as e.g. connections between electrodes of various circuit components, or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, are also referred to herein as interconnects.
  • interconnect may also be used to refer to elements providing electrical interconnections to/from/between quantum circuit elements and components and non-quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit.
  • non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog to digital converters, mixers, multiplexers, amplifiers, etc.
  • the interconnects included in a quantum circuit could have different shapes and layouts.
  • the term "line" as used herein in context of signal lines or transmission lines does not imply straight lines, unless specifically stated so.
  • some transmission lines or parts thereof e.g. signal line portions of transmission lines
  • some transmission lines or parts thereof may comprise substantially straight lines.
  • various interconnects may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using e.g. a bridge, bridging one interconnect over the other.
  • materials forming the vertical transmission lines described herein may include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), and/or niobium titanium nitride (NbTiN), all of which are particular types of superconductors, as well as their alloys. However, in various embodiments, other suitable superconductors as well as non superconducting conductors may be used as well.
  • quantum circuits such as the one described above may be used to implement components associated with a quantum integrated circuit (1C).
  • Such components may include those that are mounted on or embedded in a quantum 1C, or those connected to a quantum 1C.
  • the quantum 1C may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the integrated circuit.
  • the integrated circuit may be employed as part of a chipset for executing one or more related functions in a quantum system.
  • some or all of the non-resonant transmission lines and some or all of the resonators (if present) of a quantum circuit as described above, as well as, optionally, some or all of other microwave interconnects in a quantum circuit, may be implemented in the form of vertical transmission line structures as described herein.
  • FIGS. 1A-1E illustrate various quantum circuit assemblies with vertical transmission lines in accordance with various embodiments of the present disclosure.
  • Some of the elements referred in the description of FIGS. 1A-1E with reference numerals are indicated in FIGS. 1A-1E with different patterns, with a legend showing the correspondence between the reference numerals and patterns being provided at the bottom of each of FIGS. 1A-1E, and are not labeled in FIGS. 1A-1E with arrows pointing to them in order to not clutter the drawings.
  • the legend illustrates that FIG.
  • 1A uses different patterns to show a signal line 102, a ground structure 104, a substrate 108, etc., etc.
  • a quantum circuit assembly 100A illustrates a vertical transmission line 101A which includes a signal line 102 and a ground structure 104 at least partially surrounding the signal line 102 and separated from the signal line 102 by a gap 105.
  • the quantum circuit assembly 100A as well as those of FIGS. 1B-1E, provide only cross-sectional side-view illustrations in the y-z plane of the x-y-z coordinate system shown in these FIGS because those clearly illustrate the vertical nature of the transmission line 101A.
  • the fact that the ground structure 104 surrounds the signal line 102 is better illustrated in a top-view (i.e. an x-y plane), as e.g. shown in FIG. 3E.
  • the outer sidewalls of the vertical transmission line 101A may be surrounded by a dielectric material 106, which is preferably a substantially lossless or a low-loss dielectric, such as e.g. epitaxially grown silicon, preferably substantially intrinsic (and, hence, high resistivity) silicon, or any other highly crystalline dielectric material with as little defects as possible because such materials are believed to be low-loss in terms of TLS's.
  • the layer of the dielectric material 106 may be provided over a substrate 108 which may serve as a foundation for fabricating a quantum circuit with plurality of qubits and various interconnects, including the vertical transmission lines as described herein.
  • the substrate 108 may be a bulk silicon substrate. In other embodiments, the substrate 108 may be formed using alternative materials, which may or may not be combined with silicon, and which may include, but are not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide. Further materials classified as group ll-VI, lll-V, or IV semiconductor materials may also be used as the substrate 108.
  • FIG. 1A further schematically illustrates a metallization stack 110 which may, optionally, be present below the low-loss dielectric layer 106 in order to electrically connect the signal line 102 and the ground structure 104 of the vertical transmission line 101A to respective contacts. Details of how metallization stacks are implemented are known in the art and, therefore, are not described in detail here.
  • the dielectric 106 may be used as a foundation for providing a plurality of qubits thereon, illustrated in the example of FIG. 1A with a qubit device/circuit 112. Details of the qubit 112 are not specifically shown in FIG. 1A because the configuration and layout of the qubit 112 would depend on the type of qubit(s) being implemented in a given quantum circuit assembly. For example, out of the various physical implementations of qubits listed above, superconducting qubits are promising candidates for building a quantum computer, and if superconducting qubits are implemented, then the qubit 112 would be a superconducting qubit that includes one or more Josephson Junctions.
  • junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits.
  • a Josephson Junction includes two superconductors coupled by a so-called weak link that weakens the superconductivity between the two superconductors.
  • a weak link of a Josephson Junction may e.g.
  • the Josephson Junction provides a non-linear inductive element to the circuit and allows the qubit to become an anharmonic oscillator.
  • the anharmonicity is determined by the ratio of the charging energy, which stems from the total capacitance between various
  • the anharmonicity is what allows the state of the qubit to be controlled to a high level of fidelity.
  • the charging and Josephson energies also control the qubit frequency.
  • Resonators used to couple qubits together and to set qubit frequencies are another type of integral building blocks in superconducting quantum circuits.
  • Resonators and non-resonant transmission lines may be considered as examples of "supporting circuitry" for qubits.
  • other portions of supporting circuitry may be provided substantially horizontally (i.e. parallel to a substrate), as is e.g. shown in FIG. 1A with an electrically conductive element 114, provided over the dielectric layer 106 and extending between the qubit 112 and the signal line 102 of (i.e. electrically connected to) the vertical transmission line 101A.
  • the former supporting circuitry elements may be collectively referred to as "qubit supporting circuitry,” examples of which include shunt capacitors, superconducting loops of a SQUID, etc.
  • the latter supporting circuitry elements may be collectively referred to herein as "chip supporting circuitry,” examples of which include resonators, but also non-resonant transmission lines such as e.g. flux bias lines, microwave lines, etc.
  • the conductive element 114 is an example of the chip supporting circuitry, in particular, a portion of a qubit resonator, because it is shown in FIG. 1A to not to be in contact with the qubit 112.
  • a qubit resonator includes a vertical portion implemented as the vertical transmission line 101A, and a horizontal portion implemented as the conductive element 114 provided substantially horizontally, and dimensions/geometry of both of these portions are carefully designed to support desired resonant behavior.
  • the conductive element 114 could be directly electrically connected to a portion of the qubit 112.
  • the signal line 102, the ground structure 104, the electrically conductive elements 114 or/and 122 may include, or be made of, any conductive or superconductive material suitable for providing electrical connectivity in a quantum circuit, such as e.g. any one or more of the exemplary superconductive materials described above.
  • the quantum circuit assembly 100A may include additional vertical transmission lines in order to route, during operation of a quantum circuit with the qubit devices 112, electrical signals such as e.g. power, input/output (I/O) signals, including various control signals for external and internal control of the qubits.
  • electrical signals such as e.g. power, input/output (I/O) signals, including various control signals for external and internal control of the qubits.
  • FIGS. such as e.g. FIG. 1A does not explicitly illustrate to which elements the ground structure is connected, this is done only in order to not clutter the drawings as ways for connecting ground structures to ground potentials are well known in the art, all of which being within the scope of the present disclosure for the vertical transmission lines described herein.
  • FIG. IB illustrates a quantum circuit assembly 100B with the vertical transmission line 101B similar to the vertical transmission line 101A described with reference to FIG. 1A. Therefore, in the interests of brevity, descriptions of the vertical transmission line 101A are not repeated for the vertical transmission line 101B and only differences are described.
  • the vertical transmission line 101B of the quantum circuit assembly 100B extends all the way through the substrate 108 (i.e. the vertical transmission line 101B extends between the two opposing faces/surfaces of the substrate 108) and is connected to a packaging substrate 115 via first level interconnects 116.
  • the first level interconnects 116 couple conductive contacts 118 at a first face 119 of the qubit substrate 108 and conductive contacts 120 at the opposing face of the package substrate 115, labeled in FIG. IB as a face 121.
  • FIG. IB schematically illustrates that the first level interconnects 115 are implemented as solder bumps or balls (shown in FIG.
  • first level interconnects 116 may be flip chip (or controlled collapse chip connection, "C4") bumps disposed initially on the qubit substrate 108 or on the package substrate 115.
  • C4 controlled collapse chip connection
  • other types of first level interconnects may be used as well and are within the scope of the present disclosure.
  • connections are made for various conductive contacts on a qubit substrate and on a package substrate is well-known in the art of packaging and, therefore, in the interests of brevity, not described here in detail.
  • connections are made by providing a metallization stack similar to the metallization stack 110 shown in FIG. 1A on, or as a part of, the first face 121 of the package substrate 115, as is shown in the example of FIG. IB.
  • the length of the vertical transmission line 101B (i.e. a dimension measured along the z-axis of the coordinate system shown in FIGS. 1A-1E) may be longer than that of the vertical transmission line 101A.
  • the length of the vertical transmission line 101A may be between about 30 nanometers (nm) and 3 micrometers (um), including all values and ranges therein, e.g.
  • the transmission line 101B may be between about 300 um and 800 um, including all values and ranges therein, e.g. between about 400 um and 700 um, or between about 450 um and 600 um. Other differences may include that the transmission line 101B may be similar to through-silicon-via (TSV) structures (since it extends through the substrate) but with a coaxial-like profile.
  • TSV through-silicon-via
  • FIG. 1C illustrates a quantum circuit assembly 100C with a vertical transmission line 101C, which interconnect is also similar to the vertical transmission line 101A described with reference to FIG. 1A. Therefore, in the interests of brevity, descriptions of the vertical transmission line 101A are not repeated for the vertical transmission line 101C and only differences are described.
  • the vertical transmission line 101C of the quantum circuit assembly 100C extends upwards, above the plane of the qubit 112.
  • the dielectric material 106 may surround not all but only a part of the vertical transmission line 101, and a connection between the signal line 102 and the electrically conductive element 114 of the supporting circuitry for the qubit 112 may be made at the bottom of the signal line 102, as illustrated in FIG. 1C. While FIG.
  • FIG. 1C illustrates that the qubit 112 is provided directly over the substrate 108, in other embodiments, an intermediate layer of the low-loss dielectric such as the dielectric 106 described above, may be present so that the qubit 112 would be provided over the low-loss dielectric as described with reference to FIG. 1A.
  • FIG. 1C further illustrates an electrically conductive element 122 connected to the signal line 102, for providing electrical connectivity to the vertical transmission line 101C.
  • the length of the vertical transmission line 101C (again, a dimension measured along the z-axis of the coordinate system shown in FIGS. 1A-1E) may, but does not have to, be shorter than that of the vertical transmission line 101A.
  • the length of the vertical transmission line 101C may be between about 30 nm and 1 um, including all values and ranges therein, e.g. between about 50 nm and 600 nm, or between about 100 nm and 300 nm. In other embodiments, the length of the vertical transmission line 101C may extend to larger values, e.g.
  • the vertical transmission line 101C may be used in so-called flip-chip packages where the qubit die (i.e. a substrate on which the qubits are provided, in this case - the quantum circuit assembly 100C) is flipped upside down to connect to a packaging substrate so that the side of the qubit die on which the qubits are implemented is facing the packaging substrate.
  • the qubit die i.e. a substrate on which the qubits are provided, in this case - the quantum circuit assembly 100C
  • FIG. ID illustrates an arrangement where a vertical transmission line 101D extends above the plane of the qubit 112, similar to that of FIG. 1C, but this time, instead of having the conductive element 122 in plane of the upper end of the vertical transmission line 101D, electrical connection to further elements above (not specifically shown in FIG. ID) is provided using a ball grid array (BGA) 124.
  • BGA ball grid array
  • vertical transmission lines as described herein can provide electrical connectivity for one or more of the qubits, e.g. for one or more of the qubits 112, by virtue of having the signal line 102 of any vertical transmission line as described herein, such as e.g. the vertical transmission lines 101A-101E, being electrically connected to a conductive circuit element of supporting circuitry as represented in FIGS. 1A-1E with the electrically conductive element 114.
  • vertical transmission lines as described herein can provide electrical connectivity for one or more of the qubits, e.g. for one or more of the qubits 112, by virtue of having the signal line 102 of any vertical transmission line as described herein, such as e.g.
  • the vertical transmission lines 101A-101E being in the vicinity of the qubit 112 so that the electric fields from the vertical transmission line extend and influence the qubit 112 (i.e. the electrically conductive element 114 shown in FIGS. 1A-1E may be absent and a portion of the signal line 102 of the vertical transmission line 101 may be capacitively or inductively coupled to at least a portion of the qubit 112), e.g. when the vertical transmission line 101 is a resonator.
  • FIG. 4C shows a portion of a qubit device overlapping with a portion of the signal line of a resonator implemented as a vertical transmission line.
  • vertical transmission lines as described herein allow reducing dimensions of resonators in the plane of the substrate because the resonators can extend in a direction perpendicular to the substrate, advantageously reducing the chip area required for implementing such resonators, reducing the cost of the quantum circuit device, and enabling scaling quantum circuits to larger numbers of interconnected qubits.
  • Placing two or more vertical transmission lines as described herein in series with one another may be particularly suitable for reducing the dimensions of resonators in the plane of the substrate, as e.g. shown in FIG.
  • FIG. IE showing two vertical transmission lines 101E connected in series with an electrically conductive element 122.
  • FIG. IE illustrates an arrangement similar to that of FIG. 1C, where the vertical transmission line extends above the plane of the qubit 112, but in other embodiments two or more vertical transmission lines could similarly be arranged in series when the qubit 112 is in the upper plane as e.g. was shown in FIG. 1A or FIG. IB. Therefore, corresponding descriptions of FIGS. 1A-1C are applicable to FIG. IE and not repeated here.
  • Vertical transmission lines as described herein such as e.g. the vertical transmission lines 101A, 101B, 101C, 101D, or 101E in the quantum circuit assemblies shown in FIGS. 1A-1E, may be fabricated using various suitable techniques, all of which being within the scope of the present disclosure.
  • One such exemplary technique is shown in FIG. 2 and described below.
  • FIG. 2 is a flow diagram of an illustrative method 200 of manufacturing a vertical transmission line, e.g. any of the vertical transmission lines 101A, 101B, 101C, 101D, or 101E in accordance with various embodiments of the present disclosure.
  • Device assemblies in various example stages during the manufacture using the method 200 are illustrated in FIGS. 3A-3E, in accordance with some embodiments of the present disclosure.
  • each of FIGS. 3A-3E illustrates a cross-sectional view (the upper illustration in each of FIGS. 3A-3E) and a top view (the lower illustration in each of FIGS.
  • FIGS. 3A-3E are, respectively, a view in the z-y plane and a view in the x-y plane of the x-y-z coordinate system shown in FIGS. 3A-3E.
  • the lower illustration is a cross-section along the plane A-A of the upper illustration
  • the upper illustration is a cross-section of the respective assembly along the plane B-B of the lower illustration, where the planes A-A and B-B are shown in FIG. 3A and are applicable to each of FIGS. 3A-3E even though only shown for FIG. 3A in order to not clutter other drawings.
  • the planes A-A and B-B are shown in FIG.
  • FIGS. 3A-3E as dashed lines intended to illustrate planes which include those lines and are perpendicular to the plane of the drawings. Similar to FIGS. 1A-1E, a number of elements referred to in the description of FIGS. 3A-3E with reference numerals are indicated in these FIGS, with different patterns in order to not clutter the drawings, with a legend at the bottom of FIGS. 3A-3E showing the correspondence between the reference numerals and the patterns.
  • Various operations of the method 200 may be illustrated with reference to some exemplary embodiments discussed below, but the method 200 may be used to manufacture any suitable vertical transmission lines according to any embodiments of the present disclosure.
  • the operations of the method 200 are illustrated in FIG. 2 once each and in a particular order, the operations may be performed in any suitable order and repeated as desired.
  • one or more operations may be performed in parallel to manufacture multiple vertical transmission lines as described herein substantially simultaneously.
  • the operations may be performed in a different order to reflect the architecture of a particular quantum circuit component that may include one or more vertical transmission lines according to any of the embodiments of the present disclosure.
  • the manufacturing method 200 may include other operations, not specifically shown in FIG. 2, such as e.g. various cleaning and/or planarization operations as known in the art.
  • the substrate 108 and/or the dielectric layer 106 over the substrate 108 may be cleaned prior to or/and after any of the processes of providing the vertical transmission line as described herein, e.g. to remove oxide, surface-bound organic and metallic contaminants, as well as subsurface contamination.
  • cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using hydrofluoric acid (HF)).
  • a chemical solutions such as peroxide
  • UV radiation ultraviolet
  • oxidizing the surface e.g., using thermal oxidation
  • removing the oxide e.g. using hydrofluoric acid (HF)
  • the quantum circuit assemblies as described herein may be planarized prior to or/and after any of the processes of providing the vertical transmission line as described herein, e.g. to remove the overburden of the materials deposited on the surfaces and to expose certain underlying elements.
  • planarization may be carried out using a polishing process such as e.g. chemical mechanical planarization (CMP), using a suitable slurry formulation and mechanical polishing process to remove unwanted materials from a wafer/structure, achieving a relatively smooth upper surface upon which further components of the quantum circuit assembly may be built.
  • CMP chemical mechanical planarization
  • the method 200 may begin with a process 202 that includes providing an opening in a layer that may be referred to as an "interconnect support layer" because such a layer forms basis for fabricating a vertical transmission line therein.
  • the opening is provided in a location within the interconnect support layer where a vertical transmission line according to various embodiments of the present disclosure is to be implemented.
  • An exemplary result of the process 202 is illustrated with a quantum circuit assembly 302 shown in FIG. 3A, showing an opening 321 formed in an interconnect support layer 322 over a substrate 320.
  • the substrate 320 may be a substrate 108 described above (possibly with a metallization layer in its' upper part, or over it, as shown in FIG. 1A but not specifically shown in the substrate 320), and the interconnect support layer 322 may be an upper portion of a substrate or a dielectric layer provided over a substrate (such as e.g. the low-loss dielectric layer 106 described above , e.g. a highly crystalline dielectric material such as e.g. epitaxially deposited silicon).
  • such the opening 321 may be created in the process 202 using any suitable technique for removing desired portions of various materials, e.g. dry etch (e.g. reactive ion etch (RIE)) or wet etch, possibly in combination with any suitable patterning technique, e.g.
  • dry etch e.g. reactive ion etch (RIE)
  • wet etch e.g. wet etch
  • Opening 321 dimensions of the opening 321 would be such as to include a vertical transmission line therein, dimensions of which vertical transmission lines described in greater detail below.
  • FIG. 3A illustrates the opening 321 as having a circular cross-section in the x-y plane, i.e. the opening 321 is a cylindrical opening
  • the opening 321 may take on any other 3D shapes, described in greater detail below with reference to the vertical transmission line shown in FIG. 3E.
  • the method 200 may proceed with a process 204 that includes filling the opening 321 with a material which may be referred to as "sacrificial" because some or all of it will be removed in a later process.
  • a process 204 that includes filling the opening 321 with a material which may be referred to as "sacrificial" because some or all of it will be removed in a later process.
  • An exemplary result of the process 204 is illustrated with a quantum circuit assembly 304 shown in FIG. 3B, showing that the opening 321 is filled with a sacrificial material 326.
  • the sacrificial material 326 may include any material that has sufficient etch selectivity with respect to the materials of the interconnect support layer 322, as well as preferably etch selective with respect to the material of the substrate 320, in order for an etch process used in a later stage to remove some or all of the sacrificial material 326 to not etch into the interconnect support layer 322 or the material of the substrate 320.
  • two materials are said to have "sufficient etch selectivity" when etchants used to etch one material do not substantially etch the other, enabling selective etching of one material but not the other.
  • some other considerations in selecting a suitable material for the sacrificial material 326 may include e.g. possibilities of smooth film formation, low shrinkage and outgassing, and good dielectric properties (such as e.g. low electrical leakage, suitable value of a dielectric constant, and thermal stability).
  • the sacrificial material 326 may be a sacrificial dielectric material, such as e.g. any of the low-k or high-k dielectric materials used in semiconductor processing, including but not limited to elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • a sacrificial dielectric material such as e.g. any of the low-k or high-k dielectric materials used in semiconductor processing, including but not limited to elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • low-k materials that may be used as the sacrificial material 326 may include, but are not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, spin-on organic polymeric dielectrics such as e.g. polyimide, polynorbornenes, benzocyclobutene, and polytetrafluoroethylene (PTFE), or spin-on silicon-based polymeric dielectric such as e.g. hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ)).
  • fluorine-doped silicon dioxide such as e.g. polyimide, polynorbornenes, benzocyclobutene, and polytetrafluoroethylene (PTFE)
  • spin-on silicon-based polymeric dielectric such as e.g. hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ)
  • Any suitable deposition techniques may be used to fill the opening 321 with the sacrificial material 326 in the process 204.
  • techniques such as e.g. spin-coating, dip-coating, atomic layer deposition (ALD), chemical vapor deposition (CVD), or plasma enhanced CVD (PECVD) may be used.
  • a planarization can then be performed to remove overburden of the sacrificial material 326 and ensure that the sacrificial material 326 is confined to being within the opening 321.
  • via openings for the signal and ground vias may be formed within the opening 321 filled with the sacrificial material 326.
  • An exemplary result of the process 206 is illustrated with a quantum circuit assembly 306 shown in FIG. 3C, showing that a via opening 331 for the signal line of the future vertical transmission line may be formed substantially in the center of the opening 321, and further showing via openings 332 surrounding the via openings
  • the via openings 332 are formed to implement the plurality of ground vias of the future vertical transmission line.
  • removal of the sacrificial material 326 to form the via openings 331 and 332 may be achieved using any suitable technique for removing desired portions of dielectric materials, e.g. dry etch (e.g. RIE) or wet etch, possibly in combination with any suitable patterning technique, e.g. photolithographic or electron-beam patterning, and/or in combination with using a mask.
  • etch e.g. RIE
  • patterning technique e.g. photolithographic or electron-beam patterning
  • Dimensions of the opening 331 would be substantially as those for the final signal line of the vertical transmission line.
  • Dimensions and relative arrangement of the openings 332 would be substantially as those for the vias of the final ground structure of the vertical transmission line.
  • FIG. 3C illustrates each of the openings 331, 332 as having a circular cross-section in the x-y plane, i.e. the openings 331, 332 are cylindrical openings, in other embodiments, the openings 331,
  • the method 200 may then proceed with a process 208 that includes providing, within the via openings formed in the process 206, one or more electrically conductive, e.g. superconductive, materials.
  • a process 208 that includes providing, within the via openings formed in the process 206, one or more electrically conductive, e.g. superconductive, materials.
  • An exemplary result of the process 208 is illustrated with a quantum circuit assembly 308 shown in FIG. 3D, showing that an electrically conductive material 328 is deposited to fill the signal via opening 331 and an electrically conductive material 324 is deposited to fill the ground via openings 332.
  • the conductive material 328 provided within the signal via opening 331 in the process 208 will enable electrical conductivity of the signal via
  • the conductive material 324 provided within the ground via openings 332 will enable electrical conductivity of the ground vias surrounding the signal via.
  • the electrically conductive materials 324, 328 may include any conducting or superconducting material suitable for providing electrical connectivity in a quantum circuit, such as e.g. Al, Nb, NbN, NbTiN, TiN, MoRe, etc., or any alloy of two or more superconducting/conducting materials.
  • the electrically conductive material 328 used to enable electrical connectivity of the signal line of a vertical transmission line as described herein may be the same or different from the electrically conductive material 324 used to enable electrical connectivity of its' ground structure.
  • FIG. 3D and other FIGS illustrate the via openings 331, 332 to be filled with their respective conductive materials 328, 324 fully, in other embodiments, not specifically shown in FIGS., some or all of the via openings 331, 332, may be only lined with their respective electrically conductive materials 328, 324 (i.e. the electrically conductive materials 328, 324 could be provided as liners on the sidewalls of the via openings 331, 332, but not throughout the entire volume of these via openings).
  • the liner could e.g. be a suitable superconductive material such as e.g.
  • the remainder of the via openings 331, 332 may (but does not have to be) filled with a different material such as e.g. copper, which is an example of a conductive but not superconductive material, or be filled with a non-conductive material.
  • a different material such as e.g. copper, which is an example of a conductive but not superconductive material, or be filled with a non-conductive material.
  • the via openings 331, 332 may be filled or lined with the conductive materials 328, 324 in the process 208 using any suitable techniques for depositing conductive materials, such as ALD, CVD, PECVD, or/and physical vapor deposition (PVD) processes such as e.g. sputter.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • PECVD physical vapor deposition
  • the method 200 may proceed with a process 210 of etching at least some, preferably all, of the sacrificial material 326 to form a cavity surrounding the conductive material 328 of the signal line.
  • An exemplary result of the process 210 is illustrated in FIG. 3E with a quantum circuit assembly 310 showing all of the sacrificial material 326 removed to form a cavity, or a gap, 333 between the conductive material 324 provided within the openings 332 (thus, forming ground vias) and the conductive material 328 provided within the opening 331 (thus, forming a signal line).
  • some of the sacrificial material 326 may remain in the gap 333, e.g.
  • FIG. 3E illustrates that the ground vias are completely enclosed within a gap, i.e. enclosed on all sides, in other embodiments this may be different, e.g. the ground vias may be in contact with the material of the interconnect support layer 322, including any interfacial layers which may be formed therebetween, as long as there is a gap between the ground vias and the signal line.
  • any suitable etching techniques for removing the sacrificial material 326 without substantially removing the conductive materials 324 and 328, and without substantially etching into the interconnect support layer 322 or the substrate 320, may be used in the process 210.
  • the etch of the process 210 may advantageously include an isotropic etch (i.e. a process that etches in multiple directions, both vertically and horizontally), such as e.g. an isotropic wet etch.
  • Any substance suitable for the isotropic etch of the sacrificial material 326 without substantially etching the conductive materials 324 and 328 may be used as an etchant in the process 210.
  • an etchant may be e.g. corrosive liquid, such as e.g. H F or a chemically active ionized gas (i.e. plasma).
  • the shape and dimensions of the resulting gap 333 will be those defined by the shape and dimensions of the conductive material 328 forming a signal line and those of the conductive material 324 forming a ground structure of the final vertical transmission line/interconnect.
  • the length of the signal line 328 (i.e. a dimension measured in the direction of the z-axis of the coordinate system shown in FIGS. 3A-3E), or at least the length of the portion of the signal line which is surrounded by the ground vias 324, may be between about 30 nm and 3 um, including all values and ranges therein, e.g. between about 100 nm and 1 um, or between about 300 and 600 nm.
  • a surface area of a transverse (i.e. perpendicular to the length of the signal line) cross-section of the signal line 328 i.e. a dimension measured in the x-y plane of the coordinate system shown in FIGS.
  • 3A-3E may be between about 1600 square nanometers (nm 2 ) and 160000 square micrometers (um 2 ), including all values and ranges therein, e.g. between about 40000 nm 2 and 62500 um 2 , or between about 4 um 2 and 40000 um 2 .
  • FIG. 3E illustrates the signal line 328 and the ground vias 324 as having circular cross-sections in the x-y plane, i.e.
  • any individual one of the signal line 328 and the ground vias 324 of a vertical transmission line may take on any other 3D shape, such as e.g. a prism, possibly with rounded corners.
  • ground structure made of the plurality of ground vias 324 is shown in FIGS. 3A-3E as the ground vias 324 being arranged in a circle around/surrounding the signal line 328, in general, descriptions provided herein are applicable to all of the embodiments of the individual ground vias 324 surrounding the signal line 328 in any other suitable geometry, such as e.g. being arranged in a rectangle, a square, or any polygon around the signal line 320, as long there is a gap between the ground vias 324 and their associated signal line 328.
  • the gap 333 may have a width (defined e.g. as the average distance between the electrically conductive material 324 of the ground vias and the conductive material 328 of the signal line, a dimension measured in the x-y plane of the coordinate system shown in FIGS. 3A- 3E) between about 20 nm and 400 um, including all values and ranges therein, e.g. between about 200 nm and 200 um, or between about 2 and 100 um.
  • a width defined e.g. as the average distance between the electrically conductive material 324 of the ground vias and the conductive material 328 of the signal line, a dimension measured in the x-y plane of the coordinate system shown in FIGS. 3A- 3E
  • the interconnect support layer 322 may be a part of the substrate 320, in which case the method 200 may further include a process during which the lower part of the substrate 320 (what is actually shown as the substrate 320 in FIG. 3E) is removed, e.g. if it is desirable that the vertical transmission line comprising the signal line 328 and the ground vias 324 surrounding the signal line extend between two opposing faces/surfaces of the substrate 320 (e.g. as illustrated in FIG. IB).
  • removal of the lower part of the substrate 320 may be carried out by e.g. CMP or lapping, e.g. if the structure includes 106 and 108, e.g. TSV-like vertical transmission lines as illustrated in FIG. IB, where interconnects extend all the way through the substrate.
  • a vertical transmission line as described herein may be disposed in different configurations with respect to the substrate, such as e.g. the substrate 108, and possibly the dielectric material, such as e.g. the low- loss dielectric material 106.
  • the interconnect support layer 322 may be the dielectric material 106 as shown in FIGS., which dielectric material may remain in the final assembly, as shown in the examples of FIGS. 1A-1E. In other embodiments, some or all of the interconnect support layer 322 may be removed, e.g.
  • the vertical transmission line may be provided above a substrate, where the vertical transmission line as described with reference to FIGS. 3A-3E may extend upwards from the substrate as shown in FIGS. 1C-1E.
  • the opening 321 inside which a vertical transmission line is formed may extend through the entire layer of the interconnect support layer 322 so that the bottom of the opening 321 can later interface another material/component.
  • the vertical transmission line having the ground vias 324 surrounding the signal line 328 as described with reference to FIGS. 3A-3E may be provided in any of the configurations described with reference to FIGS. 1A-1E.
  • the method may further include a process in which the signal line of the vertical transmission line is connected to the respective supporting circuitry for one or more qubits (or one or more "future" qubits, because it may sometimes be advantageous to fabricate qubits last, in order to not subject fragile qubits to fabrication processes of other elements of a quantum circuit assembly). Examples of this are shown in FIGS. 4A-4D, where reference numerals as those used in FIGS. 3A-3E are intended to illustrate analogous/same elements.
  • FIG. 4A illustrates a quantum circuit assembly 402 having a supporting circuitry element 408 that is directly electrically connected to the signal line 328 of a vertical transmission line, above the vertical transmission line, e.g. in order to implement the assembly as shown in FIGS. 1A or IB.
  • the vertical transmission line shown in FIG. 4A is substantially as that shown in the quantum circuit assembly 310, but with some of the conductive material 324 of the upper portion of one or more of the ground vias 324 being removed/recessed (e.g. in an area 403 indicated in FIG. 4A) in order to electrically isolate the supporting circuitry element 408 from the conductive material 324 of the ground structure.
  • connection of the supporting circuitry element 408 to the signal line 328 may be realized using any suitable processes for depositing and patterning electrically conductive elements as known in the art.
  • the supporting circuitry element 408 may e.g. be a part of a resonator, a flux bias line, a microwave feed line, a direct drive line, or any other supporting circuit element as described above.
  • the supporting circuitry element 408 as shown in FIG. 4A may be used to implement the electrically conductive element 114 directly electrically connected to the signal line 102 as shown in FIG. 1A or FIG. IB, to implement the electrically conductive element 122 directly electrically connected to the signal line 102 as shown in FIG. 1C, or to implement the electrically conductive element 122 directly electrically connected to the signal lines 102 of two neighboring vertical transmission lines connected in series as shown in FIG. IE.
  • FIG. 4B illustrates a quantum circuit assembly 404 having the supporting circuitry element 408 that is directly electrically connected to the signal line 328 of the vertical transmission line as in FIG. 4A, but now below the vertical transmission line, e.g. in order to implement the assembly as shown in FIG. 1C.
  • the vertical transmission line shown in FIG. 4B is substantially as that shown in the quantum circuit assembly 310, but with some of the conductive material 324 of the lower portion of the one or more ground vias of the ground structure being removed (e.g. in an area 405 indicated in FIG. 4B) in order to electrically isolate the supporting circuitry element 408 from the conductive material 324 of the ground structure.
  • connection of the supporting circuitry element 408 to the signal line 328 may be realized using any suitable processes for depositing and patterning electrically conductive elements as known in the art and, in various embodiments, the supporting circuitry element 408 may e.g. be a part of a resonator, a flux bias line, a microwave feed line, a direct drive line, or any other supporting circuit element as described above.
  • the supporting circuitry element 408 as shown in FIG. 4B may be used to implement the electrically conductive element 114 directly electrically connected to the signal line 102 as shown in FIG. 1C or FIG. IE, or to implement the electrically conductive element 122 directly electrically connected to the signal line 102 as shown in FIG. IE.
  • the supporting circuitry element 408 as shown in FIG. 4B may be used to implement an electrically conductive element 122 directly electrically connected to the signal lines of two neighboring vertical transmission lines connected in series (similar to what is shown in FIG. IE but in an implementation when the two neighboring signal lines are connected at their bottoms).
  • FIG. 4C illustrates a quantum circuit assembly 406 having a portion of a qubit 412 (similar to the qubit 112) suspended overlapping with at least a portion of the signal line 328, e.g. in order to implement an assembly as described with reference to FIGS. 1A or IB but without the electrically conductive element 114 shown in these FIGS.
  • the vertical transmission line shown in FIG. 4C is substantially as that shown in the quantum circuit assembly 310, but now also having a support material 410 provided in order to support that a portion of the qubit 412 may be suspended over, and overlapping with, the signal line 328, where a dotted oval 407 shown in FIG. 4C illustrates the overlapping portions.
  • the portion of the qubit 410 that is suspended over the signal line 328 may include the SQUID, which may be implemented as two Josephson Junctions connected with a superconducting loop.
  • FIG. 4D schematically illustrates a quantum circuit assembly 408 with a vertical transmission line substantially as shown in FIG. 3E, but now also illustrating BGA connections 414, similar to the BGA 124 shown in FIG. ID.
  • the method may further include a process in which the signal line and the ground vias of the ground structure of the vertical transmission lines as described herein are connected to the respective signal or bias sources - e.g. the signal line is connected to a suitable signal source and the ground structure is connected to a ground potential/bias or any other reference potential/bias.
  • Such connections may be made in a plane at the bottom of the vertical transmission line (e.g. as can be done using the metallization stack 110 shown in FIG. 1A or using the conductive element 122 in the plane of the qubit 112 as shown in FIG.
  • ground plane connection is not specifically shown
  • a plane at the top of the vertical transmission line e.g. as can be done using the conductive element 122 as shown in FIG. 1C for the signal line; the ground plane connection is not specifically shown in that FIG.
  • the ground plane connections may be provided e.g. in the upper plane, not specifically shown in FIGS.).
  • Quantum circuit assemblies/structures incorporating vertical transmission lines as described above may be included in any kind of qubit devices or quantum processing devices/structures. Some examples of such devices/structures are illustrated in FIGS. 5A-5B, 6, and 7.
  • FIGS. 5A-5B are top views of a wafer 1100 and dies 1102 that may be formed from the wafer 1100, according to some embodiments of the present disclosure.
  • the dies 1102 may include any of the quantum circuit assemblies disclosed herein, e.g., quantum circuit assemblies comprising superconducting qubits, spin qubits, or any combination of various types of qubits, and may include any of the vertical transmission lines described herein, such as e.g. the vertical transmission lines shown in FIGS. 1A-1E, FIG. 3E, or FIGS. 4A-4D (each of which may be implemented according to e.g. method shown in FIG. 2), or any further embodiments of the vertical transmission lines as described herein.
  • the wafer 1100 may be any the form of the qubit substrates as proposed herein, and may further include one or more dies 1102 having conventional and quantum circuit device elements formed on a surface of the wafer 1100.
  • Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device.
  • the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product.
  • a die 1102 may include one or more quantum circuits 100, including any supporting conductive circuitry to route electrical signals within the quantum circuits 100, as well as any other 1C components.
  • the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 2002 of FIG. 7) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • a memory device e.g., a static random access memory (SRAM) device
  • a logic device e.g., AND, OR, NAND, or NOR gate
  • FIG. 6 is a cross-sectional side view of a device assembly 1200 that may include any of the vertical transmission lines disclosed herein, such as e.g. the vertical transmission lines shown in FIGS. 1A-1E, FIG. 3E, or FIGS. 4A-4D, or any further embodiments of the vertical transmission lines as described herein.
  • the device assembly 1200 includes a number of components disposed on a circuit board 1202.
  • the device assembly 1200 may include components disposed on a first face 1240 of the circuit board 1202 and an opposing second face 1242 of the circuit board 1202; generally, components may be disposed on one or both faces 1240 and 1242.
  • the circuit board 1202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1202.
  • the circuit board 1202 may be a package substrate or flexible board.
  • the 1C device assembly 1200 illustrated in FIG. 6 may include a package-on-interposer structure 1236 coupled to the first face 1240 of the circuit board 1202 by coupling components 1216.
  • the coupling components 1216 may electrically and mechanically couple the package-on- interposer structure 1236 to the circuit board 1202, and may include solder balls (as shown in FIG.
  • male and female portions of a socket an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
  • the package-on-interposer structure 1236 may include a package 1220 coupled to an interposer 1204 by coupling components 1218.
  • the coupling components 1218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1216. Although a single package 1220 is shown in FIG. 6, multiple packages may be coupled to the interposer 1204; indeed, additional interposers may be coupled to the interposer 1204.
  • the interposer 1204 may provide an intervening substrate used to bridge the circuit board 1202 and the package 1220.
  • the package 1220 may be a quantum circuit device package as described herein, e.g.
  • the package 1220 is a quantum circuit device package including at least one quantum circuit assembly with any of the vertical transmission lines described herein, the vertical transmission lines therein may be electrically connected to the interposer 1204 by the coupling components 1218.
  • the interposer 1204 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 1204 may couple the package 1220 (e.g., a die) to a BGA of the coupling components 1216 for coupling to the circuit board 1202.
  • the package 1220 and the circuit board 1202 are attached to opposing sides of the interposer 1204; in other embodiments, the package 1220 and the circuit board 1202 may be attached to a same side of the interposer 1204.
  • three or more components may be interconnected by way of the interposer 1204.
  • the interposer 1204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer 1204 may include metal interconnects 1208 and vias 1210, including but not limited to through-silicon vias (TSVs) 1206.
  • TSVs through-silicon vias
  • the interposer 1204 may further include embedded devices 1214, including both passive and active devices.
  • Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1204.
  • the package-on-interposer structure 1236 may take the form of any of the package-on-interposer structures known in the art.
  • the device assembly 1200 may include a package 1224 coupled to the first face 1240 of the circuit board 1202 by coupling components 1222.
  • the coupling components 1222 may take the form of any of the embodiments discussed above with reference to the coupling components 1216
  • the package 1224 may take the form of any of the embodiments discussed above with reference to the package 1220.
  • the package 1224 may be a package including one or more quantum circuits with qubits as described herein or may be a conventional 1C package, for example. In some embodiments, the package 1224 may take the form of any of the embodiments of the quantum circuit with any of the quantum circuit assemblies described herein.
  • the device assembly 1200 illustrated in FIG. 6 includes a package-on-package structure 1234 coupled to the second face 1242 of the circuit board 1202 by coupling components 1228.
  • the package-on-package structure 1234 may include a package 1226 and a package 1232 coupled together by coupling components 1230 such that the package 1226 is disposed between the circuit board 1202 and the package 1232.
  • the coupling components 1228 and 1230 may take the form of any of the embodiments of the coupling components 1216 discussed above, and the packages 1226 and 1232 may take the form of any of the embodiments of the package 1220 discussed above.
  • Each of the packages 1226 and 1232 may be a qubit device package as described herein, e.g. by including the qubit substrates as described herein, or may be a conventional 1C package, for example.
  • FIG. 7 is a block diagram of an exemplary quantum computing device 2000 that may include any of the quantum circuit assemblies with vertical transmission lines as disclosed herein, such as e.g. the vertical transmission lines shown in FIGS. 1A-1E, FIG. 3E, or FIGS. 4A-4D, or any further embodiments of the vertical transmission lines as described herein.
  • a number of components are illustrated in FIG. 7 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application.
  • the components included in the quantum computing device 2000 may be attached to one or more PCBs (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with any of the quantum circuit assemblies described herein. In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 7, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled.
  • display device interface circuitry e.g., a connector and driver circuitry
  • the quantum computing device 2000 may not include an audio input device 2018 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2018 or audio output device 2008 may be coupled.
  • audio input or output device interface circuitry e.g., connectors and supporting circuitry
  • the quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices).
  • processing device e.g., one or more processing devices
  • the term "processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices).
  • the quantum processing device 2026 may include one or more quantum circuit assemblies including any of the vertical transmission lines disclosed herein, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuit assemblies with any of the vertical transmission lines disclosed herein, and monitoring the result of those operations. For example, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of different qubits may be read.
  • the quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc.
  • the quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.
  • the processing device 2002 may include a non-quantum processing device 2028.
  • the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026.
  • the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc.
  • the non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026.
  • the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed herein, the display device 2006 discussed herein, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components.
  • the non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
  • DSPs digital signal processors
  • ASICs application-specific ICs
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute cryptographic algorithms within hardware
  • server processors or any other suitable processing devices.
  • the quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid-state memory
  • solid-state memory solid-state memory
  • hard drive solid-state memory
  • the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004.
  • the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
  • eDRAM embedded dynamic random access memory
  • STT-MRAM spin transfer torque magnetic random access memory
  • the quantum computing device 2000 may include a cooling apparatus 2024.
  • the cooling apparatus 2024 may maintain the quantum processing device 2026, in particular the quantum circuits with any of the vertical transmission lines as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2026.
  • This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less.
  • the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature.
  • the cooling apparatus 2024 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.
  • the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips).
  • the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UM B) project (also referred to as "3GPP2”), etc.).
  • IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for
  • Microwave Access which is a certification mark for products that pass conformity
  • the communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • HSPA High Speed Packet Access
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • the communication chip 2012 may operate in accordance with other wireless protocols in other embodiments.
  • the quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
  • the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet).
  • the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless
  • a second communication chip 2012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
  • GPS global positioning system
  • EDGE EDGE
  • GPRS global positioning system
  • CDMA Code Division Multiple Access
  • WiMAX Long Term Evolution
  • LTE Long Term Evolution
  • EV-DO EV-DO
  • a first communication chip 2012 may be dedicated to wireless communications
  • a second communication chip 2012 may be dedicated to wired communications.
  • the quantum computing device 2000 may include battery/power circuitry 2014.
  • the battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).
  • the quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above).
  • the display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
  • LCD liquid crystal display
  • the quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above).
  • the audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
  • the quantum computing device 2000 may include an audio input device 2018 (or corresponding interface circuitry, as discussed above).
  • the audio input device 2018 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
  • MIDI musical instrument digital interface
  • the quantum computing device 2000 may include a GPS device 2016 (or corresponding interface circuitry, as discussed above).
  • the GPS device 2016 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.
  • the quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. [0122]
  • the quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • QR Quick Response
  • the quantum computing device 2000 may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
  • a hand-held or mobile computing device e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.
  • PDA personal digital assistant
  • Example 1 provides a quantum circuit assembly that includes a substrate, at least one qubit, typically a plurality of qubits, provided over the substrate, and a vertical transmission line structure for providing microwave connectivity for one or more of the plurality of qubits.
  • the vertical transmission line structure includes a signal line and a ground structure.
  • the signal line is provided substantially perpendicular to the plane of the substrate.
  • At least a portion of the ground structure includes a plurality of electrically conductive ground vias surrounding the signal line along at least a portion of a length of the signal line and separated from the signal line by a respective, i.e.
  • each ground via is separated from the signal line by a certain gap, i.e. a distance between said ground via and the signal line; respective gaps for different ground vias may be different from one another; all of the respective gaps together may form, or be a part of, one continuous opening around the signal line).
  • Example 2 provides the quantum circuit assembly according to Example 1, where the ground vias are arranged substantially along a circle around (substantially concentric with) the signal line.
  • Example 3 provides the quantum circuit assembly according to Example 1, where the ground vias are arranged substantially in a rectangle around the signal line.
  • Example 4 provides the quantum circuit assembly according to Example 1, where the ground vias are arranged substantially in a square around the signal line.
  • Example 5 provides the quantum circuit assembly according to Example 1, wherein the individual gaps form a single continuous opening around at least the portion of the length of the signal line.
  • Example 6 provides the quantum circuit assembly according to any one of the preceding Examples, where a largest dimension of individual ground vias of the plurality of ground vias, in a plane substantially parallel to the plane of the substrate (e.g. the diameter of the ground vias, in case the vias have circular cross-section), is between about 20 nm and 600 um, including all values and ranges therein, e.g. between about 200 nm and 400 um, or between 2 and 200 um.
  • Example 7 provides the quantum circuit assembly according to any one of the preceding Examples, where the gap has a width between about 20 nm and 400 um, including all values and ranges therein, e.g. between about 200 nm and 200 um, or between about 2 and 100 um.
  • Example 8 provides the quantum circuit assembly according to any one of the preceding Examples, where a surface area of a transverse (i.e. perpendicular to the length of the signal line) cross-section of the signal line is between about 1600 nm 2 and 160000 um 2 , including all values and ranges therein, e.g. between about 40000 nm 2 and 62500 um 2 , or between about 4 um 2 and 40000 um 2 .
  • Example 9 provides the quantum circuit assembly according to any one of the preceding Examples, where a length of a portion of the signal line that is surrounded by said plurality of ground vias is between about 30 nm and 3 um, including all values and ranges therein, e.g. between about 100 nm and 1 um, or between about 300 and 600 nm.
  • Example 10 provides the quantum circuit assembly according to any one of Examples 1-9, where the vertical transmission line structure is provided above the substrate, i.e. the vertical transmission line structure extends away from the substrate, or is provided in a layer of a dielectric material, preferably low-loss material as described herein, which is disposed over the substrate.
  • Example 11 provides the quantum circuit assembly according to any one of Examples 1-9, where the vertical transmission line structure is provided in a layer of or over the substrate, the layer including a first face over which the at least one qubit is provided, and an opposing second face below a plane in which the plurality of qubits are provided, and the vertical transmission line structure extends between said first face and said second face.
  • Example 12 provides the quantum circuit assembly according to any one of Examples 1-9, where the vertical transmission line structure extends between a first face of the substrate (the face over which the qubits are provided) and an opposing second face of the substrate and is electrically connected to first level interconnects provided at the second face of the substrate.
  • Example 13 provides the quantum circuit assembly according to Example 12, where the second face of the substrate is coupled to a packaging substrate via first level interconnects.
  • Example 14 provides the quantum circuit assembly according to any one of Examples 1-13, where the at least one qubit is a superconducting qubit, and the vertical transmission line structure forms at least a part of a resonator for the superconducting qubit.
  • Example 15 provides the quantum circuit assembly according to any one of Examples 1-13, where the at least one qubit is a superconducting qubit, the quantum circuit assembly further includes a flux bias line, and the vertical transmission line structure is for providing electrical connectivity for (i.e. is electrically connected to) said flux bias line.
  • Example 16 provides the quantum circuit assembly according to any one of Examples 1-13, where the at least one qubit is a superconducting qubit, the quantum circuit assembly further includes a microwave feed line, and the vertical transmission line structure is for providing electrical connectivity for (i.e. is electrically connected to) said microwave feed line.
  • Example 17 provides the quantum circuit assembly according to any one of Examples 1-13, where the at least one qubit is a superconducting qubit, the quantum circuit assembly further includes a direct drive line, and the vertical transmission line structure is for providing electrical connectivity for (i.e. is electrically connected to) said direct drive line.
  • Example 18 provides a method of manufacturing a quantum assembly.
  • the method includes providing an opening in an interconnect support layer; depositing a sacrificial material in the opening; forming, within the sacrificial material, a via opening for a signal line and a plurality of via openings for ground vias, where the plurality of via openings for the ground vias surround the via opening for the signal line along at least a portion of the length of the via opening for the signal line; depositing one or more electrically conductive materials within at least a portion of the via opening for the signal line and within at least portions of the plurality of via openings for the ground vias; removing some or all of the sacrificial material around the via opening for the signal line to form a vertical transmission line structure having the ground vias separated from the signal line by respective gaps (i.e.
  • each ground via is separated from the signal line by a certain gap, i.e. a distance between said ground via and the signal line; respective gaps for different ground vias may be different from one another; all of the respective gaps together may form, or be a part of, one continuous opening around the signal line); and providing at least one qubit associated with the vertical transmission line structure.
  • Example 19 provides the method according to Example 18, where the gap is a region where the sacrificial material between the electrically conductive materials of the signal line and the ground vias is removed.
  • Example 20 provides the method according to Examples 18 or 19, where a width of the gap is between about 20 nm and 400 um.
  • Example 21 provides the method according to any one of Examples 18-20, where a largest dimension of individual via openings of the plurality of via openings for the ground vias, in a plane substantially parallel to the substrate (e.g. the diameter of the ground vias, in case the vias have circular cross-section), is between about 20 nm and 600 um, including all values and ranges therein, e.g. between about 200 nm and 400 um, or between 2 and 200 um.
  • Example 22 provides a quantum 1C package that includes a qubit die that includes a substrate including a first face, a second face opposite the first face, and a vertical transmission line extending between the first face and the second face.
  • the vertical transmission line structure includes a signal line and a ground structure, where the signal line is substantially perpendicular to the plane of the substrate and where the ground structure includes a plurality of electrically conductive ground vias surrounding the signal line along at least a portion of the length of the signal line and separated from the signal line by a gap.
  • the qubit die further includes at least one qubit device provided over the first face or over the second face
  • the quantum 1C package further includes a further 1C element coupled to the second face of the substrate by first level interconnects between the further 1C element and the signal line, and further first level interconnects between the further 1C element and the ground structure of the vertical transmission line extending to the second face of the qubit die substrate.
  • Example 23 provides the quantum 1C package according to Example 22, where the further 1C element is one of an interposer, a circuit board, a flexible board, or a package substrate.
  • Various further Examples provide the quantum 1C package according to any one of Examples 22-23, where the vertical transmission line structure is a vertical transmission line structure according to any one of Examples 1-17.
  • Example 24 provides a quantum computing device that includes a quantum processing device that includes a die including a substrate and a plurality of qubits over or in the substrate, and a memory device configured to store data generated by the plurality of qubits during operation of the quantum processing device.
  • the quantum processing device further includes at least one vertical transmission line structure for providing electrical connectivity for one or more of the plurality of qubits, where the vertical transmission line structure includes a signal line and a ground structure.
  • the signal line is provided substantially perpendicular to the plane of the substrate.
  • Example 25 provides the quantum computing device according to Example 24, further including a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
  • Example 26 provides the quantum computing device according to Examples 24 or 25, where the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
  • Example 27 provides the quantum computing device according to any one of Examples 24- 26, further including a non-quantum processing device coupled to the quantum processing device.
  • Various further Examples provide the quantum computing device according to any one of Examples 24-27, where the vertical transmission line structure is a vertical transmission line structure according to any one of Examples 1-17 or/and is included within the quantum 1C package according to any one of Examples 22-23.

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Abstract

Des modes de réalisation de la présente invention proposent des ensembles de circuits quantiques ayant des lignes de transmission hyperfréquence verticales. Un ensemble donné à titre d'exemple comprend au moins un bit quantique fourni sur un substrat de bit quantique, et une ligne de transmission verticale associée au bit quantique. La ligne de transmission verticale comprend une ligne de signal et une structure de masse, la ligne de signal étant sensiblement perpendiculaire au plan du substrat et au moins une partie de la structure de masse comprend une pluralité de trous d'interconnexion de masse entourant la ligne de signal le long d'au moins une partie de la longueur de la ligne de signal et séparés de la ligne de signal par un espace. De telles lignes de transmission verticales peuvent avantageusement faciliter l'utilisation de conceptions 3D et empilées pour des ensembles de circuits quantiques, maintenir les pertes qui conduisent à une décohérence de bits quantiques suffisamment faible, et permettre une extensibilité de dispositif et une utilisation de processus de fabrication de 300 millimètres.
PCT/US2017/066888 2017-12-17 2017-12-17 Ligne de transmission verticale de bits quantiques avec des trous d'interconnexion de masse entourant une ligne de signal WO2019117972A1 (fr)

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US10910488B2 (en) 2018-06-26 2021-02-02 Intel Corporation Quantum dot devices with fins and partially wrapped gates
US11011693B2 (en) 2019-06-24 2021-05-18 Intel Corporation Integrated quantum circuit assemblies for cooling apparatus
US11114530B2 (en) 2017-12-17 2021-09-07 Intel Corporation Quantum well stacks for quantum dot devices
CN113725208A (zh) * 2021-08-13 2021-11-30 中国科学院物理研究所 一种三维量子芯片及其制备方法
US11335778B2 (en) 2018-06-26 2022-05-17 Intel Corporation Quantum dot devices with overlapping gates
US11417765B2 (en) 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US11417755B2 (en) 2018-01-08 2022-08-16 Intel Corporation Differentially strained quantum dot devices
US11424324B2 (en) 2018-09-27 2022-08-23 Intel Corporation Multi-spacers for quantum dot device gates
EP4053865A1 (fr) * 2021-03-02 2022-09-07 Imec VZW Dispositif de condensateur de tranchée pour un circuit électronique supraconducteur et dispositif à qubit supraconducteur
CN115050886A (zh) * 2021-03-09 2022-09-13 合肥本源量子计算科技有限责任公司 一种量子芯片及制备方法
US11450765B2 (en) 2018-09-27 2022-09-20 Intel Corporation Quantum dot devices with diodes for electrostatic discharge protection
CN115438796A (zh) * 2022-03-15 2022-12-06 合肥本源量子计算科技有限责任公司 量子芯片及其制备方法、以及量子计算机
US11658212B2 (en) 2019-02-13 2023-05-23 Intel Corporation Quantum dot devices with conductive liners
US11682701B2 (en) 2019-03-27 2023-06-20 Intel Corporation Quantum dot devices
US11749721B2 (en) 2018-09-28 2023-09-05 Intel Corporation Gate walls for quantum dot devices
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US20120112857A1 (en) * 2010-11-10 2012-05-10 Jongsik Lim Double microstrip transmission line having common defected ground structure and wireless circuit apparatus using the same
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Cited By (19)

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US11721724B2 (en) 2017-12-17 2023-08-08 Intel Corporation Quantum well stacks for quantum dot devices
US11114530B2 (en) 2017-12-17 2021-09-07 Intel Corporation Quantum well stacks for quantum dot devices
US11417755B2 (en) 2018-01-08 2022-08-16 Intel Corporation Differentially strained quantum dot devices
US11417765B2 (en) 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US10910488B2 (en) 2018-06-26 2021-02-02 Intel Corporation Quantum dot devices with fins and partially wrapped gates
US11335778B2 (en) 2018-06-26 2022-05-17 Intel Corporation Quantum dot devices with overlapping gates
US10879446B2 (en) 2018-08-14 2020-12-29 Intel Corporation Vertical flux bias lines coupled to vertical squid loops in superconducting qubits
US11424324B2 (en) 2018-09-27 2022-08-23 Intel Corporation Multi-spacers for quantum dot device gates
US11450765B2 (en) 2018-09-27 2022-09-20 Intel Corporation Quantum dot devices with diodes for electrostatic discharge protection
US11749721B2 (en) 2018-09-28 2023-09-05 Intel Corporation Gate walls for quantum dot devices
US11658212B2 (en) 2019-02-13 2023-05-23 Intel Corporation Quantum dot devices with conductive liners
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US11011693B2 (en) 2019-06-24 2021-05-18 Intel Corporation Integrated quantum circuit assemblies for cooling apparatus
US11957066B2 (en) 2019-09-04 2024-04-09 Intel Corporation Stackable in-line filter modules for quantum computing
EP4053865A1 (fr) * 2021-03-02 2022-09-07 Imec VZW Dispositif de condensateur de tranchée pour un circuit électronique supraconducteur et dispositif à qubit supraconducteur
CN115050886A (zh) * 2021-03-09 2022-09-13 合肥本源量子计算科技有限责任公司 一种量子芯片及制备方法
CN113725208A (zh) * 2021-08-13 2021-11-30 中国科学院物理研究所 一种三维量子芯片及其制备方法
WO2023174307A1 (fr) * 2022-03-15 2023-09-21 本源量子计算科技（合肥）股份有限公司 Puce quantique, procédé de préparation de puce quantique, structure de disposition et ordinateur quantique
CN115438796A (zh) * 2022-03-15 2022-12-06 合肥本源量子计算科技有限责任公司 量子芯片及其制备方法、以及量子计算机

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