WO2017217961A1 - Jonctions josephson constituées de métaux réfractaires et nobles - Google Patents

Jonctions josephson constituées de métaux réfractaires et nobles Download PDF

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Publication number
WO2017217961A1
WO2017217961A1 PCT/US2016/037135 US2016037135W WO2017217961A1 WO 2017217961 A1 WO2017217961 A1 WO 2017217961A1 US 2016037135 W US2016037135 W US 2016037135W WO 2017217961 A1 WO2017217961 A1 WO 2017217961A1
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layer
superconductor
quantum
superconducting qubit
qubit
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PCT/US2016/037135
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English (en)
Inventor
Zachary R. YOSCOVITS
Jeanette M. Roberts
Ravi Pillarisetty
James S. Clarke
David J. Michalak
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Intel Corporation
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Priority to US16/097,677 priority Critical patent/US20190363239A1/en
Priority to PCT/US2016/037135 priority patent/WO2017217961A1/fr
Publication of WO2017217961A1 publication Critical patent/WO2017217961A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H10N60/12—Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/85—Superconducting active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/85—Superconducting active materials
    • H10N60/855—Ceramic superconductors

Definitions

  • This disclosure relates generally to the field of quantum computing, and more specifically, to Josephson Junctions for use in quantum circuits and to methods of fabricating thereof.
  • Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.
  • FIG. 1A provides a schematic illustration of a superconducting quantum circuit, according to some embodiments of the present disclosure.
  • FIG. IB provides a schematic illustration of an exemplary physical layout of a superconducting quantum circuit, according to some embodiments of the present disclosure.
  • FIG. 1C provides a schematic illustration of an exemplary transmon, according to some embodiments of the present disclosure.
  • FIG. 2 provides a schematic illustration of quantum computing device, according to some embodiments of the present disclosure.
  • FIGs. 3A-3C provide a schematic illustration of photoresist masks provided over a substrate for fabricating Josephson Junctions using a double-angle shadow evaporation approach, according to some embodiments of the present disclosure.
  • FIGs. 4A-4C provide a schematic illustration of fabricating Josephson Junctions using a conventional double-angle shadow evaporation approach.
  • FIGs. 5A-5G provide a schematic illustration of Damascene fabrication of Josephson Junctions, according to some embodiments of the present disclosure.
  • FIG. 6 provides a flow chart of a method for Damascene fabrication of Josephson Junctions, according to some embodiments of the present disclosure.
  • FIGs. 7A-B provide a schematic illustration of a Josephson Junction fabricated using the Damascene method described herein, according to some embodiments of the present disclosure.
  • quantum computing or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data.
  • quantum- mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states.
  • Quantum entanglement is another example of quantum- mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described
  • quantum state is given for the group of entangled particles as a whole.
  • quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).
  • Quantum computers encode data into binary values, commonly referred to as bits. At any given time, a bit is always in only one of two states - it is either 0 or 1. Quantum computers use so-called quantum bits, referred to as qubits (both terms “bits” and “qubits” often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states.
  • Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.
  • a two-level (also referred to as "two-state") system is a system that can exist in any quantum superposition of two independent and physically distinguishable quantum states.
  • qubits are often operated at cryogenic temperatures, typically just a few degrees or even just a few millidegrees above absolute zero because cryogenic temperatures minimize the detrimental effects of spurious TLS's. None of these challenges ever had to be addressed for classical computers. [0016] As the foregoing illustrates, ability to manipulate and read out quantum states, making quantum-mechanical phenomena visible and traceable, and ability to deal with and improve on the fragility of quantum states of a qubit present unique challenges not found in classical computers. These challenges explain why so many current efforts of the industry and the academics continue to focus on a search for new and improved physical systems whose functionality could approach that expected of theoretically designed qubits. Physical systems for implementing qubits that have been explored until now include e.g.
  • All of superconducting qubits operate based on the Josephson effect, which refers to a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a device known as a Josephson Junction.
  • Josephson Junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits.
  • Described herein are structures that include Josephson Junctions to be used in quantum circuit components, and methods for fabricating such structures.
  • JJs Josephson Junctions
  • the JJs of these structures are fabricated using an approach that allows a wide selection of suitable materials for use in JJs and that can be efficiently used in large scale manufacturing.
  • proposed fabrication techniques provide a substantial improvement with respect to conventional approaches, such as e.g. double-angle shadow evaporation approach, which are limited in their choice of materials and include fabrications steps that are not manufacturable at the larger wafer sizes used by leading edge device manufactures.
  • resulting Josephson Junctions may include base and/or top electrodes made from refractory and/or from noble metals.
  • tunnel barrier layers of such Josephson Junctions are not limited to oxides of the electrode materials.
  • refractory metal refers to metals that exhibit resistance to changing under high temperatures
  • non metal refers to metals that do not easily oxidize or corrode.
  • proposed fabrication approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer.
  • the proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.
  • Such an approach is referred to in the following as a "Damascene fabrication" approach to highlight the fact that it involves an additive process for creating features, as opposed to subtractive patterning commonly used in quantum computing community.
  • the phrase “A and/or B” means (A), (B), or (A and B).
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
  • the notation "A/B/C” means (A), (B), and/or (C).
  • the terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • quantum computing refers to the use of quantum mechanical properties to perform calculations. Some of these properties include superposition and entanglement.
  • a quantum computer is composed of quantum bits (i.e., qubits) which have states of
  • Quantum mechanics allows for superpositions of the
  • a qubit state When a qubit state is measured, it collapses to either state
  • a 1 2 + 1 b 1 2 1 (since the total probability must sum to unity) and ignoring an overall phase factor which does not have any observable effects, the general ⁇ ' ⁇
  • Entanglement occurs when the interaction between two particles (e.g. two qubits) is such that the states of the two cannot be specified independently, but rather can only be specified for the whole system. This causes the states of the two qubits to be linked together such that measurement of one of the qubits, causes the state of the other qubit to collapse.
  • two particles e.g. two qubits
  • Josephson Junction may form the central circuit elements of a superconducting quantum computer.
  • a Josephson Junction may include a thin layer of insulator, typically referred to as a barrier or a tunnel barrier, sandwiched between two layers of
  • the Josephson Junction acts as a superconducting tunnel junction. Cooper pairs tunnel across the barrier from one superconducting layer to the other. The electrical characteristics of this tunneling are governed by so-called Josephson relations which provide the basic equations governing the dynamics of the Josephson effect:
  • Equations (1) and (2) can be combined to give an equation (3): h
  • Equation (3) looks like the equation for an inductor with inductance L:
  • inductance is a function of ⁇ , which itself is a function of I
  • the inductance of a Josephson Junction is non-linear, which makes an LC circuit formed using a Josephson Junction as the inductor have uneven spacing between its energy states.
  • Josephson Junctions in a transmon, which is one type of superconducting qubit.
  • Josephson Junctions combined with other circuit elements have similar functionality of providing the non-linearity necessary for forming an effective two-level quantum state, or qubit.
  • one or more Josephson Junctions allow realizing a quantum circuit element which has uneven spacing between its energy levels resulting in a unique ground and excited state system for the qubit. This is illustrated in FIG.
  • an exemplary superconducting quantum circuit 100 includes two or more qubits 102 (reference numerals following after a dash, such as e.g. qubit 102-1 and 102-2 indicate different instances of the same or analogous element).
  • Each of the superconducting qubits 102 may include one or more Josephson Junctions 104 connected to one or more other circuit elements 106, which, in combination with the Josephson Junction(s) 104, form a nonlinear circuit providing a unique two-level quantum state for the qubit.
  • the circuit elements 106 could be e.g. capacitors in transmons or superconducting loops in flux qubits.
  • an exemplary superconducting quantum circuit 100 typically includes means 108 for providing external control of qubits 102 and means 110 for providing internal control of qubits 102.
  • external control refers to controlling the qubits 102 from outside of, e.g, an integrated circuit (IC) chip comprising the qubits, including control by a user of a quantum computer, while “internal control” refers to controlling the qubits 102 within the IC chip.
  • IC integrated circuit
  • external control may be implemented by means of flux bias lines (also known as “flux lines” and “flux coil lines”) and by means of readout and drive lines (also known as
  • microwave lines since qubits are typically designed to operate with microwave signals), described in greater detail below.
  • internal control lines for such qubits may be implemented by means of resonators, e.g., coupling and readout resonators, also described in greater detail below.
  • any one of the qubits 102, the external control means 108, and the external control means 110 of the quantum circuit 100 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 1A).
  • a substrate may include any substrate suitable for realizing quantum circuit components, as described above.
  • the substrate may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof. In other implementations, the substrate may be non-crystalline.
  • any material that provides sufficient advantages e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g. negative effects of spurious TLS's), and that may serve as a foundation upon which a quantum circuit may be built, falls within the spirit and scope of the present disclosure.
  • Additional examples of substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.
  • charge qubits As previously described herein, within superconducting qubit implementations, three classes are typically distinguished: charge qubits, flux qubits, and phase qubits.
  • FIG. IB provides a schematic illustration of an exemplary physical layout of a superconducting quantum circuit 100B where qubits are implemented as transmons, according to some embodiments of the present disclosure.
  • FIG. IB illustrates two qubits 102.
  • FIG. IB illustrates flux bias lines 112, microwave lines 114, a coupling resonator 116, a readout resonator 118, and wirebonding pads 120 and 122.
  • the flux bias lines 112 and the microwave lines may be viewed as examples of the external control means 108 shown in FIG. 1A.
  • the coupling resonator 116 and the readout resonator 118 may be viewed as examples of the internal control means 110 shown in FIG. 1A.
  • Running a current through the flux bias lines 112, provided from the wirebonding pads 120, allows tuning (i.e. changing) the frequency of the corresponding qubits 102 to which each line 112 is connected. In general, it operates in the following manner. As a result of running the current in a particular flux bias line 112, magnetic field is created around the line. If such a magnetic field is in sufficient proximity to the qubit 102, e.g. by a portion of the flux bias line 112 being provided next to the qubit 102, the magnetic field couples to the qubit, thereby changing the spacing between the energy levels of the qubit. This, in turn, changes the frequency of the qubit since the frequency is directly related to the spacing between the energy levels via Planck's equation.
  • each qubit 102 may be read by way of its corresponding readout resonator 118. As explained below, the qubit 102 induces a resonant frequency in the readout resonator 118. This resonant frequency is then passed to the microwave lines 114 and communicated to the pads 122.
  • a readout resonator 118 may be provided for each qubit.
  • the readout resonator 118 may be a transmission line that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side (for a quarter wavelength resonator) or has a capacitive connection to ground (for a half wavelength resonator), which results in oscillations within the transmission line (resonance), with the resonant frequency of the oscillations being close to the frequency of the qubit.
  • the readout resonator 118 is coupled to the qubit by being in sufficient proximity to the qubit 102, more specifically in sufficient proximity to the capacitor of the qubit 102, when the qubit is implemented as a transmon, either through capacitive or inductive coupling. Due to a coupling between the readout resonator 118 and the qubit 102, changes in the state of the qubit 102 result in changes of the resonant frequency of the readout resonator 118. In turn, because the readout resonator 118 is in sufficient proximity to the microwave line 114, changes in the resonant frequency of the readout resonator 118 induce changes in the current in the microwave line 114, and that current can be read externally via the wirebonding pads 122.
  • the coupling resonator 116 allows coupling different qubits together in order to realize quantum logic gates.
  • the coupling resonator 116 is similar to the readout resonator 118 in that it is a transmission line that includes capacitive connections to ground on both sides (i.e. a half wavelength resonator), which also results in oscillations within the coupling resonator 116.
  • Each side of the coupling resonator 116 is coupled (again, either capacitively or inductively) to a respective qubit by being in sufficient proximity to the qubit, namely in sufficient proximity to the capacitor of the qubit, when the qubit is implemented as a transmon.
  • each side of the coupling resonator 116 has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator 116.
  • state of one qubit depends on the state of the other qubit, and the other way around.
  • coupling resonators may be employed in order to use a state of one qubit to control a state of another qubit.
  • the microwave line 114 may be used to not only readout the state of the qubits as described above, but also to control the state of the qubits.
  • the line operates in a half-duplex mode where, at some times, it is configured to readout the state of the qubits, and, at other times, it is configured to control the state of the qubits.
  • microwave lines such as the line 114 shown in FIG. IB may be used to only readout the state of the qubits as described above, while separate drive lines such as e.g. drive lines 124 shown in FIG. IB, may be used to control the state of the qubits.
  • the microwave lines used for readout may be referred to as readout lines (e.g. readout line 114), while microwave lines used for controlling the state of the qubits may be referred to as drive lines (e.g. drive lines 124).
  • the drive lines 124 may control the state of their respective qubits 102 by providing, using e.g. wirebonding pads 126 as shown in FIG. IB, a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the 0 and 1 state of the qubit. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the 0 and 1 states of the qubit.
  • Flux bias lines, microwave lines, coupling resonators, drive lines, and readout resonators such as e.g. those described above, together form interconnects for supporting propagation of microwave signals.
  • any other connections for providing direct electrical interconnection between different quantum circuit elements and components such as e.g. connections from electrodes of Josephson Junctions to plates of the capacitors or to superconducting loops of superconducting quantum interference devices (SQUIDS) or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, are also referred to herein as interconnects.
  • SQUIDS superconducting quantum interference devices
  • interconnect may also be used to refer to elements providing electrical interconnections between quantum circuit elements and components and non- quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit.
  • non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog to digital converters, mixers, multiplexers, amplifiers, etc.
  • the interconnects as shown in FIG. IB could have different shapes and layouts.
  • some interconnects may comprise more curves and turns while other interconnects may comprise less curves and turns, and some interconnects may comprise substantially straight lines.
  • various interconnects may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using e.g. a bridge, bridging one interconnect over the other.
  • quantum circuits with different shapes and layouts of the interconnects than those illustrated in FIG. IB are all within the scope of the present disclosure.
  • Coupling resonators and readout resonators may be configured for capacitive coupling to other circuit elements at one or both ends in order to have resonant oscillations, whereas flux bias lines and microwave lines may be similar to conventional microwave transmission lines because there is no resonance in these lines.
  • Each one of these interconnects may be implemented as a coplanar waveguide, which is one type of transmission line.
  • a stripline is another type of transmission line.
  • Typical materials to make the interconnects include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), and niobium titanium nitride (NbTiN), all of which are particular types of superconductors. However, in various embodiments, other suitable superconductors may be used as well.
  • FIG. IB illustrates an embodiment specific to transmons. Subject matter is not limited in this regard and may include other embodiments of quantum circuits implementing other types of superconducting qubits that would also utilize Josephson Junctions as described herein, all of which are within the scope of the present disclosure.
  • FIG. 1C illustrates an exemplary transmon 128 which could be used as any one of the qubits 102, according to some embodiments of the present disclosure.
  • Presence of a capacitor 130 of such a size that capacitive energy is significantly larger than the Josephson energy in a qubit of FIG. 1C indicates that the qubit is a transmon.
  • the capacitor 130 is configured to store energy in an electrical field as charges between the plates of the capacitor.
  • the capacitor 130 is depicted as an interdigitated capacitor, a particular shape of capacitor that provides a large capacitance with a small area, however, in various embodiments, other shapes and types of capacitors may be used as well. For example, such a capacitor could be implemented simply as two parallel plates with vacuum in between. Furthermore, in various embodiments, the capacitor 130 may be arranged in any direction with respect to the SQUID or a single Josephson Junction, not necessarily as shown in FIG. 1C.
  • the transmon illustrated in FIG. 1C includes two Josephson Junctions 132 incorporated into a superconducting loop 134.
  • the two Josephson Junctions 132 and the superconducting loop 134 together form a superconducting quantum interference device (SQUID).
  • SQUID superconducting quantum interference device
  • Magnetic fields generated by the flux bias line 112 connected to the qubit extend to the SQUID (i.e. current in the flux bias line 112 create magnetic fields around the SQUID), which in turn tunes the frequency of the qubit.
  • a SQUID could include only one Josephson Junction, or a transmon could be implemented with a single Josephson Junction without the
  • a single Josephson Junction without the SQUID is insensitive to magnetic fields, and thus, in such an implementation, flux bias lines 112 may not be used to control the frequency of the transmon.
  • FIGs. 1A and IB illustrate examples of quantum circuits comprising only two qubits 102, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure.
  • At least some of the one or more qubits 102 shown in FIGs. 1A-1C may comprise Josephson Junction structures fabricated using the Damascene fabrication approach as described herein.
  • quantum circuits such as the one shown in FIGs. 1A-1B may be used to implement components associated with a quantum integrated circuit (IC).
  • IC quantum integrated circuit
  • Such components may include those that are mounted on or embedded in a quantum IC, or those connected to a quantum IC.
  • the quantum IC may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the integrated circuit.
  • the integrated circuit may be employed as part of a chipset for executing one or more related functions in a quantum system.
  • FIG. 2 provides an illustration of quantum computing device, e.g. a quantum computer, 200, according to some embodiments of the present disclosure.
  • the computing device 200 may be any electronic device that processes quantum information.
  • the computing device 200 may include a number of components, including, but not limited to, a quantum processor 202, a memory 204, and a cryogenic apparatus 206, as shown in FIG. 2.
  • Each of the quantum processor 202 and the memory 204 may include one or more quantum circuits comprising suspended Josephson Junction structures as described herein, e.g. quantum circuits and Josephson Junctions as illustrated in FIGs. 1A- 1C.
  • the processor 202 may be a universal quantum processor or a specialized quantum processor configured to run quantum simulations, or one or more of particular quantum algorithms.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processor 202 may be configured to execute algorithms that may be particularly suitable for quantum computers, such as e.g. cryptographic algorithms that utilize prime factorization, algorithms to optimize chemical reactions, or protein folding algorithms.
  • processor may refer to any device or portion of a device that processes quantum information.
  • the computing device 200 may include other components not shown in FIG. 2, such as e.g. one or more of a controller, I/O channels/devices, supplementary microwave control electronics, multiplexer, signal mixers, a user interface, as well as other quantum devices such as e.g. quantum amplifiers, quantum sensors, which quantum devices may also implement certain embodiments of the present dislcosure.
  • a controller e.g. one or more of a controller, I/O channels/devices, supplementary microwave control electronics, multiplexer, signal mixers, a user interface, as well as other quantum devices such as e.g. quantum amplifiers, quantum sensors, which quantum devices may also implement certain embodiments of the present dislcosure.
  • the computing device 200 may be included within a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an
  • the computing device 200 may be any other quantum electronic device that processes data by utilizing quantum mechanical phenomena.
  • evaporation/evaporation reflects the fact that the method involves metal deposition, typically carried out metal evaporation, at two different angles of incidence with respect to the substrate (hence, double-angle).
  • the name further reflects the fact that metal deposition is performed through a hanging photoresist mask which casts a shadow on at least a part of the substrate, obscuring metal deposition on that part (hence, shadow evaporation/evaporation).
  • FIGs. 3A-3C provide a schematic illustration of one example of a photoresist mask 300 provided over a substrate 302 for fabricating Josephson Junctions using a double-angle shadow evaporation approach, according to some embodiments of the present disclosure.
  • Each of FIGs. 3A-3C provides a view of the same photoresist mask 300 over the substrate 302, but perspectives of these views are different.
  • FIG. 3A provides a top-down view (i.e. a view from a point above the substrate 302).
  • FIG. 3B provides a cross-sectional view with a cross-section of the structure of FIG. 3A taken along a horizontal dashed line shown in FIG. 3A.
  • FIG. 3A provides a top-down view (i.e. a view from a point above the substrate 302).
  • FIG. 3B provides a cross-sectional view with a cross-section of the structure of FIG. 3A taken along a horizontal dashed line shown in FIG. 3A.
  • FIG. 3A provides
  • FIG. 3C provides a cross-sectional view with a cross-section of the structure of FIG. 3A taken along a vertical dashed line shown in FIG. 3A.
  • a legend provided within a dashed box at the bottom of FIGs. 3A-3C illustrates patterns used to indicate different elements shown in FIGs. 3A-3C, so that the FIGs are not cluttered by many reference numerals.
  • Josephson Junctions may be created by a double-angle shadow evaporation approach using a two-layer photoresist mask 300 that includes a bottom photoresist layer 304 and a top photoresist layer 306 as shown in FIGs. 3A-3C.
  • the bottom layer 306 is undercut from the top layer 304 in that some portions of the top layer 304 hang, or are suspended, over the bottom layer 306.
  • the bottom layer 306 is undercut in such a manner that the top layer 304 of photoresist forms a suspended bridge 308, known as a Dolan bridge, over a section of the substrate 302. Ways for fabricating such undercuts in photoresist are well-known in the art of photolithographic processing and, therefore, are not described here in detail.
  • metals are then deposited through the photoresist mask 300 with the suspended bridge. Conventionally, this is done as illustrated in FIGs. 4A-4C.
  • FIG. 4C illustrates a result of different subsequent fabrication steps.
  • FIG. 4C provides two views of the same structure.
  • the view on the right side of FIG. 4C is a top- down view (i.e. a view similar to that shown in FIG. 3A).
  • the view on the left side of FIG. 4C is a cross-sectional view with a cross-section of the structure of FIG. 4C taken along a horizontal dashed line shown in FIG. 4C (i.e. a view similar to that shown in FIG. 3B).
  • FIGs. 4A and 4B only provide a cross-sectional view similar to that of the left side of FIG. 4C but at an earlier fabrication step. Similar to FIGs.
  • FIGs. 3A-3C a legend provided within a dashed box at the bottom of FIGs. 4A-4C and at the bottom of FIGs. 5A-5G illustrates patterns used in the FIGs. to indicate different elements shown in FIGs. 4A-4C.
  • similar reference numerals in FIGs. 3A-3C, FIGs. 4A-4C, and FIGs. 5A-5G are used to illustrate analogous elements in the figures.
  • reference numerals 302, 402, and 502 shown, respectively, in FIGs. 3, 4, and 5 refer to a substrate, reference numerals 304 and 404 - to a bottom mask layer, reference numerals 414 and 514 - to a Josephson Junction, and so on.
  • a Josephson Junction comprises a thin layer of insulator sandwiched between two layers of superconductors, the insulating layer acting as the barrier in a superconducting tunnel junction.
  • a device is fabricated by, first, depositing a layer of a first superconductor 410 on the substrate 402, as shown in FIG. 4A, through the two-layer mask such as e.g. the one shown in FIGs. 3A-3C.
  • the first superconductor is deposited at an angle with respect to the substrate 402, as shown in FIG. 4A with an angle ⁇ 1.
  • Slanted dotted- dashed lines in FIG. 4A illustrate the direction of deposition of the first superconductor 410.
  • a layer of the first superconductor 410 may have a thickness between e.g. 10 and 300 nm, preferably between 40 and 100 nm.
  • the first superconductor 410 forms a base electrode of the future Josephson Junction.
  • a layer of insulator is then provided over the first superconductor 410 to form a tunnel barrier of the future Josephson Junction.
  • the tunnel barrier is formed by oxidizing the first superconductor 410, thus creating a layer of first superconductor oxide on its surface.
  • Such an oxide may have a thickness between e.g. 1 and 5 nm, typically for qubit applications between 2 and 3 nm.
  • the superconductor 412 is deposited through the mask but at a different angle with respect to the substrate 402 than ⁇ 1.
  • FIG. 4B illustrates the second angle as an angle ⁇ 2 and slanted dotted-dashed lines in FIG. 4B illustrate the direction of deposition of the second superconductor 412.
  • the first and the second superconductors 410, 412 are deposited at the opposite angles, if measured with respect to a normal to the substrate 402.
  • the second superconductor 420 is aluminum because the first superconductor must be aluminum, as described above.
  • a layer of the second superconductor 412 may have a thickness between e.g. 10 and 300 nm, typically between 40 and 100 nm.
  • the second superconductor 412 forms a counter electrode (i.e. counter to the base electrode formed by the first superconductor 410) of the future Josephson Junction.
  • the first and second superconductors 410, 412 are usually deposited using a non- conformal process, such as e.g. evaporative deposition. After deposition of the second superconductor 412, the deposition mask is removed, removing with it any first and/or second superconductor 410, 412 deposited on top of it.
  • a non- conformal process such as e.g. evaporative deposition.
  • Lift-off is a type of an additive technique, as opposed to subtracting techniques like etching, and may be applied in cases where a direct etching of structural material would have undesirable effects on one or more layers below.
  • the resulting Josephson Junction is left on the substrate 402 as shown in FIG. 4C as a Junction 414.
  • the Junction 414 is formed by the small region of overlap under the photoresist bridge 408 (i.e. the area under the bridge 408 where the first superconductor 410, covered with a layer of a thin insulating material is overlapped by the second superconductor 412).
  • Dimensions of the Junction 414 along x- axis and y-axis, shown in FIG. 4C as d x and d y , respectively, are typically between 50 and 1000 nm for any of d x and d y .
  • junctions of the first and second superconductors may also formed on each side of the Josephson Junction 414, such junctions shown in FIGs. 4B and 4C as Junctions 416.
  • junctions are of much larger dimensions than the Josephson Junction 414, e.g. measured several thousands of nm in the x-direction and hundreds of nm or more in the y-direction, they are essentially infinite for the Josephson effect to take place and, therefore, act as superconductors rather than Josephson Junctions.
  • One problem with the fabrication approach described above is that it includes steps that are not manufacturable at the larger wafer sizes used in the semiconductor industry. For example, evaporation step does not produce a uniform film across the wafer and would prohibit uniform qubit performance across large area. Moreover, the fabrication approach described above relies on lift-off of metal films to produce wires remaining on the wafer. The lift-off technique is not amenable to the chemical waste systems of wafer cleaning tools and would not facilitate high volume manufacturing.
  • Embodiments of the present disclosure are based on an insight that fabricating Josephson Junctions using techniques similar to those employed in large scale
  • embodiments of the present disclosure are further based on recognition that issues unique to quantum circuits have to be taken in consideration when evaluating applicability of conventional integrated circuit fabrications techniques to building quantum circuits, and, in particular, Josephson Junctions.
  • FIGs. 5A-5G provide a schematic illustration of Damascene fabrication of Josephson Junctions, according to some embodiments of the present disclosure.
  • the fabrication process described below improves on some of the challenges of the existing fabrication approaches described above.
  • the Damascene fabrication process described herein is manufacturable.
  • employing such fabrication process allows encapsulating some of the defects in areas that are further from Josephson Junctions compared to Junctions fabricated using the double-angle shadow evaporation approach, thus reducing the amount of spurious TLS's in the vicinity of Josephson Junctions.
  • using the Damascene fabrication process as described herein advantageously extends the arsenal of superconducting materials that may be employed as base and top electrodes of Josephson Junctions to include those besides Al.
  • FIGs. 5A-5G illustrates a result of different subsequent fabrication steps by providing a cross-sectional view with a cross-section of the structure of these figures taken as described above with reference to the view shown on the left side of FIGs. 4A-4).
  • FIGs. 5A-5G will now be described with reference to FIG. 6 providing a flow chart of a method 600 for Damascene fabrication of Josephson Junctions, according to some embodiments of the present disclosure, which method could be used for fabricating the structures of FIGs. 5A-5G.
  • superconducting materials that may be used as the SC layer 518 include, but are not limited to aluminum (Al), niobium (Nb), niobum nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TiN), molybdenum rhenium (MoRe), etc., or any alloy of two or more superconducting materials.
  • Al aluminum
  • Nb niobium
  • NbN niobum nitride
  • NbTiN niobium titanium nitride
  • TiN titanium nitride
  • MoRe molybdenum rhenium
  • any kind of photoresist patterning techniques as known in the art may be used for creating the patterned SC layer 518 as shown in FIG. 5A.
  • patterning includes depositing a layer of photoresist over the substrate 502.
  • the photoresist may be a positive or negative resist and may include for example, poly(methyl methacrylate), poly(methyl glutarimide), DNQ/novolac, or SU-8 (an expoxy based negative resist).
  • the photoresist may be deposited by a casting process such as, for example, spin-coating. Spin coating may be performed at 1 to 10,000 rpm, including all values and ranges therein, for a time period in the range of 1 second to 10 seconds, including all values and ranges therein.
  • the photoresist may then be patterned by optically projecting an image of a desired pattern onto the photoresist using photolithography, such as optical photolithography, immersion photolithography, deep UV lithography, extreme UV lithography, or other techniques, wherein the wavelength of projected light may be up to 436 nm, including all values and ranges from 157 nm to 436 nm, such as 157 nm, 193 nm, 248 nm, etc.
  • photolithography such as optical photolithography, immersion photolithography, deep UV lithography, extreme UV lithography, or other techniques, wherein the wavelength of projected light may be up to 436 nm, including all values and ranges from 157 nm to 436 nm, such as 157 nm, 193 nm, 248 nm, etc.
  • a developer such as tetramethylammonium hydroxide TMAH (with or without surfactant) at a concentration of in the range of 0.1 N to 0.3 N, may be applied to the photoresist, such as by spin-coating, and portions of the photoresist are removed to expose regions of the underlying substrate 502 correlating to the desired pattern.
  • TMAH tetramethylammonium hydroxide
  • baking of the substrate 502 may occur before or after any of the above actions.
  • the substrate 502 may be prebaked to remove surface water.
  • prebaking may be performed at a temperature in the range of 200° C to 400° C, including all values and ranges therein, for a time of 30 to 60 minutes, including all values and ranges therein.
  • a post application bake may occur, wherein at least a portion of the solvents in the photoresist are driven off.
  • a post application bake is, for example, performed at temperatures in the range of 70° C to 140° C, including all values and ranges therein, for a time period in the range of 60 seconds to 240 seconds, including all values and ranges therein.
  • the resist may be hard baked at a temperature in the range of 100° C to 300° C, including all values and ranges therein, for a time period of 1 minute to 10 minutes, including all values and ranges therein.
  • one or more superconducting materials of the SC layer 518 may be deposited through the patterned photoresist, i.e. the superconducting materials will be deposited in the openings of the patterned photoresist, isolating a portion of the SC layer 518 in one opening from portions in other openings that may be formed in the photoresist both physically and electrically.
  • the cross-section shown in FIG. 5A illustrates 3 such portions of the patterned SC layer 518.
  • any other number of portions and any suitable patterns of the SC layer may be used.
  • deposition of the one or more superconducting materials of the SC layer 518 may be performed using a conformal coating process, wherein the superconducting material is deposited on any exposed surface of the patterned photoresist layer, including on the sidewalls and bottom of any opening formed in the patterned photoresist layer.
  • a conformal coating may, therefore, be understood as a coating that is applied to exposed surfaces of the patterned photoresist layer, and not, for example, just to horizontal surfaces.
  • the coating may exhibit a variation in thickness of less than 35%, including all values and ranges from 1% to 35%, such as 10% or less, 15% or less, 20% of less, 25% or less, etc.
  • the conformal coating process may be selected from processes such as chemical vapor deposition or atomic layer deposition. Other processes that may be used include physical vapor deposition such as, magnetron sputtering, evaporative deposition or e-beam deposition.
  • one or more reactive gases are provided in a chamber including the patterned photoresist layer at a flow rate of 5 seem to 500 seem, including all values and ranges therein.
  • the reactive gas may be selected from one or more of the following: pentakis(dimethylamino)tantalum,
  • the reactive gas may be provided with a carrier gas, such as an inert gas, which may include, for example, argon.
  • the chamber may be maintained at a pressure in the range of 1 mTorr to 100 mTorr, including all values and ranges therein, and a temperature in the range of 100° C to 500° C, including all values and ranges therein.
  • the process may be plasma assisted where electrodes are provided within the process chamber and are used to ionize the gases.
  • plasma may be formed outside of the chamber and then supplied into the chamber. In the chamber, a layer of the metal is deposited on the surface of the patterned photoresist layer due to reaction of the gas.
  • a workpiece i.e. the substrate with the patterned photoresist layer
  • a reactive gas such nitrogen
  • An inert gas such as argon
  • the base pressure of the process chamber may be in the range of 10 ⁇ 8 torr and held at a pressure in the range of 10 "7 to 10 "1 torr during sputtering, such as in the range of 1 millitorr to 10 millitorr, or 2.5 millitorr.
  • the process chamber may be maintained at a temperature in the range of 10° C to 100° C, including all values and ranges therein, such as in the range of 10° C to 20° C or 17° C.
  • a metal target may be positioned in the process chamber and formed of a suitable superconducting metal.
  • the metal target may be biased by a DC sources rated in the range of -50 V to -1000 V, including all values and ranges therein.
  • the workpiece, or worktable may also be biased by an AC source rated in the range of -50 V to -100 V including all values and ranges therein, such as -70 to -80 V.
  • a plasma forms and is localized around the target due to magnets positioned proximal to or behind the target.
  • the plasma bombards the target sputtering away the metal atoms as a vapor, which is then deposited on the workpiece.
  • the process may continue for a time period in the range of 1 second to 100 seconds.
  • the remaining photoresist may be removed via a process such as ashing, wherein the photoresist is exposed to oxygen or fluorine, which combines with the photoresist to form ash.
  • dielectric 520 is deposited over the patterned SC layer (box 604 in FIG. 6), as shown in FIG. 5B. Since this dielectric surrounds the patterns of the SC layer it is referred to herein as a "surrounding dielectric" in order to differentiate it from the dielectric/insulating material forming the tunnel barrier of the Josephson Junction formed by the method 600.
  • etching properties of potential candidate materials are to be considered when selecting a suitable material to be used as the surrounding dielectric 520. Besides appropriate etching characteristics, some other considerations in selecting a suitable material may include e.g. possibilities of smooth film formation, low shrinkage and outgassing, and good dielectric properties (such as e.g. low electrical leakage, suitable value of a dielectric constant, and thermal stability).
  • dielectric materials that may be used as the surrounding dielectric 520 include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as
  • silsesquioxane siloxane
  • organosilicate glass silsesquioxane, siloxane, or organosilicate glass.
  • the surrounding dielectric 520 may be provided as an oxide deposited over the pattered SC layer 518 using e.g. chemical vapor deposition, spin-on, or atomic layer deposition techniques as known in the art.
  • the surrounding dielectric 520 may include a dielectric material formed over the pattered SC layer 518 using coating techniques involving cross-linking of liquid precursors into solid dielectric materials.
  • the surrounding dielectric 520 is etched to form at least one via opening 522, as shown in FIG. 5C, defining a location of the future Josephson Junction (box 606 in FIG. 6).
  • a patterning technique such as e.g. described above may be used in order to define location of the via opening in the surrounding dielectric layer 520.
  • the via opening is to be formed over one portion of the patterned SC layer 518 (in FIG. 5C - over the middle portion out of the three portions of the patterned SC layer 518 shown in the figure), with the via opening extending all the way to and exposing the patterned SC layer 518.
  • a via opening may be formed that is e.g. about 20 nm in the dimensions in the x-y plane shown in FIGs. 5A-5G and 50 nm or greater, possibly much greater, in the dimension in the z-axis. In principle, any dimensions are possible and are within the scope of the present disclosure.
  • the remaining photoresist may then be removed, e.g. using the ashing process as described above.
  • a Josephson Junction is formed within the via opening by depositing, within the via opening, a first superconductor 510 forming the base layer of the Josephson Junction (box 608), followed by depositing a barrier dielectric 524 forming the tunnel barrier of the Josepshson Junction (box 610), and concluding with depositing a second
  • any deposition methods for depositing the first superconductor 510, the barrier dielectric 524, and the second superconductor 512 may be employed. For example, CVD, PVD, or ALD may be used to deposit each of these materials.
  • one or more of the first superconductor 510, the barrier dielectric 524, and the second superconductor 512 may be deposited by atomic level growth, e.g. using epitaxial growth, from gaseous or liquid precursors.
  • Inventors of the present disclosure have recognized that double-angle shadow evaporation approach may lead to variations in thicknesses of the superconducting and dielectric layers of the resulting Josepshon Junctions, as previously described herein.
  • Employing atomic level growth to form these layers in Josephson Junctions advantageously allows providing controlled layers (e.g. with tightly controlled thicknesses) of specific materials that do not intermix.
  • Another advantage of atomic level growth is that it allows forming Josephson Junctions using refractory and/or noble metals, or nitrides or carbides thereof that act as superconductors at certain low temperatures as base and top electrodes.
  • examples of such materials include TiN, NbTiN, ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au).
  • any suitable superconducting materials that may be grown using atomic level growth such as e.g. Nb, NbN, NbTiN, TiN, MoRe, may be used for base and/or top electrodes of the Damascene fabrication of the method 600.
  • One advantage of having an increased arsenal of superconducting materials to choose from for the base and top electrodes of a Josephson Junction is that it gives the possibility to use metals that do not easily oxidize or corrode (i.e. noble metals) and/or metals that exhibit resistance to changing under high temperatures (i.e. refractory materials), the latter allowing the materials to be used in fabrication processes that require higher temperatures.
  • Dielectric materials that may be grown either by chemical vapor deposition (CVD) or by atomic layer deposition (ALD) in the method of FIG. 6 include e.g. SiN or SiO x C y N z , where x,y,z can take on different values. Thickness of the dielectric tunnel barrier may be between e.g. 1 and 5 nm, typically for qubit applications between 2 and 3 nm.
  • the Damascene fabrication process as described above also provides another measure for improving on the problem of qubits' decoherence: the first superconductor 510 may be grown very thin, less than 5 nm thick, preferably between 2 and 3 nm thick, providing a fresh in-situ surface for the Josephson Junction and encapsulating any defects between the patterned SC layer 518 and the base electrode superconductors. Thickness of the top electrode may be between e.g. 10 and 300 nm, e.g. between 40 and 100 nm.
  • the wafer may be polished down to the surface of the surrounding dielectric 518 (not shown in FIG. 6) to provide a flat surface as shown in FIG. 5E showing that a top surface 526 of the top electrode of the Josephson Junction 514 is aligned with a top surface 528 of the surrounding dielectric 518.
  • polishing may be carried out using any of the known planarization techniques as known in the art, e.g. using either wet or dry planarization processes.
  • planarization is performed using chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface of the top electrode of the Josephson Junction 514 and the surrounding dielectric 518.
  • CMP chemical mechanical planarization
  • FIGs. 5F and 5G illustrate optional formation of an interconnect configured to provide electrical interconnection between the top electrode of the Josephson Junction 514 and a further component of the quantum circuit. Since these steps are performed after the Josephson Junction is formed, they are not shown in FIG. 6.
  • the method may continue once the top surface of the top electrode of the Josephson Junction is planarized to be in line with the surrounting dielectric 518, as was shown in FIG. 5E.
  • a via opening 530 may be formed, as shown in FIG. 5F, for providing an electrical connection to a certain quantum circuit component, such as e.g. a SQUID loop or a capacitor in case the qubit is a transmon.
  • the via opening 530 may be formed using patterning and etching techniques similar to those described above for the formation of the via opening 522.
  • a superconducting material referred to herein as a "wireup superconductor” 532 may then be deposited and patterned to the desired shape and form, as shown in FIG. 5G. To that end, deposition and patterning techniques similar to those described above may be used. In various embodiments, the wireup superconductor 532 may be formed from any of the superconducting materials described above. Such a wireup superconductor 532 forms one of the interconnects of the quantum circuit by providing electrical interconnection between the top electrode and a further component of the quantum circuit.
  • FIGs. 7A and 7B provide schematic illustrations of cross-sections of, respectively, a structure 700A comprising a Josephson Junction formed using double-angle shadow evaporation approach and a structure 700B comprising a Josephson Junction formed using Damascene fabrication approach according to some embodiments of the present disclosure.
  • reference numerals 702A and 702B shown in FIGs. 7A and 7B respectively refer to a substrate, reference numerals 710A and 710B - to the first superconductor, reference numerals 722A and 722B - to the dielectric material for the tunnel barrier, and so on.
  • FIGs. 7A and 7B are drawn to reflect example real world process limitations, in that the features are not drawn with precise right angles and straight lines.
  • FIGs. 7A and 7B represent cross-section view similar to that shown in FIGs. 4C (left side) and 5E, respectively.
  • FIGs. 7A and 7B illustrate a substrate 702, a base electrode 710, a tunnel barrier layer 722, and a top electrode 712 of the Josephson Junction.
  • FIG. 7B illustrates the patterned superconductor layer 718 and a surrounding dielectric 720.
  • the features shown in FIGs. 7A and 7B would be visible in e.g. a scanning electron microscopy (SEM) images of structures comprising Josephson Junctions.
  • SEM scanning electron microscopy
  • Comparison of the cross-sections 700A and 700B illustrates variations in surface roughness (i.e. variations in thickness) of materials forming the base and top electrodes and the dielectric of the Josephson Junction - due to atomic level deposition techniques that may be used in the Damascene process described herein, the surface roughness is greatly reduced as shown in FIG. 7B.
  • comparison of the of the cross-sections 700A and 700B illustrates that it is immediately visible that the base electrode 710B is much thinner than the base electrode 710A, that the top electrode 712B is provided only over the tunnel barrier dielectric 722B and not overflowing on the sides as in FIG. 7A, and that, due to polishing, the top surface of the top electrode 712B is nicely aligned with the top surface of the surrounding dielectric 720B.
  • Example 1 provides superconducting qubit for a quantum circuit provided over a substrate, the superconducting qubit including a Josephson Junction provided over the substrate, the Josephson Junction including a base electrode layer, a top electrode layer, and a tunnel barrier layer provided between the base electrode layer and the top electrode layer, where at least one of the base electrode layer and the top electrode layer is made of a refractory and/or noble metal.
  • Example 2 provides the superconducting qubit according to Example 1, where the refractory and/or noble metal includes one or more of ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), Zirconium (Zr), Hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), Chromium (Cr), Molybdenum (Mo), tungsten (W), or/and nitrides and/or carbides of the refractory and/or noble metals that superconduct at temperatures above about 15 mK (e.g. niobium titanium nitride (NbTiN), titanium nitride (TiN), etc.).
  • Ru ruthenium
  • Rh palladium
  • Pd silver
  • Ag osm
  • Example 3 provides the superconducting qubit according to Examples 1 or 2, where a thickness of the base electrode layer is less than 10 nanometers (nm), e.g. less than 5 nm, e.g. between 2 and 4 nm.
  • Example 4 provides the superconducting qubit according to any one of the preceding Examples, where the tunnel barrier layer includes SiN or SiOxCyNz, where x, y, and z are integers.
  • the tunnel barrier layer may include stable metal oxides that act as a dielectric barrier, such as e.g. aluminum oxides or hafnium oxides.
  • Example 5 provides the superconducting qubit according to any one of the preceding Examples, where a thickness of the tunnel barrier layer is between 1 and 5 nanometers (nm).
  • Example 6 provides the superconducting qubit according to any one of the preceding Examples, where the tunnel barrier layer includes a dielectric material other than an oxide of a material of the base electrode layer.
  • Example 7 provides the superconducting qubit according to any one of the preceding Examples, where the Josephson Junction is provided in a via opening provided over the substrate, and the via opening is surrounded by a dielectric.
  • Example 8 provides the superconducting qubit according to Example 7, where an upper surface of the dielectric is aligned with an upper surface of the top electrode layer.
  • Example 9 provides the superconducting qubit according to Examples 7 or 8, where the via opening is substantially perpendicular to the substrate.
  • Example 10 provides the superconducting qubit according to any one of the preceding Examples, where the base electrode layer is provided on a patterned
  • Example 11 provides the superconducting qubit according to any one of the preceding Examples, further including an interconnect configured to provide electrical interconnection between the top electrode and a further component of the quantum circuit.
  • Example 12 provides the superconducting qubit according to Example 11, where the interconnect includes a first portion provided in a plane substantially parallel to a plane of the substrate, and where a part of the first portion is in contact with the top electrode.
  • Example 13 provides the superconducting qubit according to Examples 11 or 12, where the further component of the quantum circuit includes a SQUID loop.
  • Example 14 provides the superconducting qubit according to Examples 11 or 12, where the further component of the quantum circuit includes a capacitor of the superconducting qubit.
  • Example 15 provides the superconducting qubit according to any one of the preceding Examples, where the superconducting qubit is a charge qubit.
  • Example 16 provides the superconducting qubit according to any one of the preceding Examples, where the superconducting qubit is a transmon.
  • Example 17 provides the superconducting qubit according to any one of Examples 1-14, where the superconducting qubit is a flux qubit.
  • Example 18 provides a quantum integrated circuit package, including a substrate; and a first superconducting qubit and a second superconducting qubit provided over the substrate, where each of the first superconducting qubit and the a second superconducting qubit includes a Josephson Junction including a base electrode layer, a top electrode layer, and a tunnel barrier layer provided between the base electrode layer and the top electrode layer, where at least one of the base electrode layer and the top electrode layer includes a refractory and/or noble metal.
  • any of the first and the second superconducting qubits could be a superconducting qubit according to any one of the Examples above.
  • Example 19 provides the quantum integrated circuit package according to Example 18, where the first superconducting qubit and the second superconducting qubit are coupled by a coupling resonator.
  • Example 20 provides a quantum computing device, including one or more integrated circuit packages according to Examples 18 or 19.
  • Example 21 provides the quantum computing device according to Example 20, further including a cryogenic apparatus configured to maintain the first superconducting qubit and the second superconducting qubit at a cryogenic temperature during operation of the first superconducting qubit and the second superconducting qubit.
  • the quantum computing device may include
  • Example 22 provides a method for fabricating at least a Josephson Junction of a superconducting qubit, the method including depositing a first layer of superconductor over a substrate to form a base electrode of the Josephson Junction; providing a layer of barrier dielectric on the first layer of superconductor, to form a tunnel barrier layer of the Josephson Junction; and depositing a second layer of superconductor on the layer of barrier dielectric, to form a top electrode of the Josephson Junction. At least one of the first layer of superconductor and the second layer of superconductor includes a refractory and/or noble metal.
  • Example 23 provides the method according to Example 22, where the refractory and/or noble metal includes one or more of ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), Zirconium (Zr), Hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), Chromium (Cr), Molybdenum (Mo), tungsten (W), or/and nitrides and/or carbides of the refractory and/or noble metals.
  • Example 24 provides the method according to Examples 22 or 23, where the layer of barrier dielectric includes SiN or SiOxCyNz, where x, y, and z are integers, or an oxide of the refractory and/or noble metal.
  • Example 25 provides the method according to any one of Examples 22-24, further including, prior to depositing the first layer of superconductor, providing a patterned superconductor layer over the substrate; providing a layer of surrounding dielectric over the patterned superconductor layer; providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer, where depositing the first layer of superconductor includes depositing the first layer of superconductor in the via opening.
  • Example 26 provides the method according to Example 25, where the layer of barrier dielectric and the second layer of superconductor are deposited in the via opening.
  • Example 27 provides the method according to Examples 25 or 26, further including providing a further via opening in the layer of surrounding dielectric over a second portion of the patterned superconductor layer, the second portion being electrically disconnected from the first portion; and depositing a wireup superconductor in the further via opening and over the second layer of superconductor in the via opening.
  • Example 28 provides the method according to Example 27, patterning the wireup superconductor to form an interconnect configured to provide electrical interconnection between the top electrode and the second portion of the patterned superconductor layer.
  • Example 29 provides the method according to Example 28, where the second portion of the patterned superconductor layer includes or is electrically connected to a further component of the quantum circuit.
  • Example 30 provides the method according to Example 29, where the further component of the quantum circuit includes a SQUID loop.
  • Example 31 provides the method according to Example 29, where the further component of the quantum circuit includes a capacitor of the superconducting qubit.
  • Example 32 provides the method according to any one of Examples 27-31, where the further via opening is provided after the top electrode of the Josephson Junction is formed.
  • Example 33 provides the method according to any one of Examples 22-32, further including polishing the second layer of superconductor until an upper surface of the second layer of superconductor is aligned with an upper surface of the layer of surrounding dielectric.
  • Example 34 provides the method according to any one of Examples 22-33, where depositing the first layer of superconductor and/or the first layer of superconductor includes deposition by atomic level growth.
  • Example 35 provides the method according to any one of Examples 22-34, where providing the layer of barrier dielectric includes depositing the layer of barrier dielectric by atomic level growth.

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Abstract

L'invention concerne des structures qui comprennent des jonctions Josephson (JJ) destinées à être utilisées dans des bits quantiques supraconducteurs de circuits quantiques disposés sur un substrat. Les JJ de ces structures sont fabriquées à l'aide d'une approche qui permet une large sélection de matériaux appropriés pour être utilisés dans des JJ, et qui peut être utilisée efficacement dans la fabrication à grande échelle. Ainsi, les techniques de fabrication proposées offrent une amélioration importante par rapport aux approches classiques, telles que, par exemple, une approche d'évaporation sous angle double, qui sont limitées dans leur choix de matériaux et comprennent des étapes de fabrication qui ne peuvent pas être appliquées aux plus grandes tailles de tranche utilisées par des fabricants de dispositifs de pointe. Dans un aspect de la présente invention, les jonctions Josephson ainsi obtenues peuvent comprendre des électrodes de base et/ou supérieures constituées de métaux réfractaires et/ou nobles. En outre, des couches de barrière tunnel de telles jonctions Josephson ne sont pas limitées à des oxydes des matériaux d'électrode.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199554B2 (en) 2015-04-30 2019-02-05 International Business Machines Corporation Trilayer Josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits
WO2019101448A1 (fr) * 2017-11-27 2019-05-31 International Business Machines Corporation Couplage de côté arrière avec tsv partiels supraconducteurs pour bits quantiques transmon
WO2019125498A1 (fr) * 2017-12-23 2019-06-27 Intel Corporation Intégration à l'échelle de tranche de jonctions josephson à base de semi-conducteur
WO2019179732A1 (fr) * 2018-03-23 2019-09-26 International Business Machines Corporation Dispositif supraconducteur à jonction josephson verticale
WO2019179733A1 (fr) * 2018-03-23 2019-09-26 International Business Machines Corporation Dispositif à qubit transmon vertical avec guides d'ondes à microruban
WO2019179731A1 (fr) * 2018-03-23 2019-09-26 International Business Machines Corporation Dispositif de qubit transmon vertical
WO2019224155A1 (fr) * 2018-05-25 2019-11-28 International Business Machines Corporation Intégration tridimensionnelle pour bits quantiques sur un diélectrique cristallin à hauteur multiple
US10497746B1 (en) 2018-05-25 2019-12-03 International Business Machines Corporation Three-dimensional integration for qubits on crystalline dielectric
US10763420B2 (en) 2016-06-13 2020-09-01 Intel Corporation Josephson Junction damascene fabrication
US10803396B2 (en) 2018-06-19 2020-10-13 Intel Corporation Quantum circuit assemblies with Josephson junctions utilizing resistive switching materials
US11024792B2 (en) 2019-01-25 2021-06-01 Microsoft Technology Licensing, Llc Fabrication methods
WO2021170251A1 (fr) * 2020-02-28 2021-09-02 Microsoft Technology Licensing Llc Murs d'écran destinés à être utilisés dans des dispositifs de fabrication
US11121304B2 (en) 2019-11-14 2021-09-14 International Business Machines Corporation Junction fabrication method for forming qubits
US11174545B2 (en) 2019-11-06 2021-11-16 International Business Machines Corporation Oblique deposition for quantum device fabrication
JP2022528971A (ja) * 2019-04-17 2022-06-16 インターナショナル・ビジネス・マシーンズ・コーポレーション 縦型スーパーインダクタ・デバイス

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018004634A1 (fr) 2016-07-01 2018-01-04 Intel Corporation Lignes de polarisation de flux au-dessous d'un plan qubit
US10770545B2 (en) 2016-08-30 2020-09-08 Intel Corporation Quantum dot devices
US11075293B2 (en) 2016-09-24 2021-07-27 Intel Corporation Qubit-detector die assemblies
US10804399B2 (en) 2016-09-24 2020-10-13 Intel Corporation Double-sided quantum dot devices
EP3516699A4 (fr) 2016-09-24 2020-06-17 INTEL Corporation Dispositifs à réseaux de points quantiques avec grilles partagées
US11288586B2 (en) 2016-09-27 2022-03-29 Intel Corporation Independent double-gate quantum dot qubits
WO2018063270A1 (fr) 2016-09-30 2018-04-05 Intel Corporation Dispositifs à points quantiques ayant des détecteurs à transistor à électron unique
EP3520143A4 (fr) 2016-09-30 2020-06-17 INTEL Corporation Agencements de transistors à électron unique (ensembles) et de détecteurs de bits quantiques basés sur un ensemble
US11063040B2 (en) 2016-11-03 2021-07-13 Intel Corporation Quantum dot devices
EP3563308A1 (fr) 2016-12-27 2019-11-06 Intel Corporation Boîtiers de dispositif à bits quantiques supraconducteurs
US11063138B2 (en) 2017-06-24 2021-07-13 Intel Corporation Quantum dot devices
WO2018236405A1 (fr) 2017-06-24 2018-12-27 Intel Corporation Dispositifs à points quantiques
US11038021B2 (en) 2017-06-24 2021-06-15 Intel Corporation Quantum dot devices
US11557630B2 (en) 2017-09-28 2023-01-17 Intel Corporation Quantum dot devices with selectors
WO2019066840A1 (fr) 2017-09-28 2019-04-04 Intel Corporation Structures d'empilement de puits quantique pour dispositifs à points quantiques
WO2019117977A1 (fr) 2017-12-17 2019-06-20 Intel Corporation Structures d'empilement de puits quantique pour dispositifs à points quantiques
US11444188B2 (en) 2017-12-21 2022-09-13 Intel Corporation Quantum dot devices
WO2019125499A1 (fr) 2017-12-23 2019-06-27 Intel Corporation Motifs hexagonaux pour dispositifs á points quantiques
WO2019125501A1 (fr) 2017-12-23 2019-06-27 Intel Corporation Dispositifs à points quantiques
WO2019132963A1 (fr) 2017-12-29 2019-07-04 Intel Corporation Ensembles d'informatique quantique
US11417755B2 (en) 2018-01-08 2022-08-16 Intel Corporation Differentially strained quantum dot devices
US10847705B2 (en) 2018-02-15 2020-11-24 Intel Corporation Reducing crosstalk from flux bias lines in qubit devices
US11177912B2 (en) 2018-03-06 2021-11-16 Intel Corporation Quantum circuit assemblies with on-chip demultiplexers
US11355623B2 (en) 2018-03-19 2022-06-07 Intel Corporation Wafer-scale integration of dopant atoms for donor- or acceptor-based spin qubits
US11183564B2 (en) 2018-06-21 2021-11-23 Intel Corporation Quantum dot devices with strain control
US11417765B2 (en) 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US10910488B2 (en) 2018-06-26 2021-02-02 Intel Corporation Quantum dot devices with fins and partially wrapped gates
US11335778B2 (en) 2018-06-26 2022-05-17 Intel Corporation Quantum dot devices with overlapping gates
US10879446B2 (en) 2018-08-14 2020-12-29 Intel Corporation Vertical flux bias lines coupled to vertical squid loops in superconducting qubits
US11424324B2 (en) 2018-09-27 2022-08-23 Intel Corporation Multi-spacers for quantum dot device gates
US11616126B2 (en) 2018-09-27 2023-03-28 Intel Corporation Quantum dot devices with passive barrier elements in a quantum well stack between metal gates
US11450765B2 (en) 2018-09-27 2022-09-20 Intel Corporation Quantum dot devices with diodes for electrostatic discharge protection
US11749721B2 (en) 2018-09-28 2023-09-05 Intel Corporation Gate walls for quantum dot devices
US11658212B2 (en) 2019-02-13 2023-05-23 Intel Corporation Quantum dot devices with conductive liners
US11699747B2 (en) * 2019-03-26 2023-07-11 Intel Corporation Quantum dot devices with multiple layers of gate metal
US11682701B2 (en) 2019-03-27 2023-06-20 Intel Corporation Quantum dot devices
US11011693B2 (en) 2019-06-24 2021-05-18 Intel Corporation Integrated quantum circuit assemblies for cooling apparatus
US11957066B2 (en) 2019-09-04 2024-04-09 Intel Corporation Stackable in-line filter modules for quantum computing
US11387324B1 (en) 2019-12-12 2022-07-12 Intel Corporation Connectivity in quantum dot devices
US11563162B2 (en) * 2020-01-09 2023-01-24 International Business Machines Corporation Epitaxial Josephson junction transmon device
CN113517386B (zh) * 2020-08-06 2022-05-31 阿里巴巴集团控股有限公司 约瑟夫森结、约瑟夫森结的制备方法、装置及超导电路
EP4009387B1 (fr) 2020-12-07 2023-06-07 IQM Finland Oy Procédé de fabrication de jonction josephson
CN116940217A (zh) * 2022-03-29 2023-10-24 腾讯科技（深圳）有限公司 约瑟夫森结制备方法及生产线设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110175061A1 (en) * 2010-01-15 2011-07-21 Berkley Andrew J Systems and methods for superconducting integrated circuits
US20140357493A1 (en) * 2011-11-11 2014-12-04 Northrop Grumman Systems Corporation Quantum bits and methods of forming the same
US20150236235A1 (en) * 2014-02-14 2015-08-20 D-Wave Systems Inc. Systems and methods for fabrication of superconducting circuits
US20160093790A1 (en) * 2014-09-26 2016-03-31 International Business Machines Corporation Diamond substrates for superconducting quantum circuits
US20160148112A1 (en) * 2014-11-25 2016-05-26 Samsung Electronics Co., Ltd. Multi-qubit coupling structure

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6885325B2 (en) * 2002-05-24 2005-04-26 D-Wave Systems, Inc. Sub-flux quantum generator
US7893708B2 (en) * 2007-08-03 2011-02-22 Northrop Grumman Systems Corporation Quantum gate operations with a common coupled resonator
US10467544B2 (en) * 2015-12-31 2019-11-05 International Business Machines Corporation Multi-qubit tunable coupling architecture using fixed-frequency superconducting qubits

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110175061A1 (en) * 2010-01-15 2011-07-21 Berkley Andrew J Systems and methods for superconducting integrated circuits
US20140357493A1 (en) * 2011-11-11 2014-12-04 Northrop Grumman Systems Corporation Quantum bits and methods of forming the same
US20150236235A1 (en) * 2014-02-14 2015-08-20 D-Wave Systems Inc. Systems and methods for fabrication of superconducting circuits
US20160093790A1 (en) * 2014-09-26 2016-03-31 International Business Machines Corporation Diamond substrates for superconducting quantum circuits
US20160148112A1 (en) * 2014-11-25 2016-05-26 Samsung Electronics Co., Ltd. Multi-qubit coupling structure

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11133452B2 (en) 2015-04-30 2021-09-28 International Business Machines Corporation Trilayer Josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits
US10199554B2 (en) 2015-04-30 2019-02-05 International Business Machines Corporation Trilayer Josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits
US10763420B2 (en) 2016-06-13 2020-09-01 Intel Corporation Josephson Junction damascene fabrication
WO2019101448A1 (fr) * 2017-11-27 2019-05-31 International Business Machines Corporation Couplage de côté arrière avec tsv partiels supraconducteurs pour bits quantiques transmon
JP7212439B2 (ja) 2017-11-27 2023-01-25 インターナショナル・ビジネス・マシーンズ・コーポレーション 超電導部分ｔｓｖを用いたトランスモン・キュービット用の後面結合
US10446736B2 (en) 2017-11-27 2019-10-15 International Business Machines Corporation Backside coupling with superconducting partial TSV for transmon qubits
JP2021504936A (ja) * 2017-11-27 2021-02-15 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 超電導部分ｔｓｖを用いたトランスモン・キュービット用の後面結合
WO2019125498A1 (fr) * 2017-12-23 2019-06-27 Intel Corporation Intégration à l'échelle de tranche de jonctions josephson à base de semi-conducteur
JP2021518654A (ja) * 2018-03-23 2021-08-02 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 縦型トランスモン・キュービット・デバイス
CN111902941A (zh) * 2018-03-23 2020-11-06 国际商业机器公司 垂直transmon量子位器件
US10672971B2 (en) 2018-03-23 2020-06-02 International Business Machines Corporation Vertical transmon qubit device with microstrip waveguides
US10714672B2 (en) 2018-03-23 2020-07-14 International Business Machines Corporation Vertical transmon qubit device
WO2019179733A1 (fr) * 2018-03-23 2019-09-26 International Business Machines Corporation Dispositif à qubit transmon vertical avec guides d'ondes à microruban
US10784432B2 (en) 2018-03-23 2020-09-22 International Business Machines Corporation Vertical josephson junction superconducting device
JP7292781B2 (ja) 2018-03-23 2023-06-19 インターナショナル・ビジネス・マシーンズ・コーポレーション マイクロストリップ導波路を備えた縦型トランスモン・キュービット
JP2021518655A (ja) * 2018-03-23 2021-08-02 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 縦型ジョセフソン接合超電導デバイス
CN111902942A (zh) * 2018-03-23 2020-11-06 国际商业机器公司 具有微带波导的垂直transmon量子位器件
CN111937168A (zh) * 2018-03-23 2020-11-13 国际商业机器公司 垂直约瑟夫逊结超导器件
JP7362195B2 (ja) 2018-03-23 2023-10-17 インターナショナル・ビジネス・マシーンズ・コーポレーション 縦型ジョセフソン接合超電導デバイス
WO2019179732A1 (fr) * 2018-03-23 2019-09-26 International Business Machines Corporation Dispositif supraconducteur à jonction josephson verticale
US11005022B2 (en) 2018-03-23 2021-05-11 International Business Machines Corporation Vertical transmon qubit device with microstrip waveguides
WO2019179731A1 (fr) * 2018-03-23 2019-09-26 International Business Machines Corporation Dispositif de qubit transmon vertical
JP2021518652A (ja) * 2018-03-23 2021-08-02 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ マイクロストリップ導波路を備えた縦型トランスモン・キュービット
WO2019224155A1 (fr) * 2018-05-25 2019-11-28 International Business Machines Corporation Intégration tridimensionnelle pour bits quantiques sur un diélectrique cristallin à hauteur multiple
US10505096B1 (en) 2018-05-25 2019-12-10 International Business Machines Corporation Three-dimensional integration for qubits on multiple height crystalline dielectric
US11088311B2 (en) 2018-05-25 2021-08-10 International Business Machines Corporation Three-dimensional integration for qubits on multiple height crystalline dielectric
US10840296B2 (en) 2018-05-25 2020-11-17 International Business Machines Corporation Three-dimensional integration for qubits on crystalline dielectric
US10497746B1 (en) 2018-05-25 2019-12-03 International Business Machines Corporation Three-dimensional integration for qubits on crystalline dielectric
US10803396B2 (en) 2018-06-19 2020-10-13 Intel Corporation Quantum circuit assemblies with Josephson junctions utilizing resistive switching materials
US11024792B2 (en) 2019-01-25 2021-06-01 Microsoft Technology Licensing, Llc Fabrication methods
JP2022528971A (ja) * 2019-04-17 2022-06-16 インターナショナル・ビジネス・マシーンズ・コーポレーション 縦型スーパーインダクタ・デバイス
JP7427021B2 (ja) 2019-04-17 2024-02-02 インターナショナル・ビジネス・マシーンズ・コーポレーション 縦型スーパーインダクタ・デバイス
US11174545B2 (en) 2019-11-06 2021-11-16 International Business Machines Corporation Oblique deposition for quantum device fabrication
US11121304B2 (en) 2019-11-14 2021-09-14 International Business Machines Corporation Junction fabrication method for forming qubits
WO2021170251A1 (fr) * 2020-02-28 2021-09-02 Microsoft Technology Licensing Llc Murs d'écran destinés à être utilisés dans des dispositifs de fabrication

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