WO2018057023A1 - Bits quantiques à points quantiques avec des composés iii-v - Google Patents

Bits quantiques à points quantiques avec des composés iii-v Download PDF

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WO2018057023A1
WO2018057023A1 PCT/US2016/053621 US2016053621W WO2018057023A1 WO 2018057023 A1 WO2018057023 A1 WO 2018057023A1 US 2016053621 W US2016053621 W US 2016053621W WO 2018057023 A1 WO2018057023 A1 WO 2018057023A1
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quantum
fin
quantum dot
gates
gate
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PCT/US2016/053621
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Ravi Pillarisetty
Jeanette M. Roberts
Nicole K. THOMAS
Hubert C. GEORGE
James S. Clarke
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Intel Corporation
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Publication of WO2018057023A1 publication Critical patent/WO2018057023A1/fr

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122—Single quantum well structures
    • H01L29/127—Quantum box structures
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66977—Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/7613—Single electron transistors; Coulomb blockade devices
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/82—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of the magnetic field applied to the device

Definitions

  • This disclosure relates generally to the field of quantum computing, and more specifically, to quantum dot qubits using quantum wells made of lll-V compounds.
  • Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.
  • FIGS. 1-3 are cross-sectional views of a quantum dot device, in accordance with various embodiments.
  • FIGS. 4-25 illustrate various example stages in the manufacture of a quantum dot device, in accordance with various embodiments.
  • FIGS. 26-28 are cross-sectional views of various examples of quantum well stacks that may be used in a quantum dot device, in accordance with various embodiments.
  • FIGS. 29-35 illustrate example base/fin arrangements that may be used in a quantum dot device, in accordance with various embodiments.
  • FIGS. 36-38 illustrate various example stages in the manufacture of alternative gate arrangements that may be included in a quantum dot device, in accordance with various embodiments.
  • FIG. 39 illustrates an embodiment of a quantum dot device having multiple groups of gates on a single fin, in accordance with various embodiments.
  • FIGS. 40-44 illustrate various alternative stages in the manufacture of a quantum dot device, in accordance with various embodiments.
  • FIG. 45 illustrates an example alternative stage in the manufacture of a quantum dot device, in accordance with various embodiments.
  • FIGS. 46-47 illustrate detail views of various embodiments of a doped region in a quantum dot device.
  • FIG. 48 is a flow diagram of an illustrative method of manufacturing a quantum dot device, in accordance with various embodiments.
  • FIGS. 49-50 are flow diagrams of illustrative methods of operating a quantum dot device, in accordance with various embodiments.
  • FIG. 51 is a block diagram of an example quantum computing device that may include any of the quantum dot devices disclosed herein, in accordance with various embodiments.
  • quantum computing or quantum information processing, refers to the field of research related to computation systems that use quantum- mechanical phenomena to manipulate data.
  • quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states.
  • Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole.
  • quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).
  • Quantum computers use so-called quantum bits, referred to as qubits (both terms “bits” and “qubits” often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states.
  • Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.
  • quantum dot qubits are promising candidates for building a quantum computer.
  • quantum dot qubits have been employing quantum well stacks where a layer of Silicon (Si) is sandwiched between two layers of Silicon Germanium (SiGe) and serves as a quantum well layer in which charge carriers are to be confined.
  • Si Silicon
  • SiGe Silicon Germanium
  • a quantum dot device may include a base, a fin extending away from the base and including a quantum well layer made from lll-V compounds, and one or more gates disposed on the fin.
  • a quantum dot formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein.
  • Using lll-V compounds to form a quantum well layer may be advantageous compared to conventional SiGe/Si/SiGe structures for a number of reasons.
  • lll-V materials may result in quantum well layers having higher barrier offsets, leading to stronger confinement of charge carriers in the quantum well.
  • lll-V compounds may result in improved interfaces which would decrease scattering of charge carriers and increase their rate/mobility. Methods for fabricating such devices are also disclosed.
  • lll-V compounds also referred to as “lll-V semiconductors” refer to chemical compounds with at least one element from group III of the periodic table and at least one element from group V, such as e.g. gallium arsenide (GaAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), indium aluminium arsenide (InAIAs), aluminium indium antimonide (AllnSb), and aluminium gallium arsenide (AIGaAs).
  • GaAs gallium arsenide
  • InSb indium antimonide
  • InGaAs indium gallium arsenide
  • InAIAs indium aluminium arsenide
  • AllnSb aluminium indium antimonide
  • AIGaAs aluminium gallium arsenide
  • the one or more gates may include first, second, and third gates.
  • Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate.
  • the third gate may be disposed on the fin between the first and second gates and extending between the first and second spacers.
  • the quantum dot devices disclosed herein may enable the formation of quantum dots to serve as quantum bits ("qubits") in a quantum computing device, as well as the control of these quantum dots to perform quantum logic operations. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein provide strong spatial localization of the quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.
  • the terms such as “upper,” “lower,” “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • a and/or B means (A), (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
  • the notation "A/B/C” means (A), (B), and/or (C).
  • a "high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide.
  • microwaves are well known. For these reasons, typical frequencies of qubits are in 5-10 gigahertz (GHz) range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering.
  • GHz gigahertz
  • qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.
  • FIGS. 1-3 are cross-sectional views of an exemplary quantum dot device 100
  • FIG. 2 illustrates the quantum dot device 100 taken along the section A-A of FIG. 1 (while FIG. 1 illustrates the quantum dot device 100 taken along the section C-C of FIG. 2)
  • FIG. 3 illustrates the quantum dot device 100 taken along the section B-B of FIG. 1 (while FIG. 1 illustrates a quantum dot device 100 taken along the section D-D of FIG. 3).
  • FIG. 1 indicates that the cross-section illustrated in FIG. 2 is taken through the fin 104-1, an analogous cross section taken through the fin 104-2 may be identical, and thus the discussion of FIGs. 1-3 refers generally to the "fin 104.”
  • the quantum dot device 100 may include a base 102 and multiple fins 104 extending away from the base 102.
  • the base 102 and the fins 104 may include a semiconductor substrate and a quantum well stack (not shown in FIGS. 1-3, but discussed below with reference to the semiconductor substrate 144 and the quantum well stack 146), distributed in any of a number of ways between the base 102 and the fins 104.
  • the base 102 may include at least some of the semiconductor substrate, and the fins 104 may each include a quantum well layer of the quantum well stack (discussed below with reference to the quantum well layer 152). Examples of base/fin arrangements are discussed below with reference to the base fin arrangements 158 of FIGS. 29-35.
  • the total number of fins 104 included in the quantum dot device 100 is an even number, with the fins 104 organized into pairs including one active fin 104 and one read fin 104, as discussed in detail below.
  • the fins 104 may be arranged in pairs in a line (e.g., 2N fins total may be arranged in a lx2N line, or a 2xN line) or in pairs in a larger array (e.g., 2N fins total may be arranged as a 4xN/2 array, a 6xN/3 array, etc.).
  • a line e.g., 2N fins total may be arranged in a lx2N line, or a 2xN line
  • a larger array e.g., 2N fins total may be arranged as a 4xN/2 array, a 6xN/3 array, etc.
  • each of the fins 104 may include a quantum well layer (not shown in FIGS. 1-3, but discussed below with reference to the quantum well layer 152).
  • the quantum well layer included in the fins 104 may be arranged normal to the z-direction, and may provide a layer in which a two-dimensional electron gas (2DEG) may form to enable the generation of a quantum dot during operation of the quantum dot device 100, as discussed in further detail below.
  • the quantum well layer itself may provide a geometric constraint on the z-location of quantum dots in the fins 104, and the limited extent of the fins 104 (and therefore the quantum well layer) in the y-direction may provide a geometric constraint on the y-location of quantum dots in the fins 104.
  • voltages may be applied to gates disposed on the fins 104 to adjust the energy profile along the fins 104 in the x-direction and thereby constrain the x-location of quantum dots within quantum wells (discussed in detail below with reference to the gates 106/108).
  • the fins 104 may take any suitable values.
  • the fins 104 may each have a width 162 between 10 and 40 nanometers, e.g. between 20 and 40 nanometers.
  • the fins 104 may each have a height 164 between 200 and 400 nanometers (e.g., between 250 and 350 nanometers, or equal to 300 nanometers).
  • the fins 104 may be arranged in parallel, as illustrated in FIGS. 1 and 3, and may be spaced apart by an insulating material 128, which may be disposed on opposite faces of the fins 104.
  • the insulating material 128 may be a dielectric material, such as silicon oxide.
  • the fins 104 may be spaced apart by a distance 160 between 100 and 250 microns.
  • Multiple gates may be disposed on each of the fins 104.
  • three gates 106 and two gates 108 are shown as distributed on the top of the fin 104. This particular number of gates is simply illustrative, and any suitable number of gates may be used. Additionally, as discussed below with reference to FIG. 39, multiple groups of gates (like the gates illustrated in FIG. 2) may be disposed on the fin 104.
  • the gate 108-1 may be disposed between the gates 106-1 and 106-2, and the gate 108-2 may be disposed between the gates 106-2 and 106-3.
  • Each of the gates 106/108 may include a gate dielectric 114; in the embodiment illustrated in FIG. 2, the gate dielectric 114 for all of the gates 106/108 is provided by a common layer of gate dielectric material. In other embodiments, the gate dielectric 114 for each of the gates 106/108 may be provided by separate portions of gate dielectric 114 (e.g., as discussed below with reference to FIGS. 40-44).
  • the gate dielectric 114 may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the fin 104 and the corresponding gate metal).
  • the gate dielectric 114 may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric 114 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • Examples of materials that may be used in the gate dielectric 114 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric 114 to improve the quality of the gate dielectric 114.
  • Each of the gates 106 may include a gate metal 110 and a hardmask 116.
  • the hardmask 116 may be formed of silicon nitride, silicon carbide, or another suitable material.
  • the gate metal 110 may be disposed between the hardmask 116 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 110 and the fin 104. Only one portion of the hardmask 116 is labeled in FIG. 2 for ease of illustration.
  • the gate metal 110 may be a superconductor, such as aluminum, molybdenum rhenium, titanium nitride, niobium nitride, or niobium titanium nitride, e.g.
  • the hardmask 116 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 116 may be removed during processing, as discussed below).
  • the sides of the gate metal 110 may be substantially parallel, as shown in FIG. 2, and insulating spacers 134 may be disposed on the sides of the gate metal 110 and the hardmask 116. As illustrated in FIG. 2, the spacers 134 may be thicker closer to the fin 104 and thinner farther away from the fin 104. In some embodiments, the spacers 134 may have a convex shape.
  • the spacers 134 may be formed of any suitable material, such as a carbon- doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride).
  • the gate metal 110 may be any suitable metal, such as titanium nitride.
  • Each of the gates 108 may include a gate metal 112 and a hardmask 118.
  • the hardmask 118 may be formed of silicon nitride, silicon carbide, or another suitable material.
  • the gate metal 112 may be disposed between the hardmask 118 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 112 and the fin 104.
  • the hardmask 118 may extend over the hardmask 116 (and over the gate metal 110 of the gates 106), while in other embodiments, the hardmask 118 may not extend over the gate metal 110 (e.g., as discussed below with reference to FIG. 45).
  • the gate metal 112 may be a different metal from the gate metal 110; in other embodiments, the gate metal 112 and the gate metal 110 may have the same material composition.
  • the gate metal 112 may be a superconductor, such as aluminum, molybdenum rhenium, titanium nitride, niobium nitride, or niobium titanium nitride, e.g. deposited via atomic layer deposition.
  • the hardmask 118 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 118 may be removed during processing, as discussed below).
  • the gate 108 may extend between the proximate spacers 134 on the sides of the gate 106-1 and the gate 106-3, as shown in FIG. 2.
  • the gate metal 112 may extend between the spacers 134 on the sides of the gate 106-1 and the gate 106-3.
  • the gate metal 112 may have a shape that is substantially complementary to the shape of the spacers 134, as shown.
  • the gate dielectric 114 is not a layer shared commonly between the gates 108 and 106, but instead is separately deposited on the fin 104 between the spacers 134 (e.g., as discussed below with reference to FIGS.
  • the gate dielectric 114 may extend at least partially up the sides of the spacers 134, and the gate metal 112 may extend between the portions of gate dielectric 114 on the spacers 134.
  • the gate metal 112, like the gate metal 110, may be any suitable metal, such as titanium nitride.
  • the dimensions of the gates 106/108 may take any suitable values.
  • the z-height 166 of the gate metal 110 may be between 40 and 75 nanometers (e.g., approximately 50 nanometers); the z-height of the gate metal 112 may be in the same range. In embodiments like the ones illustrated in FIGS. 2, 38, and 45, the z-height of the gate metal 112 may be greater than the z-height of the gate metal 110.
  • the length 168 of the gate metal 110 i.e., in the x-direction
  • the distance 170 between adjacent ones of the gates 106 may be between 40 and 60 nanometers (e.g., 50 nanometers).
  • the thickness 172 of the spacers 134 may be between 1 and 10 nanometers (e.g., between 3 and 5 nanometers, between 4 and 6 nanometers, or between 4 and 7 nanometers).
  • the length of the gate metal 112 i.e., in the x-direction may depend on the dimensions of the gates 106 and the spacers 134, as illustrated in FIG. 2.
  • the gates 106/108 on one fin 104 may extend over the insulating material 128 beyond their respective fins 104 and towards the other fin 104, but may be isolated from their counterpart gates by the intervening insulating material 130.
  • the gates 106 and 108 may be alternatingly arranged along the fin 104 in the x-direction.
  • voltages may be applied to the gates 106/108 to adjust the potential energy in the quantum well layer (not shown) in the fin 104 to create quantum wells of varying depths in which quantum dots 142 may form.
  • Only one quantum dot 142 is labeled with a reference numeral in FIGS. 2 and 3 for ease of illustration, but five are indicated as dotted circles in each fin 104, forming what may be referred to as a "quantum dot array.”
  • the location of the quantum dots 142 in FIG. 2 is not intended to indicate a particular geometric positioning of the quantum dots 142.
  • the spacers 134 may themselves provide "passive" barriers between quantum wells under the gates 106/108 in the quantum well layer, and the voltages applied to different ones of the gates 106/108 may adjust the potential energy under the gates 106/108 in the quantum well layer; decreasing the potential energy may form quantum wells, while increasing the potential energy may form quantum barriers.
  • the fins 104 may include doped regions 140 that may serve as a reservoir of charge carriers for the quantum dot device 100.
  • an n-type doped region 140 may supply electrons for electron-type quantum dots 142
  • a p-type doped region 140 may supply holes for hole-type quantum dots 142.
  • an interface material 141 may be disposed at a surface of a doped region 140, as shown.
  • the interface material 141 may facilitate electrical coupling between a conductive contact (e.g., a conductive via 136, as discussed below) and the doped region 140.
  • the interface material 141 may be any suitable material; for example, in embodiments in which the doped region 140 includes silicon, the interface material 141 may include nickel silicide (e.g., as discussed below with reference to FIGS. 22-23).
  • the quantum dot devices 100 disclosed herein may be used to form electron-type or hole-type quantum dots 142.
  • the polarity of the voltages applied to the gates 106/108 to form quantum wells/barriers depend on the charge carriers used in the quantum dot device 100.
  • amply negative voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108
  • amply positive voltages applied to a gate 106/108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in which an electron-type quantum dot 142 may form).
  • amply positive voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108, and amply negative voltages applied to a gate 106 and 108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in which a hole-type quantum dot 142 may form).
  • the quantum dot devices 100 disclosed herein may be used to form electron-type or hole-type quantum dots.
  • Voltages may be applied to each of the gates 106 and 108 separately to adjust the potential energy in the quantum well layer under the gates 106 and 108, and thereby control the formation of quantum dots 142 under each of the gates 106 and 108. Additionally, the relative potential energy profiles under different ones of the gates 106 and 108 allow the quantum dot device 100 to tune the potential interaction between quantum dots 142 under adjacent gates. For example, if two adjacent quantum dots 142 (e.g., one quantum dot 142 under a gate 106 and another quantum dot 142 under a gate 108) are separated by only a short potential barrier, the two quantum dots 142 may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each gate 106/108 may be adjusted by adjusting the voltages on the respective gates 106/108, the differences in potential between adjacent gates 106/108 may be adjusted, and thus the interaction tuned.
  • two adjacent quantum dots 142 e.g., one quantum dot 142
  • the gates 108 may be used as plunger gates to enable the formation of quantum dots 142 under the gates 108, while the gates 106 may be used as barrier gates to adjust the potential barrier between quantum dots 142 formed under adjacent gates 108.
  • the gates 108 may be used as barrier gates, while the gates 106 are used as plunger gates.
  • quantum dots 142 may be formed under all of the gates 106 and 108, or under any desired subset of the gates 106 and 108.
  • the term “plunger gate” is used to describe a gate under which an electrostatic quantum dot is formed. By controlling the voltage applied to a plunger gate, it is possible to modulate the electric field underneath that gate to create an energy valley between the tunnel barriers created by the barrier gates.
  • the term “barrier gate” is used to describe a gate used to set a tunnel barrier (i.e. a potential barrier) between either two plunger gates (i.e. controlling tunneling of charge carrier(s), e.g. electrons, from one quantum dot to an adjacent quantum dot) or a plunger gate and an accumulation gate. Changing the voltage applied to a barrier gate changes the height of the tunnel barrier.
  • the barrier gate When a barrier gate is used to set a tunnel barrier between two plunger gates, the barrier gate may be used to transfer charge carriers between quantum dots that may be formed under these plunger gates. When a barrier gate is used to set a tunnel barrier between a plunger gate and an accumulation gate, the barrier gate may be used to transfer charge carriers in and out of the quantum dot array via the accumulation gate.
  • the term "accumulation gate” is used to describe a gate used to form a 2DEG in an area that is between the area where the quantum dots may be formed and a charge carrier reservoir. Changing the voltage applied to the accumulation gate allows to control the number of charge carriers in the area under the accumulation gate. For example, changing the voltage applied to the accumulation gate allows reducing the number of charge carriers in the area under the gate so that single charge carriers can be transferred from the reservoir into the quantum dot array, and vice versa.
  • Conductive vias and lines may make contact with the gates 106/108, and to the doped regions 140, to enable electrical connection to the gates 106/108 and the doped regions 140 to be made in desired locations.
  • the gates 106 may extend away from the fins 104, and conductive vias 120 may contact the gates 106 (and are drawn in dashed lines in FIG. 2 to indicate their location behind the plane of the drawing).
  • the conductive vias 120 may extend through the hardmask 116 and the hardmask 118 to contact the gate metal 110 of the gates 106.
  • the gates 108 may extend away from the fins 104, and conductive vias 122 may contact the gates 108 (also drawn in dashed lines in FIG.
  • the conductive vias 122 may extend through the hardmask 118 to contact the gate metal 112 of the gates 108.
  • Conductive vias 136 may contact the interface material 141 and may thereby make electrical contact with the doped regions 140.
  • the quantum dot device 100 may include further conductive vias and/or lines (not shown) to make electrical contact to the gates 106/108 and/or the doped regions 140, as desired.
  • a bias voltage may be applied to the doped regions 140 (e.g., via the conductive vias 136 and the interface material 141) to cause current to flow through the doped regions 140.
  • this voltage may be positive; when the doped regions 140 are doped with a p-type material, this voltage may be negative.
  • the magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts).
  • the conductive vias 120, 122, and 136 may be electrically isolated from each other by an insulating material 130.
  • the insulating material 130 may be any suitable material, such as an interlayer dielectric (ILD). Examples of the insulating material 130 may include silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride.
  • ILD interlayer dielectric
  • conductive vias and lines may be formed in an iterative process in which layers of structures are formed on top of each other.
  • the conductive vias 120/122/136 may have a width that is 20 nanometers or greater at their widest point (e.g., 30 nanometers), and a pitch of 80 nanometers or greater (e.g., 100 nanometers).
  • conductive lines (not shown) included in the quantum dot device 100 may have a width that is 100 nanometers or greater, and a pitch of 100 nanometers or greater.
  • the particular arrangement of conductive vias shown in FIGS. 1-3 is simply illustrative, and any electrical routing arrangement may be implemented.
  • the structure of the fin 104-1 may be the same as the structure of the fin 104-2; similarly, the construction of gates 106/108 on the fin 104-1 may be the same as the construction of gates 106/108 on the fin 104-2.
  • the gates 106/108 on the fin 104-1 may be mirrored by corresponding gates 106/108 on the parallel fin 104-2, and the insulating material 130 may separate the gates 106/108 on the different fins 104-1 and 104-2.
  • quantum dots 142 formed in the fin 104-1 (under the gates 106/108) may have counterpart quantum dots 142 in the fin 104-2 (under the corresponding gates 106/108).
  • the quantum dots 142 in the fin 104-1 may be used as "active" quantum dots in the sense that these quantum dots 142 act as qubits and are controlled (e.g., by voltages applied to the gates 106/108 of the fin 104-1) to perform quantum competitions.
  • the quantum dots 142 in the fin 104-2 may be used as "read” quantum dots in the sense that these quantum dots 142 may sense the quantum state of the quantum dots 142 in the fin 104-1 by detecting the electric field generated by the charge in the quantum dots 142 in the fin 104-1, and may convert the quantum state of the quantum dots 142 in the fin 104-1 into electrical signals that may be detected by the gates 106/108 on the fin 104-2.
  • Each quantum dot 142 in the fin 104-1 may be read by its corresponding quantum dot 142 in the fin 104-2.
  • the quantum dot device 100 enables both quantum computation and the ability to read the results of a quantum computation.
  • the quantum dot device 100 may further include one or more accumulation gates used to form a 2DEG in the quantum well area between the area with the quantum dots and the reservoir such as e.g. the doped regions 140 which, as previously described, may serve as a reservoir of charge carriers for the quantum dot device 100.
  • accumulation gates may allow to reduce the number of charge carriers in the area adjacent to the area in which quantum dots are to be formed, so that single charge carriers can be transferred from the reservoir into the quantum dot array.
  • an accumulation gate may be implemented on either side of an area where a quantum dot is to be formed.
  • the quantum dot device 100 typically further includes or is coupled to a magnetic field source used for spin manipulation of the charge carries in the quantum dots.
  • a magnetic field source used for spin manipulation of the charge carries in the quantum dots.
  • a microwave transmission line or one or more magnets with pulsed gates may be used as a magnetic field source.
  • single spins may be manipulated using electron spin resonance with a rotating magnetic field (perpendicular to its static field) and on resonance with the transition energy at which the spin flips.
  • FIGS. 4-25 illustrate various example stages in the manufacture of the quantum dot device 100 of FIGS. 1-3, in accordance with various embodiments. Although the particular manufacturing operations discussed below with reference to FIGS. 4-25 are illustrated as manufacturing a particular embodiment of the quantum dot device 100, these operations may be applied to manufacture many different embodiments of the quantum dot device 100, as discussed herein. Any of the elements discussed below with reference to FIGS. 4-25 may take the form of any of the embodiments of those elements discussed above (or otherwise disclosed herein).
  • FIG. 4 illustrates a cross-sectional view of an assembly 200 including a semiconductor substrate 144.
  • the semiconductor substrate 144 may include any suitable semiconductor material or materials.
  • the semiconductor substrate 144 may be formed of silicon.
  • FIG. 5 illustrates a cross-sectional view of an assembly 202 subsequent to providing a quantum well stack 146 on the semiconductor substrate 144 of the assembly 200 (FIG. 4).
  • the quantum well stack 146 may include a quantum well layer (not shown) in which a 2DEG may form during operation of the quantum dot device 100.
  • Various embodiments of the quantum well stack 146 are discussed below with reference to FIGS. 26-28.
  • FIG. 6 illustrates a cross-sectional view of an assembly 204 subsequent to forming fins 104 in the assembly 202 (FIG. 5).
  • the fins 104 may extend from a base 102, and may be formed in the assembly 202 by patterning and then etching the assembly 202, as known in the art. For example, a combination of dry and wet etch chemistry may be used to form the fins 104, and the appropriate chemistry may depend on the materials included in the assembly 202, as known in the art.
  • At least some of the semiconductor substrate 144 may be included in the base 102, and at least some of the quantum well stack 146 may be included in the fins 104.
  • the quantum well layer (not shown) of the quantum well stack 146 may be included in the fins 104.
  • Example arrangements in which the quantum well stack 146 and the semiconductor substrate 144 are differently included in the base 102 and the fins 104 are discussed below with reference to FIGS. 29-35.
  • FIG. 7 illustrates a cross-sectional view of an assembly 206 subsequent to providing an insulating material 128 to the assembly 204 (FIG. 6).
  • Any suitable material may be used as the insulating material 128 to electrically insulate the fins 104 from each other.
  • the insulating material 128 may be a dielectric material, such as silicon oxide.
  • FIG. 8 illustrates a cross-sectional view of an assembly 208 subsequent to planarizing the assembly 206 (FIG. 7) to remove the insulating material 128 above the fins 104.
  • the assembly 206 may be planarized using a chemical mechanical polishing (CMP) technique.
  • CMP chemical mechanical polishing
  • FIG. 9 is a perspective view of at least a portion of the assembly 208, showing the fins 104 extending from the base 102 and separated by the insulating material 128.
  • the cross- sectional views of FIGS. 4-8 are taken parallel to the plane of the page of the perspective view of FIG. 9.
  • FIG. 10 is another cross-sectional view of the assembly 208, taken along the dashed line along the fin 104-1 in FIG. 9.
  • the cross-sectional views illustrated in FIGS. 11-25 are taken along the same cross-section as FIG. 10.
  • FIG. 11 is a cross-sectional view of an assembly 210 subsequent to forming a gate stack 174 on the fins 104 of the assembly 208 (FIGS. 8-10).
  • the gate stack 174 may include the gate dielectric 114, the gate metal 110, and a hardmask 116.
  • the hardmask 116 may be formed of an electrically insulating material, such as silicon nitride or carbon-doped nitride.
  • FIG. 12 is a cross-sectional view of an assembly 212 subsequent to patterning the hardmask 116 of the assembly 210 (FIG. 11).
  • the pattern applied to the hardmask 116 may correspond to the locations for the gates 106, as discussed below.
  • the hardmask 116 may be patterned by applying a resist and then etching the hardmask 116 (using dry etching or any appropriate technique).
  • FIG. 13 is a cross-sectional view of an assembly 214 subsequent to etching the assembly 212 (FIG. 12) to remove the gate metal 110 that is not protected by the patterned hardmask 116 to form the gates 106.
  • the gate dielectric 114 may remain after the etched gate metal 110 is etched away; in other embodiments, the gate dielectric 114 may also be etched during the etching of the gate metal 110. Examples of such embodiments are discussed below with reference to FIGS. 40-44.
  • FIG. 14 is a cross-sectional view of an assembly 216 subsequent to providing spacer material 132 on the assembly 214 (FIG. 13).
  • the spacer material 132 may include any of the materials discussed above with reference to the spacers 134, for example, and may be deposited using any suitable technique.
  • the spacer material 132 may be a nitride material (e.g., silicon nitride) deposited by sputtering.
  • FIG. 15 is a cross-sectional view of an assembly 218 subsequent to etching the spacer material 132 of the assembly 216 (FIG. 14), leaving spacers 134 formed of the spacer material 132 on the sides of the gates 106 (e.g., on the sides of the hardmask 116 and the gate metal 110).
  • the etching of the spacer material 132 may be an anisotropic etch, etching the spacer material 132 "downward" to remove the spacer material 132 on top of the gates 106 and in some of the area between the gates 106, while leaving the spacers 134 on the sides of the gates 106.
  • the anisotropic etch may be a dry etch.
  • FIG. 16 is a cross-sectional view of an assembly 220 subsequent to providing the gate metal 112 on the assembly 218 (FIG. 15).
  • the gate metal 112 may fill the areas between adjacent ones of the gates 106, and may extend over the tops of the gates 106.
  • FIG. 17 is a cross-sectional view of an assembly 222 subsequent to planarizing the assembly 220 (FIG. 16) to remove the gate metal 112 above the gates 106.
  • the assembly 220 may be planarized using a CMP technique. Some of the remaining gate metal 112 may fill the areas between adjacent ones of the gates 106, while other portions 150 of the remaining gate metal 112 may be located "outside" of the gates 106.
  • FIG. 18 is a cross-sectional view of an assembly 224 subsequent to providing a hardmask 118 on the planarized surface of the assembly 222 (FIG. 17).
  • the hardmask 118 may be formed of any of the materials discussed above with reference to the hardmask 116, for example.
  • FIG. 19 is a cross-sectional view of an assembly 226 subsequent to patterning the hardmask 118 of the assembly 224 (FIG. 18).
  • the pattern applied to the hardmask 118 may extend over the hardmask 116 (and over the gate metal 110 of the gates 106, as well as over the locations for the gates 108 (as illustrated in FIG. 2).
  • the hardmask 118 may be non- coplanar with the hardmask 116, as illustrated in FIG. 19.
  • the hardmask 118 illustrated in FIG. 19 may thus be a common, continuous portion of hardmask 118 that extends over all of the hardmask 116.
  • hardmask 118 examples of embodiments in which the hardmask 118 is not disposed over the entirety of the hardmask 116 are discussed below with reference to FIGS. 36-38 and 45.
  • the hardmask 118 may be patterned using any of the techniques discussed above with reference to the patterning of the hardmask 116, for example.
  • FIG. 20 is a cross-sectional view of an assembly 228 subsequent to etching the assembly 226 (FIG. 19) to remove the portions 150 that are not protected by the patterned hardmask 118 to form the gates 108. Portions of the hardmask 118 may remain on top of the hardmask 116, as shown.
  • the operations performed on the assembly 226 may include removing any gate dielectric 114 that is "exposed" on the fin 104, as shown.
  • the excess gate dielectric 114 may be removed using any suitable technique, such as chemical etching or silicon bombardment.
  • FIG. 21 is a cross-sectional view of an assembly 230 subsequent to doping the fins 104 of the assembly 228 (FIG. 20) to form doped regions 140 in the portions of the fins 104
  • the type of dopant used to form the doped regions 140 may depend on the type of quantum dot desired, as discussed above.
  • the doping may be performed by ion implantation.
  • the quantum dot 142 is to be an electron-type quantum dot 142
  • the doped regions 140 may be formed by ion
  • the depth of the doped regions 140 may take any suitable value; for example, in some embodiments, the doped regions 140 may extend into the fin 104 to a depth 115 between 500 and 1000 Angstroms.
  • the outer spacers 134 on the outer gates 106 may provide a doping boundary, limiting diffusion of the dopant from the doped regions 140 into the area under the gates 106/108. As shown, the doped regions 140 may extend under the adjacent outer spacers 134.
  • the doped regions 140 may extend past the outer spacers 134 and under the gate metal 110 of the outer gates 106, may extend only to the boundary between the outer spacers 134 and the adjacent gate metal 110, or may terminate under the outer spacers 134 and not reach the boundary between the outer spacers 134 and the adjacent gate metal 110. Examples of such embodiments are discussed below with reference to FIGS. 46 and 47.
  • the doping concentration of the doped regions 140 may, in some embodiments, be between 1017/cm3 and 1020/cm3.
  • FIG. 22 is a cross-sectional side view of an assembly 232 subsequent to providing a layer of nickel 143 over the assembly 230 (FIG. 21).
  • the nickel 143 may be deposited on the assembly 230 using any suitable technique (e.g., a plating technique).
  • FIG. 23 is a cross-sectional side view of an assembly 234 subsequent to annealing the assembly 230 (FIG. 22) to cause the nickel 143 to interact with the doped regions 140 to form the interface material 141, then removing the unreacted nickel 143.
  • the interface material 141 may be nickel silicide. Materials other than nickel may be deposited in the operations discussed above with reference to FIG. 22 in order to form other interface materials 141.
  • FIG. 24 is a cross-sectional view of an assembly 236 subsequent to providing an insulating material 130 on the assembly 234 (FIG. 23).
  • the insulating material 130 may take any of the forms discussed above (e.g., the insulating material 130 may be a dielectric material).
  • the insulating material 130 may be provided on the assembly 234 using any suitable technique, such as spin coating, chemical vapor deposition (CVD), or plasma-enhanced CVD (PECVD).
  • FIG. 25 is a cross-sectional view of an assembly 238 subsequent to forming, in the assembly 236 (FIG. 24), conductive vias 120 through the insulating material 130 (and the hardmasks 116 and 118) to contact the gate metal 110 of the gates 106, conductive vias 122 through the insulating material 130 (and the hardmask 118) to contact the gate metal 112 of the gates 108, and conductive vias 136 through the insulating material 130 to contact the interface material 141 of the doped regions 140. Further conductive vias and/or lines may be formed on the assembly 234 using conventional interconnect techniques, if desired.
  • the resulting assembly 238 may take the form of the quantum dot device 100 discussed above with reference to FIGS. 1-3.
  • the base 102 and the fin 104 of a quantum dot device 100 may be formed from a semiconductor substrate 144 and a quantum well stack 146 disposed on the semiconductor substrate 144.
  • the quantum well stack 146 may include a quantum well layer in which a 2DEG may form during operation of the quantum dot device 100.
  • the quantum well stack 146 may take any of a number of forms, several of which are illustrated in FIGS. 26-28.
  • the various layers in the quantum well stacks 146 discussed below may be grown on the semiconductor substrate 144 (e.g., using epitaxial processes).
  • FIG. 26 is a cross-sectional view of a quantum well stack 146 including only a quantum well layer 152.
  • the quantum well layer 152 may be disposed on the semiconductor substrate 144 (e.g., as discussed above with reference to FIG. 5), and may be formed of a material such that, during operation of the quantum dot device 100, a 2DEG may form in the quantum well layer 152 proximate to the upper surface of the quantum well layer 152.
  • the gate dielectric 114 of the gates 106/108 may be disposed on the upper surface of the quantum well layer 152 (e.g., as discussed above with reference to FIG. 11).
  • the gate dielectric 114 may be formed of silicon oxide; in such an arrangement, during use of the quantum dot device 100, a 2DEG may form in the lll-V compound at the interface between the lll-V compound and the silicon oxide.
  • the gate dielectric 114 instead of silicon oxide, may be formed of aluminium oxide, tantalum pentoxide, titanium dioxide, or tantalum silicon oxide.
  • the thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 26 may take any suitable values.
  • the thickness of the quantum well layer 152 e.g., gallium arsenide, indium gallium arsenide, or indium antimonide
  • the thickness of the quantum well layer 152 may be between 0.8 and 1.2 microns.
  • FIG. 27 is a cross-sectional view of a quantum well stack 146 including a quantum well layer 152 and a barrier layer 154.
  • the quantum well stack 146 may be disposed on a semiconductor substrate 144 (e.g., as discussed above with reference to FIG. 5) such that the barrier layer 154 is disposed between the quantum well layer 152 and the semiconductor substrate 144.
  • the barrier layer 154 may provide a potential barrier between the quantum well layer 152 and the semiconductor substrate 144.
  • the quantum well layer 152 of FIG. 27 may be formed of a material such that, during operation of the quantum dot device 100, a 2DEG may form in the quantum well layer 152 proximate to the upper surface of the quantum well layer 152.
  • the quantum well layer 152 of FIG. 27 may be formed of gallium arsenide (GaAs), and the barrier layer 154 may be formed of aluminium gallium arsenide (AIGaAs).
  • the quantum well layer 152 of FIG. 27 may be formed of indium gallium arsenide (InGaAs), and the barrier layer 154 may be formed of indium aluminium arsenide (InAIAs).
  • the indium content of this indium gallium arsenide and indium gallium arsenide described herein with reference to other embodiments, may be 20-80% (e.g., 50%).
  • the barrier layer 154 may be formed of aluminium indium antimonide (AllnSb).
  • other combinations of lll-V compounds may be used for forming the quantum well layer 152 and the barrier layer 154, as long as a lll-V compound of the quantum well layer 152 is a semiconductor having a smaller bandgap than a lll-V compound of the barrier layer 154, in order to achieve quantum confinement in the quantum well layer.
  • the thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 27 may take any suitable values.
  • the thickness of the barrier layer 154 may be between 0 and 400 nanometers.
  • the thickness of the quantum well layer 152 may be between 5 and 30 nanometers.
  • FIG. 28 is a cross-sectional view of a quantum well stack 146 including a quantum well layer 152 and a barrier layer 154-1, as well as a buffer layer 176 and an additional barrier layer 154-2. Each of these layers may be formed of a lll-V material.
  • the quantum well stack 146 may be disposed on the semiconductor substrate 144 (e.g., as discussed above with reference to FIG. 5) such that the buffer layer 176 is disposed between the barrier layer 154-1 and the semiconductor substrate 144.
  • the buffer layer 176 may be present to trap defects that form in this material as it is grown on the semiconductor substrate 144.
  • the buffer layer 176 may be formed of the same or different material as the barrier layer 154.
  • the buffer layer 176 may be formed of gallium arsenide while the barrier layer 154-1 may be formed of aluminium indium antimonide, aluminium gallium arsenide, indium gallium arsenide, or indium aluminium arsenide.
  • the buffer layer 176 may be grown under different conditions (e.g., deposition temperature or growth rate) from the barrier layer 154-1.
  • the barrier layer 154-1 may be grown under conditions that achieve fewer defects than the buffer layer 176.
  • the buffer layer 176 may be a graded buffer layer in that it includes layers with varying concentrations from the semiconductor substrate 144 to the barrier layer 154-1.
  • substantially pure GaAs could be grown near the substrate, but then continuously graded up to InxGal-xAs, where X could range from 0.1 to 0.7.
  • the thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 28 may take any suitable values.
  • the thickness of the buffer layer 176 may be between 0.3 and 4 microns (e.g., 0.3-2 microns, or 0.5 microns). In some
  • the thickness of the barrier layer 154-1 may be between 0 and 400 nanometers. In some embodiments, the thickness of the quantum well layer 152 may be between 5 and 30 nanometers (e.g., 10 nanometers). In some embodiments, the thickness of the barrier layer 154-2 may be between 25 and 75 nanometers (e.g., 32 nanometers).
  • the quantum well layer 152 of FIG. 28 may be formed of a material such that, during operation of the quantum dot device 100, a 2DEG may form in the quantum well layer 152 proximate to the upper surface of the quantum well layer 152.
  • the quantum well layer 152 of FIG. 28 may be formed of gallium arsenide (GaAs)
  • the barrier layer 154-1 may be formed of aluminium gallium arsenide (AIGaAs)
  • the buffer layer 176 may be formed of indium gallium arsenide (InGaAs).
  • the buffer layer 176 may be formed of indium aluminium arsenide (InAIAs).
  • the buffer layer 176 may additionally include a layer of gallium arsenide (GaAs) disposed between a layer of indium aluminium arsenide and the substrate 144.
  • the barrier layer 154-2 may provide a potential energy barrier around the quantum well layer 152, and may take the form of any of the embodiments of the barrier layer 154-1.
  • any suitable combinations of lll-V compounds may be used for forming the quantum well layer 152, the barrier layer 154-1, the barrier layer 154-2, and the buffer layer 176, as long as a lll-V compound of the quantum well layer 152 is a semiconductor having a smaller bandgap than a lll-V compound of layers that sandwich the quantum well layer 152, in order to achieve quantum confinement in the quantum well layer.
  • the buffer layer 176 and/or the barrier layer 154-2 may be omitted.
  • the semiconductor substrate 144 and the quantum well stack 146 may be distributed between the base 102 and the fins 104 of the quantum dot device 100, as discussed above. This distribution may occur in any of a number of ways.
  • FIGS. 29-35 illustrate example base/fin arrangements 158 that may be used in a quantum dot device 100, in accordance with various embodiments.
  • the quantum well stack 146 may be included in the fins 104, but not in the base 102.
  • the semiconductor substrate 144 may be included in the base 102, but not in the fins 104.
  • the fin etching may etch through the quantum well stack 146, and stop when the semiconductor substrate 144 is reached.
  • the quantum well stack 146 may be included in the fins 104, as well as in a portion of the base 102.
  • a semiconductor substrate 144 may be included in the base 102 as well, but not in the fins 104.
  • the fin etching may etch partially through the quantum well stack 146, and stop before the semiconductor substrate 144 is reached.
  • FIG. 31 illustrates a particular
  • the quantum well stack 146 of FIG. 28 is used; the fins 104 include the barrier layer 154-1, the quantum well layer 152, and the barrier layer 154-2, while the base 102 includes the buffer layer 176 and the semiconductor substrate 144.
  • the quantum well stack 146 may be included in the fins 104, but not the base 102.
  • the semiconductor substrate 144 may be partially included in the fins 104, as well as in the base 102.
  • the fin etching may etch through the quantum well stack 146 and into the semiconductor substrate 144 before stopping.
  • FIG. 33 illustrates a particular embodiment of the base/fin arrangement 158 of FIG. 32.
  • the quantum well stack 146 of FIG. 28 is used; the fins 104 include the quantum well stack 146 and a portion of the semiconductor substrate 144, while the base 102 includes the remainder of the semiconductor substrate 144.
  • the fins 104 have been illustrated in many of the preceding figures as substantially rectangular with parallel sidewalls, this is simply for ease of illustration, and the fins 104 may have any suitable shape (e.g., shape appropriate to the manufacturing processes used to form the fins 104). For example, as illustrated in the base/fin arrangement 158 of FIG.
  • the fins 104 may be tapered. In some embodiments, the fins 104 may taper by 3-10 nanometers in x-width for every 100 nanometers in z-height (e.g., 5 nanometers in x-width for every 100 nanometers in z-height). When the fins 104 are tapered, the wider end of the fins 104 may be the end closest to the base 102, as illustrated in FIG. 34.
  • FIG. 35 illustrates a particular embodiment of the base/fin arrangement 158 of FIG. 34. In FIG.
  • the quantum well stack 146 is included in the tapered fins 104 while a portion of the semiconductor substrate 144 is included in the tapered fins and a portion of the semiconductor substrate 144 provides the base 102.
  • the z-height of the gate metal 112 of the gates 108 may be approximately equal to the sum of the z-height of the gate metal 110 and the z-height of the hardmask 116, as shown. Also in the embodiment of FIG. 2, the gate metal 112 of the gates 108 may not extend in the x-direction beyond the adjacent spacers 134.
  • FIGS. 36-38 illustrate various example stages in the manufacture of alternative gate arrangements that may be included in a quantum dot device 100, in accordance with various embodiments.
  • FIG. 36 illustrates an assembly 242 subsequent to providing the gate metal 112 and a hardmask 118 on the assembly 218 (FIG. 15).
  • the assembly 242 may be similar to the assembly 224 of FIG.
  • the gate metal 112 may be planarized prior to provision of the hardmask 118, but the hardmask 118 may still be spaced away from the hardmask 116 in the z-direction by the gate metal 112, as shown in FIG. 36.
  • FIG. 37 illustrates an assembly 244 subsequent to patterning the hardmask 118 of the assembly 242 (FIG. 36).
  • the pattern applied to the hardmask 118 may include the locations for the gates 108, as discussed below.
  • the hardmask 118 may be non-coplanar with the hardmask 116, as illustrated in FIG. 36, and may extend "over" at least a portion of the hardmask 116 (and thus over the gate metal 110 of the gates 106).
  • FIG. 38 illustrates an assembly 246 subsequent to etching the assembly 244 (FIG. 37) to remove the portions 150 that are not protected by the patterned hardmask 118 to form the gates 108.
  • the gate metal 112 of the gates 106 may extend "over" the hardmask 116 of the gates 108, and may be electrically insulated from the gate metal 110 by the hardmask 116.
  • the z-height of the gate metal 112 of the gates 108 may be greater than the sum of the z-height of the gate metal 110 and the z-height of the hardmask 116 of the gates 106.
  • the gate metal 112 of the gates 108 may extend beyond the spacers 134 in the x-direction, as shown. Further manufacturing operations may be performed on the assembly 246, as discussed above with reference to FIGS. 21-25.
  • a single fin 104 may include multiple groups of gates 106/108, spaced apart along the fin by a doped region 140.
  • FIG. 39 is a cross-sectional view of an example of such a quantum dot device 100 having multiple groups of gates 180 on a single fin 104, in accordance with various embodiments.
  • Each of the groups 180 may include gates 106/108 (not labeled in FIG. 39 for ease of illustration) that may take the form of any of the
  • a doped region 140 (and its interface material 141) may be disposed between two adjacent groups 180 (labeled in FIG. 39 as groups 180-1 and 180-2), and may provide a common reservoir for both groups 180. In some embodiments, this "common" doped region 140 may be electrically contacted by a single conductive via 136.
  • the particular number of gates 106/108 illustrated in FIG. 39, and the particular number of groups 180, is simply illustrative, and a fin 104 may include any suitable number of gates 106/108 arranged in any suitable number of groups 180.
  • FIGS. 40-44 illustrate various alternative stages in the manufacture of such an embodiment of a quantum dot device 100, in accordance with various embodiments. In particular, the operations illustrated in FIGS. 40-44 may take the place of the operations illustrated in FIGS. 13-15.
  • FIG. 40 is a cross-sectional view of an assembly 248 subsequent to etching the assembly 212 (FIG. 12) to remove the gate metal 110, and the gate dielectric 114 that is not protected by the patterned hardmask 116, to form the gates 106.
  • FIG. 41 is a cross-sectional view of an assembly 250 subsequent to providing spacer material 132 on the assembly 248 (FIG. 40).
  • the deposition of the spacer material 132 may take any of the forms discussed above with reference to FIG. 14, for example.
  • FIG. 42 is a cross-sectional view of an assembly 252 subsequent to etching the spacer material 132 of the assembly 250 (FIG. 41), leaving spacers 134 formed of the spacer material 132 on the sides of the gates 106 (e.g., on the sides of the hardmask 116, the gate metal 110, and the gate dielectric 114).
  • the etching of the spacer material 132 may take any of the forms discussed above with reference to FIG. 15, for example.
  • FIG. 43 is a cross-sectional view of an assembly 254 subsequent to providing a gate dielectric 114 on the fin 104 between the gates 106 of the assembly 252 (FIG. 42).
  • the gate dielectric 114 provided between the gates 106 of the assembly 252 may be formed by atomic layer deposition (ALD) and, as illustrated in FIG. 43, may cover the exposed fin 104 between the gates 106, and may extend onto the adjacent spacers 134.
  • ALD atomic layer deposition
  • FIG. 44 is a cross-sectional view of an assembly 256 subsequent to providing the gate metal 112 on the assembly 254 (FIG. 43).
  • the gate metal 112 may fill the areas between adjacent ones of the gates 106, and may extend over the tops of the gates 106, as shown.
  • the provision of the gate metal 112 may take any of the forms discussed above with reference to FIG. 16, for example.
  • the assembly 256 may be further processed as discussed above with reference to FIGS. 17-25.
  • the pattern applied to the hardmask 118 may not result in a common, continuous portion of hardmask 118 that extends over all of the hardmask 116.
  • FIG. 45 is a cross-sectional view of an assembly 258 in which the hardmask 118 of the assembly 224 (FIG. 18) is not patterned to extend over the gates 106, but instead is patterned so as not to extend over the gate metal 110.
  • the assembly 258 may be further processed as discussed above with reference to FIGS.
  • the hardmasks 116 and 118 may remain in the quantum dot device 100 as part of the gates 106/108, while in other embodiments, the hardmasks 116 and 118 may be removed.
  • the outer spacers 134 on the outer gates 106 may provide a doping boundary, limiting diffusion of the dopant from the doped regions 140 into the area under the gates 106/108.
  • the doped regions 140 may extend past the outer spacers 134 and under the outer gates 106.
  • the doped region 140 may extend past the outer spacers 134 and under the outer gates 106 by a distance 182 between 0 and 10 nanometers.
  • the doped regions 140 may not extend past the outer spacers 134 toward the outer gates 106, but may instead "terminate" under the outer spacers 134.
  • the doped regions 140 may be spaced away from the interface between the outer spacers 134 and the outer gates 106 by a distance 184 between 0 and 10
  • the interface material 141 is omitted from FIGS. 46 and 47 for ease of illustration.
  • FIG. 48 is a flow diagram of an illustrative method 1000 of manufacturing a quantum dot device, in accordance with various embodiments.
  • a quantum well stack may be provided on a semiconductor substrate.
  • the quantum well stack may include a quantum well layer formed of one or more lll-V materials.
  • a quantum well stack 146 including a quantum well layer 152 may be provided on a semiconductor substrate 144 (e.g., as discussed above with reference to FIGS. 4- 5 and 26-28).
  • At 1004 at least some of the quantum well stack may be removed to form fins that include the quantum well layer.
  • at least some of the quantum well stack 146 may be removed to form fins 104 that include the quantum well layer 152 (e.g. as discussed above with reference to FIGS. 6 and 29-35).
  • an insulating material may be provided between the fins.
  • the insulating material 128 may be provided between the fins 104 (e.g., as discussed above with reference to FIG. 7).
  • first and second gates may be formed on the fins.
  • multiple gates 106 may be formed on the fins 104 (e.g., as discussed above with reference to FIGS. 11-13 and 40).
  • spacers may be provided on the sides of the first and second gates.
  • a first spacer may be disposed on a side of the first gate closest to the second gate, and a second spacer, physically separate from the first spacer, may be disposed on the side of the second gate closest to the first gate.
  • spacers 134 may be disposed on the sides of the gates 106 (e.g., as discussed above with reference to FIGS. 14-15 and 41-43).
  • a third gate may be formed on the fin.
  • the third gate may extend between the first and second spacers.
  • the gates 108 may be formed on the fin 104 between the spacers 134 on the sides of adjacent gates 106 (e.g., as discussed above with reference to FIGS. 16-19 and 43-44).
  • FIGS. 49-50 are flow diagrams of particular illustrative methods 1020 and 1040, respectively, of operating a quantum dot device, in accordance with various embodiments.
  • one or more voltages may be applied to one or more gates on a first fin to cause a first quantum dot to form in the first fin.
  • the first fin may extend away from a base.
  • one or more voltages may be applied to the gates 106/108 on a fin 104-1 (extending away from the base 102) to cause at least one quantum dot 142 to form in the fin 104-1.
  • one or more voltages may be applied to one or more gates on a second fin to cause a second quantum dot to form in the second fin.
  • the second fin may extend away from the base, and an insulating material may be disposed between the first and second fins.
  • one or more voltages may be applied to the gates 106/108 on a fin 104-2 (extending away from the base 102 and spaced apart from the fin 104-1 by the insulating material 128) to cause at least one quantum dot 142 to form in the fin 104-2.
  • a quantum state of the first quantum dot may be sensed with the second quantum dot.
  • a quantum dot 142 in the fin 104-2 (the "read” fin) may sense the quantum state of a quantum dot 142 in the fin 104-1 (the “active” fin).
  • a voltage may be applied to a first gate disposed on the fin to cause a first quantum dot to form in a first quantum well in the fin under the first gate, the first quantum well comprising one or more lll-V materials.
  • the fin may extend away from a base, and an insulating material is disposed on side faces of the fin.
  • a voltage may be applied to the gate 108-1 disposed on a fin 104 to cause a first quantum dot 142 to form in the quantum well layer 152 in the fin 104 under the gate 108-1.
  • the fin 104 may extend away from the base 102, and the insulating material 128 may be disposed on side faces of the fin 104.
  • a voltage may be applied to a second gate disposed on the fin to cause a second quantum dot to form in a second quantum well in the fin under the second gate, the second quantum well comprising one or more lll-V materials.
  • a voltage may be applied to the gate 108-2 disposed on the fin 104 to cause a second quantum dot 142 to form in the quantum well layer 152 in the fin 104 under the gate 108-2.
  • a voltage may be applied to a third gate disposed on the fin to (1) cause a third quantum dot to form in a third quantum well in the fin under the third gate or (2) provide a potential barrier between the first quantum well and the second quantum well, the third quantum well comprising one or more lll-V materials.
  • a voltage may be applied to the gate 106-2 to (1) cause a third quantum dot 142 to form in the quantum well layer 152 in the fin 104 (e.g., when the gate 106-2 acts as a "plunger” gate) or (2) provide a potential barrier between the first quantum well (under the gate 108-1) and the second quantum well (under the gate 108-2) (e.g., when the gate 106-2 acts as a "barrier" gate).
  • quantum dot devices as described herein may be used to implement components associated with a quantum integrated circuit (IC).
  • IC quantum integrated circuit
  • Such components may include those that are mounted on or embedded in a quantum IC, or those connected to a quantum IC.
  • the quantum IC may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the integrated circuit.
  • the integrated circuit may be employed as part of a chipset for executing one or more related functions in a quantum system.
  • FIG. 51 is a block diagram of an example quantum computing device 2000 that may include any of the quantum dot devices disclosed herein.
  • a number of components are illustrated in FIG. 51 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application.
  • some or all of the components included in the quantum computing device 2000 may be attached to one or more printed circuit boards (e.g., a motherboard).
  • various ones of these components may be fabricated onto a single system-on-a- chip (SoC) die.
  • the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 51, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components.
  • the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled.
  • the quantum computing device 2000 may not include an audio input device 2024 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2024 or audio output device 2008 may be coupled.
  • the quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices).
  • processing device e.g., one or more processing devices.
  • the term "processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices).
  • the quantum processing device 2026 may include one or more of the quantum dot devices 100 disclosed herein, and may perform data processing by performing operations on the quantum dots that may be generated in the quantum dot devices 100, and monitoring the result of those operations. For example, as discussed above, different quantum dots may be allowed to interact, the quantum states of different quantum dots may be set or transformed, and the quantum states of quantum dots may be read (e.g., by another quantum dot).
  • the quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some
  • the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc.
  • the quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.
  • the processing device 2002 may include a non-quantum processing device 2028.
  • the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026.
  • the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc.
  • the non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026.
  • the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components.
  • the non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
  • DSPs digital signal processors
  • ASICs application-specific integrated circuits
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute cryptographic algorithms within hardware
  • server processors or any other suitable processing devices.
  • the quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid state memory
  • solid state memory solid state memory
  • hard drive solid state memory
  • the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004.
  • the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).
  • eDRAM embedded dynamic random access memory
  • STT-MRAM spin transfer torque magnetic random-access memory
  • the quantum computing device 2000 may include a cooling apparatus 2030.
  • the cooling apparatus 2030 may maintain the quantum processing device 2026 at a
  • the predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less.
  • the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature.
  • the cooling apparatus 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.
  • the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips).
  • the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 Amendment), Long-Term Evolution (LTE) project along with any IEEE standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 Amendment), Long-Term Evolution (LTE) project along with any IEEE 1402.16 standards including Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 Amendment), Long-Term Evolution (LTE) project along with any
  • IEEE 1402.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 1402.16 standards.
  • the communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile
  • the communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN),
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • the communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the communication chip 2012 may operate in accordance with other wireless protocols in other embodiments.
  • the quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
  • the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second
  • a communication chip 2012 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
  • a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.
  • the quantum computing device 2000 may include battery/power circuitry 2014.
  • the battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).
  • the quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above).
  • the display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a
  • touchscreen display a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
  • LCD liquid crystal display
  • LED light-emitting diode display
  • flat panel display for example.
  • the quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above).
  • the audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
  • the quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above).
  • the audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
  • MIDI musical instrument digital interface
  • the quantum computing device 2000 may include a global positioning system (GPS) device 2018 (or corresponding interface circuitry, as discussed above).
  • GPS global positioning system
  • the GPS device 2018 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.
  • the quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above).
  • Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
  • the quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above).
  • Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • RFID radio frequency identification
  • the quantum computing device 2000 may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
  • a hand-held or mobile computing device e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.
  • PDA personal digital assistant
  • a desktop computing device e.g., a
  • Example 1 provides a quantum dot device that includes a base; a fin extending away from the base, where the fin includes a quantum well layer including one or more lll-V compounds; and a gate disposed on the fin.
  • Example 2 provides the quantum dot device according to Example 1, where the one or more lll-V compounds include one or more of gallium arsenide (GaAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), indium aluminium arsenide (InAIAs), aluminium indium antimonide (AllnSb), and aluminium gallium arsenide (AIGaAs).
  • GaAs gallium arsenide
  • InSb indium antimonide
  • InGaAs indium gallium arsenide
  • InAIAs indium aluminium arsenide
  • AllnSb aluminium indium antimonide
  • AIGaAs aluminium gallium arsenide
  • Example 3 provides the quantum dot device according to Example 1, where the fin is a first fin, the gate is a first gate, and the quantum dot device further includes a second fin extending away from the base, where the second fin includes a quantum well layer; and a second gate disposed on the second fin.
  • Example 4 provides the quantum dot device according to Example 3, where the first and second fins are parallel.
  • Example 5 provides the quantum dot device according to Example 3, where the first and second fins are spaced apart by a distance between 100 and 250 nanometers.
  • Example 6 provides the quantum dot device according to Example 1, further including an insulating material disposed on opposite faces of the fin.
  • Example 7 provides the quantum dot device according to any one of Examples 1- 6, where the fin has a width between 10 and 40 nanometers.
  • Example 8 provides the quantum dot device according to any one of Examples 1- 6, where the fin has a tapered shape that is widest proximate to the base.
  • Example 9 provides the quantum dot device according to any one of Examples 1- 6, where the base includes a semiconductor substrate, and the semiconductor substrate extends into the fin.
  • Example 10 provides the quantum dot device according to any one of Examples 1-6, where the base includes a semiconductor substrate, and a barrier layer is disposed between the semiconductor substrate and the quantum well layer.
  • Example 11 provides the quantum dot device according to any one of Examples 1-6, further including a barrier layer disposed over the quantum well layer in the fin.
  • Example 12 provides the quantum dot device according to Example 11, where the barrier layer has a thickness above 75 nanometers.
  • Example 13 provides the quantum dot device according to any one of Examples 1-6, where the gate has a length, along the fin, between 20 and 40 nanometers.
  • Example 14 provides the quantum dot device according to any one of Examples 1-6, where the gate is a first gate, and the quantum dot device further includes a second gate disposed on the fin.
  • Example 15 provides the quantum dot device according to Example 14, where the first gate and the second gate are spaced apart by a distance between 40 and 60 nanometers.
  • Example 16 provides the quantum dot device according to any one of Examples 1-6, where the fin has a height between 250 and 350 nanometers.
  • Example 17 provides a method of operating a quantum dot device.
  • the method includes applying one or more voltages to one or more gates on a first fin to cause a first quantum dot to form in the first fin, where the first fin extends away from a base and includes a quantum well layer including one or more lll-V compounds; applying one or more voltages to one or more gates on a second fin to cause a second quantum dot to form in the second fin, where an insulating material is disposed between the first and second fins; and sensing a quantum state of the first quantum dot with the second quantum dot.
  • Example 18 provides the method according to Example 17, where applying the one or more voltages to the one or more gates on the first fin includes applying a voltage to a first gate of the one or more gates to cause the first quantum dot to form in the first fin under the first gate.
  • Example 19 provides the method according to any one of Examples 17-18, further including applying the one or more voltages to the one or more gates on the first fin to cause a third quantum dot to form in the first fin; and prior to sensing the quantum state of the first quantum dot with the second quantum dot, allowing the first and third quantum dots to interact.
  • Example 20 provides the method according to Example 19, where allowing the first and third quantum dots to interact includes applying the one or more voltages to the one or more gates on the first fin to control interaction between the first and third quantum dots.
  • Example 21 provides a method of manufacturing a quantum dot device.
  • the method includes providing a quantum well stack on a semiconductor substrate, where the quantum well stack includes a quantum well layer of one or more lll-V compounds; removing at least some of the quantum well stack to form fins, where the fins include the quantum well layer; providing an insulating material between the fins; and forming gates on top of the fins.
  • Example 22 provides the method of Example 21, where providing the insulating material between the fins includes providing the insulating material between and on the fins; and polishing back the insulating material.
  • Example 23 provides a quantum computing device that includes a quantum processing device, a non-quantum processing device, and a memory device.
  • the quantum processing device includes a first fin in parallel with a second fin, an insulating material disposed between the first fin and the second fin, an active quantum well layer in the first fin, and a read quantum well layer in the second fin.
  • Each of the active quantum well layer and the read quantum well layer includes a quantum well layer of one or more lll-V compounds.
  • the non-quantum processing device is coupled to the quantum processing device and configured to control voltages applied to gates on the first and second fin.
  • the memory device is configured to store data generated by the read quantum well layer during operation of the quantum processing device.
  • Example 24 provides the quantum computing device according to Example 23, further including a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
  • Example 25 provides the quantum computing device according to any one of Examples 23-24, where the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

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Abstract

L'invention concerne des dispositifs à points quantiques, ainsi que des dispositifs et des procédés informatiques et procédé de fonctionnement associés. Par exemple, selon certains modes de réalisation, un dispositif à points quantiques peut comprendre : une base ; une ailette s'étendant à l'extérieur à partir de la base et comprenant une couche de puits quantique fait de semi-conducteur III-V, et une ou plusieurs grilles placées sur l'ailette. L'utilisation de semi-conducteurs III-V pour former une couche de puits quantique peut être avantageuse en raison d'un confinement plus fort de porteurs de charge dans un puits quantique et d'une mobilité de porteuse de charge améliorée. Des procédés pour la fabrication de tels dispositifs sont également décrits.
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