WO2017213649A1 - Dispositifs á points quantiques avec structures de puits quantiques doubles - Google Patents

Dispositifs á points quantiques avec structures de puits quantiques doubles Download PDF

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WO2017213649A1
WO2017213649A1 PCT/US2016/036576 US2016036576W WO2017213649A1 WO 2017213649 A1 WO2017213649 A1 WO 2017213649A1 US 2016036576 W US2016036576 W US 2016036576W WO 2017213649 A1 WO2017213649 A1 WO 2017213649A1
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quantum
quantum well
gates
quantum dot
well stack
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PCT/US2016/036576
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English (en)
Inventor
Ravi Pillarisetty
Jeanette M. Roberts
Van H. Le
David J. Michalak
Zachary R. YOSCOVITS
James S. Clarke
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Intel Corporation
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Priority to PCT/US2016/036576 priority Critical patent/WO2017213649A1/fr
Publication of WO2017213649A1 publication Critical patent/WO2017213649A1/fr

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66977—Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET

Definitions

  • Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.
  • FIGS. 1-3 are cross-sectional views of a quantum dot device, in accordance with various embodiments.
  • FIGS. 4-31 illustrate various example stages in the manufacture of a quantum dot device, in accordance with various embodiments.
  • FIGS. 32-33 are cross-sectional views of various examples of quantum well stacks that may be used in a quantum dot device, in accordance with various embodiments.
  • FIG. 34 illustrates an embodiment of a quantum dot device having multiple groups of gates on a single fin, in accordance with various embodiments.
  • FIGS. 35-37 illustrate various example stages in the manufacture of alternative gate arrangements that may be included in a quantum dot device, in accordance with various embodiments.
  • FIGS. 38-42 illustrate various alternative stages in the manufacture of a quantum dot device, in accordance with various embodiments.
  • FIG. 43 illustrates an example alternative stage in the manufacture of a quantum dot device, in accordance with various embodiments.
  • FIGS. 44-45 illustrate detail views of various embodiments of a doped region in a quantum dot device.
  • FIG. 46 is a flow diagram of an illustrative method of manufacturing a quantum dot device, in accordance with various embodiments.
  • FIGS. 47-48 are flow diagrams of illustrative methods of operating a quantum dot device, in accordance with various embodiments.
  • FIG. 49 is a block diagram of an example quantum computing device that may include any of the quantum dot devices disclosed herein, in accordance with various embodiments.
  • a quantum dot device may include: a quantum well stack including first and second quantum well layers, wherein a barrier layer is disposed between the first and second quantum well layers; a first set of gates disposed on the quantum well stack such that the first quantum well layer is disposed between the barrier layer and the first set of gates; and a second set of gates disposed on the quantum well stack such that the second quantum well layer is disposed between the barrier layer and the second set of gates.
  • the quantum dot devices disclosed herein may enable the formation of quantum dots to serve as quantum bits ("qubits") in a quantum computing device, as well as the control of these quantum dots to perform quantum logic operations. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein provide strong spatial localization of the quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.
  • the phrase “A and/or B” means (A), (B), or (A and B).
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
  • the notation "A/B/C” means (A), (B), and/or (C).
  • FIGS. 1-3 are cross-sectional views of a quantum dot device 100, in accordance with various embodiments.
  • FIG. 2 illustrates the quantum dot device 100 taken along the section A- A of FIG. 1 (while FIG. 1 illustrates the quantum dot device 100 taken along the section C-C of FIG. 2)
  • FIG. 3 illustrates the quantum dot device 100 taken along the section B-B of FIG. 1 with a number of components not shown to more readily illustrate how the gates 106/108 may be patterned (while FIG. 1 illustrates a quantum dot device 100 taken along the section D-D of FIG. 3).
  • FIG. 1 indicates that the cross-section illustrated in FIG. 2 is taken through the fin 104-1, an analogous cross section taken through the fin 104-2 may be identical, and thus the discussion of FIG. 2 refers generally to the "fin 104.”
  • the quantum dot device 100 may include multiple fins 104 spaced apart by insulating material 128.
  • the fins 104 may include a quantum well stack 146, which may include a quantum well layer 152-1 and a quantum well layer 152-2 spaced apart by a barrier layer 154. Examples of quantum well stacks 146 are discussed in detail below with reference to FIGS. 32-33.
  • the quantum dot device 100 may, in some embodiments, include a support 103 to provide mechanical support for the quantum dot device 100 (e.g., in the form of a carrier or other support). In some embodiments, the quantum dot device 100 may not include a support 103.
  • the total number of fins 104 included in the quantum dot device 100 is an even number, with the fins 104 organized into pairs including one active fin 104 and one read fin 104, as discussed in detail below.
  • the fins 104 may be arranged in pairs in a line (e.g., 2N fins total may be arranged in a lx2N line, or a 2xN line) or in pairs in a larger array (e.g., 2N fins total may be arranged as a 4xN/2 array, a 6xN/3 array, etc.).
  • a line e.g., 2N fins total may be arranged in a lx2N line, or a 2xN line
  • a larger array e.g., 2N fins total may be arranged as a 4xN/2 array, a 6xN/3 array, etc.
  • each of the fins 104 may include two quantum well layers 152.
  • the quantum well layers 152 included in the fins 104 may be arranged normal to the z-direction, and may provide layers in which a two-dimensional electron gas (2DEG) may form to enable the generation of a quantum dot during operation of the quantum dot device 100, as discussed in further detail below.
  • the quantum well layers 152 themselves may provide a geometric constraint on the z-location of quantum dots in the fins 104, and the limited extent of the fins 104 (and therefore the quantum well layers 152) in the y-direction may provide a geometric constraint on the y-location of quantum dots in the fins 104.
  • the fins 104 may be applied to gates disposed on the fins 104 to adjust the energy profile along the fins 104 in the x-direction and thereby constrain the x-location of quantum dots within quantum wells (discussed in detail below with reference to the gates 106/108).
  • the dimensions of the fins 104 may take any suitable values.
  • the fins 104 may each have a width 162 between 10 and 30 nanometers.
  • the fins 104 may each have a height 164 between 200 and 400 nanometers (e.g., between 250 and 350 nanometers, or equal to 300 nanometers).
  • the fins 104 may be arranged in parallel, as illustrated in FIGS. 1 and 3, and may be spaced apart by an insulating material 128, which may be disposed on opposite faces of the fins 104.
  • the insulating material 128 may be a dielectric material, such as silicon oxide.
  • the fins 104 may be spaced apart by a distance 160 between 100 and 250 microns.
  • Multiple gates may be disposed on each of the fins 104.
  • a first set of gates 105- 1 may be disposed proximate to the "bottom" of each fin 104
  • a second set of gates 105-2 may be disposed proximate to the "top” of each fin 104.
  • the first set of gates 105-1 includes three gates 106-1 and two gates 108-1
  • the second set of gates 105-2 includes three gates 106-2 and two gates 108-2.
  • This particular number of gates is simply illustrative, and any suitable number of gates may be used.
  • multiple sets of the gates 105-1 and 105-2 may be disposed on the fin 104.
  • the gate 108-11 may be disposed between the gates 106-11 and 106-12, and the gate 108-12 may be disposed between the gates 106-12 and 106-13.
  • the gates 106-21, 108- 21, 106-22, 108-22, and 106-23 are distributed along the fin 104 analogously to the distribution of the gates 106-11, 108-11, 106-12, 108-12, and 106-13 (of the set of gates 105-1).
  • References to a "gate 106" herein may refer to any of the gates 106, while reference to a "gate 108" herein may refer to any of the gates 108.
  • gates 106-1 herein may refer to any of the gates 106 of the first set of gates 105-1 (and analogously for the “gates 106-2") and reference to the "gates 108-1” herein may refer to any of the gates 108 of the first set of gates 105-1 (and analogously for the "gates 108-2").
  • Each of the gates 106/108 may include a gate dielectric 114 (e.g., the gate dielectric 114-1 for the gates 106-1/108-1, and the gate dielectric 114-2 for the gates 106-2/108-2).
  • the gate dielectric 114 for all of the gates 106/108 in a particular set of gates 105 is provided by a common layer of gate dielectric material.
  • the gate dielectric 114 for each of the gates 106/108 in a particular set of gates 105 may be provided by separate portions of gate dielectric 114 (e.g., as discussed below with reference to FIGS. 38-42).
  • the gate dielectric 114 may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the fin 104 and the corresponding gate metal).
  • the gate dielectric 114 may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric 114 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • Examples of materials that may be used in the gate dielectric 114 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric 114 to improve the quality of the gate dielectric 114.
  • the gate dielectric 114-1 may be a same material as the gate dielectric 114-2, or a different material.
  • Each of the gates 106-1 may include a gate metal 110-1.
  • the gate dielectric 114-1 may be disposed between the gate metal 110-1 and the quantum well stack 146.
  • the gate metal 110-1 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride.
  • the sides of the gate metal 110-1 may be substantially parallel, as shown in FIG. 2, and insulating spacers 134-1 may be disposed on the sides of the gate metal 110-1. As illustrated in FIG. 2, the spacers 134-1 may be thinner farther from the fin 104 and thicker closer to the fin 104.
  • the spacers 134-1 may have a convex shape.
  • the spacers 134-1 may be formed of any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride).
  • Each of the gates 108-1 may include a gate metal 112-1.
  • the gate dielectric 114-1 may be disposed between the gate metal 112-1 and the quantum well stack 146.
  • the gate metal 112-1 may be a different metal from the gate metal 110-1; in other embodiments, the gate metal 112-1 and the gate metal 110-1 may have the same material composition.
  • the gate metal 112-1 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride.
  • Each of the gates 106-2 may include a gate metal 110-2 and a hardmask 116-2.
  • the hardmask 116-2 may be formed of silicon nitride, silicon carbide, or another suitable material.
  • the gate metal 110-2 may be disposed between the hardmask 116-2 and the gate dielectric 114-2, and the gate dielectric 114-2 may be disposed between the gate metal 110-2 and the fin 104. Only one portion of the hardmask 116-2 is labeled in FIG. 2 for ease of illustration.
  • the gate metal 110-2 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride.
  • the hardmask 116-2 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 116-2 may be removed during processing, as discussed below).
  • the sides of the gate metal 110-2 may be substantially parallel, as shown in FIG. 2, and insulating spacers 134-2 may be disposed on the sides of the gate metal 110-2 and the hardmask 116-2.
  • the spacers 134-2 may be thicker closer to the fin 104 and thinner farther away from the fin 104.
  • the spacers 134-2 may have a convex shape.
  • the spacers 134-2 may be formed of any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride).
  • the gate metal 110-2 may be a different metal from the gate metal 110-1; in other embodiments, the gate metal 110-2 and the gate metal 110-1 may have the same material composition.
  • Each of the gates 108-2 may include a gate metal 112-2 and a hardmask 118-2.
  • the hardmask 118-2 may be formed of any of the materials discussed above with reference to the hardmask 116-2.
  • the gate metal 112-2 may be disposed between the hardmask 118-2 and the gate dielectric 114-2, and the gate dielectric 114-2 may be disposed between the gate metal 112-2 and the fin 104.
  • the hardmask 118-2 may extend over the hardmask 116-2 (and over the gate metal 110-2 of the gates 106-2), while in other embodiments, the hardmask 118-2 may not extend over the gate metal 110-2 (e.g., as discussed below with reference to FIG. 43).
  • the gate metal 112-2 may be a different metal from the gate metal 110-2; in other embodiments, the gate metal 112-2 and the gate metal 110-2 may have the same material composition. In some embodiments, the gate metal 112-2 may be a different metal from the gate metal 112-1; in other embodiments, the gate metal 112-2 and the gate metal 112-1 may have the same material composition. In some embodiments, the gate metal 112-2 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride. In some embodiments, the hardmask 118-2 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 118-2 may be removed during processing, as discussed below).
  • the gate 108-11 may extend between the proximate spacers 134-1 on the sides of the gate 106-11 and the gate 106-12, as shown in FIG. 2.
  • the gate metal 112-1 of the gate 108-11 may extend between the spacers 134-1 on the sides of the gate 106-11 and the gate 106-12.
  • the gate metal 112-1 of the gate 108-11 may have a shape that is substantially complementary to the shape of the spacers 134-1, as shown.
  • the gate 108-12 may extend between the proximate spacers 134-1 on the sides of the gate 106-12 and the gate 106-13.
  • the gates 106-2/108-2 and the dielectric material 114-2 of the second set of gates 105-2 may take the form of any of these embodiments of the gates 106-1/108-1 and the dielectric material 114-1. As illustrated in FIGS. 1 and 2, in some embodiments, the gates 106-1/108-1 may be mirror images of the gates 106-2/108-2 around the quantum well stack 146. In some embodiments in which the gate dielectric 114 is not a layer shared commonly between the associated gates 106 and 108, but instead is separately deposited on the fin 104 between the associated spacers 134 (e.g., as discussed below with reference to FIGS. 38-42), the gate dielectric 114 may extend at least partially up the sides of the associated spacers 134, and the gate metal 112 may extend between the portions of the associated gate dielectric 114 on the associated spacers 134.
  • the dimensions of the gates 106/108 may take any suitable values.
  • the z-height 166 of the gate metal 110 may be between 40 and 75 nanometers (e.g., approximately 50 nanometers); the z-height of the gate metal 112 may be in the same range. In embodiments like the ones illustrated in FIGS. 2, 37, and 43, the z-height of the gate metal 112 may be greater than the z-height of the gate metal 110.
  • the length 168 of the gate metal 110 i.e., in the x-direction
  • the distance 170 between adjacent ones of the gates 106 may be between 40 and 60 nanometers (e.g., 50 nanometers).
  • the thickness 172 of the spacers 134 may be between 1 and 10 nanometers (e.g., between 3 and 5 nanometers, between 4 and 6 nanometers, or between 4 and 7 nanometers).
  • the length of the gate metal 112 i.e., in the x-direction may depend on the dimensions of the gates 106 and the spacers 134, as illustrated in FIG. 2. As indicated in FIG.
  • the gates 106/108 on one fin 104 may extend over the insulating material 128 beyond their respective fins 104 and towards the other fin 104, but may be isolated from their counterpart gates by the intervening insulating material 130 and spacers 134.
  • the gates 106 and 108 of each set 105 may be alternatingly arranged along the fin 104 in the x-direction.
  • voltages may be applied to the gates 106-1/108-1 to adjust the potential energy in the quantum well layer 152-1 in the fin 104 to create quantum wells of varying depths in which quantum dots 142-1 may form.
  • quantum dots 142-2 may form. Only one quantum dot 142-1 and one quantum dot 142-2 are labeled with a reference numeral in FIG. 2 for ease of illustration, but five are indicated as dotted circles in each fin 104.
  • the spacers 134 may themselves provide "passive" barriers between quantum wells under the gates 106/108 in the associated quantum well layer 152, and the voltages applied to different ones of the gates 106/108 may adjust the potential energy under the gates 106/108 in the quantum well layer; decreasing the potential energy may form quantum wells, while increasing the potential energy may form quantum barriers.
  • the discussion below may generally refer to gates 106/108, quantum dots 142, and quantum well layers 152. This discussion may apply to the gates 106-1/108- 1, quantum dots 142-1, and quantum well layer 152-1, respectively; to the gates 106-2/108-2, quantum dots 142-2, and quantum well layer 152-2, respectively; or to both.
  • the fins 104 may include doped regions 140 that may serve as a reservoir of charge carriers for the quantum dot device 100.
  • the doped regions 140-1 may be in conductive contact with the quantum well layer 152-1
  • the doped regions 140-2 may be in conductive contact with the quantum well layer 152-2.
  • an n-type doped region 140 may supply electrons for electron-type quantum dots 142
  • a p-type doped region 140 may supply holes for hole-type quantum dots 142.
  • an interface material 141 may be disposed at a surface of a doped region 140, as shown by the interface material 141-1 at the surface of the doped regions 140-1 and the interface material 141-2 at the surface of the doped regions 140-2.
  • the interface material 141 may facilitate electrical coupling between a conductive contact (e.g., a conductive via 136, as discussed below) and the doped region 140.
  • the interface material 141 may be any suitable metal-semiconductor ohmic contact material; for example, in embodiments in which the doped region 140 includes silicon, the interface material 141 may include nickel silicide, aluminum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tungsten silicide, or platinum silicide (e.g., as discussed below with reference to FIGS. 28-29).
  • the interface material 141 may be a non-silicide compound, such as titanium nitride.
  • the interface material 141 may be a metal (e.g., aluminum, tungsten, or indium).
  • the quantum dot devices 100 disclosed herein may be used to form electron-type or hole- type quantum dots 142.
  • the polarity of the voltages applied to the gates 106/108 to form quantum wells/barriers depend on the charge carriers used in the quantum dot device 100.
  • amply negative voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108
  • amply positive voltages applied to a gate 106/108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in the associated quantum well layer 152 in which an electron-type quantum dot 142 may form).
  • amply positive voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108, and amply negative voltages applied to a gate 106 and 108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in the associated quantum well layer 152 in which a hole-type quantum dot 142 may form).
  • the quantum dot devices 100 disclosed herein may be used to form electron-type or hole-type quantum dots.
  • Voltages may be applied to each of the gates 106 and 108 separately to adjust the potential energy in the quantum well layer under the gates 106 and 108, and thereby control the formation of quantum dots 142 under each of the gates 106 and 108. Additionally, the relative potential energy profiles under different ones of the gates 106 and 108 allow the quantum dot device 100 to tune the potential interaction between quantum dots 142 under adjacent gates. For example, if two adjacent quantum dots 142 (e.g., one quantum dot 142-1 under a gate 106-1 and another quantum dot 142-1 under a gate 108-1) are separated by only a short potential barrier, the two quantum dots 142 may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each gate 106/108 may be adjusted by adjusting the voltages on the respective gates 106/108, the differences in potential between adjacent gates 106/108 may be adjusted, and thus the interaction tuned.
  • two adjacent quantum dots 142 e.g., one quantum do
  • the gates 108 may be used as plunger gates to enable the formation of quantum dots 142 under the gates 108, while the gates 106 may be used as barrier gates to adjust the potential barrier between quantum dots 142 formed under adjacent gates 108.
  • the gates 108 may be used as barrier gates, while the gates 106 are used as plunger gates.
  • quantum dots 142 may be formed under all of the gates 106 and 108, or under any desired subset of the gates 106 and 108.
  • Conductive vias and lines may make contact with the gates 106/108, and with the doped regions 140, to enable electrical connection to the gates 106/108 and the doped regions 140 to be made in desired locations.
  • the gates 106-1 may extend away from the fins 104, and conductive vias 120-1 may extend through the insulating material 130-2 to contact the gate metal 110-1 of the gates 106-1.
  • the gates 108-1 may extend away from the fins 104, and conductive vias 122-1 may extend through the insulating material 130-2 to contact the gate metal 112-1 of the gates 108-1.
  • the gates 106-2 may extend away from the fins 104, and conductive vias 120-2 may contact the gates 106-2 (and are drawn in dashed lines in FIG. 2 to indicate their location behind the plane of the drawing).
  • the conductive vias 120-2 may extend through the hardmask 116-2 and the hardmask 118-2 to contact the gate metal 110-2 of the gates 106-2.
  • the gates 108-2 may extend away from the fins 104, and conductive vias 122-2 may contact the gates 108-2 (also drawn in dashed lines in FIG. 2 to indicate their location behind the plane of the drawing).
  • the conductive vias 122-2 may extend through the hardmask 118-2 to contact the gate metal 112-2 of the gates 108-2.
  • Conductive vias 136 may contact the interface material 141 and may thereby make electrical contact with the doped regions 140.
  • the conductive vias 136-1 may extend through the insulating material 130 and make contact with the doped regions 140-1
  • the conductive vias 136-2 may extend through the insulating material 130 and make contact with the doped regions 140-2.
  • the quantum dot device 100 may include further conductive vias and/or lines (not shown) to make electrical contact to the gates 106/108 and/or the doped regions 140, as desired.
  • the conductive vias and lines included in a quantum dot device 100 may include any suitable materials, such as copper, tungsten (deposited, e.g., by CVD), or a superconductor (e.g., aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium).
  • tungsten deposited, e.g., by CVD
  • a superconductor e.g., aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium.
  • the fins 104 may include recesses 107 that extend down to the interface material 141-1 to make conductive contact with the doped regions 140-1 (and thereby the quantum well layer 152-1).
  • the recesses 107 may be filled with the insulating material 130, and the bottoms of the recesses 107 may be doped to provide the doped regions 140-1.
  • a bias voltage may be applied to the doped regions 140 (e.g., via the conductive vias 136 and the interface material 141) to cause current to flow through the doped regions 140.
  • this voltage may be positive; when the doped regions 140 are doped with a p-type material, this voltage may be negative.
  • the magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts).
  • the conductive vias 120, 122, and 136 may be electrically isolated from each other by an insulating material 130.
  • the insulating material 130 may be any suitable material, such as an interlayer dielectric (ILD). Examples of the insulating material 130 may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride.
  • ILD interlayer dielectric
  • conductive vias and lines may be formed in an iterative process in which layers of structures are formed on top of each other.
  • the conductive vias 120/122/136 may have a width that is 20 nanometers or greater at their widest point (e.g., 30 nanometers), and a pitch of 80 nanometers or greater (e.g., 100 nanometers). In some embodiments,
  • conductive lines (not shown) included in the quantum dot device 100 may have a width that is 100 nanometers or greater, and a pitch of 100 nanometers or greater.
  • the particular arrangement of conductive vias shown in FIGS. 1-3 is simply illustrative, and any electrical routing arrangement may be implemented.
  • the structure of the fin 104-1 may be the same as the structure of the fin 104-2; similarly, the construction of gates 106/108 on the fin 104-1 may be the same as the construction of gates 106/108 on the fin 104-2.
  • the gates 106/108 on the fin 104-1 may be mirrored by corresponding gates 106/108 on the parallel fin 104-2.
  • the insulating material 130-1 and the spacers 134-1 may separate the sets of gates 105-1 on the different fins 104-1 and 104-2, and the insulating material 130-2 and the spacers 134-2 may separate the sets of gates 105-2 on the different fins 104-1 and 104-2.
  • the quantum dots 142-2 in a fin 104 may be used as "active" quantum dots in the sense that these quantum dots 142-2 act as qubits and are controlled (e.g., by voltages applied to the gates 106-2/108-2 of the fin 104-1) to perform quantum computations.
  • the quantum dots 142-1 in a fin 104 may be used as "read” quantum dots in the sense that these quantum dots 142-2 may sense the quantum state of the quantum dots 142-2 in the same fin 104 by detecting the electric field generated by the charge in the quantum dots 142-1, and may convert the quantum state of the quantum dots 142-2 into electrical signals that may be detected by the gates 106-1/108-1.
  • Each quantum dot 142-2 in a fin 104 may be read by its corresponding quantum dot 142-1 in the fin 104.
  • the quantum dot device 100 enables both quantum computation and the ability to read the results of a quantum computation within a single fin, if desired.
  • the quantum dots 142 in the fin 104-1 may be used as "active" quantum dots in the sense that these quantum dots 142 act as qubits and are controlled (e.g., by voltages applied to the gates 106/108 of the fin 104-1) to perform quantum computations.
  • the quantum dots 142 in the fin 104-2 may be used as "read” quantum dots in the sense that these quantum dots 142 may sense the quantum state of the quantum dots 142 in the fin 104-1 by detecting the electric field generated by the charge in the quantum dots 142 in the fin 104-1, and may convert the quantum state of the quantum dots 142 in the fin 104-1 into electrical signals that may be detected by the gates 106/108 on the fin 104-2.
  • Each quantum dot 142 in the fin 104-1 may be read by its corresponding quantum dot 142 in the fin 104-2.
  • the quantum dot device 100 enables both quantum computation and the ability to read the results of a quantum computation across two fins 104.
  • FIGS. 4-31 illustrate various example stages in the manufacture of the quantum dot device 100 of FIGS. 1-3, in accordance with various embodiments. Although the particular manufacturing operations discussed below with reference to FIGS. 4-31 are illustrated as manufacturing a particular embodiment of the quantum dot device 100, these operations may be applied to manufacture many different embodiments of the quantum dot device 100, as discussed herein. Any of the elements discussed below with reference to FIGS. 4-31 may take the form of any of the embodiments of those elements discussed above (or otherwise disclosed herein). For ease of illustration, not all elements in each of FIGS. 4-31 are expressly labeled with reference numerals, but reference numerals for each element are included among the drawings of FIGS. 4-31.
  • FIG. 4 illustrates a cross-sectional view of an assembly 200 including a substrate 144.
  • the substrate 144 may include any suitable semiconductor material or materials.
  • the substrate 144 may include a semiconductor material.
  • the substrate 144 may include silicon (e.g., may be formed from a silicon wafer).
  • FIG. 5 illustrates a cross-sectional view of an assembly 202 subsequent to providing a quantum well stack 146 on the substrate 144 of the assembly 200 (FIG. 4).
  • the quantum well stack 146 may include a quantum well layer 152-1, a quantum well layer 152-2, and a barrier layer 154 disposed therebetween.
  • a 2DEG may form in the quantum well layer 152-1 and/or the quantum well layer 152-2 during operation of the quantum dot device 100.
  • FIGS. 32-33 Various embodiments of the quantum well stack 146 are discussed below with reference to FIGS. 32-33.
  • FIG. 6 illustrates a cross-sectional view of an assembly 204 subsequent to forming fins 104 in the assembly 202 (FIG. 5).
  • the fins 104 may extend from a base 102, and may be formed in the assembly 202 by patterning and then etching the assembly 202, as known in the art. For example, a combination of dry and wet etch chemistry may be used to form the fins 104, and the appropriate chemistry may depend on the materials included in the assembly 202, as known in the art.
  • At least some of the substrate 144 may be included in the base 102, and at least some of the quantum well stack 146 may be included in the fins 104.
  • the quantum well layers 152-1 and 152-2 (and the intervening barrier layer 154) of the quantum well stack 146 may be included in the fins 104.
  • FIG. 7 illustrates a cross-sectional view of an assembly 206 subsequent to providing an insulating material 128 to the assembly 204 (FIG. 6).
  • Any suitable material may be used as the insulating material 128 to electrically insulate the fins 104 from each other.
  • the insulating material 128 may be a dielectric material, such as silicon oxide.
  • FIG. 8 illustrates a cross-sectional view of an assembly 208 subsequent to planarizing the assembly 206 (FIG. 7) to remove the insulating material 128 above the fins 104.
  • the assembly 206 may be planarized using a chemical mechanical polishing (CMP) technique.
  • CMP chemical mechanical polishing
  • FIG. 9 is a perspective view of at least a portion of the assembly 208, showing the fins 104 extending from the base 102 and separated by the insulating material 128.
  • the cross-sectional views of FIGS. 4-8 are taken parallel to the plane of the page of the perspective view of FIG. 9.
  • FIG. 10 is another cross-sectional view of the assembly 208, taken along the dashed line along the fin 104-1 in FIG. 9.
  • the cross-sectional views illustrated in FIGS. 11-31 are taken along the same cross- section as FIG. 10.
  • FIG. 11 is a cross-sectional view of an assembly 210 subsequent to forming a gate stack 174 on the fins 104 of the assembly 208 (FIGS. 8-10).
  • the gate stack 174 may include the gate dielectric 114-1, the gate metal 110-1, and a hardmask 116-1.
  • the hardmask 116-1 may be formed of an electrically insulating material, such as silicon nitride or carbon-doped nitride.
  • FIG. 12 is a cross-sectional view of an assembly 212 subsequent to patterning the hardmask 116-1 of the assembly 210 (FIG. 11).
  • the pattern applied to the hardmask 116-1 may correspond to the locations for the gates 106-1, as discussed below.
  • the hardmask 116-1 may be patterned by applying a resist, patterning the resist using lithography, and then etching the hardmask (using dry etching or any appropriate technique).
  • FIG. 13 is a cross-sectional view of an assembly 214 subsequent to etching the assembly 212 (FIG. 12) to remove the gate metal 110-1 that is not protected by the patterned hardmask 116-1 to form the gates 106-1.
  • the gate dielectric 114-1 may remain after the etched gate metal 110-1 is etched away; in other embodiments, the gate dielectric 114-1 may also be etched during the etching of the gate metal 110-1. Examples of such
  • FIG. 14 is a cross-sectional view of an assembly 216 subsequent to providing spacer material 132 on the assembly 214 (FIG. 13).
  • the spacer material 132 may include any of the materials discussed above with reference to the spacers 134-1, for example, and may be deposited using any suitable technique.
  • the spacer material 132 may be a nitride material (e.g., silicon nitride) deposited by sputtering.
  • FIG. 15 is a cross-sectional view of an assembly 218 subsequent to etching the spacer material 132 of the assembly 216 (FIG. 14), leaving spacers 134-1 formed of the spacer material 132 on the sides of the gates 106-1 (e.g., on the sides of the hardmask 116-1 and the gate metal 110-1).
  • the etching of the spacer material 132 may be an anisotropic etch, etching the spacer material 132 "downward" to remove the spacer material 132 on top of the gates 106-1 and in some of the area between the gates 106-1, while leaving the spacers 134-1 on the sides of the gates 106.
  • the anisotropic etch may be a dry etch.
  • FIG. 16 is a cross-sectional view of an assembly 220 subsequent to providing the gate metal 112-1 on the assembly 218 (FIG. 15).
  • the gate metal 112-1 may fill the areas between adjacent ones of the gates 106-1, and may extend over the tops of the gates 106-1.
  • FIG. 17 is a cross-sectional view of an assembly 222 subsequent to planarizing the assembly 220 (FIG. 16) to remove the gate metal 112-1 above the gates 106-1.
  • the assembly 220 may be planarized using a CMP technique. Some of the remaining gate metal 112-1 may fill the areas between adjacent ones of the gates 106-1, while other portions 150 of the remaining gate metal 112-1 may be located "outside" of the gates 106-1.
  • FIG. 18 is a cross-sectional view of an assembly 224 subsequent to providing a hardmask 118-1 on the planarized surface of the assembly 222 (FIG. 17).
  • the hardmask 118-1 may be formed of any of the materials discussed above with reference to the hardmask 116-1, for example.
  • FIG. 19 is a cross-sectional view of an assembly 226 subsequent to patterning the hardmask 118-1 of the assembly 224 (FIG. 18).
  • the pattern applied to the hardmask 118-1 may extend over the hardmask 116-1 (and over the gate metal 110-1 of the gates 106-1, as well as over the locations for the gates 108-1 (as illustrated in FIG. 2).
  • the hardmask 118-1 may be non-coplanar with the hardmask 116-1, as illustrated in FIG. 19.
  • the hardmask 118-1 illustrated in FIG. 19 may thus be a common, continuous portion of hardmask 118-1 that extends over all of the hardmask 116-1.
  • the hardmask 118-1 may be patterned using any of the techniques discussed above with reference to the patterning of the hardmask 116-1, for example.
  • FIG. 20 is a cross-sectional view of an assembly 228 subsequent to etching the assembly 226 (FIG. 19) to remove the portions 150 that are not protected by the patterned hardmask 118-1 to form the gates 108-1. Portions of the hardmask 118-1 may remain on top of the hardmask 116-1, as shown.
  • the operations performed on the assembly 226 may include removing any gate dielectric 114-1 that is "exposed" on the fin 104, as shown.
  • the excess gate dielectric 114-1 may be removed using any suitable technique, such as chemical etching or silicon bombardment.
  • FIG. 21 is a cross-sectional view of an assembly 230 subsequent to providing an insulating material 130-1 on the assembly 228 (FIG. 20).
  • the insulating material 130-1 may take any of the forms discussed above.
  • the insulating material 130-1 may be a dielectric material, such as silicon oxide.
  • the insulating material 130-1 may be provided on the assembly 228 using any suitable technique, such as spin coating, chemical vapor deposition (CVD), or plasma-enhanced CVD (PECVD).
  • the insulating material 130-1 may be polished back after deposition, and before further processing.
  • the assembly 230 may be planarized to remove the hardmasks 116-1 and 118-1, then additional insulating material 130-1 may optionally be provided on the planarized surface; in such an embodiment, the hardmasks 116-1 and 118-1 would not be present in the quantum dot device 100.
  • FIG. 22 is a cross-sectional view of an assembly 232 subsequent to attaching a support 103 to the insulating material 130-1.
  • the support 103 may take any suitable form for providing mechanical support for the operations discussed below.
  • the support 103 may be a carrier wafer and may be secured to the insulating material 130-1 using an adhesive.
  • the support 103 may be a mechanical fixture that may be temporarily secured to the insulating material 130-1, and removed when no longer needed.
  • FIG. 23 is a cross-sectional view of an assembly 234 subsequent to removing the base 102 from the assembly 232 (FIG. 22).
  • the fin 104 may remain secured to the gates 106-1/108-1 and the insulating material 130-1 (which may be mechanically supported by the support 103).
  • Any suitable technique may be used to separate the base 102 from the rest of the assembly 232.
  • an ion implantation and wafer bonding technique may be used in which the support 103 is adhered to the assembly 230 (as discussed above with reference to FIG. 22) and then the base 102 is polished or etched away.
  • the base 102 may be mechanically separated from the rest of the assembly 232, and then the "broken" surface of the assembly 234 may be polished or etched.
  • FIG. 24 is a cross-sectional view of an assembly 236 subsequent to turning the assembly 234 (FIG. 23) "upside down" so that further processing may be performed on the exposed fin 104.
  • the assembly 234 need not be physically reoriented (as illustrated in FIG. 24) in order for subsequent processing operations to be performed.
  • FIG. 25 is a cross-sectional view of an assembly 238 subsequent to forming gates 106-2/108- 2 with a gate dielectric 114-2 on the fin 104 proximate to the quantum well layer 152-2.
  • the gates 106-2/108-2 may be formed using any of the techniques discussed above with reference to the formation of the gates 106-1/108-1 (e.g., discussed above with reference to FIGS. 11-20), or any of the techniques discussed below (e.g., with reference to FIGS. 36-44).
  • hardmasks 116-2 and 118-2 may be part of the gates 106-2/108-2, analogously to the hardmasks 116-1 and 118-1 of the gates 106-1/108-1.
  • FIG. 25 is a cross-sectional view of an assembly 238 subsequent to forming gates 106-2/108- 2 with a gate dielectric 114-2 on the fin 104 proximate to the quantum well layer 152-2.
  • the gates 106-2/108-2 may be formed using any of the techniques discussed above with reference to the formation
  • FIG. 26 is a cross-sectional view of an assembly 240 subsequent to forming recesses 107 in the quantum well stack 146 of the assembly 238 (FIG. 25).
  • the recesses 107 may be formed using any of the fin patterning techniques discussed above with reference to FIG. 6, and as discussed above, may extend down to the barrier layer 154 (and may extend down into the quantum well layer 152-1).
  • FIG. 27 is a cross-sectional view of an assembly 242 subsequent to doping the quantum well stack 146 of the assembly 240 (FIG. 26) to form doped regions 140-1 at the bottoms of the recesses 107 in the quantum well stack 146, and doped regions 140-2 adjacent to the gates 106-2/108-2.
  • the doped regions 140-1 may be in conductive contact with the quantum well layer 152-1
  • the doped regions 140-2 may be in conductive contact with the quantum well layer 152-2.
  • the type of dopant used to form the doped regions 140 may depend on the type of quantum dot desired, as discussed above. In some embodiments, the doping may be performed by ion implantation.
  • the doped regions 140 may be formed by ion implantation of phosphorous, arsenic, or another n-type material.
  • the doped regions 140 may be formed by ion implantation of boron or another p-type material. An annealing process that activates the dopants and causes them to diffuse farther into the fins 104 may follow the ion implantation process.
  • the depth of the doped regions 140 may take any suitable value; for example, in some embodiments, the doped regions 140 may each have a depth 115 between 500 and 1000
  • the outer spacers 134-2 on the outer gates 106-2 may provide a doping boundary, limiting diffusion of the dopant from the doped regions 140-2 into the area under the gates 106-2/108-2. As shown, the doped regions 140-2 may extend under the adjacent outer spacers 134-2. In some embodiments, the doped regions 140-2 may extend past the outer spacers 134-2 and under the gate metal 110-2 of the outer gates 106-2, may extend only to the boundary between the outer spacers 134-2 and the adjacent gate metal 110-2, or may terminate under the outer spacers 134-2 and not reach the boundary between the outer spacers 134-2 and the adjacent gate metal 110-2. Examples of such embodiments are discussed below with reference to FIGS. 44 and 45.
  • the doping concentration of the doped regions 140 may, in some embodiments, be between 10 17 /cm 3 and 10 20 /cm 3 .
  • FIG. 28 is a cross-sectional side view of an assembly 244 subsequent to providing a layer of nickel or other material 143 over the assembly 242 (FIG. 27).
  • the nickel or other material 143 may be deposited on the assembly 242 using any suitable technique (e.g., a plating technique, chemical vapor deposition, or atomic layer deposition).
  • FIG. 29 is a cross-sectional side view of an assembly 246 subsequent to annealing the assembly 244 (FIG. 28) to cause the material 143 to interact with the doped regions 140 to form the interface material 141, then removing the unreacted material 143.
  • the interface material 141 may be nickel silicide.
  • interface materials 141 Materials other than nickel may be deposited in the operations discussed above with reference to FIG. 28 in order to form other interface materials 141, including titanium, aluminum, molybdenum, cobalt, tungsten, or platinum, for example. More generally, the interface material 141 of the assembly 246 may include any of the materials discussed herein with reference to the interface material 141.
  • FIG. 30 is a cross-sectional view of an assembly 248 subsequent to providing an insulating material 130-2 on the assembly 246 (FIG. 29).
  • the insulating material 130-2 may take any of the forms discussed above.
  • the insulating material 130-2 may be a dielectric material, such as silicon oxide.
  • the insulating material 130-2 may be provided on the assembly 246 using any suitable technique, such as spin coating, chemical vapor deposition (CVD), or plasma-enhanced CVD (PECVD).
  • the insulating material 130-2 may be polished back after deposition, and before further processing.
  • FIG. 31 is a cross-sectional view of an assembly 250 subsequent to forming, in the assembly 248 (FIG. 30), conductive vias 120 through the insulating material 130-2 (and the hardmasks 116 and 118) to contact the gate metal 110 of the gates 106 (only the conductive vias 120-2 are illustrated in FIG. 31, but the conductive vias 120-1 are illustrated in FIG. 3), conductive vias 122 through the insulating material 130 (and the hardmask 118) to contact the gate metal 112 of the gates 108 (only the conductive vias 122-2 are illustrated in FIG. 31, but the conductive vias 122-1 are illustrated in FIG.
  • the resulting assembly 250 may take the form of the quantum dot device 100 discussed above with reference to FIGS. 1-3.
  • the assembly 250 may be planarized to remove the hardmasks 116-2 and 118-2, then additional insulating material 130-2 may be provided on the planarized surface before forming the conductive vias 120, 122, and 136; in such an embodiment, the hardmasks 116-2 and 118-2 would not be present in the quantum dot device 100.
  • a quantum well stack 146 included in a quantum dot device 146 may take any of a number of forms, several of which are illustrated in FIGS. 32-33.
  • FIG. 32 is a cross-sectional view of a quantum well stack 146 including only a quantum well layer 152-1, a barrier layer 154, and a quantum well layer 152-2.
  • the quantum well layers 152 of FIG. 32 may be formed of intrinsic silicon, and the gate dielectrics 114 may be formed of silicon oxide; in such an arrangement, during use of the quantum dot device 100, a 2DEG may form in the intrinsic silicon at the interface between the intrinsic silicon and the proximate silicon oxide.
  • the quantum well layers 152 of FIG. 32 are formed of intrinsic silicon may be particularly advantageous for electron-type quantum dot devices 100.
  • the gate dielectrics 114 may be formed of germanium oxide; in such an arrangement, during use of the quantum dot device 100, a 2DEG may form in the intrinsic germanium at the interface between the intrinsic germanium and the proximate germanium oxide. Such embodiments may be particularly advantageous for hole-type quantum dot devices 100.
  • the quantum well layers 152 may be strained, while in other embodiments, the quantum well layers 152 may not be strained.
  • the barrier layer 154 of FIG. 32 may provide a potential barrier between the quantum well layer 152-1 and the quantum well layer 152-2.
  • the barrier layer 154 may be formed of silicon germanium.
  • the germanium content of this silicon germanium may be 20-80% (e.g., 30%).
  • the barrier layer 154 may be formed of silicon germanium (with a germanium content of 20-80% (e.g., 70%)).
  • the thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 32 may take any suitable values.
  • the thickness of the barrier layer 154 e.g., silicon germanium
  • the thickness of the quantum well layers 152 e.g., silicon or germanium
  • the quantum well stack 146 of FIG. 32 may be disposed between the sets of gates 105-1 and 105-2, as discussed above.
  • the layers of the quantum well stack 146 of FIG. 32 (and 33) may be grown on the substrate 144 (and on each other) by epitaxy.
  • FIG. 33 is a cross-sectional view of a quantum well stack 146 including quantum well layers 152-1 and 152-2, a barrier layer 154-2 disposed between the quantum well layers 152-1 and 152-2, and additional barrier layers 154-1 and 154-3.
  • the quantum well stack 146 may be disposed on the gate dielectric 114-1 such that the barrier layer 154-1 is disposed between the quantum well layer 152-1 and the gate dielectric 114-1.
  • the barrier layer 154-3 may be disposed between the quantum well layer 152-2 and the gate dielectric 114-2.
  • the barrier layer 154-3 may be formed of a material (e.g., silicon germanium), and when the quantum well stack 146 is being grown on the substrate 144, the barrier layer 154-3 may include a buffer region of that material. This buffer region may trap defects that form in this material as it is grown on the substrate 144, and in some embodiments, the buffer region may be grown under different conditions (e.g., deposition temperature or growth rate) from the rest of the barrier layer 154-3. In particular, the rest of the barrier layer 154-3 may be grown under conditions that achieve fewer defects than the buffer region.
  • the quantum well stack 146 may be "broken" in a buffer region of the barrier layer 154-3.
  • the barrier layers 154-1 and 154-3 may provide potential energy barriers around the quantum well layers 152-1 and 152-2, respectively, and the barrier layer 154-1 may take the form of any of the embodiments of the barrier layer 154-3 discussed herein.
  • the barrier layer 154-2 may take the form of any of the embodiments of the barrier layer 154 discussed above with reference to FIG. 32.
  • the thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 33 may take any suitable values.
  • the thickness of the barrier layers 154-1 and 154-3 e.g., silicon germanium
  • the thickness of the barrier layers 154-1 and 154-3 may be between 0 and 400 nanometers.
  • the thickness of the quantum well layers 152 may be between 5 and 30 nanometers (e.g., 10 nanometers). In some embodiments, the thickness of the barrier layer 154-2 (e.g., silicon germanium) may be between 25 and 75 nanometers (e.g., 32 nanometers).
  • the fins 104 have been illustrated in many of the preceding figures as substantially rectangular with parallel sidewalls, this is simply for ease of illustration, and the fins 104 may have any suitable shape (e.g., a shape appropriate to the manufacturing processes used to form the fins 104).
  • the fins 104 may be tapered, narrowing as they extend away from the base 102 (FIG. 6).
  • the fins 104 may taper by 3-10 nanometers in x-width for every 100 nanometers in z-height (e.g., 5 nanometers in x-width for every 100 nanometers in z-height).
  • a single fin 104 may include multiple groups of the sets of gates 105-1 and 105-2, spaced apart along the fin 104.
  • FIG. 34 is a cross-sectional view of an example of such a quantum dot device 100 having multiple groups of sets of gates 180 on a single fin 104, in accordance with various embodiments.
  • Each of the groups 180 may include a set of gates 105-1 and a set of gates 105-2 (not labeled in FIG. 34 for ease of illustration) that may take the form of any of the embodiments of the sets of gates 105-1 and 105-2 discussed herein.
  • a doped region 140-1 (and its interface material 141-1) may be disposed between the sets of gates 105-1 of two adjacent groups 180 (labeled in FIG.
  • this "common" doped region 140-1 may be electrically contacted by a single conductive via 136-1.
  • the particular number of gates 106/108 illustrated in FIG. 34, and the particular number of groups 180, is simply illustrative, and a fin 104 may include any suitable number of gates 106/108 arranged in any suitable number of groups 180.
  • the z-height of the gate metal 112 of the gates 108 may be approximately equal to the sum of the z-height of the gate metal 110 and the z-height of the hardmask 116, as shown. Also in the embodiment of FIG. 2, the gate metal 112 of the gates 108 may not extend in the x-direction beyond the adjacent spacers 134.
  • FIGS. 35-37 illustrate various example stages in the manufacture of alternative gate arrangements that may be included in a quantum dot device 100, in accordance with various embodiments.
  • FIGS. 35-37 illustrate these example stages with reference to the formation of the gates 106-1/108-1, but the same stages may be used to form the gates 106-1/108-1 instead of or in addition to the gates 106-1/108-1.
  • FIG. 35 illustrates an assembly 252 subsequent to providing the gate metal 112-1 and a hardmask 118-1 on the assembly 218 (FIG. 15).
  • the assembly 252 may be similar to the assembly 224 of FIG. 18 (and may be formed using any of the techniques discussed above with reference to FIGS. 16-18), but may include additional gate metal 112-1 between the hardmask 116-1 and the hardmask 118-1, of any desired thickness.
  • the gate metal 112-1 may be planarized prior to provision of the hardmask 118-1, but the hardmask 118-1 may still be spaced away from the hardmask 116-1 in the z-direction by the gate metal 112, as shown in FIG. 35.
  • FIG. 36 illustrates an assembly 254 subsequent to patterning the hardmask 118-1 of the assembly 252 (FIG. 35).
  • the pattern applied to the hardmask 118-1 may include the locations for the gates 108-1, as discussed below.
  • the hardmask 118-1 may be non-coplanar with the hardmask 116- 1, as illustrated in FIG. 35, and may extend "over" at least a portion of the hardmask 116-1 (and thus over the gate metal 110-1 of the gates 106-1).
  • FIG. 37 illustrates an assembly 256 subsequent to etching the assembly 254 (FIG. 36) to remove the portions 150 of the gate metal 112-1 that are not protected by the patterned hardmask 118-1 to form the gates 108-1.
  • the gate metal 112-1 of the gates 106-1 may extend "over" the hardmask 116-1 of the gates 108-1, and may be electrically insulated from the gate metal 110-1 by the hardmask 116-1.
  • the z-height of the gate metal 112-1 of the gates 108-1 may be greater than the sum of the z-height of the gate metal 110-1 and the z- height of the hardmask 116-1 of the gates 106-1.
  • the gate metal 112-1 of the gates 108-1 may extend beyond the spacers 134-1 in the x-direction, as shown. Further manufacturing operations may be performed on the assembly 246, as discussed above with reference to FIGS. 21- 31.
  • FIGS. 38-42 illustrate various alternative stages in the manufacture of such an embodiment of a quantum dot device 100, in accordance with various embodiments.
  • the operations illustrated in FIGS. 38-42 may take the place of the operations illustrated in FIGS. 13-15 with reference to the formation of the gates 106-1/108-1, but the same stages may be used to form the gates 106-1/108-1 instead of or in addition to the gates 106-1/108-1.
  • FIG. 38 is a cross-sectional view of an assembly 258 subsequent to etching the assembly 212 (FIG. 12) to remove the gate metal 110-1, and the gate dielectric 114-1 that is not protected by the patterned hardmask 116-1, to form the gates 106-1.
  • FIG. 39 is a cross-sectional view of an assembly 260 subsequent to providing spacer material 132 on the assembly 258 (FIG. 38).
  • the deposition of the spacer material 132 may take any of the forms discussed above with reference to FIG. 14, for example.
  • FIG. 40 is a cross-sectional view of an assembly 262 subsequent to etching the spacer material 132 of the assembly 260 (FIG. 39), leaving spacers 134-1 formed of the spacer material 132 on the sides of the gates 106-1 (e.g., on the sides of the hardmask 116-1, the gate metal 110-1, and the gate dielectric 114-1).
  • the etching of the spacer material 132 may take any of the forms discussed above with reference to FIG. 15, for example.
  • FIG. 41 is a cross-sectional view of an assembly 264 subsequent to providing a gate dielectric 114-1 on the fin 104 between the gates 106-1 of the assembly 262 (FIG. 40).
  • the gate dielectric 114-1 provided between the gates 106-1 of the assembly 262 may be formed by atomic layer deposition (ALD) and, as illustrated in FIG. 41, may cover the exposed fin 104 between the gates 106-1, and may extend onto the adjacent spacers 134-1.
  • ALD atomic layer deposition
  • FIG. 42 is a cross-sectional view of an assembly 266 subsequent to providing the gate metal 112-1 on the assembly 264 (FIG. 41).
  • the gate metal 112-1 may fill the areas between adjacent ones of the gates 106-1, and may extend over the tops of the gates 106-1, as shown.
  • the provision of the gate metal 112-1 may take any of the forms discussed above with reference to FIG. 16, for example.
  • the assembly 256 may be further processed as discussed above with reference to FIGS. 17-31.
  • the pattern applied to the hardmask 118-1 may not result in a common, continuous portion of hardmask 118-1 that extends over all of the hardmask 116-1.
  • FIG. 43 is a cross-sectional view of an assembly 268 in which the hardmask 118-1 of the assembly 224 (FIG. 18) is not patterned to extend over the gates 106-1, but instead is patterned so as not to extend over the gate metal 110-1.
  • the assembly 268 may be further processed as discussed above with reference to FIGS.
  • the hardmasks 116-1 and 118-1 may remain in the quantum dot device 100 as part of the gates 106-1/108-1, while in other embodiments, the hardmasks 116-1 and 118-1 may be removed. Analogous structures and operations may be performed with respect to the gates 106-2/108-2, instead of or in addition to the gates 106-1/108-1.
  • the outer spacers 134-2 on the outer gates 106-2 may provide a doping boundary, limiting diffusion of the dopant from the doped regions 140-2 into the area under the gates 106-2/108-2.
  • the doped regions 140-2 may extend past the outer spacers 134-2 and under the outer gates 106-2.
  • the doped region 140-2 may extend past the outer spacers 134-2 and under the outer gates 106-2 by a distance 182 between 0 and 10 nanometers.
  • the doped regions 140-2 may not extend past the outer spacers 134-2 toward the outer gates 106-2, but may instead "terminate" under the outer spacers 134-2.
  • the doped regions 140-2 may be spaced away from the interface between the outer spacers 134-2 and the outer gates 106-2 by a distance 184 between 0 and 10 nanometers.
  • the interface material 141-2 is omitted from FIGS. 44 and 45 for ease of illustration.
  • FIG. 46 is a flow diagram of an illustrative method 1000 of manufacturing a quantum dot device, in accordance with various embodiments. Although the operations discussed below with reference to the method 1000 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 1000 may be illustrated with reference to one or more of the
  • a quantum well stack may be provided.
  • the quantum well stack may include first and second quantum well layers spaced apart by a barrier layer.
  • a quantum well stack 146 may be provided (e.g., on the substrate 144), and may include quantum well layers 152-1 and 152-2 spaced apart by a barrier layer 154 (e.g., as discussed above with reference to FIGS. 4-5 and 32-33).
  • first gates may be formed above a first face of the quantum well stack, proximate to the first quantum well layer.
  • gates 106-1 and 108-1 may be formed proximate to the quantum well layer 152-1 (e.g., as discussed above with reference to FIGS. 11-20).
  • second gates may be formed above a second face of the quantum well stack.
  • the second face may be opposite to the first face, and proximate to the second quantum well layer.
  • gates 106-2 and 108-2 may be formed proximate to the quantum well layer 152-2 (e.g., as discussed above with reference to FIG. 25).
  • FIGS. 47-48 are flow diagrams of particular illustrative methods 1020 and 1040, respectively, of operating a quantum dot device, in accordance with various embodiments. Although the operations discussed below with reference to the methods 1020 and 1040 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the methods 1020 and 1040 may be illustrated with reference to one or more of the embodiments discussed above, but the methods 1020 and 1040 may be used to operate any suitable quantum dot device (including any suitable ones of the embodiments disclosed herein).
  • electrical signals may be applied to a first set of gates disposed proximate to a first face of a quantum well stack to cause a first quantum dot to form in a first quantum well layer in the quantum well stack under the first set of gates.
  • one or more voltages may be applied to the gates 106-1/108-1 on a quantum well stack 146 to cause at least one quantum dot 142-1 to form in the quantum well layer 152-1.
  • electrical signals may be applied to a second set of gates disposed proximate to a second face of the quantum well stack to cause a second quantum dot to form in a second quantum well layer in the quantum well stack under the second set of gates.
  • the first and second quantum well layers may be spaced apart by a barrier layer, and the first and second faces of the quantum well stack may be opposing faces of the quantum well stack.
  • one or more voltages may be applied to the gates 106-2/108-2 on a quantum well stack 146 to cause at least one quantum dot 142-2 to form in the quantum well layer 152-2.
  • a quantum state of the first quantum dot may be sensed with the second quantum dot.
  • a quantum state of a quantum dot 142-1 in the quantum well layer 152-1 may be sensed by a quantum dot 142-2 in the quantum well layer 152-2.
  • electrical signals may be provided to a first gate disposed on a quantum well stack to cause a first quantum dot to form in a first quantum well layer in the quantum well stack under the first gate.
  • the quantum well stack may also include a second quantum well layer spaced apart from the first quantum well layer by a barrier layer.
  • a voltage may be applied to the gate 108-11 disposed on a fin 104 to cause a first quantum dot 142-1 to form in the quantum well layer 152-1 in the fin 104 under the gate 108-11.
  • a quantum well stack 146 in the fin 104 may also include a quantum well layer 152-2 spaced apart from the quantum well layer 152-1 by a barrier layer 154.
  • electrical signals may be provided to a second gate disposed on the quantum well stack to cause a second quantum dot to form in the first quantum well layer in the quantum well stack under the second gate.
  • a voltage may be applied to the gate 108-12 disposed on the fin 104 to cause a second quantum dot 142-2 to form in the quantum well layer 152-1 under the gate 108-12.
  • electrical signals may be provided to a third gate disposed on the quantum well stack to (1) cause a third quantum dot to form in the first quantum well layer under the third gate or (2) provide a potential barrier between the first quantum dot in the second quantum dot.
  • a voltage may be applied to the gate 106-12 to (1) cause a third quantum dot 142-1 to form in the quantum well layer 152-1 in the fin 104 (e.g., when the gate 106-12 acts as a "plunger” gate) or (2) provide a potential barrier between the first quantum dot 142-1 (under the gate 108-11) and the second quantum dot 142-1 (under the gate 108-12) (e.g., when the gate 106-12 acts as a "barrier" gate).
  • FIG. 49 is a block diagram of an example quantum computing device 2000 that may include any of the quantum dot devices disclosed herein.
  • a number of components are illustrated in FIG. 49 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application.
  • some or all of the components included in the quantum computing device 2000 may be attached to one or more printed circuit boards (e.g., a motherboard).
  • various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die.
  • the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 49, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components.
  • the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled.
  • the quantum computing device 2000 may not include an audio input device 2024 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2024 or audio output device 2008 may be coupled.
  • the quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices).
  • processing device e.g., one or more processing devices
  • the term "processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices).
  • the quantum processing device 2026 may include one or more of the quantum dot devices 100 disclosed herein, and may perform data processing by performing operations on the quantum dots that may be generated in the quantum dot devices 100, and monitoring the result of those operations. For example, as discussed above, different quantum dots may be allowed to interact, the quantum states of different quantum dots may be set or transformed, and the quantum states of quantum dots may be read (e.g., by another quantum dot).
  • the quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc.
  • the quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.
  • the processing device 2002 may include a non-quantum processing device 2028.
  • the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026.
  • the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc.
  • the non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026.
  • the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components.
  • the non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
  • DSPs digital signal processors
  • ASICs application-specific integrated circuits
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute cryptographic algorithms within hardware
  • server processors or any other suitable processing devices.
  • the quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid state memory
  • solid state memory solid state memory
  • hard drive solid state memory
  • the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004.
  • the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).
  • eDRAM embedded dynamic random access memory
  • STT-MRAM spin transfer torque magnetic random-access memory
  • the quantum computing device 2000 may include a cooling apparatus 2030.
  • the cooling apparatus 2030 may maintain the quantum processing device 2026 at a predetermined low temperature during operation to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less.
  • the non- quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature.
  • the cooling apparatus 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.
  • the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips).
  • the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UM B) project (also referred to as "3GPP2”), etc.).
  • IEEE 1402.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for
  • Microwave Access which is a certification mark for products that pass conformity
  • the communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • High Speed Packet Access HSPA
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • the communication chip 2012 may operate in accordance with other wireless protocols in other embodiments.
  • the quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless
  • the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet).
  • the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless
  • a second communication chip 2012 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
  • a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.
  • the quantum computing device 2000 may include battery/power circuitry 2014.
  • the battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).
  • the quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above).
  • the display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
  • LCD liquid crystal display
  • the quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above).
  • the audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
  • the quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above).
  • the audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (M IDI) output).
  • M IDI musical instrument digital interface
  • the quantum computing device 2000 may include a global positioning system (GPS) device 2018 (or corresponding interface circuitry, as discussed above).
  • GPS global positioning system
  • the GPS device 2018 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.
  • the quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above).
  • Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
  • the quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above).
  • Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • RFID radio frequency identification
  • the quantum computing device 2000 may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
  • a hand-held or mobile computing device e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.
  • PDA personal digital assistant
  • a desktop computing device e.g., a
  • any of the quantum dot devices 100 (or associated methods or devices) discussed herein may include three or more quantum well layers 152, in accordance with the teachings of the present disclosure.
  • various ones of the quantum dot devices 100 disclosed herein may be regarded as stacked quantum well structures including two or more quantum well layers 152.
  • a double quantum well structure in a quantum dot device 100 may include two or more quantum well layers 152.
  • Example 1 is a quantum dot device, including: a quantum well stack including first and second quantum well layers, wherein a barrier layer is disposed between the first and second quantum well layers; a first set of gates disposed on the quantum well stack such that the first quantum well layer is disposed between the barrier layer and the first set of gates; and a second set of gates disposed on the quantum well stack such that the second quantum well layer is disposed between the barrier layer and the second set of gates.
  • Example 2 may include the subject matter of Example 1, and may further specify that the first and second quantum well layers are formed of silicon.
  • Example 3 may include the subject matter of any of Examples 1-2, and may further specify that the barrier layer is formed of silicon germanium.
  • Example 4 may include the subject matter of any of Examples 1-3, and may further include: an insulating material disposed on the quantum well stack; first and second conductive pathways that extend through the insulating material to conductively contact the first quantum well layer; and third and fourth conductive pathways that extend through the insulating material to conductively contact the second quantum well layer.
  • Example 5 may include the subject matter of Example 4, and may further specify that the insulating material extends between the second quantum well layer and the third conductive pathway.
  • Example 6 may include the subject matter of any of Examples 4-5, and may further specify that the third and fourth conductive pathways extend through the barrier layer.
  • Example 7 may include the subject matter of any of Examples 4-5, and may further specify that the first and second conductive pathways conductively contact the first quantum well layer via first doped regions in the quantum well stack.
  • Example 8 may include the subject matter of Example 7, and may further specify that the third and fourth conductive pathways contact the second quantum well layer via second doped regions in the quantum well stack.
  • Example 9 may include the subject matter of any of Examples 1-8, and may further specify that the first set of gates includes first, second, and third gates, and the quantum dot device further includes spacers disposed on sides of the first and second gates; wherein a first spacer is disposed on a side of the first gate proximate to the second gate, a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed on the quantum well stack between the first and second gates and extending between the first and second spacers.
  • Example 10 may include the subject matter of any of Examples 1-9, and may further include a first insulating material disposed on at least two opposing faces of the quantum well stack.
  • Example 11 may include the subject matter of Example 10, and may further include:
  • Example 12 may include the subject matter of any of Examples 1-11, and may further specify that the second set of gates is a mirror image of the first set of gates around the quantum well stack.
  • Example 13 may include the subject matter of any of Examples 1-12, and may further specify that the quantum well stack is a first quantum well stack, and the quantum dot device further includes: a second quantum well stack including first and second quantum well layers, wherein a barrier layer of the second quantum well stack is disposed between the first and second quantum well layers of the second quantum well stack; a third set of gates disposed on the second quantum well stack such that the first quantum well layer of the second quantum well stack is disposed between the barrier layer and the third set of gates of the second quantum well stack; and a fourth set of gates disposed on the second quantum well stack such that the second quantum well layer of the second quantum well stack is disposed between the barrier layer and the fourth set of gates of the second quantum well stack.
  • Example 14 may include the subject matter of Example 13, and may further specify that the first and third sets of gates are spaced apart by a first insulating material, and the second and fourth sets of gates are spaced apart by a second insulating material.
  • Example 15 may include the subject matter of any of Examples 13-14, and may further specify that the first and second quantum well stacks are arranged parallel to one another.
  • Example 16 is a method of operating a quantum dot device, including: applying electrical signals to a first set of gates disposed proximate to a first face of a quantum well stack to cause a first quantum dot to form in a first quantum well layer in the quantum well stack under the first set of gates; applying electrical signals to a second set of gates disposed proximate to a second face of the quantum well stack to cause a second quantum dot to form in a second quantum well layer in the quantum well stack under the second gate, wherein the first and second quantum well layers are spaced apart by a barrier layer, and the first and second faces of the quantum well stack are opposing faces of the quantum well stack; and sensing a quantum state of the first quantum dot with the second quantum dot.
  • Example 17 may include the subject matter of Example 16, and may further specify that sensing the quantum state of the first quantum dot with the second quantum dot comprises sensing a spin state of the first quantum dot with the second quantum dot.
  • Example 18 may include the subject matter of any of Examples 16-17, and may further include: applying the electrical signals to the first set of gates to cause a third quantum dot to form in the first quantum well layer; and prior to sensing the quantum state of the first quantum dot with the second quantum dot, allowing the first and third quantum dots to interact.
  • Example 19 may include the subject matter of Example 18, and may further specify that allowing the first and third quantum dots to interact includes applying the electrical signals to the first set of gates to control interaction between the first and third quantum dots.
  • Example 20 may include the subject matter of any of Examples 16-19, and may further include applying the electrical signals to the first set of gates to cause a third quantum dot to form in the first quantum well layer.
  • Example 21 may include the subject matter of Example 20, and may further include applying the electrical signals to the first set of gates to provide a potential barrier between the first quantum dot and the third quantum dot.
  • Example 22 is a method of manufacturing a quantum dot device, including: providing a quantum well stack, wherein the quantum well stack includes first and second quantum well layers spaced apart by a barrier layer; forming first gates above a first face of the quantum well stack proximate to the first quantum well layer; and forming second gates above a second face of the quantum well stack, wherein the second face of the quantum well stack is opposite to the first face of the quantum well stack and proximate to the second quantum well layer.
  • Example 23 may include the subject matter of Example 22, and may further specify that providing the quantum well stack includes providing the quantum well stack on a support, and the method further includes, after forming the first gates, separating the quantum well stack from the support.
  • Example 24 may include the subject matter of any of Examples 22-23, and may further include: after forming the second gates, removing at least some of the second quantum well layer from the quantum well stack to form recesses; and providing insulating material in the recesses.
  • Example 25 may include the subject matter of Example 24, and may further include, before providing the insulating material in the recesses, doping the quantum well stack to introduce dopant to portions of the first quantum well layer and to portions of the second quantum well layer.
  • Example 26 may include the subject matter of any of Examples 24-25, and may further include forming conductive pathways through the insulating material to the first quantum well layer.
  • Example 27 may include the subject matter of any of Examples 22-26, and may further specify that providing the quantum well stack includes forming the quantum well stack by epitaxy.
  • Example 28 may include the subject matter of any of Examples 22-27, and may further include, prior to forming the first gates, removing at least some of the quantum well stack to form fins, and providing an insulating material between the fins.
  • Example 29 is a quantum computing device, including: a quantum processing device, wherein the quantum processing device includes a quantum well stack including an active quantum well layer and a read quantum well layer spaced apart by a barrier layer, first gates to control formation of quantum dots in the active quantum well layer, and second gates to control formation of quantum dots in the read quantum well layer; a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the first gates and the second gates; and a memory device to store data generated by the read quantum well layer during operation of the quantum processing device.
  • a quantum processing device includes a quantum well stack including an active quantum well layer and a read quantum well layer spaced apart by a barrier layer, first gates to control formation of quantum dots in the active quantum well layer, and second gates to control formation of quantum dots in the read quantum well layer
  • a non-quantum processing device coupled to the quantum processing device, to control voltages applied to the first gates and the second gates
  • a memory device to store data generated by the read quantum well layer during operation of the quantum processing device.
  • Example 30 may include the subject matter of Example 29, and may further include a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
  • Example 31 may include the subject matter of Example 30, and may further specify that the cooling apparatus includes a dilution refrigerator.
  • Example 32 may include the subject matter of Example 30, and may further specify that the cooling apparatus includes a liquid helium refrigerator.
  • Example 33 may include the subject matter of any of Examples 29-32, and may further specify that the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
  • Example 34 may include the subject matter of any of Examples 29-33, and may further specify that the barrier layer includes silicon germanium.
  • Example 35 may include the subject matter of any of Examples 29-34, and may further specify that the quantum well stack includes first and second additional barrier layers arranged such that the active quantum well layer and the read quantum well layer are disposed between the first and second additional barrier layers.

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Abstract

L'invention concerne des dispositifs à points quantiques comprenant des portes formant des motifs, ainsi que des dispositifs et procédés de calcul associés. Par exemple, dans certains modes de réalisation, un dispositif à points quantiques peut comprendre : un empilement de puits quantiques comprenant des premières et secondes couches de puits quantiques, une couche barrière étant disposée entre les premières et secondes couches de puits quantiques; un premier ensemble de portes disposées sur l'empilement de puits quantiques de sorte que la première couche de puits quantique soit disposée entre la couche barrière et le premier ensemble de portes; et un second ensemble de portes disposées sur l'empilement de puits quantiques de telle sorte que la seconde couche de puits quantique soit disposée entre la couche barrière et le second ensemble de portes.
PCT/US2016/036576 2016-06-09 2016-06-09 Dispositifs á points quantiques avec structures de puits quantiques doubles WO2017213649A1 (fr)

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US11616047B2 (en) 2018-06-14 2023-03-28 Intel Corporation Microelectronic assemblies
US11183564B2 (en) 2018-06-21 2021-11-23 Intel Corporation Quantum dot devices with strain control
US11417765B2 (en) 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US11335778B2 (en) 2018-06-26 2022-05-17 Intel Corporation Quantum dot devices with overlapping gates
US10910488B2 (en) 2018-06-26 2021-02-02 Intel Corporation Quantum dot devices with fins and partially wrapped gates
US10879446B2 (en) 2018-08-14 2020-12-29 Intel Corporation Vertical flux bias lines coupled to vertical squid loops in superconducting qubits
US11424324B2 (en) 2018-09-27 2022-08-23 Intel Corporation Multi-spacers for quantum dot device gates
US11616126B2 (en) 2018-09-27 2023-03-28 Intel Corporation Quantum dot devices with passive barrier elements in a quantum well stack between metal gates
US11450765B2 (en) 2018-09-27 2022-09-20 Intel Corporation Quantum dot devices with diodes for electrostatic discharge protection
US11749721B2 (en) 2018-09-28 2023-09-05 Intel Corporation Gate walls for quantum dot devices
US11658212B2 (en) 2019-02-13 2023-05-23 Intel Corporation Quantum dot devices with conductive liners
US11699747B2 (en) 2019-03-26 2023-07-11 Intel Corporation Quantum dot devices with multiple layers of gate metal
US11682701B2 (en) 2019-03-27 2023-06-20 Intel Corporation Quantum dot devices
US11011693B2 (en) 2019-06-24 2021-05-18 Intel Corporation Integrated quantum circuit assemblies for cooling apparatus
US11957066B2 (en) 2019-09-04 2024-04-09 Intel Corporation Stackable in-line filter modules for quantum computing
US11387324B1 (en) 2019-12-12 2022-07-12 Intel Corporation Connectivity in quantum dot devices

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