WO2019125423A1 - Ensembles de circuits quantiques avec capteurs de température sur puce - Google Patents

Ensembles de circuits quantiques avec capteurs de température sur puce Download PDF

Info

Publication number
WO2019125423A1
WO2019125423A1 PCT/US2017/067465 US2017067465W WO2019125423A1 WO 2019125423 A1 WO2019125423 A1 WO 2019125423A1 US 2017067465 W US2017067465 W US 2017067465W WO 2019125423 A1 WO2019125423 A1 WO 2019125423A1
Authority
WO
WIPO (PCT)
Prior art keywords
quantum
quantum circuit
circuit component
substrate
qubit
Prior art date
Application number
PCT/US2017/067465
Other languages
English (en)
Inventor
Ravi Pillarisetty
Nicole K. THOMAS
Kanwaljit SINGH
Hubert C. GEORGE
Payam AMIN
Zachary R. YOSCOVITS
Roman CAUDILLO
Jeanette M. Roberts
Lester LAMPERT
James S. Clarke
David J. Michalak
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/067465 priority Critical patent/WO2019125423A1/fr
Publication of WO2019125423A1 publication Critical patent/WO2019125423A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122—Single quantum well structures
    • H01L29/127—Quantum box structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66977—Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/7613—Single electron transistors; Coulomb blockade devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/82—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of the magnetic field applied to the device

Definitions

  • This disclosure relates generally to the field of quantum computing, and more specifically, to integration of temperature sensors with quantum circuits.
  • Quantum computing refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. These quantum-mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.
  • Quantum computers use so-called quantum bits, referred to as qubits (both terms “bits” and “qubits” often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states - a uniquely quantum-mechanical phenomenon.
  • Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.
  • qubits are often operated at cryogenic temperatures, typically just a few degrees Kelvin or even just a few milliKelvin above absolute zero, because at cryogenic temperatures thermal energy is low enough to not cause spurious excitations, which is thought to help minimize qubit decoherence. Estimating and controlling temperatures of qubits is not a trivial task where further improvements are needed.
  • FIGS. 1-3 are cross-sectional views of an exemplary device implementing quantum dot qubits, according to some embodiments of the present disclosure.
  • FIGS. 4-6 are cross-sectional views of various examples of quantum well stacks that may be used in a quantum dot device, according to some embodiments of the present disclosure.
  • FIGS. 7-13 illustrate example base/fin arrangements that may be used in a quantum dot device, according to some embodiments of the present disclosure.
  • FIG. 14 provides a schematic illustration of an exemplary device implementing
  • FIG. 15 provides a schematic illustration of an exemplary physical layout of a device implementing superconducting qubits, according to some embodiments of the present disclosure.
  • FIG. 16 provides a schematic illustration of a quantum circuit assembly having one or more temperature sensors integrated with a quantum circuit component that includes one or more qubits, according to some embodiments of the present disclosure.
  • FIG. 17 provides a schematic illustration a cross-sectional side view of one exemplary implementation of the quantum circuit assembly as shown in FIG. 16, according to some embodiments of the present disclosure.
  • FIG. 18 provides a schematic illustration a top view of another exemplary implementation of the quantum circuit assembly as shown in FIG. 16, according to some embodiments of the present disclosure.
  • FIGS. 19-20 provide flow charts of various exemplary methods for fabricating one or more temperature sensors integrated with a quantum circuit component, according to some
  • FIGS. 21A and 21B are top views of a wafer and dies that may include one or more of quantum circuit assemblies disclosed herein.
  • FIG. 22 is a cross-sectional side view of a device assembly that may include one or more of quantum circuit assemblies disclosed herein.
  • FIG. 23 is a block diagram of an exemplary quantum computing device that may include one or more of quantum circuit assemblies disclosed herein, in accordance with various embodiments.
  • quantum computing or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data.
  • quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states.
  • Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole.
  • quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).
  • ruthenium oxide (RuOx) or germanium (Ge) temperature sensors are used to estimate qubit temperatures, where such sensors, in their entirety, are provided within the mixing chamber of a cooling apparatus, e.g. a dilution refrigerator, in which the qubits are kept, and are connected to the qubits with conductive wires which may be as long as tens of millimeters.
  • a cooling apparatus e.g. a dilution refrigerator
  • temperature sensors are devices which are "external" to qubits in a sense that they are provided in a different package from that containing the qubits, and are connected to the qubit package with wires.
  • Embodiments of the present disclosure propose quantum circuit assemblies which include one or more temperature sensors, temperature-measuring portions of which (e.g. RuOx or Ge materials of which resistance is measured to determine the temperature using RuOx or Ge thermometer sensors) are integrated on a single die with one or more qubits.
  • temperature-measuring portions of temperature sensors e.g. RuOx or Ge materials of which resistance is measured to determine the temperature using RuOx or Ge thermometer sensors
  • more functionality can be provided on-chip, enabling improved control of the qubits.
  • integration can greatly reduce complexity and lower the cost of quantum computing devices, reduce interfacing bandwidth, and provide an approach that can be efficiently used in large-scale manufacturing. Methods of fabricating such assemblies are disclosed as well.
  • quantum circuit assemblies that include quantum circuit component(s) integrated with one or more temperature sensors on a single die as described herein may be used to implement components associated with a quantum integrated circuit (1C).
  • Such components may include those that are mounted on or embedded in a quantum 1C, or those connected to a quantum 1C.
  • the quantum 1C may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the integrated circuit.
  • the integrated circuit may be employed as part of a chipset for executing one or more related functions in a quantum system.
  • quantum dot qubits and to superconducting qubits in particular to transmons, a particular class of superconducting qubits
  • teachings of the present disclosure may be applicable to implementations of any qubits, e.g. including superconducting qubits other than transmons and/or including qubits other than superconducting qubits and quantum dot qubits, which may implement one or more temperature sensors integrated on a single die with one or more qubits, all of which implementations are within the scope of the present disclosure.
  • the quantum circuit device assemblies described herein may be used in hybrid semiconducting-superconducting quantum circuits.
  • some or all of the electrically conductive portions of various quantum circuit elements described herein may be made from one or more superconductive materials. However, some or all of these electrically conductive portions could be made from electrically conductive materials which are not superconductive.
  • reference to an electrically conductive material or circuit element implies that a superconductive material can be used, and vice versa (i.e. reference to a superconductor implies that a conductive material which is not superconductive may be used).
  • any material described herein as a "superconductive/superconducting material” may refer to one or more materials, including alloys of materials, which exhibit superconducting behavior at typical qubit operating conditions (e.g. materials which exhibit superconducting behavior at very low
  • Such materials include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), niobium titanium nitride (NbTiN), indium (In), and molybdenum rhenium (MoRe), all of which are particular types of superconductors at qubit operating temperatures, as well as their alloys.
  • the phrase “A and/or B” means (A), (B), or (A and B).
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
  • the notation "A/B/C” means (A), (B), and/or (C).
  • the terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • perpendicular generally refers to being within +/- 5-10% of a target value based on the context of a particular value as described herein or as known in the art.
  • terms indicating what may be considered an idealized behavior such as e.g.
  • the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are typically operated at.
  • techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-10 GFIz, e.g. in 4-10 GFIz, range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering.
  • qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.
  • the type of qubits used in a quantum circuit component would affect how temperature readings acquired by on-chip temperature sensors described herein would be used by a control logic, integrated either on the same or on a different die as the one including the temperature measuring portions of the temperature sensors and qubits, to control operation of a device or an apparatus implementing such a component.
  • a control logic integrated either on the same or on a different die as the one including the temperature measuring portions of the temperature sensors and qubits, to control operation of a device or an apparatus implementing such a component.
  • Quantum dot devices may enable the formation of quantum dots to serve as quantum bits (i.e. as qubits) in a quantum computing device.
  • One type of quantum dot devices includes devices having a base, a fin extending away from the base, where the fin includes a quantum well layer, and one or more gates disposed on the fin.
  • a quantum dot formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein.
  • quantum dot devices with fins provide strong spatial localization of the quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices. Therefore, this is the type of quantum dot device that is described as a first exemplary quantum circuit component that may be integrated with on-chip temperature sensor(s) according to some embodiments of the present disclosure.
  • FIGS. 1-3 are cross-sectional views of an exemplary quantum dot device 100 implementing quantum dot qubits, in accordance with various embodiments.
  • FIG. 2 illustrates the quantum dot device 100 taken along the section A-A of FIG. 1 (while FIG. 1 illustrates the quantum dot device 100 taken along the section C-C of FIG. 2)
  • FIG. 3 illustrates the quantum dot device 100 taken along the section B-B of FIG. 1 (while FIG. 1 illustrates a quantum dot device 100 taken along the section D-D of FIG. 3).
  • FIG. 1 indicates that the cross-section illustrated in FIG. 2 is taken through the fin 104-1, an analogous cross section taken through the fin 104-2 may be identical, and thus the discussion of FIGS. 1-3 refers generally to the "fin 104.”
  • a quantum circuit component integrated on-chip with one or more temperature sensors as described herein may include one or more of the quantum dot devices 100.
  • the quantum dot device 100 may include a base 102 and multiple fins 104 extending away from the base 102.
  • the base 102 and the fins 104 may include a semiconductor substrate and a quantum well stack (not shown in FIGS. 1-3, but discussed below with reference to the semiconductor substrate 144 and the quantum well stack 146), distributed in any of a number of ways between the base 102 and the fins 104.
  • the base 102 may include at least some of the semiconductor substrate, and the fins 104 may each include a quantum well layer of the quantum well stack (discussed below with reference to the quantum well layer 152 of FIGS. 4-6). Examples of base/fin arrangements are discussed below with reference to the base fin arrangements 158 of FIGS. 7-13.
  • the total number of fins 104 included in the quantum dot device 100 is an even number, with the fins 104 organized into pairs including one active fin 104 and one read fin 104, as discussed in detail below.
  • the fins 104 may be arranged in pairs in a line (e.g., 2N fins total may be arranged in a lx2N line, or a 2xN line) or in pairs in a larger array (e.g., 2N fins total may be arranged as a 4xN/2 array, a 6xN/3 array, etc.).
  • a line e.g., 2N fins total may be arranged in a lx2N line, or a 2xN line
  • a larger array e.g., 2N fins total may be arranged as a 4xN/2 array, a 6xN/3 array, etc.
  • each of the fins 104 may include a quantum well layer (not shown in FIGS. 1-3, but discussed below with reference to the quantum well layer 152).
  • the quantum well layer included in the fins 104 may be arranged normal to the z-direction, and may provide a layer in which a two-dimensional electron gas (2DEG) may form to enable the generation of a quantum dot during operation of the quantum dot device 100, as discussed in further detail below.
  • the quantum well layer itself may provide a geometric constraint on the z-location of quantum dots in the fins 104, and the limited extent of the fins 104 (and therefore the quantum well layer) in the y-direction may provide a geometric constraint on the y-location of quantum dots in the fins 104.
  • the fins 104 may take any suitable values.
  • the fins 104 may each have a width 162 between 10 and 30 nanometers.
  • the fins 104 may each have a height 164 between 200 and 400 nanometers (e.g., between 250 and 350 nanometers, or equal to 300 nanometers).
  • the fins 104 may be arranged in parallel, as illustrated in FIGS. 1 and 3, and may be spaced apart by an insulating material 128, which may be disposed on opposite faces of the fins 104.
  • the insulating material 128 may be a dielectric material, such as silicon oxide.
  • the fins 104 may be spaced apart by a distance 160 between 100 and 250 microns.
  • Multiple gates may be disposed on each of the fins 104.
  • three gates 106 and two gates 108 are shown as distributed on the top of the fin 104. This particular number of gates is simply illustrative, and any suitable number of gates may be used. Additionally, multiple groups of gates like the gates illustrated in FIG. 2 may be disposed on the fin 104.
  • the gate 108-1 may be disposed between the gates 106-1 and 106-2, and the gate 108-2 may be disposed between the gates 106-2 and 106-3.
  • Each of the gates 106/108 may include a gate dielectric 114.
  • the gate dielectric 114 for all of the gates 106/108 is provided by a common layer of gate dielectric material.
  • the gate dielectric 114 for each of the gates 106/108 may be provided by separate portions of gate dielectric 114.
  • the gate dielectric 114 may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the fin 104 and the
  • the gate dielectric 114 may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric 114 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • Examples of materials that may be used in the gate dielectric 114 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric 114 to improve the quality of the gate dielectric 114.
  • Each of the gates 106 may include a gate metal 110 and a hardmask 116.
  • the hardmask 116 may be formed of silicon nitride, silicon carbide, or another suitable material.
  • the gate metal 110 may be disposed between the hardmask 116 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 110 and the fin 104. Only one portion of the hardmask 116 is labeled in FIG. 2 for ease of illustration.
  • the gate metal 110 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride.
  • the hardmask 116 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 116 may be removed during processing, as discussed below).
  • the sides of the gate metal 110 may be substantially parallel, as shown in FIG. 2, and insulating spacers 134 may be disposed on the sides of the gate metal 110 and the hardmask 116. As illustrated in FIG. 2, the spacers 134 may be thicker closer to the fin 104 and thinner farther away from the fin 104. In some embodiments, the spacers 134 may have a convex shape.
  • the spacers 134 may be formed of any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride).
  • the gate metal 110 may be any suitable metal, such as titanium nitride.
  • Each of the gates 108 may include a gate metal 112 and a hardmask 118.
  • the hardmask 118 may be formed of silicon nitride, silicon carbide, or another suitable material.
  • the gate metal 112 may be disposed between the hardmask 118 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 112 and the fin 104.
  • the hardmask 118 may extend over the hardmask 116 (and over the gate metal 110 of the gates 106), while in other embodiments, the hardmask 118 may not extend over the gate metal 110 (e.g., as discussed below with reference to FIG. 45).
  • the gate metal 112 may be a different metal from the gate metal 110; in other embodiments, the gate metal 112 and the gate metal 110 may have the same material composition.
  • the gate metal 112 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride.
  • the hardmask 118 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 118 may be removed during processing, as discussed below).
  • the gate 108 may extend between the proximate spacers 134 on the sides of the gate 106-1 and the gate 106-3, as shown in FIG. 2.
  • the gate metal 112 may extend between the spacers 134 on the sides of the gate 106-1 and the gate 106-3.
  • the gate metal 112 may have a shape that is substantially complementary to the shape of the spacers 134, as shown.
  • the gate dielectric 114 is not a layer shared commonly between the gates 108 and 106, but instead is separately deposited on the fin 104 between the spacers 134 (e.g., as discussed below with reference to FIGS.
  • the gate dielectric 114 may extend at least partially up the sides of the spacers 134, and the gate metal 112 may extend between the portions of gate dielectric 114 on the spacers 134.
  • the gate metal 112, like the gate metal 110, may be any suitable metal, such as titanium nitride.
  • the dimensions of the gates 106/108 may take any suitable values.
  • the z-height 166 of the gate metal 110 may be between 40 and 75 nanometers (e.g., approximately 50 nanometers); the z-height of the gate metal 112 may be in the same range. In embodiments like the ones illustrated in FIG.
  • the z-height of the gate metal 112 may be greater than the z-height of the gate metal 110.
  • the length 168 of the gate metal 110 i.e., in the x-direction
  • the distance 170 between adjacent ones of the gates 106 may be between 40 and 60 nanometers (e.g., 50 nanometers).
  • the thickness 172 of the spacers 134 may be between 1 and 10 nanometers (e.g., between 3 and 5 nanometers, between 4 and 6 nanometers, or between 4 and 7 nanometers).
  • the length of the gate metal 112 (i.e., in the x-direction) may depend on the dimensions of the gates 106 and the spacers 134, as illustrated in FIG. 2.
  • the gates 106/108 on one fin 104 may extend over the insulating material 128 beyond their respective fins 104 and towards the other fin 104, but may be isolated from their counterpart gates by the intervening insulating material 130.
  • the gates 106 and 108 may be alternatingly arranged along the fin 104 in the x-direction.
  • voltages may be applied to the gates 106/108 to adjust the potential energy in the quantum well layer (not shown) in the fin 104 to create quantum wells of varying depths in which quantum dots 142 may form.
  • Only one quantum dot 142 is labeled with a reference numeral in FIGS. 2 and 3 for ease of illustration, but five are indicated as dotted circles in each fin 104, forming what may be referred to as a "quantum dot array.”
  • the location of the quantum dots 142 in FIG. 2 is not intended to indicate a particular geometric positioning of the quantum dots 142.
  • the spacers 134 may themselves provide "passive" barriers between quantum wells under the gates 106/108 in the quantum well layer, and the voltages applied to different ones of the gates 106/108 may adjust the potential energy under the gates 106/108 in the quantum well layer; decreasing the potential energy may form quantum wells, while increasing the potential energy may form quantum barriers.
  • the fins 104 may include doped regions 140 that may serve as a reservoir of charge carriers for the quantum dot device 100.
  • an n-type doped region 140 may supply electrons for electron-type quantum dots 142
  • a p-type doped region 140 may supply holes for hole-type quantum dots 142.
  • an interface material 141 may be disposed at a surface of a doped region 140, as shown.
  • the interface material 141 may facilitate electrical coupling between a conductive contact (e.g., a conductive via 136, as discussed below) and the doped region 140.
  • the interface material 141 may be any suitable material; for example, in embodiments in which the doped region 140 includes silicon, the interface material 141 may include nickel silicide.
  • the quantum dot devices 100 disclosed herein may be used to form electron-type or hole- type quantum dots 142.
  • the polarity of the voltages applied to the gates 106/108 to form quantum wells/barriers depend on the charge carriers used in the quantum dot device 100.
  • amply negative voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108
  • amply positive voltages applied to a gate 106/108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in which an electron-type quantum dot 142 may form).
  • amply positive voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108, and amply negative voltages applied to a gate 106 and 108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in which a hole-type quantum dot 142 may form).
  • the quantum dot devices 100 disclosed herein may be used to form electron-type or hole-type quantum dots.
  • Voltages may be applied to each of the gates 106 and 108 separately to adjust the potential energy in the quantum well layer under the gates 106 and 108, and thereby control the formation of quantum dots 142 under each of the gates 106 and 108. Additionally, the relative potential energy profiles under different ones of the gates 106 and 108 allow the quantum dot device 100 to tune the potential interaction between quantum dots 142 under adjacent gates. For example, if two adjacent quantum dots 142 (e.g., one quantum dot 142 under a gate 106 and another quantum dot 142 under a gate 108) are separated by only a short potential barrier, the two quantum dots 142 may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each gate 106/108 may be adjusted by adjusting the voltages on the respective gates 106/108, the differences in potential between adjacent gates 106/108 may be adjusted, and thus the interaction tuned.
  • two adjacent quantum dots 142 e.g., one quantum dot 142
  • the gates 108 may be used as plunger gates to enable the formation of quantum dots 142 under the gates 108, while the gates 106 may be used as barrier gates to adjust the potential barrier between quantum dots 142 formed under adjacent gates 108.
  • the gates 108 may be used as barrier gates, while the gates 106 are used as plunger gates.
  • quantum dots 142 may be formed under all of the gates 106 and 108, or under any desired subset of the gates 106 and 108.
  • Conductive vias and lines may make contact with the gates 106/108, and to the doped regions 140, to enable electrical connection to the gates 106/108 and the doped regions 140 to be made in desired locations.
  • the gates 106 may extend away from the fins 104, and conductive vias 120 may contact the gates 106 (and are drawn in dashed lines in FIG. 2 to indicate their location behind the plane of the drawing).
  • the conductive vias 120 may extend through the hardmask 116 and the hardmask 118 to contact the gate metal 110 of the gates 106.
  • the gates 108 may extend away from the fins 104, and conductive vias 122 may contact the gates 108 (also drawn in dashed lines in FIG. 2 to indicate their location behind the plane of the drawing).
  • the conductive vias 122 may extend through the hardmask 118 to contact the gate metal 112 of the gates 108.
  • Conductive vias 136 may contact the interface material 141 and may thereby make electrical contact with the doped regions 140.
  • the quantum dot device 100 may include further conductive vias and/or lines (not shown) to make electrical contact to the gates 106/108 and/or the doped regions 140, as desired.
  • a bias voltage may be applied to the doped regions 140 (e.g., via the conductive vias 136 and the interface material 141) to cause current to flow through the doped regions 140.
  • this voltage may be positive; when the doped regions 140 are doped with a p-type material, this voltage may be negative.
  • the magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts).
  • the conductive vias 120, 122, and 136 may be electrically isolated from each other by an insulating material 130.
  • the insulating material 130 may be any suitable material, such as an interlayer dielectric (ILD). Examples of the insulating material 130 may include silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride.
  • ILD interlayer dielectric
  • conductive vias and lines may be formed in an iterative process in which layers of structures are formed on top of each other. In some embodiments, the conductive vias
  • 120/122/136 may have a width that is 20 nanometers or greater at their widest point (e.g., 30 nanometers), and a pitch of 80 nanometers or greater (e.g., 100 nanometers). In some
  • conductive lines (not shown) included in the quantum dot device 100 may have a width that is 100 nanometers or greater, and a pitch of 100 nanometers or greater.
  • the particular arrangement of conductive vias shown in FIGS. 1-3 is simply illustrative, and any electrical routing arrangement may be implemented.
  • the structure of the fin 104-1 may be the same as the structure of the fin 104-2; similarly, the construction of gates 106/108 on the fin 104-1 may be the same as the construction of gates 106/108 on the fin 104-2.
  • the gates 106/108 on the fin 104-1 may be mirrored by corresponding gates 106/108 on the parallel fin 104-2, and the insulating material 130 may separate the gates 106/108 on the different fins 104-1 and 104-2.
  • quantum dots 142 formed in the fin 104-1 (under the gates 106/108) may have counterpart quantum dots 142 in the fin 104-2 (under the corresponding gates 106/108).
  • the quantum dots 142 in the fin 104-1 may be used as "active" quantum dots in the sense that these quantum dots 142 act as qubits and are controlled (e.g., by voltages applied to the gates 106/108 of the fin 104-1) to perform quantum computations.
  • the quantum dots 142 in the fin 104-2 may be used as "read” quantum dots in the sense that these quantum dots 142 may sense the quantum state of the quantum dots 142 in the fin 104-1 by detecting the electric field generated by the charge in the quantum dots 142 in the fin 104-1, and may convert the quantum state of the quantum dots 142 in the fin 104-1 into electrical signals that may be detected by the gates 106/108 on the fin 104-2.
  • Each quantum dot 142 in the fin 104-1 may be read by its corresponding quantum dot 142 in the fin 104-2.
  • the quantum dot device 100 enables both quantum computation and the ability to read the results of a quantum computation.
  • the quantum dot device 100 may further include one or more accumulation gates used to form a 2DEG in the quantum well area between the area with the quantum dots and the reservoir such as e.g. the doped regions 140 which, as previously described, may serve as a reservoir of charge carriers for the quantum dot device 100.
  • accumulation gates may allow to reduce the number of charge carriers in the area adjacent to the area in which quantum dots are to be formed, so that single charge carriers can be transferred from the reservoir into the quantum dot array.
  • an accumulation gates used to form a 2DEG in the quantum well area between the area with the quantum dots and the reservoir such as e.g. the doped regions 140 which, as previously described, may serve as a reservoir of charge carriers for the quantum dot device 100.
  • accumulation gates may allow to reduce the number of charge carriers in the area adjacent to the area in which quantum dots are to be formed, so that single charge carriers can be transferred from the reservoir into the quantum dot array.
  • accumulation gate may be implemented on either side of an area where a quantum dot is to be formed.
  • some implementations of the quantum dot device 100 further include or are coupled to a magnetic field source used for spin manipulation of the charge carriers in the quantum dots.
  • a magnetic field source used for spin manipulation of the charge carriers in the quantum dots.
  • a microwave transmission line or one or more magnets with pulsed gates may be used as a magnetic field source.
  • spin manipulation may be carried out with either a single spin or pairs of spin or possibly larger numbers of spins.
  • single spins may be manipulated using electron spin resonance with a rotating magnetic field (perpendicular to its static field) and on resonance with the transition energy at which the spin flips.
  • the base 102 and the fin 104 of a quantum dot device 100 may be formed from a semiconductor substrate 144 and a quantum well stack 146 disposed on the semiconductor substrate 144.
  • the quantum well stack 146 may include a quantum well layer in which a 2DEG may form during operation of the quantum dot device 100.
  • the quantum well stack 146 may take any of a number of forms, several of which are illustrated in FIGS. 4-6.
  • the various layers in the quantum well stacks 146 discussed below may be grown on the semiconductor substrate 144 (e.g., using epitaxial processes).
  • FIG. 4 is a cross-sectional view of a quantum well stack 146 including only a quantum well layer 152.
  • the quantum well layer 152 may be disposed on the semiconductor substrate 144, and may be formed of a material such that, during operation of the quantum dot device 100, a 2DEG may form in the quantum well layer 152 proximate to the upper surface of the quantum well layer 152.
  • the gate dielectric 114 of the gates 106/108 may be disposed on the upper surface of the quantum well layer 152.
  • the gate dielectric 114 may be formed of silicon oxide; in such an arrangement, during use of the quantum dot device 100, a 2DEG may form in the intrinsic silicon at the interface between the intrinsic silicon and the silicon oxide.
  • the intrinsic silicon may be strained, while in other embodiments, the intrinsic silicon may not be strained.
  • the thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 4 may take any suitable values.
  • the thickness of the quantum well layer 152 e.g., intrinsic silicon
  • the thickness of the quantum well layer 152 may be between 0.8 and 1.2 microns.
  • FIG. 5 is a cross-sectional view of a quantum well stack 146 including a quantum well layer 152 and a barrier layer 154.
  • the quantum well stack 146 may be disposed on a semiconductor substrate 144 such that the barrier layer 154 is disposed between the quantum well layer 152 and the semiconductor substrate 144.
  • the barrier layer 154 may provide a potential barrier between the quantum well layer 152 and the semiconductor substrate 144.
  • the quantum well layer 152 of FIG. 5 may be formed of a material such that, during operation of the quantum dot device 100, a 2DEG may form in the quantum well layer 152 proximate to the upper surface of the quantum well layer 152.
  • the quantum well layer 152 of FIG. 5 may be formed of silicon, and the barrier layer 154 may be formed of silicon germanium.
  • the germanium content of this silicon germanium may be 20-80% (e.g., 30%).
  • the thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 5 may take any suitable values.
  • the thickness of the barrier layer 154 e.g., silicon germanium
  • the thickness of the quantum well layer 152 e.g., silicon
  • the quantum well layer 152 may be between 5 and 30 nanometers.
  • FIG. 6 is a cross-sectional view of a quantum well stack 146 including a quantum well layer 152 and a barrier layer 154-1, as well as a buffer layer 176 and an additional barrier layer 154-2.
  • the quantum well stack 146 may be disposed on the semiconductor substrate 144 such that the buffer layer 176 is disposed between the barrier layer 154-1 and the semiconductor substrate 144.
  • the buffer layer 176 may be formed of the same material as the barrier layer 154, and may be present to trap defects that form in this material as it is grown on the semiconductor substrate 144.
  • the buffer layer 176 may be grown under different conditions (e.g., deposition temperature or growth rate) from the barrier layer 154-1.
  • the barrier layer 154-1 may be grown under conditions that achieve fewer defects than the buffer layer 176.
  • the silicon germanium of the buffer layer 176 may have a germanium content that varies from the semiconductor substrate 144 to the barrier layer 154-1.
  • the silicon germanium of the buffer layer 176 may have a germanium content that varies from zero percent at the silicon semiconductor substrate 144 to a nonzero percent (e.g., 30%) at the barrier layer 154-1.
  • the thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 6 may take any suitable values.
  • the thickness of the buffer layer 176 may be between 0.3 and 4 microns (e.g., 0.3-2 microns, or 0.5 microns).
  • the thickness of the barrier layer 154-1 e.g., silicon germanium
  • the thickness of the quantum well layer 152 e.g., silicon
  • the thickness of the barrier layer 154-2 e.g., silicon germanium
  • the thickness of the barrier layer 154-2 may be between 25 and 75 nanometers (e.g., 32 nanometers).
  • the quantum well layer 152 of FIG. 6 may be formed of a material such that, during operation of the quantum dot device 100, a 2DEG may form in the quantum well layer 152 proximate to the upper surface of the quantum well layer 152.
  • the quantum well layer 152 of FIG. 6 may be formed of silicon
  • the barrier layer 154-1 and the buffer layer 176 may be formed of silicon germanium.
  • the silicon germanium of the buffer layer 176 may have a germanium content that varies from the semiconductor substrate 144 to the barrier layer 154-1.
  • the silicon germanium of the buffer layer 176 may have a germanium content that varies from zero percent at the silicon semiconductor substrate 144 to a nonzero percent (e.g., 30%) at the barrier layer 154-1.
  • the barrier layer 154-1 may in turn have a germanium content equal to the nonzero percent.
  • the buffer layer 176 may have a germanium content equal to the germanium content of the barrier layer 154-1, but may be thicker than the barrier layer 154-1 so as to absorb the defects that may arise during growth.
  • the barrier layer 154-2 like the barrier layer 154-1, may provide a potential energy barrier around the quantum well layer 152, and may take the form of any of the embodiments of the barrier layer 154- 1. In some embodiments of the quantum well stack 146 of FIG. 6, the buffer layer 176 and/or the barrier layer 154-2 may be omitted.
  • the semiconductor substrate 144 and the quantum well stack 146 may be distributed between the base 102 and the fins 104 of the quantum dot device 100, as discussed above. This distribution may occur in any of a number of ways.
  • FIGS. 7-13 illustrate example base/fin arrangements 158 that may be used in a quantum dot device 100, in accordance with various embodiments.
  • the quantum well stack 146 may be included in the fins 104, but not in the base 102.
  • the semiconductor substrate 144 may be included in the base 102, but not in the fins 104.
  • Manufacturing of the base/fin arrangement 158 of FIG. 22 may include fin etching through the quantum well stack 146, stopping when the semiconductor substrate 144 is reached.
  • the quantum well stack 146 may be included in the fins 104, as well as in a portion of the base 102.
  • a semiconductor substrate 144 may be included in the base 102 as well, but not in the fins 104.
  • Manufacturing of the base/fin arrangement 158 of FIG. 23 may include fin etching that etches partially through the quantum well stack 146, and stops before the semiconductor substrate 144 is reached.
  • FIG. 9 illustrates a particular embodiment of the base/fin arrangement 158 of FIG. 23.
  • the quantum well stack 146 of FIG. 6 is used; the fins 104 include the barrier layer 154-1, the quantum well layer 152, and the barrier layer 154-2, while the base 102 includes the buffer layer 176 and the semiconductor substrate 144.
  • the quantum well stack 146 may be included in the fins 104, but not the base 102.
  • the semiconductor substrate 144 may be partially included in the fins 104, as well as in the base 102.
  • Manufacturing the base/fin arrangement 158 of FIG. 10 may include fin etching that etches through the quantum well stack 146 and into the semiconductor substrate 144 before stopping.
  • FIG. 11 illustrates a particular embodiment of the base/fin arrangement 158 of FIG. 10.
  • the quantum well stack 146 of FIG. 6 is used; the fins 104 include the quantum well stack 146 and a portion of the semiconductor substrate 144, while the base 102 includes the remainder of the semiconductor substrate 144.
  • the fins 104 have been illustrated in many of the preceding figures as substantially rectangular with parallel sidewalls, this is simply for ease of illustration, and the fins 104 may have any suitable shape (e.g., shape appropriate to the manufacturing processes used to form the fins 104).
  • the fins 104 may be tapered.
  • the fins 104 may taper by 3-10 nanometers in x-width for every 100 nanometers in z-height (e.g., 5 nanometers in x-width for every 100 nanometers in z-height).
  • FIG. 13 illustrates a particular embodiment of the base/fin arrangement 158 of FIG. 12.
  • the quantum well stack 146 is included in the tapered fins 104 while a portion of the semiconductor substrate 144 is included in the tapered fins and a portion of the semiconductor substrate 144 provides the base 102.
  • the z-height of the gate metal 112 of the gates 108 may be approximately equal to the sum of the z-height of the gate metal 110 and the z-height of the hardmask 116, as shown. Also in the embodiment of FIG. 2, the gate metal 112 of the gates 108 may not extend in the x-direction beyond the adjacent spacers 134.
  • the z-height of the gate metal 112 of the gates 108 may be greater than the sum of the z-height of the gate metal 110 and the z-height of the hardmask 116, and in some such embodiments, the gate metal 112 of the gates may extend beyond the spacers 134 in the x- direction.
  • an exemplary superconducting quantum circuit 200 may include two or more qubits 202 (reference numerals following after a dash, such as e.g. qubit 202-1 and 202-2 indicate different instances of the same or analogous element). All of superconducting qubits operate based on the Josephson effect, which refers to a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a non-linear inductive element such as a Josephson Junction.
  • Josephson Junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits. Therefore FIG. 14 illustrates that each of the superconducting qubits 202 may include one or more Josephson Junctions 204.
  • a Josephson Junction includes two superconductors coupled by a so-called weak link that weakens the superconductivity between the two superconductors.
  • weak links of Josephson Junctions may be implemented by providing a thin layer of an insulating material, a conductive but not superconductive material, or a semiconducting material, typically referred to as a "barrier” or a “tunnel barrier,” sandwiched, in a stack-like arrangement, between two layers of superconductor, which two superconductors typically referred to, respectively, as a "first electrode” and a "second electrode” of a Josephson Junction.
  • Josephson Junction provides a non-linear inductive element to the circuit and allows the qubit to become an anharmonic oscillator. The anharmonicity is what allows the state of the qubit to be controlled to a high level of fidelity.
  • a frequency of the qubit cannot be changed substantially beyond what is defined by the design unless one of the qubit capacitive elements is tunable.
  • SQUID superconducting quantum interference device
  • superconducting qubit includes a pair of Josephson Junctions and a loop of a conductive, typically superconductive material (i.e. a superconducting loop), connecting a pair of Josephson Junctions.
  • Applying a net magnetic field in a certain orientation to the SQUID loop of a superconducting qubit allows controlling the frequency of the qubit.
  • applying magnetic field to the SQUID region of a superconducting qubit is generally referred to as a "flux control" of a qubit, and the magnetic field is generated by providing direct current (DC) or a pulse of current through an electrically conductive or superconductive line generally referred to as a "flux bias line” (also known as a "flux line” or a “flux coil line”).
  • the one or more Josephson Junctions 204 may be directly electrically connected to one or more other circuit elements 206, which, in combination with the Josephson Junction(s) 204, form a non-linear oscillator circuit providing multi level quantum system where the first two to three levels define the qubit under normal operation.
  • the circuit elements 206 could be e.g.
  • shunt capacitors superconducting loops of a SQUID
  • electrodes for setting an overall capacitance of a qubit
  • a coupling or "bus” component for capacitively coupling the qubit to one or more of a readout resonator, a coupling or "bus" component, and a direct microwave drive line, or electromagnetically coupling the qubit to a flux bias line.
  • an exemplary superconducting quantum circuit 200 may include means 208 for providing external control of qubits 202 and means 210 for providing internal control of qubits 202.
  • external control refers to controlling the qubits 202 from outside of, e.g. an integrated circuit (1C) chip comprising the qubits, including control by a user of a quantum computer, while “internal control” refers to controlling the qubits 202 within the 1C chip.
  • qubits 202 are transmons
  • external control may be implemented by means of flux bias lines (also known as “flux lines” and “flux coil lines”) and by means of readout and drive lines (also known as "microwave lines” since qubits are typically designed to operate with microwave signals), described in greater detail below.
  • flux bias lines also known as “flux lines” and “flux coil lines”
  • readout and drive lines also known as “microwave lines” since qubits are typically designed to operate with microwave signals
  • internal control lines for such qubits may be implemented by means of resonators, e.g., coupling and readout resonators, also described in greater detail below.
  • any one of the qubits 202, the external control means 208, and the external control means 210 of the quantum circuit 200 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 14).
  • FIG. 15 provides a schematic illustration of an exemplary physical layout of a
  • superconducting quantum circuit 211 where qubits are implemented as transmons, according to some embodiments of the present disclosure.
  • FIG. 15 illustrates two qubits 202.
  • FIG. 15 illustrates flux bias lines 212, microwave lines 214, a coupling resonator 216, a readout resonator 218, and connections (e.g. wirebonding pads or any other suitable connections) 220 and 222.
  • the flux bias lines 212 and the microwave lines 214 may be viewed as examples of the external control means 208 shown in FIG. 14.
  • the coupling resonator 216 and the readout resonator 218 may be viewed as examples of the internal control means 210 shown in FIG. 14.
  • Running a current through the flux bias lines 212, provided from the connections 220, allows tuning (i.e. changing) the frequency of the corresponding qubits 202 to which each line 212 is connected. In general, it operates in the following manner. As a result of running the current in a particular flux bias line 212, magnetic field is created around the line. If such a magnetic field is in sufficient proximity to the qubit 202, e.g. by a portion of the flux bias line 212 being provided next to the qubit 202, the magnetic field couples to the qubit, thereby changing the spacing between the energy levels of the qubit. This, in turn, changes the frequency of the qubit since the frequency is directly related to the spacing between the energy levels via Planck's equation.
  • the qubit frequency may be controlled in order to bring the frequency either closer to or further away from another resonant item, for example a coupling resonator such as 216 shown in FIG. 15 that connects two or more qubits together, as may be desired in a particular setting.
  • a coupling resonator such as 216 shown in FIG. 15 that connects two or more qubits together, as may be desired in a particular setting.
  • both qubits 202 may need to be tuned to be at nearly the same frequency.
  • One way in which such two qubits could interact is that, if the frequency of the first qubit 202 is tuned very close to the resonant frequency of the coupling resonator 216, the first qubit can, when in the excited state, relax back down to the ground state by emitting a photon (similar to how an excited atom would relax) that would resonate within the coupling resonator 216. If the second qubit 202 is also at this energy (i.e. if the frequency of the second qubit is also tuned very close to the resonant frequency of the coupling resonator 216), then it can absorb the photon emitted from the first qubit, via the coupling resonator 216, and be excited from its ground state to an excited state.
  • the two qubits interact in that a state of one qubit is controlled by the state of another qubit.
  • two qubits could interact via a coupling resonator at specific frequencies, but these three elements do not have to be tuned to be at nearly the same frequency with one another.
  • two or more qubits could be configured to interact with one another by tuning their frequencies to specific values or ranges.
  • two qubits coupled by a coupling resonator do not interact, i.e. the qubits are independent.
  • magnetic flux by means of controlling the current in the appropriate flux bias line, to one qubit it is possible to cause the frequency of the qubit to change enough so that the photon it could emit no longer has the right frequency to resonate on the coupling resonator. If there is nowhere for such a frequency-detuned photon to go, the qubit will be better isolated from its surroundings and will live longer in its current state.
  • two or more qubits could be configured to avoid or eliminate interactions with one another by tuning their frequencies to specific values or ranges.
  • each qubit 202 may be read by way of its corresponding readout resonator 218. As explained below, the qubit 202 induces a resonant frequency in the readout resonator 218. This resonant frequency is then passed to the microwave lines 214 and communicated to the pads 222.
  • a readout resonator 218 may be provided for each qubit.
  • the readout resonator 218 may be a transmission line that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side (for a quarter wavelength resonator) or has a capacitive connection to ground (for a half wavelength resonator), which results in oscillations within the transmission line (resonance), with the resonant frequency of the oscillations being close to the frequency of the qubit.
  • the readout resonator 218 is coupled to the qubit by being in sufficient proximity to the qubit 202, more specifically in sufficient proximity to the capacitor of the qubit 202, when the qubit is implemented as a transmon, either through capacitive or inductive coupling. Due to a coupling between the readout resonator 218 and the qubit 202, changes in the state of the qubit 202 result in changes of the resonant frequency of the readout resonator 218. In turn, because the readout resonator 218 is in sufficient proximity to the microwave line 214, changes in the resonant frequency of the readout resonator 218 induce changes in the current in the microwave line 214, and that current can be read externally via the wire bonding pads 222.
  • the coupling resonator 216 allows coupling different qubits together, e.g. as described above, in order to realize quantum logic gates.
  • the coupling resonator 216 is similar to the readout resonator 218 in that it is a transmission line that includes capacitive connections to ground on both sides (i.e. a half wavelength resonator), which also results in oscillations within the coupling resonator 216.
  • Each side of the coupling resonator 216 is coupled (again, either capacitively or inductively) to a respective qubit by being in sufficient proximity to the qubit, namely in sufficient proximity to the capacitor of the qubit, when the qubit is implemented as a transmon.
  • each side of the coupling resonator 216 has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator 216.
  • state of one qubit depends on the state of the other qubit, and the other way around.
  • coupling resonators may be employed in order to use a state of one qubit to control a state of another qubit.
  • the microwave line 214 may be used to not only readout the state of the qubits as described above, but also to control the state of the qubits.
  • the line operates in a half-duplex mode where, at some times, it is configured to readout the state of the qubits, and, at other times, it is configured to control the state of the qubits.
  • microwave lines such as the line 214 shown in FIG. 15 may be used to only readout the state of the qubits as described above, while separate drive lines such as e.g. drive lines 224 shown in FIG. 15, may be used to control the state of the qubits.
  • the microwave lines used for readout may be referred to as readout lines (e.g. readout line 214), while microwave lines used for controlling the state of the qubits may be referred to as drive lines (e.g. drive lines 224).
  • the drive lines 224 may control the state of their respective qubits 202 by providing, using e.g. connections 226 as shown in FIG. 15, a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the states of the qubit. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the states of the qubit.
  • Coupling resonators and readout resonators of the superconducting quantum circuit 200 or 211 may be configured for capacitive coupling to other circuit elements at one or both ends in order to have resonant oscillations, whereas flux bias lines and microwave lines are intended to be non- resonant microwave transmission lines.
  • a resonator of a quantum circuit differs from a non-resonant microwave transmission line in that a resonator is a transmission line that is deliberately designed to support resonant oscillations (i.e. resonance) within the line, under certain conditions.
  • non-resonant transmission lines may be similar to conventional microwave transmission lines in that they are designed to avoid resonances, especially resonances at frequencies/wavelengths close to the resonant frequencies/wavelengths of any resonators in the proximity of such non-resonant lines.
  • non-resonant transmission lines Once non-resonant transmission lines are manufactured, some of them may inadvertently support some resonances, but, during its design, efforts are taken to minimize resonances, standing waves, and reflected signals as much as possible, so that all of the signals can be transmitted through these lines without, or with as little resonance as possible.
  • the ends of non-resonant transmission lines are typically engineered to have a specific impedance (e.g. substantially 50 Ohm) to minimize impedance mismatches to other circuit elements to which the lines are connected, in order to minimize the amount of reflected signal at transitions (e.g., transitions from the chip to the package, the package to the connector, etc.).
  • Each one of the resonators and non-resonant transmission lines of a superconducting quantum circuit may be implemented as any suitable architecture of a microwave transmission line, such as e.g. a coplanar waveguide, a stripline, a microstrip line, or an inverted microstrip line.
  • Typical materials to make the lines and resonators include Al, Nb, NbN, TiN, MoRe, and NbTiN, all of which are particular types of superconductors. However, in various embodiments, other suitable superconductors and alloys of superconductors may be used as well.
  • various lines and qubits shown in FIG. 15 could have shapes and layouts different from those shown in that FIG.
  • some lines or resonators may comprise more curves and turns while other lines or resonators may comprise less curves and turns, and some lines or resonators may comprise substantially straight lines.
  • various lines or resonators may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using e.g. a bridge, bridging one interconnect over the other.
  • FIGS. 14 and 15 illustrate examples of quantum circuits comprising only two qubits 202, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure. Furthermore, while FIGS. 14 and 15 illustrate embodiments specific to transmons, subject matter disclosed herein is not limited in this regard and may include other embodiments of quantum circuits implementing other types of superconducting qubits that would also utilize Josephson Junctions as described herein, all of which are within the scope of the present disclosure.
  • FIG. 16 provides a schematic illustration of a quantum circuit assembly 300 that includes a quantum circuit component 302 integrated with portions 304 of one or more temperature sensors 306 on the same die (integration on the same die is indicated in FIG. 16 with a dotted line surrounding the quantum circuit component 302 and the portions 304 of one or more temperature sensors 306).
  • the term "die” refers to a small block of semiconductor material/substrate on which a particular functional circuit is fabricated.
  • An 1C chip also referred to as simply a chip or a microchip, sometimes refers to a semiconductor wafer on which thousands or millions of such devices or dies are fabricated. Other times, an 1C chip refers to a portion of a semiconductor wafer (e.g. after the wafer has been diced) containing one or more dies.
  • a device is referred to as "integrated” if it is manufactured on one or more dies of an 1C chip.
  • the quantum circuit component 302 may be any component that includes one or more, typically a plurality, of qubits which may be used to perform quantum processing operations.
  • the quantum circuit component 302 may include one or more quantum dot devices 100 or one or more devices 200 or 211 implementing superconducting qubits.
  • the quantum circuit component 300 may include any type of qubits, all of which are within the scope of the present disclosure.
  • the one or more temperature sensors 306 may include any suitable devices able to determine or estimate a temperature of the quantum circuit component or any part thereof with a desired resolution.
  • RuOx or Ge temperature sensors may be implemented as temperature sensors 306.
  • such sensors are resistance sensors in that a block of material is provided, e.g. a material that includes RuOx or Ge when implementing RuOx or Ge sensor, respectively, resistance of which material is measured.
  • at least four electrical connections are made to the material resistance of which is measured - two connections to drive current and two connections to measure voltage. Measured voltage is indicative of the resistance, which is, in turn, indicative of the temperature.
  • Flence by measuring voltage, temperature can be determined/estimated.
  • a block of such a material of which resistance is measured to determine temperature can be the portions 304 shown in FIG. 16, integrated on or in a single substrate with the quantum circuit component 302.
  • the portions 304 may include materials such as Ge, SiGe, InAs, GaAs, RuOx, Hf02, Ta02, or any material or a combination of materials which could be used as a resistance thermometer.
  • FIG. 16 further illustrates that the quantum circuit assembly 300 may further include a control logic 308 configured to receive temperature readings from the temperature sensors 306 and control operation of the quantum circuit component 302 based on the measured temperatures.
  • the control logic 308 may be communicatively connected to the quantum circuit component 302 using one or more interconnects 310, and to the temperature sensors 306 using one or more interconnects 312.
  • the interconnects 310 may include any type of interconnects suitable for enabling the control logic 308 to control the quantum circuit component 302.
  • the interconnects 310 may include electrically conductive structures that would allow the control logic 308 to apply appropriate voltages to any of the plunger, barrier, and/or accumulation gates of one or more quantum dot arrays that may be realized in the quantum circuit component 302.
  • the interconnects 310 may include electrically conductive structures that support direct currents.
  • the interconnects 310 may include electrically conductive structures that support microwave currents or pulsed currents at microwave frequencies.
  • Such interconnects may be implemented as microwave transmission lines using various transmission line architectures, such as e.g. a coplanar waveguide, a stripline, a microstrip line, or an inverted microstrip line.
  • the interconnects 310 may be made from any of the superconductive materials as described herein.
  • the interconnects 312 may include any type of interconnects suitable for communicating data between the control logic 308 and the temperature sensors 306, such as e.g. temperature readings, or any control parameters for controlling the temperature sensors 306.
  • control logic 308 may be advantageously integrated on the same die with the quantum circuit component 302 and the portions 304 of the temperature sensors 306.
  • control logic 308 may be provided on a different die.
  • FIGS. 17 and 18 provide schematic illustrations of, respectively, a cross-sectional side view and a top view of quantum circuit assemblies implementing the quantum circuit component 302 and one or more temperature sensors 306, according to some embodiments of the present disclosure, and may be seen as examples of implementing the quantum circuit assembly 300 as shown in FIG. 16.
  • the quantum circuit component 302 may include not only a single qubit, but be an array of qubits, e.g. an array of quantum dot qubit devices 100 or an array of superconducting qubit devices 200 or 211.
  • FIG. 17 and 18 provide schematic illustrations of, respectively, a cross-sectional side view and a top view of quantum circuit assemblies implementing the quantum circuit component 302 and one or more temperature sensors 306, according to some embodiments of the present disclosure, and may be seen as examples of implementing the quantum circuit assembly 300 as shown in FIG. 16.
  • the quantum circuit component 302 may include not only a single qubit, but be an array of qubits, e.g. an array of quantum dot qubit devices 100 or
  • FIG. 17 illustrates a quantum circuit assembly 320 that includes the quantum circuit component 302 and the temperature sensor 306 as described above, where the portion 304 of the temperature sensor 306 is monolithically integrated with the quantum circuit component 302 on a single substrate 322.
  • the control logic 308 as described above could also be provided on the substrate 322.
  • the control logic 308 could be provided on a different substrate, e.g. on a substrate 324 shown in FIG. 17.
  • the control logic 308 may be implemented in a package 1220 shown in FIG.
  • the die housing the quantum circuit component 302 and the temperature sensor(s) 306 may be implemented in any of packages 1224, 1226, or 1232.
  • the control logic 308 when the control logic 308 is implemented on a substrate different from that housing the quantum circuit component 302 and the portions 304 of the temperature sensor(s) 306, the control logic 308 may be implemented in any of the packages 1220, 1224, 1226, or 1232 shown in FIG. 22, while the quantum circuit component 302 and the portions 304 of the temperature sensor(s) 306 may be implemented in another one of the packages 1220, 1224, 1226, or 1232.
  • the substrate 322 may comprise any substrate suitable for realizing quantum circuit components described herein.
  • the substrate 322 may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof.
  • the substrate 322 may be non-crystalline.
  • any material that provides sufficient advantages e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques
  • to outweigh the possible disadvantages e.g. negative effects of various defects
  • Additional examples of substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.
  • FIG. 17 illustrates that the portion 304 of the temperature sensor 306 may be integrated within a substrate 322.
  • the portion 304 may include a material comprising germanium, resistance of which is measured to determine temperature of the qubit substrate 322.
  • ART aspect ratio trapping
  • the portion 304 may include a material comprising ruthenium and oxygen, resistance of which is measured to determine temperature of the qubit substrate 322.
  • Such a material 304 may be integrated within the substrate 322 using e.g.
  • the portion 304 may have a width (a dimension measured in the horizontal direction of the page of FIG. 17) between about 5 and 10000 nanometers (nm), including all values and ranges therein, e.g. between about 50 and 5000 nm, or between about 100 and 1000 nm. Further, in various embodiments, the portion 304 may have a depth (a dimension measured in the vertical direction of the page of FIG. 17) between about 10 and 1000 nm, including all values and ranges therein, e.g. between about 25 and 500 nm, or between about 50 and 100 nm.
  • the portion 304 may have a length (a dimension measured in the direction perpendicular to the page of FIG. 17) between about 100 and 10000 nm, including all values and ranges therein, e.g. between about 250 and 5000 nm, or between about 500 and 1000 nm.
  • FIG. 17 further illustrates a substrate 324, which may be coupled to the substrate 322, and which may, in some embodiments, be used to house the remaining portions of the temperature sensor 306, such as e.g. a resistance bridge 326.
  • the resistance bridge 326 may include elements configured to implement any of the standard circuit techniques using a bridge circuit where, e.g. four resistors are used, two of which are known, one is variable in a known way, and one is unknown (the latter one is the one dependent on the temperature of the qubit die). By tuning the variable resistor of the resistance bridge circuit to bring the circuit into resonance, high accuracy
  • the resistance bridge 326 may be connected to the portions 304 using at least four connections as described above - two to drive current to the portions 304, and two to measure voltage on the portions 304 in order to estimate the temperature of the substrate 322 and, hence, the quantum circuit component 302.
  • Such connections are schematically illustrated in FIG. 17 with electrical connections 328.
  • the substrate 324 may further include a control logic for controlling operation of the one or more temperature sensors 306. Such a control logic could be implemented similar to the control logic 308 described herein.
  • portions of the temperature sensors 306, besides the portions 304, may also be implemented on the qubit substrate 322.
  • the resistance bridge 326 and the wires 328 thereto may be implemented over or in the substrate 322, and/or the control logic for controlling operation of the one or more temperature sensors 306 may be implemented over or in the substrate 322.
  • FIG. 17 illustrates that, in some embodiments, the substrate 324 may be coupled to the qubit substrate 322 using an interposer 330, possibly with an interlayer dielectric (ILD) 332 provided between the interposer 330 and the qubit substrate 322, as shown in this FIG. 17.
  • the ILD 332 may include any suitable ILD material as known in the art, e.g. for supporting interconnects 334 between the quantum circuit component 302 and the substrate 324, which may e.g. include the interconnects 310 in case the control logic 308 is implemented on the substrate 324, and for supporting the electrical connections 328 that enable the resistance measurements on the portions 304 integrated in the substrate 322.
  • FIG. 18 illustrates a top view of a quantum circuit assembly 340 implementing the quantum circuit component 302 and two portions 304 of the one or more temperature sensors 306 as described above.
  • resistor material 304 e.g. a material comprising ruthenium and oxygen (e.g. RuOx) or a material comprising germanium (Ge)
  • resistor material 304 e.g. a material comprising ruthenium and oxygen (e.g. RuOx) or a material comprising germanium (Ge)
  • resistor material 304 e.g. a material comprising ruthenium and oxygen (e.g. RuOx) or a material comprising germanium (Ge)
  • RuOx ruthenium and oxygen
  • Ge germanium
  • control logic 308 may provide peripheral logic to support the operation of the quantum computing component 302.
  • control logic 308 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc.
  • the control logic 308 may also perform conventional computing functions to supplement the computing functions which may be provided by the quantum circuit component 302.
  • the control logic 308 may interface with one or more of the other components of a quantum computing device, such as e.g. a quantum computing device 2000 described below, in a conventional manner, and may serve as an interface between the quantum circuit component 302 and conventional components.
  • the control logic 308 may be implemented in or may be used to implement a non-quantum processing device 2028 described below with reference to FIG. 23.
  • mechanisms by which the control logic 308 controls operation of the quantum circuit component 302 may be take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects.
  • the control logic 308 may implement an algorithm executed by one or more processing units, e.g. one or more
  • aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s), preferably non-transitory, having computer readable program code embodied, e.g., stored, thereon.
  • a computer program may, for example, be downloaded (updated) to the control logic 308 or be stored upon manufacturing of the control logic 308.
  • control logic 308 may include at least one processor and at least one memory element (not shown in FIG. 16), along with any other suitable hardware and/or software to enable its intended functionality of controlling operation of the quantum circuit component(s) 302 as described herein.
  • a processor of the control logic can execute software or an algorithm to perform the activities as discussed herein.
  • a processor of the control logic 308 may be configured to communicatively couple to other system elements via one or more interconnects or buses.
  • Such a processor may include any combination of hardware, software, or firmware providing programmable logic, including by way of non-limiting example a microprocessor, a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic array (PLA), an application specific integrated circuit (ASIC), or a virtual machine processor.
  • the processor of the control logic 308 may be communicatively coupled to the memory element of the control logic 308, for example in a direct-memory access (DMA) configuration.
  • DMA direct-memory access
  • Such a memory element of the control logic 308 may include any suitable volatile or non-volatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash, read-only memory (ROM), optical media, virtual memory regions, magnetic or tape memory, or any other suitable technology.
  • DDR double data rate
  • RAM random access memory
  • SRAM synchronous RAM
  • DRAM dynamic RAM
  • flash read-only memory
  • ROM read-only memory
  • optical media virtual memory regions, magnetic or tape memory, or any other suitable technology.
  • control logic 308 can further include suitable interfaces for receiving, transmitting, and/or otherwise communicating data or information in a network environment.
  • control logic 308 may be configured to receive sensor readings from the one or more temperature sensors 306, determine various control parameters based on the temperature readings, and then exercise control over the operation of the quantum circuit component 302 using the determined control parameters.
  • a specific nature of control that the control logic 308 would exercise over the operation of the quantum circuit component 302 would depend on the type of qubits that the quantum circuit component uses.
  • the control logic 308 could be configured to determine, based on the temperature readings received from the temperature sensors 306, appropriate voltages to any one of plunger, barrier gates, and/or accumulation gates in order to initialize and manipulate the quantum dots, and then control application of those voltages to the respective gates.
  • Some examples of controlling the voltages on these gates are explained above with reference to the quantum dot device 100. In the interests of brevity, these explanations are not repeated in detail here, but it is understood that, unless specified otherwise, all of the control mechanisms explained above may be performed by the control logic 308 based on the temperature readings received from the temperature sensors 306.
  • control logic 308 may be configured to use the received temperature information to determine variations in gate voltages for forming different quantum dots. To that end, the control logic 308 may be configured to characterize formation of each quantum dot, i.e. to characterize at which gate voltage configurations the charge carriers can be exchanged between the neighboring quantum dots. The control logic may also be configured to read out the exchange of charge carriers in a first quantum dot array by reading out the
  • the variations in gate voltages may then be determined based on an outcome of the characterization of the formation of the quantum dots.
  • the term "plunger gate” is used to describe a gate under which an electro-static quantum dot is formed.
  • the control logic 308 is able to modulate the electric field underneath that gate to create an energy valley (assuming electron-based quantum dot qubits) between the tunnel barriers created by the barrier gates.
  • the term "barrier gate” is used to describe a gate used to set a tunnel barrier (i.e. a potential barrier) between either two plunger gates (i.e. controlling tunneling of charge carrier(s), e.g. electrons, from one quantum dot to an adjacent quantum dot) or a plunger gate and an accumulation gate.
  • a tunnel barrier i.e. a potential barrier
  • the control logic 308 changes the voltage applied to a barrier gate, it changes the height of the tunnel barrier.
  • the barrier gate may be used to transfer charge carriers between quantum dots that may be formed under these plunger gates.
  • the barrier gate may be used to transfer charge carriers in and out of the quantum dot array via the accumulation gate.
  • the term "accumulation gate” is used to describe a gate used to form a 2DEG in an area that is between the area where the quantum dots may be formed and a charge carrier reservoir. Changing the voltage applied to the accumulation gate allows the control logic 308 to control the number of charge carriers in the area under the accumulation gate. For example, changing the voltage applied to the accumulation gate allows reducing the number of charge carriers in the area under the gate so that single charge carriers can be transferred from the reservoir into the quantum dot array, and vice versa.
  • the control logic 308 may further be configured to control spins of charge carriers in quantum dots of the one or more qubits by controlling a magnetic field generated by the magnetic field generator. In this manner, the control logic 308 may be able to initialize and manipulate spins of the charge carriers in the quantum dots to implement qubit operations.
  • the magnetic field generator generates a microwave magnetic field of a frequency matching that of the qubit. If the magnetic field for the quantum circuit component 302 is generated by a microwave transmission line, then the control logic may set/manipulate the spins of the charge carriers by applying appropriate pulse sequences to manipulate spin precession. Alternatively, the magnetic field for the quantum circuit component 302 is generated by a magnet with one or more pulsed gates.
  • the control logic 308 could be configured to determine, based on the temperature information received from the one or more temperature sensors 306, appropriate currents in any of flux bias lines, microwave lines, and/or drive lines, and then apply the determined currents in order to initialize and manipulate the superconducting qubits.
  • the control logic 308 may be configured to detect current(s) in microwave line(s) and to control the operation of the quantum circuit component 302 based on the detected current(s). By detecting current in a microwave line, the control logic 308 is able to assess/detect the state of the corresponding qubit(s) to which the line is coupled. In some further embodiments, the control logic 308 may further be configured to also control the current(s) in microwave line(s). By controlling the current in a microwave line, control logic is configured to control (e.g. change) the state of the corresponding qubit(s) to which the line is coupled.
  • control logic may be configured to switch operation of the microwave lines between controlling the current in the microwave lines to control states of the qubit(s) and detecting the current in the microwave lines to detect the states of the qubit(s).
  • control logic 308 can operate the microwave lines in a half-duplex mode where the microwave lines are either used for readout or for setting the state(s) of the corresponding qubits.
  • control logic 308 may be configured to control current(s) in one or more drive lines. By controlling the current in a drive line, control logic is configured to control (e.g. change) the state of the corresponding qubit(s) to which the line is coupled. When drive lines are used, the control logic can use the microwave lines for readout of the state(s) of the corresponding qubits and use the drive lines for setting the state(s) of the qubits, which would be an alternative to the half-duplex mode implementation described above. For example, the control logic 308 may be configured to control the current in the one or more drive lines by ensuring provision of one or more pulses of the current at a frequency of the one or more qubits.
  • control logic 308 can provide a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the states of the corresponding qubit.
  • control logic 308 may be configured to a duration of these pulses. By varying the length/duration of the pulse(s), the control logic 308 can stimulate a partial transition between the states of the corresponding qubit, giving a superposition of the states of the qubit.
  • control logic 308 may be configured to determine at least some values of the control parameters applied to the elements of the quantum circuit component 302 based on the temperature readings received from the one or more temperature sensors 306, e.g. determine the voltages to be applied to the various gates of a quantum dot device or determine the currents to be provided in various lines of a superconducting qubit device.
  • control logic 308 may be pre-programmed with at least some of the control parameters, e.g. with the values for the voltages to be applied to the various gates of a quantum dot device such as e.g. the device 100 during the initialization of the device.
  • FIGS. 19-20 provide flow charts of various exemplary methods for fabricating one or more temperature sensors integrated with a quantum circuit component on a single die, according to some embodiments of the present disclosure.
  • each of the methods of FIGS. 19-20 may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable.
  • Various operations of each of the methods of FIGS. 19-20 may be illustrated with reference to one or more of some the embodiments discussed above. Flowever, each of the methods of FIGS. 19-20 may be used to manufacture any suitable quantum circuit assembly comprising one or more temperature sensors integrated with a quantum circuit component on a single die according to any other embodiments disclosed herein.
  • this method may be applicable to situations when not only the one or more temperature sensors 306 but also the control logic 308 is implemented on a single die with the quantum circuit component 302.
  • the method 1000 may begin with providing a substrate on which the quantum circuit component 302 will be provided (process 1002 of FIG. 19), e.g. providing the substrate 322 described above.
  • the substrate 322 may be cleaned to e.g. remove oxides, surface- bound organic and metallic contaminants, as well as subsurface contamination, prior to fabrication of the quantum circuit component 302 and the temperature sensor(s) 306.
  • cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using hydrofluoric acid (HF)).
  • the substrate is selectively processed to form all three of the quantum circuit component 302, the one or more portions 304 of the one or more temperature sensors 306, and the control logic 308. Since some fabrication processes may be applicable to fabricating the one of these three components/elements but not the other, the method 1000 may proceed to determining whether a particular fabrication process is applicable to all three or only a subset of the three of the quantum circuit component 302, the portion(s) 304 of the temperature sensor(s) 306, and the control logic 308 (process 1004 of FIG. 19). This may be performed iteratively, at each given fabrication stage.
  • a particular fabrication process may include any known techniques for fabricating parts of the quantum circuit component 302, the portion(s) 304 of the temperature sensor(s) 306, and the control logic 308.
  • a fabrication process may include patterning and then etching, as known in the art. For example, patterning may include patterning using photolithographic techniques, while etching may include any combination of dry and wet etch chemistry with the appropriate chemistry selected depending on the materials included in the assembly 300, as known in the art for forming the quantum circuit component 302, the portion(s) 304 of the temperature sensor(s) 306, and the control logic 308 individually.
  • a fabrication process may include depositing conducting/superconducting materials using e.g.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • electroplating as known in the art.
  • a fabrication process may include planarizing the assembly, e.g. using a chemical mechanical polishing (CMP) technique.
  • CMP chemical mechanical polishing
  • fabrication processes used in the method 1000 may use standard Complementary Metal-Oxide Semiconductor (CMOS) or Bi-CMOS (i.e. technology combining CMOS with bipolar junction transistor) processes, possibly with additional custom fabrication steps.
  • CMOS Complementary Metal-Oxide Semiconductor
  • Bi-CMOS i.e. technology combining CMOS with bipolar junction transistor
  • One example of a fabrication process which may not be applicable for all three of the quantum circuit component 302, the portion(s) 304 of the temperature sensor(s) 306, and the control logic 308 is deposition of material that is specific to some but not all of these components. For example, forming an opening (e.g. a trench) in the qubit substrate and filling the opening with the material 304 suitable for serving as a resistance thermometer as described above is specific to integrating portions of the temperature sensors 306 within the substrate. Therefore, the sections where the quantum circuit component 302 and the control logic 308 would later be formed could be masked during such deposition.
  • an opening e.g. a trench
  • Another example of a fabrication process which may be applicable to one section but not another includes integration of a second metal gate in the quantum dot base qubits (as a part of fabricating the quantum circuit component 302), as opposed to e.g. using only one metal gate in the control logic section of the chip (as a part of fabricating the control logic 308).
  • Yet another example includes integration of specific materials in the qubit area only, e.g. providing cobalt for the micromagnets in quantum dot based designs or depositing superconducting materials for superconducting resonators and waveguides in quantum circuits.
  • Other examples include forming tunnel junctions in Josephson Junctions made of specific stack(s) of material(s) which are not part of the regular (Bi)CMOS process, selectively implanting dopants in the qubit array but not in the control logic section of the chip, etc.
  • a section of the substrate may be masked against application of a particular fabrication process using an oxide or a nitride. This may be carried out e.g. by providing a layer of an oxide or a nitride across the entire wafer and then using lithography as known in the art to pattern and etch it off in certain regions (i.e. in regions where masking is not needed).
  • Processes 1004-1010 shown in FIG. 19 may be performed iteratively, until the quantum circuit component 302, the portion(s) 304 of the temperature sensor(s) 306, and the control logic 308 are provided on a single substrate. After the quantum circuit component 302, the portion(s)
  • masks may be removed using a wet etch process (e.g. using hydrofluoric acid or hypophosphite ion as etchants) or a dry etch process (e.g. using tetrafluoromethane as an etchant), as known in the art.
  • a wet etch process e.g. using hydrofluoric acid or hypophosphite ion as etchants
  • a dry etch process e.g. using tetrafluoromethane as an etchant
  • the method may begin with providing a substrate on which the quantum circuit component 302 will be provided (process 1042 of FIG. 20).
  • the method 1040 may then proceed with providing the portion(s) 304 of the temperature sensor(s) 306 on the substrate (process 1044 of FIG. 20).
  • the process 1044 may include providing an opening in the substrate 322, and then depositing resistance thermometer materials suitable for forming the portions 304 of the one or more temperature sensors 306, e.g. using any of the techniques described above.
  • the process 1044 may also include masking sections of the substrate on which the quantum circuit component 302 will later be formed, prior to providing the portion(s) 304 of the temperature sensor(s) 306 on the substrate.
  • materials which may be deposited on the portions for the future quantum circuit component 302 as a consequence of fabrication steps performed for forming the portion(s) 304 of the temperature sensor(s) 306 will not have to be removed from the substrate later, prior to fabrication of the quantum circuit component 302.
  • Masking of the sections of the substrate on which the quantum circuit component 302 will later be formed may be performed by e.g. depositing oxide or nitride as described above.
  • the section of the substrate with the portions 304 may be masked (process 1046 of FIG. 20). Masking may be performed by e.g. depositing oxide or nitride as described above.
  • process 1046 may further include removing these masks, so that the quantum circuit component 302 can be provided on the substrate starting with process 1048.
  • the method 1040 may conclude with removing all of the masks (process 1050 of FIG. 20), e.g. using a mask removal process as described above.
  • FIGS. 21A-21B are top views of a wafer 1100 and dies 1102 that may be formed from the wafer 1100, according to some embodiments of the present disclosure.
  • the dies 1102 may include any of the quantum circuits assemblies disclosed herein, e.g. the quantum circuit assemblies 300, 320, or 340, any further embodiments of such assemblies as described herein, or any combinations of such assemblies.
  • the wafer 1100 may include semiconductor material and may include one or more dies 1102 having conventional and quantum circuit device elements formed on a surface of the wafer 1100.
  • Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device.
  • the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the
  • a die 1102 may include the quantum circuit component 302 and the one or more temperature sensors 306 as described herein, as well as, optionally, the control logic 308 (in case it is an on-chip control logic as described herein), as well as any other 1C components.
  • the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102.
  • a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 2002 of FIG. 23) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • FIG. 22 is a cross-sectional side view of a device assembly 1200 that may include any of the embodiments of the quantum circuit assemblies disclosed herein.
  • the device assembly 1200 includes a number of components disposed on a circuit board 1202.
  • the device assembly 1200 may include components disposed on a first face 1240 of the circuit board 1202 and an opposing second face 1242 of the circuit board 1202; generally, components may be disposed on one or both faces 1240 and 1242.
  • the circuit board 1202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1202.
  • the circuit board 1202 may be a package substrate or flexible board.
  • the 1C device assembly 1200 illustrated in FIG. 22 may include a package-on-interposer structure 1236 coupled to the first face 1240 of the circuit board 1202 by coupling components 1216.
  • the coupling components 1216 may electrically and mechanically couple the package-on- interposer structure 1236 to the circuit board 1202, and may include solder balls (as shown in FIG. 22), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
  • the package-on-interposer structure 1236 may include a package 1220 coupled to an interposer 1204 by coupling components 1218.
  • the coupling components 1218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1216. Although a single package 1220 is shown in FIG. 22, multiple packages may be coupled to the interposer 1204; indeed, additional interposers may be coupled to the interposer 1204.
  • the interposer 1204 may provide an intervening substrate used to bridge the circuit board 1202 and the package 1220.
  • the package 1220 may be a quantum circuit device package as described herein, e.g. a package including any of the quantum circuit assemblies disclosed herein, e.g.
  • the interposer 1204 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 1204 may couple the package 1220 (e.g., a die) to a ball grid array (BGA) of the coupling components 1216 for coupling to the circuit board 1202.
  • BGA ball grid array
  • the package 1220 and the circuit board 1202 are attached to opposing sides of the interposer 1204; in other embodiments, the package 1220 and the circuit board 1202 may be attached to a same side of the interposer 1204.
  • three or more components may be interconnected by way of the interposer 1204.
  • the interposer 1204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer 1204 may include metal interconnects 1208 and vias 1210, including but not limited to through-silicon vias (TSVs) 1206.
  • TSVs through-silicon vias
  • the interposer 1204 may further include embedded devices 1214, including both passive and active devices.
  • Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1204.
  • the package-on-interposer structure 1236 may take the form of any of the package-on-interposer structures known in the art.
  • the device assembly 1200 may include a package 1224 coupled to the first face 1240 of the circuit board 1202 by coupling components 1222.
  • the coupling components 1222 may take the form of any of the embodiments discussed above with reference to the coupling components 1216, and the package 1224 may take the form of any of the embodiments discussed above with reference to the package 1220.
  • the package 1224 may be a package including one or more quantum circuit assemblies described herein, e.g. the quantum circuit assemblies 300, 320, or 340, any further embodiments of such assemblies as described herein, or any combinations of such assemblies, or may be a conventional 1C package, for example.
  • the package 1224 may take the form of any of the embodiments of the quantum circuit component 302 integrated with the one or more temperature sensors 306 as described herein, as well as, optionally, the control logic 308 (in case it is an on-chip control logic as described herein described herein).
  • the device assembly 1200 illustrated in FIG. 22 includes a package-on-package structure 1234 coupled to the second face 1242 of the circuit board 1202 by coupling components 1228.
  • the package-on-package structure 1234 may include a package 1226 and a package 1232 coupled together by coupling components 1230 such that the package 1226 is disposed between the circuit board 1202 and the package 1232.
  • the coupling components 1228 and 1230 may take the form of any of the embodiments of the coupling components 1216 discussed above, and the packages 1226 and 1232 may take the form of any of the embodiments of the package 1220 discussed above.
  • Each of the packages 1226 and 1232 may be a qubit device package as described herein or may be a conventional 1C package, for example.
  • one or both of the packages 1226 and 1232 may take the form of any of the embodiments of the quantum circuit component 302 integrated with the one or more temperature sensors 306 as described herein, as well as, optionally, the control logic 308 (in case it is an on-chip control logic as described herein described herein).
  • FIG. 23 is a block diagram of an exemplary quantum computing device 2000 that may include any of the quantum circuits with any of the quantum circuit assemblies disclosed herein.
  • a number of components are illustrated in FIG. 23 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application.
  • some or all of the components included in the quantum computing device 2000 may be attached to one or more PCBs (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with any of the quantum circuit assemblies described herein.
  • various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die.
  • SoC system-on-a-chip
  • the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 23, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components.
  • the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled.
  • the quantum computing device 2000 may not include an audio input device 2018 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2018 or audio output device 2008 may be coupled.
  • the quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices).
  • processing device or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices).
  • the quantum processing device 2026 may include any of the quantum circuit assemblies disclosed herein, e.g.
  • the quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc.
  • the quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.
  • the processing device 2002 may include a non-quantum processing device 2028.
  • the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026.
  • the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc.
  • the non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026.
  • the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components.
  • the non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
  • DSPs digital signal processors
  • ASICs application-specific ICs
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute cryptographic algorithms within hardware
  • server processors or any other suitable processing devices.
  • the quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid-state memory
  • solid-state memory solid-state memory
  • hard drive solid-state memory
  • the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004.
  • the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
  • eDRAM embedded dynamic random access memory
  • STT-MRAM spin transfer torque magnetic random access memory
  • the quantum computing device 2000 may include a cooling apparatus 2024.
  • the cooling apparatus 2024 may maintain the quantum processing device 2026, in particular the quantum circuits 100 as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2026.
  • This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less.
  • the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature.
  • the cooling apparatus 2024 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.
  • the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips).
  • the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
  • IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for
  • Microwave Access which is a certification mark for products that pass conformity
  • the communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • HSPA High Speed Packet Access
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • the communication chip 2012 may operate in accordance with other wireless protocols in other embodiments.
  • the quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless
  • the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet).
  • the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless
  • a second communication chip 2012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
  • GPS global positioning system
  • EDGE EDGE
  • GPRS global positioning system
  • CDMA Code Division Multiple Access
  • WiMAX Long Term Evolution
  • LTE Long Term Evolution
  • EV-DO EV-DO
  • a first communication chip 2012 may be dedicated to wireless communications
  • a second communication chip 2012 may be dedicated to wired communications.
  • the quantum computing device 2000 may include battery/power circuitry 2014.
  • the battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).
  • the quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above).
  • the display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
  • LCD liquid crystal display
  • the quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above).
  • the audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
  • the quantum computing device 2000 may include an audio input device 2018 (or corresponding interface circuitry, as discussed above).
  • the audio input device 2018 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
  • MIDI musical instrument digital interface
  • the quantum computing device 2000 may include a GPS device 2016 (or corresponding interface circuitry, as discussed above).
  • the GPS device 2016 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.
  • the quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above).
  • Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
  • the quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above).
  • Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • RFID radio frequency identification
  • the quantum computing device 2000 may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
  • a hand-held or mobile computing device e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.
  • PDA personal digital assistant
  • Example 1 provides a quantum circuit assembly that includes a substrate; a quantum circuit component including at least one qubit provided over, on, or at least partially in the substrate; and a portion of at least one temperature sensor provided over, on, or at least partially in the substrate (i.e. is integrated on a single substrate with the quantum circuit component that includes at least one qubit) and configured to enable estimation of a temperature of the quantum circuit component.
  • Example 2 provides the quantum circuit assembly according to Example 1, further including a control logic coupled (e.g. communicatively connected) to the quantum circuit component and to the at least one temperature sensor, and configured to control operation of the quantum circuit component based on the temperature of the quantum circuit component estimated by the at least one temperature sensor.
  • a control logic coupled (e.g. communicatively connected) to the quantum circuit component and to the at least one temperature sensor, and configured to control operation of the quantum circuit component based on the temperature of the quantum circuit component estimated by the at least one temperature sensor.
  • Example 3 provides the quantum circuit assembly according to Example 2, where the at least one qubit includes at least one quantum dot qubit, the quantum circuit component further includes at least one plunger gate, and the control logic is configured to control the operation of the quantum circuit component by determining, based on the temperature of the quantum circuit component, at least one plunger voltage to be applied to the at least one plunger gate to control formation of one or more quantum dots in the at least one qubit, and controlling application of the determined at least one plunger voltage to the at least one plunger gate.
  • Example 4 provides the quantum circuit assembly according to Example 3, where the at least one plunger gate includes two or more plunger gates, the quantum circuit component further includes at least one barrier gate, and the control logic is further configured to control the operation of the quantum circuit component by determining, based on the temperature of the quantum circuit component, at least one barrier voltage to be applied to the at least one barrier gate to control a potential barrier between two adjacent plunger gates of the two or more plunger gates, and controlling application of the determined at least one barrier voltage to the at least one barrier gate.
  • Example 5 provides the quantum circuit assembly according to Example 3, where the quantum circuit component further includes at least one barrier gate and at least one accumulation gate, and the control logic is further configured to control the operation of the quantum circuit component by determining, based on the temperature of the quantum circuit component, at least one barrier voltage to be applied to the at least one barrier gate to control a potential barrier between the at least one plunger gate and an adjacent one of the at least one accumulation gate, and controlling application of the determined at least one barrier voltage to the at least one barrier gate.
  • Example 6 provides the quantum circuit assembly according to Examples 4 or 5, where the control logic is further configured to control the operation of the quantum circuit component by initializing the quantum circuit component using the determined at least one barrier voltage.
  • Example 7 provides the quantum circuit assembly according to any one of Examples 3-6, where the control logic is further configured to control the operation of the quantum circuit component by initializing the quantum circuit component using the determined at least one plunger voltage.
  • Example 8 provides the quantum circuit assembly according to Example 2, where the at least one qubit includes at least one quantum dot qubit, the quantum circuit component further includes at least one accumulation gate, and the control logic is configured to control the operation of the quantum circuit component by determining, based on the temperature of the quantum circuit component, at least one accumulation voltage to be applied to the at least one accumulation gate to control a number of charge carriers in an area between an area where one or more quantum dots are to be formed and a charge carrier reservoir, and controlling application of the determined at least one accumulation voltage to the at least one accumulation gate.
  • Example 9 provides the quantum circuit assembly according to Example 2, where the at least one qubit includes at least one quantum dot qubit, the quantum circuit component further includes at least one magnetic field generator, and the control logic is configured to control the operation of the quantum circuit component by determining, based on the temperature of the quantum circuit component, a magnetic field to be generated by the at least one magnetic field generator to control a spin of at least one charge carrier in the at least one quantum dot qubit, and controlling that the at least one magnetic field generator generates the determined magnetic field.
  • Example 10 provides the quantum circuit assembly according to Example 9, where the at least one magnetic field generator includes a microwave transmission line or a magnet with one or more pulsed gates.
  • Example 11 provides the quantum circuit assembly according to Example 2, where the at least one qubit includes at least one superconducting qubit, the quantum circuit component further includes at least one flux bias line, and the control logic is configured to control the operation of the quantum circuit component by determining, based on the temperature of the quantum circuit component, a current to be provided in the at least one flux bias line, and controlling that the determined current is provided in the at least one flux bias line.
  • Example 12 provides the quantum circuit assembly according to Example 2, where the at least one qubit includes at least one superconducting qubit, the quantum circuit component further includes at least one microwave line, and the control logic is configured to control the operation of the quantum circuit component by determining, based on the temperature of the quantum circuit component, a current to be provided in the at least one microwave line, and controlling that the determined current is provided in the at least one microwave line.
  • Example 13 provides the quantum circuit assembly according to Example 2, where the at least one qubit includes at least one superconducting qubit, the quantum circuit component further includes at least one drive line, and the control logic is configured to control the operation of the quantum circuit component by determining, based on the temperature of the quantum circuit component, a current to be provided in the at least one drive line, and controlling that the determined current is provided in the at least one drive line.
  • Example 14 provides the quantum circuit assembly according to any one of Examples 2-13, where the control logic is provided over, on, or at least partially in the substrate (i.e. is integrated on a single substrate with the at least one temperature sensor and with the quantum circuit component that includes at least one qubit).
  • Example 15 provides the quantum circuit assembly according to any one of Examples 2-13, where the substrate is a first substrate, the quantum circuit assembly further includes a second substrate, the second substrate coupled to the first substrate, and the control logic is provided over, on, or at least partially in the second substrate.
  • Example 16 provides the quantum circuit assembly according to Example 15, where the second substrate is coupled to the first substrate via one or more first-level interconnects.
  • Example 17 provides the quantum circuit assembly according to Example 15, where the second substrate is coupled to the first substrate via an interposer, where each of the first substrate and the second substrate is coupled to the interposer.
  • Example 18 provides the quantum circuit assembly according to any one of the preceding Examples, where the substrate includes an opening (e.g. a trench opening) and the portion of the at least one temperature sensor is integrated within the opening.
  • the substrate includes an opening (e.g. a trench opening) and the portion of the at least one temperature sensor is integrated within the opening.
  • Example 19 provides the quantum circuit assembly according to any one of the preceding Examples, where the portion of the at least one temperature sensor includes a material including ruthenium and oxygen (e.g. ruthenium oxide) or a material including germanium.
  • ruthenium and oxygen e.g. ruthenium oxide
  • germanium e.g. germanium
  • Example 20 provides the quantum circuit assembly according to any one of the preceding Examples, further including first electrical connections for providing current to the portion of the at least one temperature sensor and second electrical connections for measuring voltage on the portion of the at least one temperature sensor.
  • Example 21 provides the quantum circuit assembly according to Example 20, where the first and second electrical connections are a part of a resistance bridge.
  • Example 22 provides a method for forming a quantum circuit assembly. The method includes providing a first mask over one or more portions of a substrate on which a quantum circuit component including at least one qubits is to be formed; carrying out one or more first fabrication processes on the substrate with the first mask, the one or more first fabrication process forming a portion of at least one temperature sensor configured to enable estimation of a temperature of the quantum circuit component; removing the first mask; and carrying out one or more second fabrication processes on the substrate, the one or more second fabrication processes forming the quantum circuit component.
  • Example 23 provides the method according to Example 22, where the first mask includes a layer of a material including oxygen (e.g. a layer of an oxide material) or nitrogen (e.g. a layer of a nitride material).
  • oxygen e.g. a layer of an oxide material
  • nitrogen e.g. a layer of a nitride material
  • Example 24 provides a quantum computing device that includes a quantum processing device that includes a die including a substrate, a quantum circuit component including plurality of qubits provided over, on, or at least partially in the substrate, and a portion of at least one temperature sensor provided over, on, or at least partially in the substrate and configured to enable estimation of a temperature of the quantum circuit component.
  • the quantum computing device also includes a memory device configured to store data generated by the plurality of qubits during operation of the quantum processing device.
  • Example 25 provides the quantum computing device according to Example 24, further including a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
  • Example 26 provides the quantum computing device according to Examples 24 or 25, where the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
  • Example 27 provides the quantum computing device according to any one of Examples 24- 26, further including a non-quantum processing device coupled to the quantum processing device.
  • At least portions of the quantum processing device of Example provides the quantum computing device according to any one of Examples 24-27 may include features of any of the quantum circuit assemblies according to any one of Examples 1-21. In still further examples, at least portions of the quantum processing device of Example provides the quantum computing device according to any one of Examples 24-27 may be fabricated using the method according to any one of Examples 22-23.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

Des modes de réalisation de la présente invention proposent des ensembles de circuits quantiques qui comprennent un ou plusieurs capteurs de température, des parties de mesure de température, qui sont intégrées sur une puce unique avec un ou plusieurs bits quantiques. En mettant en œuvre des parties de mesure de températures de capteurs de températures sur la même puce en tant que composants de circuit quantique, un supplément de fonctionnalités peut être fourni sur puce, ce qui permet un contrôle amélioré des bits quantiques. En outre, cette intégration peut réduire considérablement la complexité et réduire le coût de dispositifs informatiques quantiques, réduire la largeur de bande d'interface et fournir une approche qui peut être efficacement utilisée dans la production à grande échelle. L'invention concerne également des procédés de fabrication de tels ensembles.
PCT/US2017/067465 2017-12-20 2017-12-20 Ensembles de circuits quantiques avec capteurs de température sur puce WO2019125423A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2017/067465 WO2019125423A1 (fr) 2017-12-20 2017-12-20 Ensembles de circuits quantiques avec capteurs de température sur puce

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2017/067465 WO2019125423A1 (fr) 2017-12-20 2017-12-20 Ensembles de circuits quantiques avec capteurs de température sur puce

Publications (1)

Publication Number Publication Date
WO2019125423A1 true WO2019125423A1 (fr) 2019-06-27

Family

ID=66995071

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2017/067465 WO2019125423A1 (fr) 2017-12-20 2017-12-20 Ensembles de circuits quantiques avec capteurs de température sur puce

Country Status (1)

Country Link
WO (1) WO2019125423A1 (fr)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879446B2 (en) 2018-08-14 2020-12-29 Intel Corporation Vertical flux bias lines coupled to vertical squid loops in superconducting qubits
US10910488B2 (en) 2018-06-26 2021-02-02 Intel Corporation Quantum dot devices with fins and partially wrapped gates
US11011693B2 (en) 2019-06-24 2021-05-18 Intel Corporation Integrated quantum circuit assemblies for cooling apparatus
US11335778B2 (en) 2018-06-26 2022-05-17 Intel Corporation Quantum dot devices with overlapping gates
US11417755B2 (en) 2018-01-08 2022-08-16 Intel Corporation Differentially strained quantum dot devices
US11417765B2 (en) 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US11424324B2 (en) 2018-09-27 2022-08-23 Intel Corporation Multi-spacers for quantum dot device gates
US11450765B2 (en) 2018-09-27 2022-09-20 Intel Corporation Quantum dot devices with diodes for electrostatic discharge protection
US11658212B2 (en) 2019-02-13 2023-05-23 Intel Corporation Quantum dot devices with conductive liners
US11682701B2 (en) 2019-03-27 2023-06-20 Intel Corporation Quantum dot devices
US11749721B2 (en) 2018-09-28 2023-09-05 Intel Corporation Gate walls for quantum dot devices
US11957066B2 (en) 2019-09-04 2024-04-09 Intel Corporation Stackable in-line filter modules for quantum computing

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7515776B1 (en) * 2004-12-09 2009-04-07 The Board Of Trustees Of The Leland Stanford Junior University Temperature-controlled optical modulator
US20140070894A1 (en) * 2012-09-10 2014-03-13 Seiko Epson Corporation Atom cell module, quantum interference device, electronic apparatus, and atom cell magnetic field control method
US20150311422A1 (en) * 2013-03-15 2015-10-29 International Business Machines Corporation Suspended superconducting qubits
EP3217336A1 (fr) * 2016-03-11 2017-09-13 Rigetti & Co., Inc. Systèmes de circuit quantique à micro-ondes à adaptation d'impédance
WO2017155531A1 (fr) * 2016-03-10 2017-09-14 Technische Universiteit Delft Trous d'interconnexion hyperfréquence supraconducteurs pour circuits quantiques multiplanaires

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7515776B1 (en) * 2004-12-09 2009-04-07 The Board Of Trustees Of The Leland Stanford Junior University Temperature-controlled optical modulator
US20140070894A1 (en) * 2012-09-10 2014-03-13 Seiko Epson Corporation Atom cell module, quantum interference device, electronic apparatus, and atom cell magnetic field control method
US20150311422A1 (en) * 2013-03-15 2015-10-29 International Business Machines Corporation Suspended superconducting qubits
WO2017155531A1 (fr) * 2016-03-10 2017-09-14 Technische Universiteit Delft Trous d'interconnexion hyperfréquence supraconducteurs pour circuits quantiques multiplanaires
EP3217336A1 (fr) * 2016-03-11 2017-09-13 Rigetti & Co., Inc. Systèmes de circuit quantique à micro-ondes à adaptation d'impédance

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11417755B2 (en) 2018-01-08 2022-08-16 Intel Corporation Differentially strained quantum dot devices
US11417765B2 (en) 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US10910488B2 (en) 2018-06-26 2021-02-02 Intel Corporation Quantum dot devices with fins and partially wrapped gates
US11335778B2 (en) 2018-06-26 2022-05-17 Intel Corporation Quantum dot devices with overlapping gates
US10879446B2 (en) 2018-08-14 2020-12-29 Intel Corporation Vertical flux bias lines coupled to vertical squid loops in superconducting qubits
US11424324B2 (en) 2018-09-27 2022-08-23 Intel Corporation Multi-spacers for quantum dot device gates
US11450765B2 (en) 2018-09-27 2022-09-20 Intel Corporation Quantum dot devices with diodes for electrostatic discharge protection
US11749721B2 (en) 2018-09-28 2023-09-05 Intel Corporation Gate walls for quantum dot devices
US11658212B2 (en) 2019-02-13 2023-05-23 Intel Corporation Quantum dot devices with conductive liners
US11682701B2 (en) 2019-03-27 2023-06-20 Intel Corporation Quantum dot devices
US11011693B2 (en) 2019-06-24 2021-05-18 Intel Corporation Integrated quantum circuit assemblies for cooling apparatus
US11957066B2 (en) 2019-09-04 2024-04-09 Intel Corporation Stackable in-line filter modules for quantum computing

Similar Documents

Publication Publication Date Title
US10803396B2 (en) Quantum circuit assemblies with Josephson junctions utilizing resistive switching materials
TWI767926B (zh) 量子電路組件、量子計算裝置及用於形成量子電路組件的方法
US10565515B2 (en) Quantum circuit assemblies with triaxial cables
US20190164959A1 (en) On-chip control logic for qubits
US11177912B2 (en) Quantum circuit assemblies with on-chip demultiplexers
WO2019125423A1 (fr) Ensembles de circuits quantiques avec capteurs de température sur puce
US10665769B2 (en) Quantum circuit assemblies with vertically-stacked parallel-plate capacitors
US20220147858A1 (en) Independent double-gate quantum dot qubits
AU2018282484B2 (en) Wafer-scale integration of dopant atoms for donor- or acceptor-based spin qubits
US10686007B2 (en) Quantum circuit assemblies with at least partially buried transmission lines and capacitors
US20200265334A1 (en) Improved qubit designs for quantum circuits
US10319896B2 (en) Shielded interconnects
US10388848B2 (en) Donor- or acceptor-based spin qubits with isotopically purified materials
WO2019032114A1 (fr) Dispositifs à bits quantiques ayant des éléments de circuit conducteur à contre-dépouille
WO2018182571A1 (fr) Lignes de polarisation de flux de courant commandé dans des dispositifs à bits quantiques
WO2019117975A1 (fr) Intégration de trou d'interconnexion traversant le silicium pour circuits quantiques
WO2018063168A1 (fr) Accord de fréquence sur puce de structures de résonateur dans des circuits quantiques
US20200373351A1 (en) Substrate engineering for qubits
WO2018182584A1 (fr) Dispositifs à bits quantiques avec résonateurs à ondes lentes
WO2019032115A1 (fr) Dispositifs à bits quantiques à jonctions josephson connectées en dessous de circuits de support
WO2018057024A1 (fr) Échangeur de chaleur en argent fritté pour bits quantiques
WO2019125498A1 (fr) Intégration à l'échelle de tranche de jonctions josephson à base de semi-conducteur
WO2019117929A1 (fr) Fabrication à l'échelle de tranche de jonctions josephson pour bits quantiques
WO2019117883A1 (fr) Dispositifs à bits quantiques à jonctions josephson fabriquées à l'aide d'un pont aérien ou d'un porte-à-faux
WO2018160185A1 (fr) Structures de ligne de transmission de guide d'ondes coplanaire à blindage flottant pour bits quantiques

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17935383

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17935383

Country of ref document: EP

Kind code of ref document: A1