Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/42—Vias, e.g. via plugs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/43—Layouts of interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/65—Shapes or dispositions of interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/019—Manufacture or treatment of bond pads
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general

Definitions

• a Land Grid Array package is a surface mount package for integrated circuits including conductive land pads that can be electrically coupled to pins or conductive leads of an LGA socket that is coupled to a printed circuit board or directly coupled to conductors on a printed circuit board.
• LGA land pads are square or rectangular and have a capacitance, which loads the associated terminal or signal path and may limit high speed performance of terminals coupled to the land pads. Accordingly, improved land pad techniques are desired.
• an integrated circuit assembly includes an integrated circuit package substrate and a conductive land pad disposed on a surface of the integrated circuit package substrate.
• the conductive land pad comprises a conductor portion, an isolated conductor portion, and an isolation portion disposed between the conductor portion and the isolated conductor portion.
• the isolated conductor portion may surround a first side of the conductor portion and a second side of the conductor portion.
• the isolated conductor portion may surround a portion of a perimeter of the conductor portion.
• the isolation portion may include a gap between the conductor portion and the isolated conductor portion. The gap may have a width smaller than a radius of an interconnect structure of a receiving structure.
• a method for manufacturing an integrated circuit assembly includes forming a conductive layer on a surface of a multi-layer package substrate.
• the method includes forming a conductive land pad from the conductive layer.
• the conductive land pad has a conductor portion, an isolated conductor portion, and an isolation portion disposed between the conductor portion and the isolated conductor portion.
• the isolation portion may have a width smaller than a radius of a contact tip of an interconnection structure of a receiving structure.
• the isolation portion may include a gap between the conductor portion and the isolated conductor portion. The gap may be filled with an electrically insulating material.
• a method for manufacturing an integrated circuit assembly includes stacking an integrated circuit package and a receiving structure in a stack. A land side of the integrated circuit package is adjacent to and aligned with interconnection structures of the receiving structure, causing the interconnection structures to land on isolated conductor portions of corresponding land pads. The method includes traversing the receiving structure by the
• interconnection structures in response to a force exerted on the stack in a direction orthogonal to a surface of the land side.
• the traversing is in a direction parallel to the surface of the land side, from the isolated conductor portion of the corresponding land pads, across isolation portions of the corresponding land pads disposed between isolated conductor portions and conductor portions of the corresponding land pads, to the conductor portions of the corresponding land pads.
• the conductor portions may be separated from the corresponding isolated portions by a width smaller than a radius of the interconnection structure of the receiving structure.
• Figure 1 illustrates a cross-sectional view of an integrated circuit assembly including an LGA package coupled to a printed circuit board using a socket.
• Figure 2 illustrates a plan view of conventional land pads of an LGA package.
• Figure 3 illustrates a plan view of a contact wipe path across a conventional land pad in response to a force applied to an integrated circuit assembly including a conventional LGA package.
• Figure 4 illustrates cross-sectional views of a contact wipe path across a conventional land pad in response to a force applied to an integrated circuit assembly including a conventional LGA package.
• Figure 5 illustrates a plan view of split LGA land pads consistent with at least one embodiment of the invention.
• Figure 6 illustrates a detailed plan view of a contact wipe path across a split LGA land pad consistent with at least one embodiment of the invention.
• Figure 7 illustrates an exemplary interconnection structure of a receiving structure for use with an LGA package.
• Figure 8 illustrates cross-sectional views of a contact wipe path across a split land pad in response to a force applied to an integrated circuit assembly including a conventional LGA package consistent with at least one embodiment of the invention.
• Figure 9 illustrates cross-sectional views of a contact wipe path across another embodiment of a split land pad in response to a force applied to an integrated circuit assembly including a conventional LGA package consistent with at least one embodiment of the invention.
• Figure 10 illustrates a detailed plan view of a contact wipe path across another embodiment of a split LGA land pad consistent with at least one embodiment of the invention.
• Figure 11 illustrates a detailed plan view of a contact wipe path across another embodiment of a split LGA land pad consistent with at least one embodiment of the invention.
• Figure 12 illustrates an area of conductive material contributing to capacitance of a conventional LGA land pad and area of conductive material contributing to capacitance of a split LGA land pad consistent with at least one embodiment of the invention.
• Figure 13 illustrates an area of conductive material exemplary cross- sectional view of an integrated circuit package substrate consistent with at least one embodiment of the invention.
• a land grid array (LGA) package includes a multi-layer substrate formed by conventional packaging manufacturing techniques using a ceramic or plastic material (e.g., bismaleimide triazine (BT) substrate).
• the multi- layer substrate includes conductive layers used to redistribute signals within the substrate.
• the LGA package includes one or more contacts (i.e., land pads or conductive lands) on an underside of the LGA package.
• the conductive layers and land pads couple an integrated circuit housed by the LGA package to corresponding contacts on a receiving structure (e.g., a socket or printed circuit board).
• Typical land pads are flat or planar structures that may vary in size and pitch and are arranged in rectangular grids that may be located at the periphery of the package, or in other patterns on the underside of the LGA package.
• a printed circuit board or a socket attached to a printed circuit board is a receiving structure that provides mechanical and electrical connections between the land pads of the LGA package and the printed circuit board.
• integrated circuit socket 104 is coupled to electrical contacts on printed circuit board 106 by electrical contacts 108 (e.g., solder balls, pins, leads, or other type of electrical contacts).
• electrical contacts 108 e.g., solder balls, pins, leads, or other type of electrical contacts.
• Integrated circuit socket 104 applies compression force F in response to a handle or surface plate 105 being put in place. If the printed circuit board itself is the receiving structure, a compression force is applied to the LGA package while attaching the LGA package to the printed circuit board (e.g., using solder paste).
• Compression force F which is applied in a first direction (e.g., a vertical direction orthogonal to the underside of LGA package 102), causes a sliding action of interconnection structures 110 (e.g., pins, leads, or other electrical contacts) of integrated circuit socket 104 in a second direction (e.g., a direction orthogonal to the first direction and parallel to the underside of LGA package 102) across land pads 112 of LGA package 102.
• contact wipe or engagement wipe is the relative motion between mating contact surfaces (e.g., a land pad and a corresponding interconnection structure) during contact engagement or insertion into a socket.
• Integrated circuit socket 104 is exemplary only and may have other designs and use different connection mechanisms.
• integrated circuit socket 104 may be an LGA dual compression socket having contacts on the top and bottom of the socket. Electrical connection between LGA package 102 and integrated circuit socket 104 and between integrated circuit socket 104 and printed circuit board 106 are made using force application techniques or heatsink.
• a heatsink is used to apply compression force F in the absence of a force application mechanism.
• land pad 112 is a conventional rectangular land pad formed as part of an array of land pads 200 on an underside of an integrated circuit package substrate.
• Land pad 112 is formed from a conductive material (e.g., gold- plated copper or gold-plated, nickel-plated copper) using conventional surface mount package manufacturing techniques, which may include conventional printed circuit board manufacturing technologies adapted for tighter geometries.
• An exemplary manufacturing technique forms land pads 112 by forming a dielectric layer on the underside of the integrated circuit package substrate, followed by conventional photolithographic patterning of a conductive layer formed above the dielectric layer.
• tip 408 of interconnection structure 406 initially lands at initial location 402 of land pad 112 and in response to compression force F, traverses land pad 112, following path D, to final position 404 on land pad 112.
• Path D is oblique to the sides of the land pad (e.g., travels at a 30-40 degree angle with respect to an edge of land pad 112).
• the entirety of land pad 112 contributes capacitance that loads the associated terminal. That capacitance limits high-speed performance of the terminal.
• a technique that reduces capacitive loading of a land pad on an associated terminal includes a split land pad design that considers the contact wipe path of an interconnection structure across the land pad.
• each split land pad 502 includes a conductor portion 506 that couples an interconnection structure at its final landing location to a signal of an integrated circuit housed by the LGA package, e.g., couples to a terminal of an integrated circuit housed by the LGA package.
• isolated conductor portion 508 is electrically isolated from conductor portion 506 and does not couple the interconnection structure to a signal of the integrated circuit housed by the LGA package, although it may be coupled to a voltage that reduces effects of the isolated conductor portion 506 on performance of split land pad 502 (e.g., isolated conductor portion 508 is coupled to a ground voltage and conductor portion 506 is connected to high-speed I/O).
• isolated conductor portion 508 is formed from the same material as conductor portion 506, although it may be formed from another conductive material.
• Isolated conductor portion 508 receives the interconnection structure at initial landing location 512, prior to contact wipe.
• Isolated conductor portion 508 is formed from a conductor material, which in some embodiments is the same material as conductor portion 506, so that any debris from isolation conductor portion 508 that collects on the interconnection structure as a result of traversing isolated conductor portion 508, is unlikely to interfere with establishing an electrical connection between the interconnection structure and conductor portion 506 at final landing location 504.
• Split land pad 502 also includes isolating portion 510 between conductor portion 506 and isolated conductor portion 508.
• Isolating portion 510 is a physical barrier that provides electrical isolation between conductor portion 506 and isolated conductor portion 508.
• Isolating portion 510 may be a gap filled with an electrically insulating material (e.g., air or solder resist) between conductor portion 506 and isolated conductor portion 508 (Fig. 9) or may be filled with another low relative permittivity (i.e., low dielectric constant) material (e.g., a solder resist, polyimide solder mask, or other material having a relative permittivity of less than 10.0 as illustrated in Fig. 8).
• isolating portion 510 has a width that is wide enough to provide sufficient electrical isolation, but narrow enough to reduce or eliminate debris build-up on tip 408 of interconnection structure 406.
• an electrically insulating material e.g., air or solder resist
• another low relative permittivity material e.g., low
• width di e.g., 50 microns or less
• An exemplary manufacturing technique forms split land pads 502 by first forming a dielectric layer on the underside of the integrated circuit package substrate, followed by conventional photolithographic patterning to form the split pad structure. For example, a conductive layer (e.g., a copper layer) is formed on the package surface. Then, the conductive layer is plated with another conductive material (e.g., gold). A photoresist is applied and a reticle including the split land pad pattern is used to selectively expose the photoresist material and unwanted material is removed (e.g., etched away). Instead of a subtractive patterning process, an additive patterning process may be used to form conductive structures only in regions that need the material may be used.
• a conductive layer e.g., a copper layer
• another conductive material e.g., gold
• a photoresist is applied and a reticle including the split land pad pattern is used to selectively expose the photoresist material and unwanted material is removed (e.g., etched away).
• split land pads may be formed as solder mask defined land pads, which have a solder mask opening smaller than the land pad.
• the split land pads are on-solder mask defined land pads, which have a split land pad smaller than the solder mask opening.
• the split land pads are formed using a copper etch process. The split land pads may be finished with a solderability coating.
• the split pad structure substantially reduces the effective land pad area (i.e., the area of conductive material contributing to capacitive loading of the associated terminal, e.g., from approximately 670 mm 2 to approximately 335 mm 2 , a reduction of approximately 50%) and reduces the associated capacitive loading of the corresponding signal line (e.g., from 0.49 pF to 0.19 pF, a reduction of approximately 61%).
• the effective land pad area i.e., the area of conductive material contributing to capacitive loading of the associated terminal, e.g., from approximately 670 mm 2 to approximately 335 mm 2 , a reduction of approximately 50%
• the associated capacitive loading of the corresponding signal line e.g., from 0.49 pF to 0.19 pF, a reduction of approximately 61%.
• other land pad shapes and geometries may be used.
• a split land pad having an isolated conductor portion and a conductor portion separated by isolating portion 510 may be formed from a rhombus-shaped land pad (e.g., Fig. 10), a trapezoidal-shaped land pad (e.g., Fig. 11), or other regular or irregular shape tailored to an angle and distance of contact wipe from an initial landing point on an isolated conductor portion to a final landing point on a conductor portion. Tailoring may include providing minimum dimensions for a conductor portion based on the distance D and a predetermined range of angles of the contact wipe.
• Comers may be reduced consistent with manufacturing design rules (e.g., by forming conductors having edges of 45 degree angles or rounded corners) to further reduce the area of the conductor portion of the split land pad and thus further reduce capacitive loading.
• the wipe angle is standardized across manufacturers of a target receiving structure (e.g., limited to an angle range less than 10 degrees)
• the geometry of conductive portion 506 may be further tailored according to the wipe angle, thereby further reducing capacitance of split land pad 502.
• the split land pads are formed in a last conductive layer of a multi-layer package substrate (e.g., conductive layer M20 of a 20-layer package).
• Another technique that may be used to reduce the capacitance of individual split land pads includes removing conductor material in a next adjacent conductive layer (e.g., conductive layer M19) above split land pads 502 of the multilayer package.
• voids 904 may be formed in a penultimate conductive layer (e.g., conductive layer M19) using patterning techniques described above.
• the voids may have the same size and shape of an outer perimeter of the split land pads formed in conductive layer M20 and are aligned with split land pads of conductive layer M20.

Landscapes

• Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Geometry (AREA)
• Electric Connection Of Electric Components To Printed Circuits (AREA)
• Manufacturing & Machinery (AREA)
• General Engineering & Computer Science (AREA)
• Wire Bonding (AREA)

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Citations (5)

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• 2017
  • 2017-12-08 US US15/836,239 patent/US10636736B2/en active Active
• 2018
  • 2018-09-18 WO PCT/US2018/051539 patent/WO2019112674A1/en not_active Ceased
  • 2018-09-18 EP EP18886250.2A patent/EP3721474A4/en active Pending
  • 2018-09-18 JP JP2020528968A patent/JP6971403B2/ja active Active
  • 2018-09-18 KR KR1020207018605A patent/KR102410350B1/ko active Active
  • 2018-09-18 CN CN201880075684.8A patent/CN111406317B/zh active Active

Patent Citations (5)

Non-Patent Citations (1)

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