WO2019111091A1 - 半導体装置、および半導体装置の作製方法 - Google Patents

半導体装置、および半導体装置の作製方法 Download PDF

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WO2019111091A1
WO2019111091A1 PCT/IB2018/059278 IB2018059278W WO2019111091A1 WO 2019111091 A1 WO2019111091 A1 WO 2019111091A1 IB 2018059278 W IB2018059278 W IB 2018059278W WO 2019111091 A1 WO2019111091 A1 WO 2019111091A1
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Prior art keywords
oxide
insulator
conductor
transistor
film
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PCT/IB2018/059278
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
澤井寛美
徳丸亮
竹内敏彦
村川努
永松翔
森若智昭
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株式会社半導体エネルギー研究所
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Priority to CN201880079057.1A priority Critical patent/CN111448669A/zh
Priority to JP2019557700A priority patent/JPWO2019111091A1/ja
Priority to KR1020207012655A priority patent/KR20200090760A/ko
Priority to US16/760,050 priority patent/US11282964B2/en
Priority to KR1020247002470A priority patent/KR20240013863A/ko
Publication of WO2019111091A1 publication Critical patent/WO2019111091A1/ja
Priority to US17/697,152 priority patent/US11784259B2/en
Priority to US18/368,782 priority patent/US20240006539A1/en

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components

Definitions

  • One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Further, one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • a semiconductor circuit such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of a semiconductor device.
  • Display devices liquid crystal display devices, light emitting display devices, etc.
  • projection devices lighting devices
  • electro-optical devices power storage devices
  • storage devices semiconductor circuits
  • imaging devices electronic devices, and the like may have semiconductor devices in some cases. .
  • one embodiment of the present invention is not limited to the above technical field.
  • One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • Oxide semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
  • oxide semiconductor for example, not only single-component metal oxides such as indium oxide and zinc oxide but also multi-component metal oxides are known.
  • oxides of multi-element metals in particular, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.
  • Non-Patent Documents 1 to 3 a c-axis aligned crystalline (CAAC) structure and an nc (nanocrystalline) structure which are neither single crystal nor amorphous are found in an oxide semiconductor (see Non-Patent Documents 1 to 3) ).
  • Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure.
  • non-patent documents 4 and 5 show that even oxide semiconductors that are less crystalline than the CAAC structure and the nc structure have minute crystals.
  • Non-Patent Document 6 a transistor using IGZO as an active layer has extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing its characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8) ).
  • An object of one embodiment of the present invention is to provide a semiconductor device with a large on current. Another object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity.
  • Another object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long time. Further, an object of one embodiment of the present invention is to provide a semiconductor device with high information writing speed. Another object of one embodiment of the present invention is to provide a semiconductor device with a high degree of freedom in design. Another object of one embodiment of the present invention is to provide a semiconductor device whose power consumption can be suppressed. Another object of one embodiment of the present invention is to provide a novel semiconductor device.
  • One embodiment of the present invention is a conductor, a first insulator in contact with a side surface of the conductor, a top surface of the conductor, and a second insulator in contact with the top surface of the first insulator, and a second insulator. And an oxide on the insulator, the oxide having a region overlapping with the conductor through the second insulator, and the maximum height (Rz) of the roughness curve on the top surface of the conductor
  • the semiconductor device is a semiconductor device, the region of which includes a crystal and the c-axis of the crystal is oriented in the normal direction of the top surface of the conductor.
  • the average length (RSm) of the roughness curvilinear element on the top surface of the conductor is less than 60 nm.
  • One embodiment of the present invention is a conductor, a first insulator in contact with a side surface of the conductor, a top surface of the conductor, and a second insulator in contact with the top surface of the first insulator; And the oxide on the insulator, the oxide having a region overlapping the conductor through the second insulator, and the average length of the roughness curvilinear element on the top surface of the conductor
  • the semiconductor device is a semiconductor device having a thickness (RSm) of 60 nm or more, a region including a crystal, and a c-axis of the crystal being oriented in the normal direction of the top surface of the conductor.
  • the maximum height (Rz) of the roughness curve on the top surface of the conductor is greater than 6.0 nm.
  • One embodiment of the present invention is a conductor, a first insulator in contact with a side surface of the conductor, a top surface of the conductor, and a second insulator in contact with the top surface of the first insulator; And an oxide on the insulator, the oxide having a region overlapping with the conductor through the second insulator, and the arithmetic mean height of the roughness curve on the top surface of the conductor
  • the semiconductor device is a semiconductor device having a dimension (Ra) of 0.5 nm or less, a region including a crystal, and a c-axis of the crystal being oriented in the normal direction of the top surface of the conductor.
  • the oxide is indium (In), element M (M is aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn)), zinc (Zn), oxygen It is preferable to have and.
  • a semiconductor device with large on-state current can be provided.
  • a semiconductor device having high frequency characteristics can be provided.
  • a semiconductor device with high reliability can be provided.
  • a semiconductor device which can be miniaturized or highly integrated can be provided.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device with high productivity can be provided.
  • a semiconductor device capable of holding data for a long time can be provided. Further, a semiconductor device with high information writing speed can be provided. In addition, a semiconductor device having a high degree of freedom in design can be provided. Further, a semiconductor device capable of suppressing power consumption can be provided. In addition, a novel semiconductor device can be provided.
  • FIG. 6 illustrates the shape of a film according to one embodiment of the present invention.
  • 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 7A and 7B are a top view and a cross-sectional view illustrating a configuration example of a semiconductor device according to one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention.
  • FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a schematic view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a schematic view of a memory device according to one embodiment of the present invention.
  • FIG. 7 illustrates an electronic device according to one embodiment of the present invention. High resolution TEM images of cross sections of the samples A1 to A3.
  • the size, layer thicknesses, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale.
  • the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings.
  • a layer, a resist mask, and the like may be unintentionally reduced by a process such as etching, but may not be reflected in the drawings for ease of understanding.
  • the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and repeated description may be omitted.
  • the hatch pattern may be the same and no reference numeral may be given.
  • the description of some of the components may be omitted particularly in a top view (also referred to as a "plan view") or a perspective view.
  • the description of some hidden lines may be omitted.
  • the ordinal numbers given as the first, second and the like are used for convenience and do not indicate the order of steps or the order of layers. Therefore, for example, “first” can be appropriately replaced with “second” or “third” and the like.
  • the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
  • the present invention is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the sentence, and anything other than the connection relationship shown in the figure or the sentence is also disclosed in the figure or the sentence.
  • X and Y each denote an object (eg, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like).
  • the functions of the source and the drain may be switched when adopting transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in the present specification and the like, the terms “source” and “drain” may be used interchangeably.
  • the channel width in the region where the channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width shown in the top view of the transistor (Hereafter, it may also be called “apparent channel width.”) May be different.
  • the effective channel width may be larger than the apparent channel width, and the effect may not be negligible.
  • the ratio of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
  • channel width may refer to an apparent channel width.
  • channel width may refer to an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the impurity of a semiconductor refers to, for example, an element other than the main component of the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be said to be an impurity.
  • the inclusion of an impurity may cause, for example, an increase in the density of defect states in the semiconductor, or a decrease in crystallinity.
  • examples of impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors.
  • transition metals other than the main component and examples thereof include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like.
  • water may also function as an impurity.
  • oxygen vacancies may be formed, for example, by the addition of impurities.
  • the impurity that changes the characteristics of the semiconductor include oxygen, a group 1 element excluding hydrogen, a group 2 element, a group 13 element, and a group 15 element.
  • silicon oxynitride has a higher content of oxygen than nitrogen as its composition.
  • silicon nitride oxide has a nitrogen content higher than that of oxygen as its composition.
  • the term “insulator” can be reworded as an insulating film or an insulating layer. Further, the term “conductor” can be rephrased as a conductive film or a conductive layer. Further, the term “semiconductor” can be reworded as a semiconductor film or a semiconductor layer.
  • parallel means the state in which two straight lines are arrange
  • substantially parallel refers to a state in which two straight lines are arranged at an angle of ⁇ 30 degrees or more and 30 degrees or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • substantially perpendicular refers to a state in which two straight lines are disposed at an angle of 60 degrees or more and 120 degrees or less.
  • a barrier film is a film having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, and in the case where the barrier film has conductivity, a conductive barrier film and I sometimes call.
  • the metal oxide is a metal oxide in a broad sense.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductor or simply OS), and the like.
  • oxide semiconductors also referred to as oxide semiconductor or simply OS
  • the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing an OS transistor, it can be said to be a transistor having an oxide or an oxide semiconductor.
  • normally-off means that the drain current per 1 ⁇ m of the channel width flowing in the transistor is 1 ⁇ 10 ⁇ at room temperature when no potential is applied to the gate or the ground potential is applied to the gate. 20 A or less, 1 ⁇ 10 ⁇ 18 A or less at 85 ° C., or 1 ⁇ 10 ⁇ 16 A or less at 125 ° C.
  • Embodiment 1 In this embodiment mode, a film typified by a metal oxide according to one embodiment of the present invention will be described. Note that in this specification, in the case where the film of one embodiment of the present invention has a semiconductor function, the film can be used for a region where a channel of a transistor is formed (hereinafter, also referred to as a channel formation region). Below, the film
  • a metal oxide which functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is preferably used in a channel formation region.
  • a transistor in which a metal oxide is used for a channel formation region has extremely low leak current in a non-conduction state, and thus can provide a semiconductor device with low power consumption.
  • the metal oxide can be used for a transistor included in a highly integrated semiconductor device.
  • a metal oxide for the channel formation region of the transistor it is preferable to use a metal oxide with high crystallinity.
  • a metal oxide with high crystallinity for the channel formation region of the transistor the stability or the reliability of the transistor can be improved.
  • a highly crystalline metal oxide for example, there is a c-axis aligned crystalline oxide semiconductor (CAAC-OS).
  • the CAAC-OS has c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction to form a strained crystal structure.
  • the nanocrystal refers to, for example, a small crystal having periodicity in atomic arrangement in a region of 1 nm to 10 nm, particularly in a region of 1 nm to 3 nm.
  • the nanocrystals in the CAAC-OS are crystals having a layered structure, and in the TEM image in the plane parallel to the c-axis of the nanocrystals, an image in which bright stripes and dark stripes appear alternately in the c-axis direction It is also observed.
  • distortion refers to a portion where the orientation of the lattice arrangement changes between the region in which the lattice arrangement is aligned and the region in which another lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.
  • CAAC-OS it is difficult to confirm clear crystal grain boundaries even in the vicinity of a strain.
  • the atomic arrangement may have periodicity even in a region where a plurality of nanocrystals are connected.
  • a region having periodicity in atomic arrangement in the entire structure in which a plurality of nanocrystals are connected is referred to as a region A.
  • the minimum size of region A is the size of nanocrystals.
  • the size of the region A may be, for example, 30 nm.
  • CAAC-OS it is difficult to confirm clear crystal grain boundaries also in a region where a plurality of regions A are connected or a region where a nanocrystal and the region A are connected.
  • the crystallinity of the metal oxide In order to increase the size of the region A, it is necessary to enhance the crystallinity of the metal oxide.
  • As a method of enhancing the crystallinity of the metal oxide there are, for example, raising the substrate temperature, increasing the flow rate of oxygen gas, and the like when forming the metal oxide.
  • raising the substrate temperature or increasing the flow rate of the oxygen gas the metal oxide has a polycrystalline structure and the probability of forming grain boundaries is high.
  • the crystallinity of the metal oxide is easily affected by the flatness of the film located under the metal oxide.
  • the normal direction of the top surface of the film becomes substantially uniform over a wide range. Therefore, the c-axis of the nanocrystals in the metal oxide is oriented in the normal direction, whereby the nanocrystals are easily connected to each other, and the metal oxide has a region A with a large size and the distortion is reduced. Can be formed.
  • the normal direction is the average direction of the normal vector with respect to the top surface of the film in the region where the nanocrystal and the film overlap.
  • the c axis of the nanocrystals is oriented in the normal direction means that the angle between the c axis of the nanocrystals and the normal direction is an angle of ⁇ 15 degrees or more and 15 degrees or less.
  • a formation surface of the metal oxide is an upper surface of an insulating film which functions as a gate insulator or an interlayer film, and a formation surface of the insulating film is a gate electrode.
  • a conductive film which functions as a wiring.
  • the conductive film include a tungsten film, a titanium nitride film, and a tantalum nitride film.
  • the conductive film is formed by a sputtering method or the like.
  • the sputtering method is a film forming method in which particles emitted from a target are deposited. Therefore, the planarity of the conductive film may be low.
  • examples of the insulating film include a silicon oxynitride film, an aluminum oxide film, and a hafnium oxide film.
  • the insulating film is formed by a CVD method, an ALD method, or the like.
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, the flatness of the insulating film is easily influenced by the flatness of the conductive film which is the formation surface of the insulating film.
  • the flatness of the film located below the metal oxide can be increased. Is preferred. That is, in order to improve the flatness of the formation surface of the metal oxide, it is preferable to increase the flatness of the conductive film located below the metal oxide. By increasing the planarity of the conductive film, the crystallinity of the metal oxide can be increased.
  • FIGS. 1A to 1D are schematic views of a metal oxide and a film located below the metal oxide.
  • the film 51 is formed on the film 50
  • the oxide film 52 is formed on the film 51.
  • oxide film 52 has a plurality of regions 53.
  • the film 50 is a film functioning as a conductor
  • the film 51 is a film functioning as an insulator
  • the oxide film 52 is a metal oxide
  • the region 53 is Region A
  • the film 50 and the film 51 may each have a stacked structure.
  • FIG. 1E is a schematic view of a region 53 of the oxide film 52.
  • the region 53 has periodicity in atomic arrangement.
  • the region 53 includes a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer containing the element M, zinc and oxygen (hereinafter referred to as It has a layered crystal structure (also referred to as a layered structure) in which M, Zn) layers are stacked. Further, the normal direction of each layer is taken as c axis, and the plane formed by each layer is taken as ab plane.
  • the size of the region 53 in the a-b plane direction may be 30 nm depending on the film forming conditions of the oxide film 52 or the flatness of the film located below the oxide film 52.
  • the size in the c-axis direction of the region 53 is shown to be the same size as the film thickness of the oxide film 52 in FIG. 1, this is not restrictive.
  • the region 53 may be formed at least in the channel formation region of the transistor. Therefore, the size of the region 53 in the c-axis direction may be larger than the minimum size (for example, 0.7 nm) of the nanocrystal in the c-axis direction and smaller than the film thickness of the oxide film 52.
  • a method of evaluating the flatness of a film for example, there is a method of obtaining a roughness curve of the film and calculating a roughness curve parameter.
  • the roughness curve is a contour curve obtained by blocking long wavelength components from the cross-sectional curve.
  • the roughness curve parameters are obtained from the roughness curve.
  • the roughness curve parameters include the arithmetic mean height (Ra) of the roughness curve, the average length (RSm) of the roughness curve element, and the maximum height (Rz) of the roughness curve.
  • the roughness curve parameters can be evaluated, for example, with an atomic force microscope (AFM).
  • the arithmetic mean height (Ra) of the roughness curve is the mean of the absolute values of the ordinate value Z (X) at the reference length.
  • the ordinate value Z (X) is the height of the roughness curve at an arbitrary position X.
  • the average length (RSm) of the roughness curvilinear element is an average of the length (Xs) of the contour curvilinear element at the reference length. The larger the average length (RSm) of the roughness curvilinear element, the higher the flatness of the film.
  • the maximum height (Rz) of the roughness curve is the sum of the maximum peak height Zp and the maximum valley depth Zv of the contour curve at the reference length.
  • the maximum height (Rz) of a roughness curve may be called a PV value (Peak-to-Valley Roughness).
  • roughness curve parameters may be evaluated by performing image analysis of a TEM image.
  • image analysis of a TEM image for example, the contrast observed in the TEM image is taken as the interface between the layer and the layer, and the shape of the interface is the roughness curve of the layer located below the interface Suppose. Then, from the assumed roughness curve, a parameter corresponding to the roughness curve parameter is calculated.
  • the reference length may be the length of the upper surface of the film 50 observed in the TEM image, or may be the length of the region where the film 50 and the oxide film 52 overlap.
  • the maximum height (Rz) of the roughness curve may be the sum of the maximum peak height and the maximum valley depth of the roughness curve assumed by the evaluation method.
  • the average length (RSm) of the roughness curve element is the average of the length from the peak of the roughness curve assumed by the evaluation method to the peak next to it, or the length from the valley to the valley next to it It may be an average of
  • the length in the short direction in the shape of the film may be shorter than the reference length.
  • the roughness curve parameter can be calculated by setting the direction of the reference length to the long direction in the shape of the film.
  • the size of the region 53 of the oxide film 52 is preferably large.
  • FIG. 1A is a schematic view in the case where the film 50 is flat.
  • the flatness of the film 51 is enhanced, and the flatness of the oxide film 52 is also likely to be enhanced.
  • a large area 53 can be formed in the oxide film 52.
  • different regions 53 are connected in the a-b plane direction.
  • the average length (RSm) of the roughness curvilinear elements of the film 50 located below the oxide film 52 be large.
  • the average length (RSm) of the roughness curvilinear element of the film 50 is, for example, preferably 60 nm or more, and more preferably 80 nm or more.
  • FIG. 1B is a schematic view in the case where the average length (RSm) of the roughness curvilinear element of the film 50 is large.
  • the average length (RSm) of the roughness curvilinear element of the film 50 is 60 nm or more
  • the length from the convex portion to the concave portion (approximately half the length of RSm) on the film top surface of the film 50 and the film 51 Increases the proportion of regions with a wavelength of 30 nm or more.
  • the normal direction to the upper surface of the film in the region is substantially uniform. Therefore, in the case where the upper surface of the film in the region is a formation surface of the oxide film 52, the nanocrystals are easily connected with small strain, and the large region 53 can be formed in the oxide film 52.
  • the maximum height (Rz) or the arithmetic average height (Ra) of the roughness curve of the film 50 located below the oxide film 52 be small.
  • the maximum height (Rz) of the roughness curve of the film 50 is, for example, preferably 10 nm or less, more preferably 6.0 nm or less, and still more preferably 4.0 nm or less.
  • membrane 50 1.0 nm or less is preferable, for example, 0.5 nm or less is more preferable, and 0.3 nm or less is more preferable.
  • FIG. 1C is a schematic view when the maximum height (Rz) of the roughness curve of the film 50 is small.
  • Rz maximum height
  • Ra arithmetic average height
  • the maximum height (Rz) or the arithmetic average height (Ra) of the roughness curve of the film 50 is large but the size is large. Region 53 can be formed.
  • the maximum height (Rz) of the roughness curve of the film 50 is greater than 6.0 nm or the roughness of the film 50
  • the arithmetic mean height (Ra) of the curve may be greater than 0.5 nm.
  • the height (Rz) or arithmetic average height (Ra) of the roughness curve of the film 50 is sufficiently small, the area having a large size even if the average length (RSm) of the roughness curve element of the film 50 is small. 53 can be formed.
  • the maximum height (Rz) of the roughness curve of the film 50 is 6.0 nm or less, or the arithmetic average height (Ra) of the roughness curve of the film 50 is 0.5 nm or less, the roughness of the film 50 is
  • the average length (RSm) of the curvature curve elements may be less than 60 nm.
  • FIG. 1D is a schematic diagram when the average length (RSm) of the roughness curve element of the film 50 is small and the maximum height (Rz) or arithmetic average height (Ra) of the roughness curve of the film 50 is large.
  • RSm average length
  • Rz maximum height
  • Ra arithmetic average height
  • the nanocrystals can be easily connected to each other, and the region A having a large size can be formed in the metal oxide.
  • the metal oxide for the channel formation region of the transistor, the stability or the reliability of the transistor can be improved.
  • CMP Chemical Mechanical Polishing
  • smoothing treatment using CMP treatment or the like may be performed as a method for enhancing the planarity of the film located below the metal oxide.
  • 2A, 2B, and 2C are a top view and a cross-sectional view of a transistor 200 and a periphery of the transistor 200 according to one embodiment of the present invention.
  • FIG. 2A is a top view of a semiconductor device including the transistor 200.
  • FIG. 2B and 2C are cross-sectional views of the semiconductor device.
  • FIG. 2B is a cross-sectional view of a portion indicated by dashed dotted line A1-A2 in FIG. 2A, which is also a cross-sectional view of the transistor 200 in the channel length direction.
  • 2C is a cross-sectional view of a portion indicated by an alternate long and short dash line A3-A4 in FIG. 2A, and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of FIG. 2A, some elements are omitted for the sake of clarity.
  • the semiconductor device of one embodiment of the present invention includes the transistor 200 and an insulator 281 which functions as an interlayer film. Further, the transistor 200 includes the conductor 240 (the conductor 240 a and the conductor 240 b) which is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 241 (insulator 241 a and insulator 241 b) is provided in contact with the side surface of the conductor 240 functioning as a plug.
  • an insulator 241 is provided in contact with the inner wall of the opening formed in the insulator 254, the insulator 274, the insulator 280, and the insulator 281, and the first conductor of the conductor 240 is provided in contact with the side surface thereof.
  • a second conductor of the conductor 240 is provided inside.
  • the height of the top surface of the conductor 240 and the height of the top surface of the insulator 281 can be approximately the same.
  • the transistor 200 illustrates a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this.
  • the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. In the case where the structure has a stacked structure, ordinal numbers may be assigned in order of formation to be distinguished.
  • the transistor 200 includes an insulator 214 and an insulator 216 disposed on a substrate (not shown), and a conductor disposed to be embedded in the insulator 214 and the insulator 216. 205, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, and an oxide 230 (provided on the insulator 224).
  • the conductor 260 has a conductor 260a and a conductor 260b, and the conductor 260a is disposed so as to wrap the bottom and the side of the conductor 260b.
  • the top surface of the conductor 260 is disposed so as to substantially coincide with the top surface of the insulator 250 and the top surface of the oxide 230c.
  • the insulator 274 is in contact with the top surfaces of the conductor 260, the oxide 230c, and the insulator 250, and the side surface of the insulator 241.
  • the insulator 222, the insulator 254, and the insulator 274 preferably have a function of suppressing diffusion of hydrogen (eg, at least one of a hydrogen atom, a hydrogen molecule, and the like).
  • the insulator 222, the insulator 254, and the insulator 274 preferably have a function of suppressing diffusion of oxygen (eg, at least one of oxygen atom, oxygen molecule, and the like).
  • the insulator 222, the insulator 254, and the insulator 274 preferably each have lower permeability to one or both of oxygen and hydrogen than the insulator 224, respectively.
  • the insulator 222, the insulator 254, and the insulator 274 preferably each have lower permeability to one or both of oxygen and hydrogen than the insulator 250, respectively.
  • the insulator 222, the insulator 254, and the insulator 274 preferably each have lower permeability to one or both of oxygen and hydrogen than the insulator 280.
  • the insulator 254 has top and side surfaces of the conductor 242a, top and side surfaces of the conductor 242b, side surfaces of the oxide 230a and the oxide 230b, and a top surface of the insulator 224. It is preferable to touch.
  • the insulator 280 is separated from the insulator 224 and the oxide 230 by the insulator 254. Accordingly, entry of impurities such as hydrogen from the outside of the transistor 200 can be suppressed, so that the transistor 200 can have favorable electrical characteristics and reliability.
  • the oxide 230 is disposed on the oxide 230a disposed on the insulator 224, the oxide 230b disposed on the oxide 230a, and the oxide 230b, and at least a part of the oxide 230 is disposed. And an oxide 230c in contact with the top surface of 230b.
  • the transistor 200 illustrates a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked in the channel formation region and in the vicinity thereof, the present invention is not limited to this. .
  • a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided.
  • the conductor 260 functions as a gate electrode of the transistor, and the conductor 242a and the conductor 242b function as a source electrode or a drain electrode, respectively.
  • a conductor 260 functioning as a gate electrode is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242a and the conductor 242b without alignment.
  • the conductor 260 preferably includes a conductor 260 a and a conductor 260 b disposed on the conductor 260 a.
  • the conductor 260 is illustrated as a stacked-layer structure of two layers, but the present invention is not limited to this.
  • the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.
  • the transistor 200 is disposed so as to be embedded in the insulator 214 disposed on a substrate (not shown), the insulator 216 disposed on the insulator 214, and the insulator 214 and the insulator 216. It is preferable to have the conductor 205 and the insulator 222 disposed on the insulator 216 and the conductor 205. Furthermore, the insulator 224 is preferably disposed on the insulator 222.
  • a metal oxide which functions as an oxide semiconductor is used for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including a channel formation region. It is preferred to use.
  • the transistor 200 in which an oxide semiconductor is used for a channel formation region has extremely low leak current (off current) in a non-conduction state; thus, a semiconductor device with low power consumption can be provided. Further, an oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200 included in a highly integrated semiconductor device.
  • In-M-Zn oxide as the oxide 230 (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium It is preferable to use a metal oxide such as one or more selected from neodymium, hafnium, tantalum, tungsten, or magnesium.
  • a metal oxide such as one or more selected from neodymium, hafnium, tantalum, tungsten, or magnesium.
  • the element M aluminum, gallium, yttrium or tin may be used.
  • an In-Ga oxide or an In-Zn oxide may be used as the oxide 230.
  • the transistor including an oxide semiconductor when impurities and oxygen vacancies are present in a region of the oxide semiconductor in which a channel is formed, the electrical characteristics are easily changed and the reliability might be reduced.
  • oxygen vacancies when oxygen vacancies are included in the region in the oxide semiconductor in which a channel is formed, the transistor is likely to be normally on. Therefore, it is preferable that oxygen deficiency in the region where the channel is formed be reduced as much as possible.
  • oxygen may be supplied to the oxide 230 through the insulator 250 or the like to compensate for oxygen vacancies. Accordingly, it is possible to provide a transistor in which the variation in the electrical characteristics is suppressed, the stable electrical characteristics are provided, and the reliability is improved.
  • an element provided in contact with the oxide 230 and functioning as a source electrode or a drain electrode and included in the conductor 242 has a function of absorbing oxygen in the oxide 230.
  • a low resistance region may be partially formed between the oxide 230 and the conductor 242 or in the vicinity of the surface of the oxide 230.
  • an impurity such as hydrogen, nitrogen, or a metal element
  • hydrogen that has entered oxygen deficiency may be referred to as V o H.
  • FIG. 3A an enlarged view of a partial region of the transistor 200 illustrated in FIG. 2B is illustrated in FIG.
  • a conductor 242 is provided to be in contact with the oxide 230b, and a region 243 (a low resistance region) is formed in the oxide 230 at the interface with the conductor 242 and in the vicinity thereof.
  • a region 243a and a region 243b) may be formed.
  • the oxide 230 includes a region 234 which functions as a channel formation region of the transistor 200 and a region 231 (a region 231 a and a region 231 b) which includes part of the region 243 and functions as a source region or a drain region.
  • a similar region 243 may be formed.
  • the region 243a and the region 243b are provided to be diffused in the depth direction in the vicinity of the conductor 242 of the oxide 230b, the present invention is not limited to this.
  • the regions 243a and 243b may be formed as appropriate depending on the desired electrical characteristics of the transistor. Further, in the oxide 230, it may be difficult to clearly detect the boundary of each region.
  • the concentration of the element detected in each region is not limited to stepwise change in each region, and may be continuously changed (also referred to as gradation) in each region.
  • FIG. 3B illustrates an example of a transistor in which the insulator 283 is provided between the insulator 280 and the insulator 274. That is, the insulator 274 and the insulator 250 do not contact with each other.
  • an impurity such as hydrogen contained in the insulator 280 or the like may be mixed into the insulator 250 through the insulator 283. Impurities such as hydrogen mixed in the insulator 250 may diffuse to the oxide 230 in the channel formation region, which may adversely affect the electrical characteristics of the transistor and the reliability of the transistor.
  • the insulator 274 and the insulator 250 are in direct contact with each other.
  • mixing of impurities such as hydrogen contained in the insulator 280 and the like into the insulator 250 can be suppressed, so that the above-described adverse influence on the electrical characteristics and reliability can be suppressed. it can.
  • the height of the bottom surface of the conductor 260 in a region overlapping with the region 234 is lower than the height of the top surfaces of the conductor 242a and the conductor 242b with reference to the bottom surface of the insulator 224 in FIG. Is preferred.
  • the electric field from the conductor 260 functioning as a gate electrode can act on the entire channel formation region, which is preferable because the operation of the transistor is improved.
  • T1 is 0 nm to 30 nm, preferably 0 nm to 15 nm I assume.
  • FIG. 4 is an enlarged view of a channel formation region in the channel width direction of the transistor 200.
  • the height of the bottom surface of the conductor 260 in the region where the oxide 230 a and the oxide 230 b and the conductor 260 do not overlap with respect to the bottom surface of the insulator 224 is the bottom surface of the oxide 230 b It is preferable to be lower than the height of Assuming that the difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxide 230b and the conductor 260 do not overlap is T2, T2 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.
  • the conductor 260 functioning as a gate electrode covers the side surface and the top surface of the oxide 230 b in the channel formation region with the oxide 230 c and the insulator 250 interposed therebetween. It is easy to act on the entire oxide 230 b in the formation region. Thus, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved.
  • a semiconductor device having a transistor with a large on current can be provided.
  • a semiconductor device having a transistor with high frequency characteristics can be provided.
  • a semiconductor device having a transistor with small off current can be provided.
  • the conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260.
  • the conductor 205 is preferably provided so as to be embedded in the insulator 214 and the insulator 216.
  • the conductor 260 may function as a first gate (also referred to as a top gate) electrode.
  • the conductor 205 may function as a second gate (also referred to as a back gate) electrode.
  • the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking.
  • Vth of the transistor 200 can be increased and off current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no potential is applied.
  • the conductor 205 may be larger than the region 234 in the oxide 230 as illustrated in FIG.
  • the conductor 205 is preferably extended also in a region outside the end of the region 234 of the oxide 230 which intersects the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other through an insulator outside the side surface of the oxide 230 in the channel width direction.
  • the channel formation region of the region 234 is electrically driven by the electric field of the conductor 260 having a function as a first gate electrode and the electric field of the conductor 205 having a function as a second gate electrode.
  • a structure of a transistor which electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • a conductive material mainly containing tungsten, copper, or aluminum is preferably used. Note that although the conductor 205 is illustrated as a single layer, it may have a stacked structure, for example, a stack of titanium and titanium nitride and the above conductive material.
  • the insulator 214 preferably functions as a barrier insulating film which suppresses impurities such as water and hydrogen from entering the transistor 200 from the substrate side. Therefore, the insulator 214 has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 and the like), and copper atoms. (It is difficult for the above impurities to permeate). It is preferable to use an insulating material. Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atoms, oxygen molecules, and the like) (the above oxygen is difficult to permeate).
  • oxygen eg, at least one of oxygen atoms, oxygen molecules, and the like
  • silicon nitride or the like is preferably used as the insulator 214. Accordingly, diffusion of an impurity such as water or hydrogen from the substrate side to the transistor 200 side with respect to the insulator 214 can be suppressed. Alternatively, oxygen contained in the insulator 224 or the like can be suppressed from diffusing to the substrate side more than the insulator 214.
  • the insulator 216, the insulator 280, and the insulator 281 preferably have a lower dielectric constant than the insulator 214.
  • a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, carbon oxide, and nitrogen are added. Silicon oxide, silicon oxide having holes, or the like may be used as appropriate.
  • the insulator 222 and the insulator 224 have a function as a gate insulator.
  • the insulator 224 in contact with the oxide 230 preferably releases oxygen by heating.
  • oxygen released by heating may be referred to as excess oxygen.
  • silicon oxide, silicon oxynitride, or the like may be used as appropriate.
  • an oxide material from which part of oxygen is released by heating is preferably used as the insulator 224.
  • the oxide from which oxygen is released by heating is a desorption amount of oxygen of at least 1.0 ⁇ 10 18 atoms / cm 3 , preferably 1 in terms of oxygen atom in TDS (thermal desorption spectroscopy) analysis. It is an oxide film having a concentration of not less than 0 ⁇ 10 19 atoms / cm 3 , more preferably not less than 2.0 ⁇ 10 19 atoms / cm 3 , or not less than 3.0 ⁇ 10 20 atoms / cm 3 .
  • the surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.
  • the thickness of a region in which the insulator 224 does not overlap with the insulator 254 and does not overlap with the oxide 230b may be thinner than the thickness in the other regions. is there.
  • the thickness of a region which does not overlap with the insulator 254 and does not overlap with the oxide 230b is preferably a thickness which can sufficiently diffuse the oxygen.
  • the insulator 222 preferably functions as a barrier insulating film which suppresses diffusion of an impurity such as water or hydrogen into the transistor 200 from the substrate side.
  • the insulator 222 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 222 preferably has a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atoms, oxygen molecules, and the like) (the above-described oxygen is difficult to transmit).
  • the insulator 222 preferably has lower oxygen permeability than the insulator 224. Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, oxygen included in the oxide 230 can be preferably reduced because diffusion to the insulator 216 side can be reduced.
  • the conductor 205 can be inhibited from reacting with the insulator 224 and oxygen in the oxide 230.
  • the insulator 222 may be an insulator including an oxide of one or both of aluminum and hafnium which are insulating materials.
  • an insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.
  • the insulator 222 suppresses the release of oxygen from the oxide 230 and the entry of impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Act as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, or the like may be added to these insulators.
  • these insulators may be nitrided.
  • silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 222 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba, Sr) TiO 3 (BST), or the like.
  • An insulator containing a so-called high-k material may be used in a single layer or a stack. As the miniaturization and higher integration of transistors progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, it is possible to reduce the gate potential at the time of transistor operation while maintaining the physical thickness.
  • the insulator 222 and the insulator 224 may have a stacked structure of two or more layers.
  • the invention is not limited to the laminated structure made of the same material, but may be a laminated structure made of different materials.
  • the oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b.
  • the oxide 230a under the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed.
  • the oxide 230c over the oxide 230b, diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.
  • the oxide 230 preferably has a stacked-layer structure of oxides having different atomic ratios of metal atoms.
  • the atomic ratio of the element M in the constituent elements is larger than the atomic ratio of the element M in the constituent elements of the metal oxide used for the oxide 230b.
  • the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the oxide 230c a metal oxide which can be used for the oxide 230a or the oxide 230b can be used.
  • the oxide 230 b preferably has crystallinity.
  • An oxide having crystallinity such as CAAC-OS has a dense structure with high crystallinity, with few impurities and defects (such as oxygen deficiency). Accordingly, extraction of oxygen from the oxide 230 b by the source electrode or the drain electrode can be suppressed. Thus, even when heat treatment is performed, extraction of oxygen from the oxide 230 b can be reduced, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.
  • the energy level at the lower end of the conduction band of the oxide 230a and the oxide 230c be higher than the energy level at the lower end of the conduction band of the oxide 230b.
  • the electron affinity of the oxide 230a and the oxide 230c be smaller than the electron affinity of the oxide 230b.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the bottom of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c can be said to be continuously changed or connected continuously.
  • the density of defect states in the mixed layer formed at the interface between the oxide 230 a and the oxide 230 b and at the interface between the oxide 230 b and the oxide 230 c may be lowered.
  • the oxide 230c has a stacked structure
  • In: Ga: Zn 4: 2: 3 [atom And a stacked structure of gallium oxide and the like.
  • the main route of the carrier is the oxide 230b.
  • the oxide 230 a and the oxide 230 c described above the density of defect states in the interface between the oxide 230 a and the oxide 230 b and the interface between the oxide 230 b and the oxide 230 c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain high on current and high frequency characteristics.
  • the constituent element of the oxide 230c is on the insulator 250 side.
  • the oxide 230c has a stacked structure and an oxide which does not contain In is positioned above the stacked structure, it is possible to suppress In which can diffuse to the insulator 250 side. Since the insulator 250 functions as a gate insulator, when In is diffused, the characteristics of the transistor become defective. Therefore, by forming the oxide layer 230c in a stacked structure, a highly reliable semiconductor device can be provided.
  • a metal oxide which functions as an oxide semiconductor is preferably used.
  • the metal oxide to be the region 234 one having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used.
  • the off-state current of the transistor can be reduced.
  • a semiconductor device with low power consumption can be provided.
  • a conductor 242 (a conductor 242 a and a conductor 242 b) functioning as a source electrode and a drain electrode is provided over the oxide 230 b.
  • the thickness of the conductor 242 may be, for example, 1 nm to 50 nm, preferably 2 nm to 25 nm.
  • the conductor 242 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum or an alloy containing the above-described metal element as a component, or an alloy in which the above-described metal element is combined.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are used. Is preferred.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material which maintains conductivity even by absorbing oxygen.
  • the insulator 254 preferably functions as a barrier insulating film which suppresses entry of an impurity such as water or hydrogen into the transistor 200 from the insulator 280 side like the insulator 214 or the like.
  • the insulator 254 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 254 includes the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the oxide 230a and the oxide 230b, and the insulator 224. It is preferable to contact the upper surface of With such a structure, hydrogen contained in the insulator 280 can be prevented from entering the channel formation region of the oxide 230.
  • the insulator 254 preferably has a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atom, oxygen molecule, and the like) (the above-described oxygen is less likely to be transmitted).
  • the insulator 254 preferably has lower oxygen permeability than the insulator 224.
  • the insulator 254 is preferably deposited using a sputtering method.
  • oxygen can be added in the vicinity of the region of the insulator 224 in contact with the insulator 254.
  • oxygen can be supplied from the region to the oxide 230 through the insulator 224.
  • the insulator 254 has a function of suppressing the diffusion of oxygen upward, whereby oxygen can be prevented from diffusing from the oxide 230 to the insulator 280.
  • the insulator 222 has a function of suppressing the diffusion of oxygen downward, whereby oxygen can be prevented from diffusing from the oxide 230 to the insulator 216.
  • oxygen is supplied to the region 234 which functions as a channel formation region of the oxide 230.
  • oxygen vacancies in the oxide 230 can be reduced and normally on conversion of the transistor can be suppressed.
  • the insulator 254 can have a multilayer structure of two or more layers.
  • a first layer may be formed using a sputtering method in an atmosphere containing oxygen, and then a second layer may be formed using an ALD method to form a two-layer structure.
  • the ALD method is a film forming method with good coverage, and thus can prevent formation of steps and the like due to the unevenness of the first layer.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be deposited.
  • aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing one or both of the oxides of aluminum and hafnium.
  • the insulator 250 functions as a gate insulator.
  • the insulator 250 is preferably placed in contact with the top surface of the oxide 230c.
  • the insulator 250 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with holes, or the like. It can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.
  • the insulator 250 is preferably formed using an insulator from which oxygen is released by heating.
  • an insulator from which oxygen is released by heating By providing an insulator from which oxygen is released by heating as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied to the region 234 of the oxide 230b.
  • the concentration of impurities such as water and hydrogen in the insulator 250 is preferably reduced.
  • the thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.
  • a metal oxide may be provided between the insulator 250 and the conductor 260.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260.
  • the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a reduction in the amount of oxygen supplied to the oxide 230 can be suppressed.
  • oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.
  • the metal oxide may have a function as part of a gate insulator. Therefore, in the case of using silicon oxide, silicon oxynitride, or the like for the insulator 250, it is preferable to use a metal oxide which is a high-k material having a high relative dielectric constant.
  • a metal oxide which is a high-k material having a high relative dielectric constant By forming the gate insulator to have a stacked structure of the insulator 250 and the metal oxide, a stacked structure that is stable to heat and has a high relative dielectric constant can be obtained. Therefore, while maintaining the physical thickness of the gate insulator, it is possible to reduce the gate potential applied at the time of transistor operation. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as a gate insulator.
  • EOT equivalent oxide thickness
  • metal oxides containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like can be used.
  • aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like, which is an insulator containing one or both oxides of aluminum and hafnium, is preferably used.
  • the conductor 260a has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 etc.), copper atoms, etc. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atom, oxygen molecule, and the like).
  • the conductor 260a having a function of suppressing the diffusion of oxygen can suppress the oxidation of the conductor 260b due to the oxygen contained in the insulator 250 to reduce the conductivity.
  • a conductive material having a function of suppressing diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide or the like is preferably used.
  • the conductor 260 also functions as a wiring, a conductor with high conductivity is preferably used.
  • the conductor 260b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 260b may have a stacked structure, for example, a stacked structure of titanium and titanium nitride and the above conductive material.
  • the insulator 280 is provided over the insulator 224, the oxide 230, and the conductor 242 through the insulator 254.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, or the like is included. Is preferred.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • a material such as silicon oxide, silicon oxynitride, or silicon oxide having holes is preferable because a region containing oxygen which is released by heating can be easily formed.
  • the concentration of impurities such as water and hydrogen in the insulator 280 be reduced.
  • the top surface of the insulator 280 may be planarized.
  • the insulator 274 preferably functions as a barrier insulating film which suppresses entry of an impurity such as water or hydrogen into the insulator 280 from the top, similarly to the insulator 214 and the like.
  • an insulator that can be used for the insulator 214, the insulator 254, and the like may be used.
  • an insulator 281 which functions as an interlayer film is preferably provided over the insulator 274.
  • the insulator 281 preferably has a reduced concentration of impurities such as water and hydrogen in the film, similarly to the insulator 224 and the like.
  • the conductor 240 a and the conductor 240 b are provided in the openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254.
  • the conductor 240 a and the conductor 240 b are provided opposite to each other with the conductor 260 interposed therebetween. Note that the heights of the top surfaces of the conductor 240 a and the conductor 240 b may be on the same plane as the top surface of the insulator 281.
  • an insulator 241a is provided in contact with the inner wall of the opening formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a conductor 240a is formed in contact with the side surface.
  • the conductor 242a is positioned at least at a part of the bottom of the opening, and the conductor 240a is in contact with the conductor 242a.
  • an insulator 241 b is provided in contact with the inner wall of an opening formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a conductor 240 b is formed in contact with the side surface thereof.
  • the conductor 242 b is positioned at least at a part of the bottom of the opening, and the conductor 240 b is in contact with the conductor 242 b.
  • the conductor 240 a and the conductor 240 b may have a stacked structure.
  • the conductor in contact with the oxide 230a, the oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, the insulator 281, and the like includes water and hydrogen.
  • a conductive material having a function of suppressing permeation of impurities such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide or the like is preferably used.
  • a conductive material having a function of suppressing permeation of impurities such as water and hydrogen may be used in a single layer or a stack.
  • oxygen added to the insulator 280 can be prevented from being absorbed by the conductor 240 a and the conductor 240 b. Further, impurities such as water and hydrogen can be prevented from being mixed into the oxide 230 from above the insulator 281 through the conductor 240 a and the conductor 240 b.
  • an insulator that can be used for the insulator 254 or the like may be used as the insulator 241a and the insulator 241b. Since the insulators 241a and 241b are provided in contact with the insulator 254, impurities such as water and hydrogen can be prevented from being mixed into the oxide 230 from the insulator 280 or the like through the conductor 240a and the conductor 240b. be able to. Further, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240 a and the conductor 240 b.
  • a conductor that functions as a wiring may be disposed in contact with the top surface of the conductor 240a and the top surface of the conductor 240b. It is preferable to use a conductive material whose main component is tungsten, copper, or aluminum as the conductor functioning as the wiring.
  • the conductor may have a stacked structure, for example, a stack of titanium and titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in an insulator.
  • a substrate for forming the transistor 200 for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate may be, for example, a semiconductor substrate of silicon, germanium or the like, or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide.
  • the conductive substrate there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate.
  • the conductive substrate there are a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate and the like.
  • a substrate provided with a conductor or a semiconductor on an insulator substrate a substrate provided with a conductor or an insulator on a semiconductor substrate, a substrate provided with a semiconductor or an insulator on the conductor substrate, and the like.
  • those provided with elements on these substrates may be used.
  • the elements provided on the substrate include a capacitor, a resistor, a switch, a light-emitting element, a memory element, and the like.
  • the insulator includes, for example, an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, and the like.
  • the thinning of the gate insulator may cause problems such as leakage current.
  • a high-k material for the insulator that functions as a gate insulator voltage reduction during transistor operation can be achieved while maintaining the physical thickness.
  • a material having a low relative dielectric constant for an insulator functioning as an interlayer film parasitic capacitance generated between wirings can be reduced. Therefore, depending on the function of the insulator, the material may be selected.
  • oxides of gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium, oxynitrides of aluminum and hafnium, oxides of silicon and hafnium, silicon and hafnium can be used.
  • oxides of silicon and hafnium, silicon and hafnium can be used.
  • oxynitride, a nitride having silicon and hafnium, and the like are examples of silicon and hafnium, and the like.
  • the transistor including an oxide semiconductor is surrounded by an insulator (such as the insulator 214, the insulator 222, the insulator 254, and the insulator 274) having a function of suppressing permeation of impurities such as hydrogen and oxygen.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium
  • An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stack.
  • metal oxides such as tantalum oxide, metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride can be used.
  • the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen which is desorbed by heating.
  • the structure in which silicon oxide or silicon oxynitride having a region containing oxygen released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.
  • Conductor aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum It is preferable to use a metal element selected from the like, or an alloy containing the above-described metal element as a component, or an alloy in which the above-described metal element is combined.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are used. Is preferred.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are difficult to oxidize.
  • a semiconductor with high electrical conductivity typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a plurality of conductive layers formed of the above materials may be stacked.
  • a stacked structure in which a material containing a metal element described above and a conductive material containing oxygen are combined may be used.
  • a stacked structure in which the material containing the metal element described above and the conductive material containing nitrogen are combined may be used.
  • a stacked structure in which the above-described material containing a metal element, the conductive material containing oxygen, and the conductive material containing nitrogen are combined may be used.
  • a stacked structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate electrode.
  • a conductive material containing oxygen may be provided on the channel formation region side.
  • a conductor functioning as a gate electrode a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used.
  • a conductive material containing the above-described metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • metal oxides As the oxide 230, a metal oxide which functions as an oxide semiconductor is preferably used. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.
  • the metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. In addition, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.
  • the metal oxide is an In-M-Zn oxide having indium, an element M and zinc.
  • the element M is aluminum, gallium, yttrium, tin or the like.
  • Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.
  • the element M a plurality of the aforementioned elements may be combined in some cases.
  • metal oxides having nitrogen may also be collectively referred to as metal oxides.
  • a metal oxide having nitrogen may be referred to as metal oxynitride.
  • Oxide semiconductors can be divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor for example, CAAC-OS, polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), pseudo amorphous oxide semiconductor (a-like OS: a-like OS: a-like OS), And amorphous oxide semiconductors.
  • the CAAC-OS has c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction to form a strained crystal structure.
  • distortion refers to a portion where the orientation of the lattice arrangement changes between the region in which the lattice arrangement is aligned and the region in which another lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.
  • the nanocrystals are based on hexagons, but may not be regular hexagons and may be non-hexagonal.
  • distortion may have a lattice arrangement such as pentagon or heptagon.
  • it is difficult to confirm clear crystal grain boundaries (also referred to as grain boundaries) even in the vicinity of strain. That is, it is understood that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, or that the bonding distance between atoms is changed due to metal element substitution. It is for.
  • a CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer containing element M, zinc and oxygen (hereinafter referred to as (M, Zn) layer) are stacked. It tends to have a structure (also referred to as a layered structure).
  • In layer a layer containing indium and oxygen
  • M, Zn zinc and oxygen
  • indium and the element M can be substituted with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as a (In, M, Zn) layer.
  • indium in the In layer is substituted with the element M, it can also be represented as an (In, M) layer.
  • CAAC-OS is a highly crystalline metal oxide. On the other hand, it is difficult to confirm clear crystal grain boundaries in CAAC-OS, so it can be said that the decrease in electron mobility due to crystal grain boundaries does not easily occur. In addition, since the crystallinity of the metal oxide may be lowered due to the mixing of impurities, generation of defects, or the like, CAAC-OS can also be said to be a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, the metal oxide having a CAAC-OS has stable physical properties. Therefore, a metal oxide having a CAAC-OS is resistant to heat and has high reliability.
  • the nc-OS has periodicity in atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • nc-OS has no regularity in crystal orientation among different nanocrystals. Therefore, no orientation can be seen in the entire film. Therefore, the nc-OS may not be distinguished from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.
  • IGZO indium-gallium-zinc oxide
  • IGZO indium-gallium-zinc oxide
  • IGZO may have a stable structure by using the above-mentioned nanocrystals.
  • IGZO tends to be difficult to grow crystals in the atmosphere, so smaller crystals (for example, the above-mentioned nanocrystals) than large crystals (here, crystals of a few mm or crystals of a few cm) But may be structurally stable.
  • the a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a wrinkle or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • the metal oxide contains an alkali metal or an alkaline earth metal
  • a defect level may be formed to generate a carrier. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to be normally on. For this reason, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide.
  • the concentration of alkali metal or alkaline earth metal in the metal oxide obtained by secondary ion mass spectrometry (SIMS) is 1 ⁇ 10 18 atoms / cm 3 or less, preferably The concentration is 2 ⁇ 10 16 atoms / cm 3 or less.
  • hydrogen contained in the metal oxide reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons that are carriers may be generated.
  • a part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor using a metal oxide which contains hydrogen is likely to be normally on.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm. It is less than 3 and more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • a thin film with high crystallinity As the metal oxide used for the semiconductor of the transistor, the stability or the reliability of the transistor can be improved.
  • the thin film include thin films of single crystal metal oxides or thin films of polycrystalline metal oxides.
  • a high temperature or laser heating step is required to form a thin film of monocrystalline metal oxide or a thin film of polycrystalline metal oxide on a substrate. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.
  • CAAC-IGZO In-Ga-Zn oxide
  • nc-IGZO In-Ga-Zn oxide having an nc structure was discovered (see Non-Patent Document 3).
  • nc-IGZO has periodicity in atomic arrangement in a minute area (for example, an area of 1 nm or more and 3 nm or less) and regularity in crystal orientation is not observed between different areas. There is.
  • Non-Patent Document 4 and Non-Patent Document 5 show the transition of the average crystal size by the irradiation of an electron beam to the thin films of the above-described CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity.
  • a low crystalline IGZO thin film crystalline IGZO of about 1 nm has been observed even before electron beam irradiation. Therefore, it is reported here that in IGZO, the presence of a completely amorphous structure could not be confirmed.
  • the thin film of CAAC-IGZO and the thin film of nc-IGZO have high stability to electron beam irradiation as compared with the thin film of IGZO having low crystallinity. Therefore, it is preferable to use a thin film of CAAC-IGZO or a thin film of nc-IGZO as a semiconductor of the transistor.
  • a transistor using a metal oxide has extremely low leakage current in the non-conductive state, specifically, the off-state current per ⁇ m channel width of the transistor is on the order of yA / ⁇ m (10 -24 A / ⁇ m).
  • Non-Patent Document 6 For example, a low power consumption CPU or the like to which a characteristic that a leak current of a transistor using a metal oxide is low is disclosed (see Non-Patent Document 7).
  • Non-Patent Document 8 application of a transistor using a metal oxide to a display device utilizing a characteristic that a leak current of the transistor is low has been reported (see Non-Patent Document 8).
  • the displayed image is switched several tens of times per second.
  • the number of times of switching images per second is called a refresh rate.
  • the refresh rate may be referred to as a drive frequency.
  • Such fast screen switching which is difficult for human eyes to perceive, is considered as the cause of eye fatigue. Therefore, it has been proposed to reduce the number of image rewrites by reducing the refresh rate of the display device.
  • power consumption of the display device can be reduced by driving with a lower refresh rate.
  • Such a driving method is called idling stop (IDS) driving.
  • IDS idling stop
  • the discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of a transistor using a metal oxide having a CAAC structure or an nc structure, as well as to the cost reduction and the throughput improvement of the manufacturing process.
  • researches on application of the transistor to a display device and an LSI using the characteristic that the leakage current of the transistor is low have been advanced.
  • FIG. 2 illustrates the configuration example of the semiconductor device including the transistor 200 in which the conductor 242 functioning as a source electrode or a drain electrode is formed in contact with the oxide 230, the configuration of the semiconductor device is limited thereto. Absent.
  • an example of a semiconductor device including the transistor 200A according to one embodiment of the present invention will be described with reference to FIG.
  • FIG. 5A is a top view of a semiconductor device including the transistor 200A.
  • 5B and 5C are cross-sectional views of the semiconductor device.
  • FIG. 5B is a cross-sectional view of a portion indicated by an alternate long and short dash line A1-A2 in FIG. 5A, and is also a cross-sectional view in the channel length direction of the transistor 200A.
  • 5C is a cross-sectional view of a portion indicated by an alternate long and short dash line A3-A4 in FIG. 5A, and is also a cross-sectional view in the channel width direction of the transistor 200A. Note that, in the top view of FIG. 5A, some elements are omitted for the sake of clarity.
  • the configuration of the semiconductor device will be described with reference to FIG. Also in this item, as the constituent material of the semiconductor device, the materials described in detail in ⁇ Configuration Example of Semiconductor Device> can be used.
  • the transistor 200A included in the semiconductor device illustrated in FIG. 5 is a modified example of the transistor 200 included in the semiconductor device illustrated in ⁇ Configuration Example of Semiconductor Device>. Therefore, in order to prevent repetition of the description, points different from the transistor 200 described in ⁇ Configuration Example of Semiconductor Device> will be mainly described.
  • the transistor 200A illustrated in FIG. 5 is different from the transistor 200 illustrated in ⁇ Structure Example of Semiconductor Device> in that the conductor 242 and the insulator 254 are not included but the insulator 244 and the insulator 245 are included.
  • a source region or a drain region is provided in the oxide 230b by selectively reducing the resistance of the oxide 230 without providing the conductor 242.
  • a metal oxide which functions as an oxide semiconductor can be used as the oxide 230 including a channel formation region, similarly to the transistor 200 illustrated in FIG.
  • an element that forms an oxygen vacancy or an element that bonds to an oxygen vacancy may increase the carrier density and reduce the resistance of the oxide 230.
  • an element for reducing the resistance of the oxide 230 boron or phosphorus can typically be mentioned.
  • hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, a rare gas or the like may be used.
  • Representative examples of the noble gas include helium, neon, argon, krypton, xenon and the like.
  • concentration of the above element may be measured using SIMS or the like.
  • boron and phosphorus are preferable because they can use equipment of an amorphous silicon or low-temperature polysilicon production line. By diverting the apparatus of the manufacturing line, equipment investment can be suppressed.
  • a region 243 (a region 243 a and a region 243 b) illustrated in FIG. 5 is a region in which the above element is added to the oxide 230 b.
  • the region 243 can be formed, for example, by using a dummy gate.
  • a dummy gate may be provided over the oxide 230b, and the dummy gate may be used as a mask to add an element which reduces the resistance of the oxide 230b. That is, the element is added to a region where the oxide 230 does not overlap with the dummy gate, whereby the region 243 is formed.
  • a method of adding the element an ion injection method in which an ionized source gas is separated by mass separation, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, etc. Can be used.
  • an insulator may be provided between the oxide 230 b and the dummy gate, and the dummy gate may be used as a mask to add an element that reduces the resistance of the oxide 230 b.
  • the insulator for example, the same material as the insulator 224 can be used.
  • an insulating film to be the insulator 244 and an insulating film to be the insulator 245 may be formed over the oxide 230 b and the dummy gate.
  • the insulating film to be the insulator 280 is subjected to a CMP process to form one of the insulating films to be the insulator 280.
  • the part is removed to expose the dummy gate.
  • part of an insulating film to be the insulator 244 in contact with the dummy gate may be removed. Therefore, the insulator 245 and the insulator 244 are exposed on the side surface of the opening provided in the insulator 280, and a part of the region 243 provided in the oxide 230b is exposed on the bottom surface of the opening.
  • an oxide film to be the oxide 230c, an insulating film to be the insulator 250, and a conductive film to be the conductor 260 are sequentially formed in the opening, and then CMP is performed until the insulator 280 is exposed.
  • CMP is performed until the insulator 280 is exposed.
  • the insulator 244 and the insulator 245 it is preferable to use an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. Note that the insulator 244 and the insulator 245 are not essential components. It may be appropriately designed according to the transistor characteristics to be obtained.
  • the transistor 200A shown in FIG. 5 can divert an existing device, and further, unlike the transistor 200 shown in FIG. 2, since the conductor 242 is not provided, cost can be reduced.
  • FIG. 1 An example of a semiconductor device (storage device) using a capacitor, which is one embodiment of the present invention, is illustrated in FIG.
  • the semiconductor device of one embodiment of the present invention includes the capacitor 100, the transistor 200, and the transistor 300.
  • the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has low off-state current, stored data can be held for a long time by using the transistor for the memory device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, power consumption of the memory device can be sufficiently reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the memory device illustrated in FIG. 6 can form a memory cell array by being arranged in a matrix.
  • the transistor 300 is provided over the substrate 311 and functions as a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and a source region or a drain region. It has low resistance region 314a and low resistance region 314b.
  • the transistor 300 may be either p-channel or n-channel.
  • the semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape.
  • the conductor 316 is provided to cover the side surface and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween.
  • the conductor 316 may use a material for adjusting a work function.
  • Such a transistor 300 is also referred to as a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulator which functions as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion.
  • a semiconductor film having a convex shape may be formed by processing the SOI substrate.
  • transistor 300 illustrated in FIG. 6 is an example, and is not limited to the structure, and an appropriate transistor may be used depending on the circuit configuration and the driving method.
  • the capacitor 100 includes the conductor 110 functioning as a first electrode, the conductor 120 functioning as a second electrode, and the insulator 130 functioning as a dielectric.
  • the conductor 110 can be formed at the same time as the conductor 112 provided over the conductor 246.
  • the conductor 112 has a function as a plug electrically connected to the capacitor 100, the transistor 200, or the transistor 300, or a wiring.
  • the conductor 112 and the conductor 110 each have a single-layer structure in FIG. 6, the structure is not limited to this structure, and a stacked structure of two or more layers may be used. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor having high adhesion to a conductor having a barrier property and a conductor having high conductivity may be formed.
  • the insulator 130 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, hafnium nitride Or the like may be used, and they can be provided in a stack or a single layer.
  • the capacitive element 100 can secure a sufficient capacity by having an insulator with a high dielectric constant (high-k), and by having an insulator with a large dielectric strength, the dielectric strength can be improved, and the capacitance can be increased.
  • the electrostatic breakdown of the element 100 can be suppressed.
  • an insulator of a high dielectric constant (high-k) material (a material with a high relative dielectric constant), an oxide having gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium, an oxynitride having aluminum and hafnium And oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, nitrides containing silicon and hafnium, and the like.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon is added, carbon and nitrogen are materials having high dielectric strength (materials having low dielectric constant). There are silicon oxide added, silicon oxide having pores, resin and the like.
  • a wiring layer provided with an interlayer film, a wiring, a plug and the like may be provided between the respective structures. Also, a plurality of wiring layers can be provided depending on the design.
  • a conductor having a function as a plug or a wiring may be provided with the same reference numeral collectively as a plurality of structures.
  • the wiring and the plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as an interlayer film.
  • a conductor 328 electrically connected to the capacitor 100 or the transistor 300, a conductor 330, and the like are embedded. Note that the conductor 328 and the conductor 330 function as a plug or a wiring.
  • the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape below it.
  • the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance the planarity.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked and provided.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wire.
  • the conductor 218, a conductor (conductor 205) included in the transistor 200, and the like are embedded.
  • the conductor 218 has a function as a plug electrically connected to the capacitor 100 or the transistor 300, or a wiring.
  • an insulator 150 is provided over the conductor 120 and the insulator 130.
  • an insulator which can be used as an interlayer film, an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, or the like can be given.
  • the material may be selected depending on the function of the insulator.
  • the insulator 150 for the insulator 150, the insulator 212, the insulator 352, the insulator 354 and the like, an insulator with a low relative permittivity is preferably used.
  • the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having voids. And resins, etc. are preferred.
  • the insulator may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having voids. It is preferable to have a laminated structure of and a resin. Silicon oxide and silicon oxynitride are thermally stable, and thus, when combined with a resin, a stacked structure with a thermally stable and low dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • the transistor including an oxide semiconductor electrical characteristics of the transistor can be stabilized by being surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen. Therefore, for the insulator 210, the insulator 350, and the like, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen can be used.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium
  • An insulator containing lanthanum, neodymium, hafnium or tantalum may be used in a single layer or a stack.
  • aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium
  • a material containing one or more metal elements selected from ruthenium and the like can be used.
  • a semiconductor with high electrical conductivity typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above materials
  • the elastic material can be used as a single layer or a laminate. It is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.
  • an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor.
  • the insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
  • an insulator 276 may be provided between the insulator 224 having excess oxygen and the conductor 246. With the insulator 276, the insulator 222, and the insulator 274 provided in contact with each other, the insulator 224 and the transistor 200 can be sealed by an insulator having a barrier property. Further, the insulator 276 is preferably in contact with the insulator 280. With the insulator 276 extending to the insulator 280, diffusion of oxygen and impurities can be further suppressed.
  • an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen and oxygen can be used as the insulator 276, an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen and oxygen can be used.
  • aluminum oxide or hafnium oxide is preferably used.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, silicon nitride oxide, silicon nitride, and the like can be used.
  • FIG. 7 An example of a memory device using the semiconductor device of one embodiment of the present invention is illustrated in FIG.
  • the memory device illustrated in FIG. 7 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 illustrated in FIG.
  • the transistor 400 can control the second gate voltage of the transistor 200.
  • the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200.
  • the negative potential of the second gate of the transistor 200 is held in this structure, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source are 0 V.
  • the power of the transistor 200 and the transistor 400 need not be supplied to the second gate of the transistor 200. Negative potential can be maintained for a long time. Accordingly, the memory device including the transistor 200 and the transistor 400 can hold stored data for a long time.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the first gate of the transistor 400, the wiring 1009 is electrically connected to the second gate of the transistor 400, and the wiring 1010 Is electrically connected to the drain of the transistor 400.
  • the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.
  • the memory device illustrated in FIG. 7 can form a memory cell array by being arranged in a matrix as in the memory device illustrated in FIG. Note that one transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, the number of transistors 400 may be smaller than that of the transistors 200.
  • the transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel.
  • the transistor 400 includes a conductor 460 (conductor 460a and a conductor 460b) functioning as a first gate electrode, a conductor 405 functioning as a second gate electrode, and an insulator 222 functioning as a gate insulator.
  • the conductor 405 and the conductor 205 are formed in the same layer.
  • the oxide 431a and the oxide 432a and the oxide 230a are formed in the same layer, and the oxide 431b and the oxide 432b and the oxide 230b are formed in the same layer.
  • the conductor 442 and the conductor 242 are formed in the same layer.
  • the oxide 430c and the oxide 230c are formed in the same layer.
  • the insulator 450 and the insulator 250 are formed in the same layer.
  • the conductor 460 and the conductor 260 are formed in the same layer.
  • the oxide 430c can be formed by processing an oxide film to be the oxide 230c.
  • the oxide 430 c functioning as an active layer of the transistor 400 oxygen vacancies are reduced and impurities such as hydrogen and water are reduced as in the case of the oxide 230 and the like. Accordingly, the threshold voltage of the transistor 400 can be increased, the off-state current can be reduced, and the drain current can be extremely reduced when the second gate voltage and the first gate voltage are 0 V.
  • dicing lines (sometimes referred to as scribe lines, dividing lines, or cutting lines) provided when a plurality of semiconductor devices are taken out in chip form by dividing a large-area substrate into semiconductor elements will be described.
  • a dividing method for example, there is a method of first forming a groove (dicing line) for dividing a semiconductor element in a substrate and then cutting along a dicing line to divide (divide) into a plurality of semiconductor devices.
  • a region where the insulator 254 and the insulator 222 are in contact it is preferable to design a region where the insulator 254 and the insulator 222 are in contact to be a dicing line. That is, an opening is provided in the insulator 224 in the vicinity of a memory cell including the plurality of transistors 200 and a region to be a dicing line provided on the outer edge of the transistor 400.
  • an insulator 254 is provided to cover the side surface of the insulator 224.
  • the insulator 222 and the insulator 254 are in contact with each other in the opening provided in the insulator 224.
  • the insulator 222 and the insulator 254 may be formed using the same material and the same method.
  • adhesion can be improved. For example, it is preferable to use aluminum oxide.
  • the insulator 224, the transistor 200, and the transistor 400 can be surrounded by the insulator 222 and the insulator 254. Since the insulator 222 and the insulator 254 have a function of suppressing diffusion of oxygen, hydrogen, and water, the substrate is divided in each of the circuit regions in which the semiconductor element described in this embodiment is formed. Accordingly, even when processed into a plurality of chips, impurities such as hydrogen and water can be prevented from being mixed from the side direction of the divided substrate and diffused into the transistor 200 and the transistor 400.
  • the structure can prevent excess oxygen in the insulator 224 from diffusing to the insulator 254 and the outside of the insulator 222. Accordingly, excess oxygen in the insulator 224 is efficiently supplied to the transistor 200 or the oxide in which the channel in the transistor 400 is formed.
  • the oxygen can reduce oxygen vacancies in the oxide in which a channel in the transistor 200 or the transistor 400 is formed. Accordingly, the oxide in which the channel in the transistor 200 or the transistor 400 is formed can be an oxide semiconductor with low density of defect states and stable characteristics. That is, variation in the electrical characteristics of the transistor 200 or the transistor 400 can be suppressed, and the reliability can be improved.
  • Embodiment 4 a transistor using an oxide as a semiconductor (hereinafter, may be referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are applied with reference to FIGS. 8 and 9.
  • a storage device hereinafter sometimes referred to as an OS memory device
  • the OS memory device is a storage device including at least a capacitor and an OS transistor which controls charge and discharge of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory.
  • FIG. 8A shows an example of the configuration of the OS memory device.
  • the memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470.
  • Peripheral circuit 1411 includes row circuit 1420, column circuit 1430, output circuit 1440, and control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying a data signal read from the memory cell.
  • the wiring is a wiring connected to a memory cell included in the memory cell array 1470, which will be described in detail later.
  • the amplified data signal is output as the data signal RDATA to the outside of the storage device 1400 through the output circuit 1440.
  • the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.
  • the storage device 1400 is externally supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 as a power supply voltage. Further, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.
  • the control logic circuit 1460 processes external control signals (CE, WE, RE) to generate control signals for row decoders and column decoders.
  • the control signal CE is a chip enable signal
  • the control signal WE is a write enable signal
  • the control signal RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as necessary.
  • Memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings.
  • the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC provided in one column, and the like.
  • the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, and the like.
  • FIG. 8A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
  • the present embodiment is not limited to this.
  • the memory cell array 1470 may be provided so as to overlap with part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap below the memory cell array 1470.
  • [DOSRAM] 9A to 9C show an example of circuit configuration of a memory cell of a DRAM.
  • a DRAM using a memory cell of one OS transistor and one capacitive element type may be referred to as DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory).
  • DOSRAM registered trademark
  • the memory cell 1471 illustrated in FIG. 9A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes referred to as a top gate) and a back gate.
  • the first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 Is connected to the wiring BGL.
  • the second terminal of the capacitive element CA is connected to the wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. It is preferable to apply a low level potential to the wiring CAL at the time of data writing and reading.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1471 and can change the circuit configuration.
  • the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL.
  • the memory cell MC may be a memory cell including a single gate transistor, that is, a transistor M1 having no back gate.
  • the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA.
  • the leak current of the transistor M1 can be made extremely small. That is, since the written data can be held for a long time by the transistor M1, the frequency of refresh of the memory cell can be reduced. In addition, the refresh operation of the memory cell can be made unnecessary.
  • the leakage current is very small, multi-level data or analog data can be stored in the memory cell 1471, the memory cell 1472, and the memory cell 1473.
  • the bit line when the sense amplifier is provided so as to overlap below the memory cell array 1470, the bit line can be shortened.
  • the bit line capacitance can be reduced, and the storage capacitance of the memory cell can be reduced.
  • [NOSRAM] 9D to 9G show circuit configuration examples of a gain cell type memory cell of two transistors and one capacitor.
  • the memory cell 1474 illustrated in FIG. 9D includes a transistor M2, a transistor M3, and a capacitor CB.
  • the transistor M2 has a gate (sometimes referred to as a top gate) and a back gate.
  • NOSRAM registered trademark
  • Nonvolatile Oxide Semiconductor RAM Nonvolatile Oxide Semiconductor RAM
  • the first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 Is connected to the wiring BGL.
  • the second terminal of the capacitive element CB is connected to the wiring CAL.
  • the first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, holding data, and reading data, it is preferable to apply a low level potential to the wiring CAL.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1474, and the configuration of the circuit can be changed as appropriate.
  • the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL.
  • the memory cell MC may be a memory cell including a single-gate transistor, that is, a transistor M2 having no back gate.
  • the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into one wiring BIL.
  • the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB.
  • the leakage current of the transistor M2 can be made extremely small.
  • the frequency of refresh of the memory cell can be reduced.
  • the refresh operation of the memory cell can be made unnecessary.
  • the memory cell 1474 can hold multilevel data or analog data. The same applies to memory cells 1475 to 1477.
  • the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor).
  • the conductivity type of the Si transistor may be n-channel or p-channel.
  • the Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read out transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by being stacked on the transistor M3, so that the area occupied by the memory cell can be reduced and high integration of the memory device can be achieved.
  • the transistor M3 may be an OS transistor.
  • OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.
  • FIG. 9H shows an example of a gain cell type memory cell of three transistors and one capacitance element.
  • the memory cell 1478 illustrated in FIG. 9H includes transistors M4 to M6 and a capacitor CC.
  • the capacitive element CC is appropriately provided.
  • the memory cell 1478 is electrically connected to the wirings BIL, RWL, WWL, BGL, and GNDL.
  • the wiring GNDL is a wiring for applying a low level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.
  • the transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.
  • the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively.
  • the transistors M4 to M6 may be OS transistors.
  • the memory cell array 1470 can be configured using only n-type transistors.
  • the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitive element 100 can be used as the capacitive element CC.
  • the leak current of the transistor M4 can be made extremely small.
  • peripheral circuit 1411 the memory cell array 1470, and the like described in this embodiment are not limited to the above. Arrangements or functions of these circuits, wirings connected to the circuits, circuit elements and the like may be changed, deleted, or added as needed.
  • FIG. 1200 An example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown using FIG.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system on chip
  • the chip 1200 includes a central processing unit (CPU) 1211, a graphics processing unit (GPU) 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more Interface 1215, one or more network circuits 1216, and the like.
  • CPU central processing unit
  • GPU graphics processing unit
  • analog operation units 1213 one or more analog operation units 1213
  • memory controllers 1214 one or more memory controllers 1214
  • Interface 1215 one or more network circuits 1216, and the like.
  • the chip 1200 is provided with a bump (not shown), and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in FIG. 10B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.
  • PCB printed circuit board
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222.
  • a storage device such as a DRAM 1221 and a flash memory 1222.
  • the DOS RAM described in the above embodiment can be used for the DRAM 1221.
  • the NOSRAM described in the above embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the memory the aforementioned NOSRAM or DOSRAM can be used.
  • the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum operation. By providing the image processing circuit and the product-sum operation circuit using the oxide semiconductor of the present invention in the GPU 1212, image processing and product-sum operation can be performed with low power consumption.
  • the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between memories of the CPU 1211 and the GPU 1212 And, after the calculation by the GPU 1212, transfer of the calculation result from the GPU 1212 to the CPU 1211 can be performed at high speed.
  • the analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum operation circuit may be provided in the analog operation unit 1213.
  • the memory controller 1214 has a circuit functioning as a controller of the DRAM 1221 and a circuit functioning as an interface of the flash memory 1222.
  • the interface 1215 includes an interface circuit with an external connection device such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface or the like can be used.
  • the network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also have circuitry for network security.
  • LAN Local Area Network
  • the circuits can be formed in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be referred to as a GPU module 1204.
  • the GPU module 1204 has a chip 1200 using SoC technology, so its size can be reduced. Moreover, since it is excellent in image processing, it is suitable to use for portable electronic devices, such as a smart phone, a tablet terminal, a laptop PC, and a portable (portable) game machine.
  • DNN deep neural network
  • CNN convolutional neural network
  • RNN recursive neural network
  • DBM deep layer Boltzmann machine
  • the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module, since a technique such as DBN can be performed.
  • the semiconductor device described in the above embodiment is, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording and reproducing device, a navigation system, etc.)
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device described in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • FIG. 11 schematically shows some configuration examples of the removable storage device.
  • the semiconductor device described in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG. 11A is a schematic view of a USB memory.
  • the USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104.
  • the substrate 1104 is housed in a housing 1101.
  • the memory chip 1105 and the controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like.
  • FIG. 11 (B) is a schematic view of the appearance of the SD card
  • FIG. 11 (C) is a schematic view of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111, a connector 1112 and a substrate 1113.
  • the substrate 1113 is housed in a housing 1111.
  • the memory chip 1114 and the controller chip 1115 are attached to the substrate 1113.
  • the capacity of the SD card 1110 can be increased.
  • a wireless chip provided with a wireless communication function may be provided over the substrate 1113.
  • data can be read and written from the memory chip 1114 by wireless communication between the host device and the SD card 1110.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1114 or the like.
  • FIG. 11D is a schematic view of the external appearance of the SSD
  • FIG. 11E is a schematic view of the internal structure of the SSD.
  • the SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153.
  • the substrate 1153 is housed in a housing 1151.
  • the memory chip 1154, the memory chip 1155, and the controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the capacity of the SSD 1150 can be increased.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1154 or the like.
  • the semiconductor device can be used for a processor such as a CPU or a GPU or a chip.
  • FIG. 12 illustrates a specific example of an electronic device provided with a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention.
  • the GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices.
  • electronic devices include television devices, desktop or notebook personal computers, monitors for computers, etc., relatively large screens of large-sized game machines such as digital signage (Digital Signage) and pachinko machines.
  • digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, and the like can be given.
  • artificial intelligence can be mounted on an electronic device by providing the integrated circuit or the chip according to one embodiment of the present invention to the electronic device.
  • the electronic device of one embodiment of the present invention may have an antenna. By receiving the signal with the antenna, display of images, information, and the like can be performed on the display portion.
  • the antenna may be used for contactless power transmission.
  • the electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow, humidity, inclination, vibration, odor or infrared.
  • the electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying date or time, etc., a function of executing various software (programs), wireless communication A function, a function of reading a program or data recorded in a recording medium, or the like can be provided.
  • FIG. 12 shows an example of the electronic device.
  • FIG. 12A shows a mobile phone (smart phone) which is a type of information terminal.
  • the information terminal 5500 includes a housing 5510 and a display portion 5511.
  • a touch panel is provided in the display portion 5511 as an input interface, and a button is provided in the housing 5510.
  • the information terminal 5500 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • an application using artificial intelligence for example, an application that recognizes a conversation and displays the content of the conversation on the display unit 5511, recognizes characters, figures, and the like input by the user with respect to a touch panel included in the display unit 5511; An application displayed on the display portion 5511, an application for performing biometric authentication such as fingerprint or voiceprint, and the like can be given.
  • a desktop information terminal 5300 is illustrated in FIG.
  • the desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • applications using artificial intelligence include design support software, text correction software, and menu automatic generation software.
  • new artificial intelligence can be developed.
  • the smartphone and the desktop information terminal are illustrated in FIGS. 12A and 12B as the electronic device as an example, an information terminal other than the smartphone and the desktop information terminal may be applied. it can.
  • an information terminal other than a smart phone and a desktop information terminal for example, a PDA (Personal Digital Assistant), a notebook information terminal, a work station, etc. may be mentioned.
  • PDA Personal Digital Assistant
  • FIG. 12C shows an electric refrigerator-freezer 5800 which is an example of the electric appliance.
  • the electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803 and the like.
  • an electric refrigerator-freezer 5800 having artificial intelligence can be realized.
  • the electric refrigerator-freezer 5800 is automatically stored in the electric refrigerator-freezer 5800, which automatically generates a menu based on the food stored in the electric refrigerator-freezer 5800, the expiration date of the food, etc. It can have a function of automatically adjusting to the temperature according to the food.
  • the electric refrigerator-freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electronic oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Appliances, washing machines, dryers, audiovisual equipment etc. may be mentioned.
  • FIG. 12D shows a portable game console 5200 which is an example of the game console.
  • the portable game machine includes a housing 5201, a display portion 5202, a button 5203, and the like.
  • a low-power consumption portable game device 5200 can be realized. Further, since low power consumption can reduce heat generation from the circuit, it is possible to reduce the influence of heat generation on the circuit itself, peripheral circuits, and modules.
  • a portable game device 5200 having artificial intelligence can be realized.
  • expressions such as the progress of the game, the behavior and behavior of creatures appearing on the game, and the phenomena occurring on the game are determined by the program possessed by the game, but by applying artificial intelligence to the portable game machine 5200
  • the expression which is not limited to the program of the game becomes possible. For example, it is possible to express that the contents asked by the player, the progress of the game, the time, and the behavior of the person appearing on the game change.
  • FIG. 12D illustrates a portable game machine as an example of a game machine
  • a game machine to which a GPU or a chip of one embodiment of the present invention is applied is not limited thereto.
  • a game machine to which the GPU or chip of one embodiment of the present invention is applied for example, a home-use stationary game machine, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a sports facility Pitching machines for batting practice.
  • the GPU or chip of one embodiment of the present invention can be applied to an automobile that is a mobile body and the driver seat area of the automobile.
  • FIG. 12 (E1) shows a car 5700 which is an example of a moving body
  • FIG. 12 (E2) shows a periphery of a windshield in a room of the car.
  • FIG. 12E1 in addition to the display panel 5701 attached to the dashboard, the display panel 5702, and the display panel 5703, a display panel 5704 attached to a pillar is illustrated.
  • the display panel 5701 to the display panel 5703 can provide various information by displaying a speedometer, a tachometer, a travel distance, a fuel gauge, a gear state, settings of an air conditioner, and the like.
  • display items, layouts, and the like displayed on the display panel can be appropriately changed in accordance with the user's preference, and design can be enhanced.
  • the display panels 5701 to 5703 can also be used as lighting devices.
  • the display panel 5704 By projecting an image from an imaging device (not shown) provided in the automobile 5700 on the display panel 5704, it is possible to complement the view (dead angle) blocked by the pillar. That is, by displaying an image from an imaging device provided outside the automobile 5700, a blind spot can be compensated to enhance safety. In addition, by displaying an image that complements the invisible part, it is possible to check the safety more naturally and without discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used for an autonomous driving system of a car 5700. Moreover, the said chip
  • a mobile body is not limited to a motor vehicle.
  • a moving object a train, a monorail, a ship, a flying object (a helicopter, a drone, a plane, a rocket) and the like can also be mentioned, and the chip of one embodiment of the present invention is applied to these moving objects.
  • a system using artificial intelligence can be provided.
  • the GPU or chip of one embodiment of the present invention can be applied to a broadcast system.
  • FIG. 12F schematically shows data transmission in the broadcast system. Specifically, FIG. 12F shows a path until the radio wave (broadcast signal) transmitted from the broadcast station 5680 reaches the television receiver (TV) 5600 of each home.
  • the TV 5600 includes a receiver (not shown), and a broadcast signal received by the antenna 5650 is transmitted to the TV 5600 through the receiver.
  • the antenna 5650 is a UHF (Ultra High Frequency) antenna.
  • a BS ⁇ 110 ° CS antenna, a CS antenna, or the like can also be used.
  • the radio wave 5675A and the radio wave 5675B are broadcast signals for ground wave broadcasting, and the radio wave tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B.
  • Each household can view terrestrial TV broadcast on the TV 5600 by receiving the radio wave 5675 B by the antenna 5650.
  • the broadcast system is not limited to the terrestrial broadcast shown in FIG. 12F, and may be satellite broadcast using an artificial satellite, data broadcast by an optical line, or the like.
  • the above-described broadcast system may be a broadcast system using artificial intelligence by applying the chip of one embodiment of the present invention.
  • compression of the broadcast data is performed by the encoder, and when the antenna 5650 receives the broadcast data, the decoder of the receiving apparatus included in the TV 5600 Restoration is performed.
  • artificial intelligence for example, in motion compensation prediction which is one of compression methods of an encoder, it is possible to recognize a display pattern included in a display image.
  • intra-frame prediction using artificial intelligence can also be performed.
  • image interpolation processing such as up conversion can be performed in restoration of broadcast data by the decoder.
  • the above-described broadcast system using artificial intelligence is suitable for ultra high definition television (UHDTV: 4K, 8K) broadcast where the amount of broadcast data is increased.
  • the TV 5600 may be provided with a recording device having artificial intelligence.
  • a recording device having artificial intelligence it is possible to automatically record a program according to the user's preference by making the recording device learn the user's preference to the artificial intelligence.
  • the electronic device described in this embodiment the function of the electronic device, the application example of artificial intelligence, the effect thereof, and the like can be combined with the description of other electronic devices as appropriate.
  • a transistor (referred to as a sample A1) according to one embodiment of the present invention was manufactured, and a cross-sectional TEM image of the vicinity of a channel formation region of a metal oxide was obtained.
  • Samples A2 and A3 in which the fabrication method is different from Sample A1 were fabricated, and a cross-sectional TEM image in the vicinity of the channel formation region of metal oxide was obtained.
  • a silicon oxide film and a first aluminum oxide film were sequentially formed on a substrate.
  • a first tungsten film was formed over the first aluminum oxide film by sputtering. Thereafter, the first tungsten film was processed by a lithography method to form a conductor.
  • a first silicon oxynitride film was formed over the first aluminum oxide film and the conductor by a CVD method. Thereafter, the first silicon oxynitride film was polished by the first CMP treatment until the top surface of the conductor was reached.
  • a second aluminum oxide film is formed to a thickness of 5 nm by ALD on the first silicon oxynitride film and the conductor, and a CVD method is formed on the second aluminum oxide film.
  • a second silicon oxynitride film was formed to a thickness of 35 nm. After that, smoothing was performed on the second silicon oxynitride film.
  • an oxide film to be a first oxide and an oxide film to be a second oxide were successively formed.
  • an oxide film to be a first oxide an In—Ga—Zn oxide was formed to a thickness of 5 nm by a sputtering method.
  • an In—Ga—Zn oxide was formed to a thickness of 20 nm by a sputtering method.
  • the film was formed under the conditions of 15 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200.degree.
  • a first heat treatment was performed.
  • treatment was performed at a temperature of 400 ° C. for one hour in an atmosphere containing nitrogen, followed by treatment for one hour at a temperature of 400 ° C. in an atmosphere containing oxygen.
  • a tantalum nitride film was formed over the oxide film to be the second oxide. After that, the tantalum nitride film, the oxide film to be the second oxide, and the oxide film to be the first oxide were processed to form a second oxide and a first oxide.
  • a third aluminum oxide film and a third silicon oxynitride film were formed in order. After that, the top surface of the third silicon oxynitride film was planarized by a second CMP process.
  • the third silicon oxynitride film was processed to form an opening reaching the upper surface of the third aluminum oxide film in the third silicon oxynitride film. After that, the third aluminum oxide film and part of the tantalum nitride film in the openings were etched.
  • an In—Ga—Zn oxide was formed to a thickness of 5 nm by a sputtering method.
  • the film was formed under the conditions of 7 Pa and a substrate temperature of 130 ° C.
  • a fourth silicon oxynitride film is formed over the oxide film to be the third oxide by a CVD method, a titanium nitride film is formed over the fourth silicon oxynitride film, and the nitride is concerned.
  • a second tungsten film was formed on the titanium film.
  • a second tungsten film, the above titanium nitride film, a fourth silicon oxynitride film, and a third oxide are formed by the third CMP process until the top surface of the third silicon oxynitride film is reached.
  • the oxide film was polished to form a third oxide.
  • Sample A1 was produced by the above.
  • a silicon oxide film and a first aluminum oxide film were sequentially formed on a substrate.
  • a first silicon oxynitride film was formed over the first aluminum oxide film by a CVD method.
  • a first tungsten film was formed by sputtering. Thereafter, the first tungsten film was processed by lithography to form a first hard mask.
  • the first silicon oxynitride film was processed using the first hard mask to form an opening in the first silicon oxynitride film.
  • a first tantalum nitride film is formed by sputtering, and a first titanium nitride film is formed on the first tantalum nitride film by ALD, and the first titanium nitride film is formed on the first titanium nitride film.
  • the second tungsten film was formed by the CVD method.
  • the second tungsten film, the first titanium nitride film, and the first tantalum nitride film are polished until the upper surface of the first silicon oxynitride film is reached by the first CMP process, and the first The hard mask was removed.
  • a conductor is formed in the opening of the first silicon oxynitride film.
  • a second silicon oxynitride film is formed to a thickness of 10 nm on the first silicon oxynitride film and the conductor by CVD, and an ALD method is formed on the second silicon oxynitride film.
  • a hafnium oxide film was formed to a thickness of 20 nm, and a third silicon oxynitride film was formed to a thickness of 30 nm on the hafnium oxide film by a CVD method.
  • an oxide film to be a first oxide and an oxide film to be a second oxide were successively formed.
  • an oxide film to be a first oxide an In—Ga—Zn oxide was formed to a thickness of 5 nm by a sputtering method.
  • the oxide film to be the first oxide was formed under the same conditions as the sample A1.
  • an In—Ga—Zn oxide was formed to a thickness of 15 nm by a sputtering method.
  • the film was formed under the conditions of 5 sccm, a pressure of 0.7 Pa, and a substrate temperature of 130 ° C.
  • a first heat treatment was performed.
  • treatment was performed at a temperature of 400 ° C. for one hour in an atmosphere containing nitrogen, followed by treatment for one hour at a temperature of 400 ° C. in an atmosphere containing oxygen.
  • a second tantalum nitride film was formed over the oxide film to be the second oxide. After that, the second tantalum nitride film, the oxide film to be the second oxide, and the oxide film to be the first oxide were processed to form the first oxide and the second oxide.
  • an oxide film to be a third oxide an In—Ga—Zn oxide was formed to a thickness of 5 nm by a sputtering method.
  • the oxide film to be the third oxide was formed under the same conditions as the sample A1.
  • a fourth silicon oxynitride film was formed over the oxide film to be the third oxide by a CVD method.
  • the oxide film to be the third oxide was processed to form the third oxide.
  • Sample A2 was produced by the above.
  • sample A3 the preparation method of sample A3 is demonstrated. Note that the steps until the opening was formed in the first silicon oxynitride film and the conductor was formed in the opening were the same as the steps of the sample A2.
  • a second silicon oxynitride film is formed to a thickness of 5 nm on the first silicon oxynitride film and the conductor by CVD, and an ALD method is formed on the second silicon oxynitride film.
  • a hafnium oxide film was formed to a thickness of 10 nm
  • a third silicon oxynitride film was formed to a thickness of 30 nm on the hafnium oxide film by a CVD method.
  • an oxide film to be a first oxide and an oxide film to be a second oxide were successively formed.
  • An In—Ga—Zn oxide film is formed with a thickness of 5 nm as an oxide film to be a first oxide by a sputtering method, and an In—Ga—Zn oxide is formed as an oxide film to be a second oxide. To a film thickness of 15 nm. Note that the oxide film to be the first oxide and the oxide film to be the second oxide were formed under the same conditions as the sample A1.
  • a first heat treatment was performed.
  • treatment was performed at a temperature of 400 ° C. for one hour in an atmosphere containing nitrogen, followed by treatment for one hour at a temperature of 400 ° C. in an atmosphere containing oxygen.
  • a second tantalum nitride film was formed over the oxide film to be the second oxide. After that, the second tantalum nitride film, the oxide film to be the second oxide, and the oxide film to be the first oxide were processed to form the first oxide and the second oxide.
  • an oxide film to be a third oxide an In—Ga—Zn oxide was formed to a thickness of 5 nm by a sputtering method.
  • the oxide film to be the third oxide was formed under the same conditions as the sample A1.
  • a fourth silicon oxynitride film was formed over the oxide film to be the third oxide by a CVD method.
  • the third oxide was formed by processing the oxide film to be the third oxide.
  • Sample A3 was produced by the above.
  • FIG. 13 shows a high resolution TEM image of a cross section of the oxide observed from a direction substantially parallel to the sample surface.
  • High resolution TEM images were observed using a spherical aberration corrector function.
  • the high resolution TEM image was taken by irradiating an electron beam with an acceleration voltage of 200 kV using an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL.
  • FIG. 13 (A) is a TEM image of the cross section of the sample A1
  • FIG. 13 (B) is a TEM image of the cross section of the sample A2
  • FIG. 13 (C) is a TEM image of the cross section of the sample A3.
  • the bright regions observed at the top and bottom of FIG. 13 are silicon oxynitride films, and the dark regions observed near the center of FIG. 13 are oxides. In the dark region, the first oxide is located below, the second oxide is located at the center, and the third oxide is located above.
  • the aligned regions of the lattice arrangement were observed over a wide area from the second oxide to the third oxide.
  • This embodiment can be implemented by appropriately combining at least a part of the other embodiments described in the present specification.

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US16/760,050 US11282964B2 (en) 2017-12-07 2018-11-26 Semiconductor device
KR1020247002470A KR20240013863A (ko) 2017-12-07 2018-11-26 반도체 장치, 및 반도체 장치의 제작 방법
US17/697,152 US11784259B2 (en) 2017-12-07 2022-03-17 Oxide semiconductor device
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