WO2019087809A1 - Convertisseur analogique/numérique - Google Patents

Convertisseur analogique/numérique Download PDF

Info

Publication number
WO2019087809A1
WO2019087809A1 PCT/JP2018/038902 JP2018038902W WO2019087809A1 WO 2019087809 A1 WO2019087809 A1 WO 2019087809A1 JP 2018038902 W JP2018038902 W JP 2018038902W WO 2019087809 A1 WO2019087809 A1 WO 2019087809A1
Authority
WO
WIPO (PCT)
Prior art keywords
filter
output
data
quantizer
converter
Prior art date
Application number
PCT/JP2018/038902
Other languages
English (en)
Japanese (ja)
Inventor
恭英 高▲瀬▼
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2019087809A1 publication Critical patent/WO2019087809A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/02—Delta modulation, i.e. one-bit differential modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/04—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation

Definitions

  • the present invention relates to an A / D converter that quantizes a difference between an analog input signal and a predicted value output from a prediction filter with a quantizer to convert the analog input signal into a digital signal.
  • the A / D converter comprises a resistor, a continuous time filter, a summing circuit, a quantizer, a continuous time DAC, a delay element, a discrete time DAC, and a switch.
  • a continuous time filter receives the analog input signal and the feedback signal from the switch.
  • the feedback signal is a signal from one feedback path including a discrete time DAC and a delay element used when the clock signal has a relatively large jitter due to switch switching, and a high quality clock signal with a relatively small amount of jitter.
  • the signal from the other feedback path, including the continuous time DAC which requires
  • the continuous time filter is implemented as an Nth-order integrator and provides multiple feed forward path outputs to multiple inputs of the summing circuit.
  • Each of the plurality of inputs of the summing circuit includes a gain element.
  • the quantizer has an input terminal connected to the output terminal of the summing circuit and a plurality of output terminals, and generates a quantized discrete multi-bit output based on the input received from the summing circuit.
  • the decimation filter has a plurality of input terminals connected to a plurality of output terminals of the quantizer and a plurality of output terminals for providing a plurality of digital output bits. This decimation filter is coupled to the multi-bit output of the quantizer and is used to lower the data frequency, remove additional noise, and increase the resolution of the output.
  • the above-described conventional A / D converter has a multi-bit quantizer, as described above, it is necessary to process multi-bit data at a high oversampling frequency in the decimation filter. Therefore, the above-described conventional A / D converter has a problem that power consumption is increased.
  • An adder for calculating a difference between an analog input signal and a predicted value, a quantizer for quantizing a difference output from the adder, and a prediction filter for generating a predicted value from a signal output from the quantizer.
  • An A / D converter comprising: a decimation filter for limiting the frequency band of an A / D conversion output which is converted into a digital signal and output an analog input signal input to an adder and outputting the digital signal;
  • a decimation filter is connected to the output of the quantizer,
  • the present invention is characterized by comprising a compensation filter that compensates for frequency characteristics of output data at the output side of the decimation filter.
  • the short word length and high frequency data output from the quantizer are output to the decimation filter, and the decimation filter first performs frequency band limitation for the short word length and high frequency data and Data frequency reduction processing is performed. Then, at the output side of the decimation filter, the frequency characteristic of the output data is compensated by the compensation filter at the low-speed data frequency reduced by the decimation filter. For this reason, the power consumption of the A / D converter is reduced in the decimation filter as compared to the conventional processing of multi-bit data at a high oversampling frequency.
  • the prediction filter uses the predicted value of the digital value before analog conversion to be fed back to the adder by the prediction filter as the A / D converted output of the analog input signal inputted to the adder.
  • a decimation filter is connected to the output of the prediction filter to limit the frequency band of the A / D conversion output and to lower the data frequency. For this reason, in the decimation filter, data processing is performed on data having a word length longer than that of data output from the quantizer at the same high data frequency as that of the quantizer, and power consumption increases.
  • the decimation filter is connected to the output of the quantizer, and the decimation filter performs frequency band limitation and data frequency reduction on data having a word length shorter than that of the prediction filter. Then, at the output side of the decimation filter, the frequency characteristic of the output data is compensated by the compensation filter at the low-speed data frequency reduced by the decimation filter. Therefore, the data processed by the decimation filter is quantized with a word length shorter than that of the data output from the prediction filter, as compared with the case where the prediction value output from the prediction filter is subjected to the decimation filter as an A / D conversion output. Power consumption of the A / D converter.
  • the decimation filter is A first decimation filter connected to the output of the quantizer to reduce the data frequency to an intermediate data frequency lower than the data frequency of the quantizer and higher than the data frequency of the A / D conversion output; Characterized in that it is divided into a second decimation filter connected to the output of the compensation filter and further reducing the data frequency from the intermediate data frequency pulled down by the first decimation filter to the data frequency of the A / D conversion output. Do.
  • the compensation filter data processing is performed at an intermediate data frequency higher than the data frequency of the A / D conversion output. Therefore, the compensation of the frequency characteristic of the output data performed by the compensation filter is performed more accurately than in the case of the data frequency of the A / D conversion output. Therefore, the A / D conversion output obtained through the second decimation filter becomes an output that is more faithful to the analog input signal.
  • the present invention is characterized in that the decimation filter or the first decimation filter is constituted by a second-order or higher-order sinc filter.
  • the decimation filter or the first decimation filter configured by the sinc filter can keep aliasing noise at its output to a sufficient SNR (signal-to-noise ratio) even at the compensation filter output. , Can be suppressed. For this reason, the A / D conversion output becomes an output that is more faithful to the analog input signal.
  • the present invention is characterized in that an integrator is provided between the adder and the quantizer.
  • the quantization noise is noise-shaped such that the spectrum distribution becomes high in the high frequency region by the integrator provided between the adder and the quantizer. Therefore, the quantization noise is efficiently removed by the band limiting function of the decimation filter, the SNR is improved, and the A / D conversion output becomes an output faithful to the analog input signal.
  • the present invention is characterized in that the compensation filter is configured by an integrator.
  • the compensation filter can be formed with a simple circuit configuration, and the circuit scale of the A / D converter can be reduced. Therefore, a compact and low power consumption A / D converter can be provided.
  • decimation filter data processing of a signal with a high data frequency is performed with a short word length, and in the compensation filter, data with long word length data with a low data frequency reduced by the decimation filter The processing reduces the power consumed by the A / D converter.
  • FIG. 1 is a circuit block diagram showing a schematic configuration of an A / D converter according to a first embodiment of the present invention.
  • FIG. 6 is a circuit block diagram showing a schematic configuration of an A / D converter that uses an output of a prediction filter as an A / D conversion output.
  • FIG. 7 is a circuit block diagram showing a schematic configuration of an A / D converter according to a second embodiment of the present invention.
  • (A) is a circuit block diagram which shows schematic structure of the A / D converter by 3rd Embodiment of this invention
  • (b) is the A / D converter by 4th Embodiment of this invention.
  • FIG. 18A is a circuit block diagram showing a schematic configuration of an A / D converter according to an eighth embodiment of the present invention.
  • FIG. 1 is a circuit block diagram showing a schematic configuration of an A / D converter 1A according to a first embodiment of the present invention.
  • the A / D converter 1A is configured to include an adder 2, a quantizer 3, a prediction filter 4, a decimation filter 5 and a compensation filter 6.
  • the adder 2 calculates the difference between the analog input signal U and the predicted value P.
  • the quantizer 3 quantizes the difference output from the adder 2 each time the sampling clock clk of the data frequency fs is input, and converts the analog input signal U into a word data length WL0, for example, a digital data string of 1 bit. Do.
  • the prediction filter 4 operates based on the sampling clock clk having the same data frequency fs as the quantizer 3, and a predicted value of the word length WL1 (WL0 ⁇ WL1) from the digital data string of the word length WL0 output from the quantizer 3 Generate P.
  • the decimation filter 5 has a low-pass band-limiting filter function and a decimation function, and is connected to the output of the quantizer 3.
  • the band limiting filter function attenuates the high frequency noise included in the output of the quantizer 3 and converts the analog input signal U input to the adder 2 into a digital signal and outputs the digital signal.
  • the frequency band is limited. Further, the data frequency is lowered from the frequency fs to the frequency fo (fs> fo) by the thinning-out function, and the output of the quantizer 3 is resampled to low-speed, multi-bit data of word length WL2 (WL0 ⁇ WL2). It is converted.
  • the compensation filter 6 connected to the output of the decimation filter 5 integrates the output of the decimation filter 5 to compensate the frequency characteristic of the output data. Data processing in the compensation filter 6 is performed at the same data frequency fo as the decimation filter 5.
  • the decimation filter 5 data having a high frequency fs and a short word length WL0 output from the quantizer 3 is output to the decimation filter 5, and the decimation filter 5 initially has a short word length.
  • Frequency band limitation and data frequency reduction processing are performed on data having a high frequency fs at WL0.
  • the integration filter is performed by the compensation filter 6 at the low-speed data frequency fo lowered by the decimation filter 5, and the frequency characteristic of the output data is compensated. For this reason, the power consumption of the A / D converter 1A is reduced in the decimation filter of the conventional A / D converter disclosed in Patent Document 1 as compared with the case of processing multi-bit data at a high oversampling frequency. Be done.
  • the analog input to be input to the adder 22 is the predicted value P of the digital value before being analog converted and fed back to the adder 22 by the prediction filter 24. It is also conceivable to use an A / D conversion output Dout of the signal U.
  • the A / D converter 21 is configured to include an adder 22, a quantizer 23, a prediction filter 24, and a D / A converter 26.
  • the adder 22 calculates the difference between the analog input signal U and the predicted value P.
  • the quantizer 23 quantizes the difference output from the adder 22 each time the sampling clock clk is input, and converts the analog input signal U into a digital signal D.
  • the prediction filter 24 generates a prediction value P from the digital signal D output from the quantizer 23, and further delays the prediction value P by the delay unit 25 and outputs it.
  • the prediction filter 24 is composed of a second delay unit 27, a multiplier 28, a second adder 29, an attenuator 30, and a series circuit of an integrator 31, an incomplete differentiator 32, and a delay unit 25.
  • the D / A converter 26 converts the predicted value P from a digital signal to an analog signal and outputs the analog value to the adder 22.
  • the predicted value P before being converted into an analog signal by the D / A converter 26 is taken as the A / D conversion output Dout of the analog input signal U input to the adder 22. .
  • a decimation filter is connected to the output of the prediction filter 24 to limit the frequency band of the A / D conversion output Dout and to lower the data frequency. Since the prediction filter 24 is configured to include an integral element, the word length of data to be processed becomes long. Therefore, in the decimation filter, data processing is performed on data having a word length longer than the data of the word length WL0 output from the quantizer 23 at the same high data frequency fs as the quantizer 23. Power consumption increases.
  • the decimation filter 5 is connected to the output of the quantizer 3 by the A / D converter 1A according to the present embodiment, and the output of the quantizer 3 is converted to the A / D conversion output Dout.
  • the decimation filter 5 performs frequency band limitation and data frequency reduction on data having a word length WL0 shorter than the prediction filter 4 and the prediction filter 4. Then, at the output side of the decimation filter 5, the integration filter is performed by the compensation filter 6 at the low-speed data frequency fo lowered by the decimation filter 5, the frequency characteristic of the prediction filter 4 is compensated, and the frequency characteristic of the output data is Be compensated.
  • the data processed by the decimation filter 5 compared to the case where the prediction value P output from the prediction filter 24 is subjected to the decimation filter as the A / D conversion output Dout as in the A / D converter 21 shown in FIG. Is data output from the quantizer 3 having a word length WL0 shorter than the data of the word length WL1 output from the prediction filter 4, and the power consumption of the A / D converter 1A is reduced.
  • the decimation filter 5 data processing of the signal of high data frequency fs is performed with a short word length WL0, and in the compensation filter 6, it is reduced by the decimation filter 5.
  • the power consumed by the A / D converter 1A is reduced.
  • FIG. 3 is a circuit block diagram showing a schematic configuration of an A / D converter 1B according to a second embodiment of the present invention.
  • the same reference numerals as in FIG. 1 denote the same parts in FIG. 3, and a description thereof will be omitted.
  • the first decimation filter 5 a is connected to the output of the quantizer 3, and the second decimation is connected to the output of the compensation filter 6.
  • the point divided into the filter 5b is different from the A / D converter 1A according to the first embodiment.
  • the configuration other than this point is the same as that of the A / D converter 1A according to the first embodiment.
  • the first decimation filter 5a lowers the data frequency to an intermediate data frequency fd (fs> fd> fo) lower than the data frequency fs of the quantizer 3 and higher than the data frequency fo of the A / D conversion output Dout.
  • the compensation filter 6 performs integration processing on the data of the word length WL2 lowered to the intermediate data frequency fd to perform data processing to compensate the frequency characteristic of the output data, and the word length WL3 (WL2 ⁇ WL3). Output as data.
  • the second decimation filter 5b performs decimation processing on the data of word length WL3 input from the compensation filter 6, and the data of the A / D conversion output Dout from the intermediate data frequency fd reduced by the first decimation filter 5a.
  • the data frequency is further lowered to the frequency fo, and the data is output as data of the word length WLo (WL3 ⁇ WLo).
  • the compensation filter 6 data processing is performed at an intermediate data frequency fd higher than the data frequency fo of the A / D conversion output Dout. Therefore, the compensation of the frequency characteristic of the output data performed by the compensation filter 6 is performed more accurately than in the case of the data frequency fo with a low A / D conversion output Dout. Therefore, the A / D conversion output Dout obtained through the second decimation filter 5b becomes an output that is more faithful to the analog input signal U.
  • FIG. 4 (a) is an A / D converter 1C according to the third embodiment of the present invention
  • FIG. 4 (b) is a circuit block schematically showing the configuration of an A / D converter 1D according to the fourth embodiment.
  • FIG. 4 the same parts as in FIG. 1 and FIG. 3 are assigned the same reference numerals and explanation thereof is omitted.
  • the A / D converter 1C according to the third embodiment is characterized in that the decimation filter 5 in the A / D converter 1A according to the first embodiment is constituted by a second or higher-order sinc M filter (M ⁇ 2) 5c. Is different from the A / D converter 1A according to the first embodiment.
  • the configuration other than this point is similar to that of the A / D converter 1A according to the first embodiment.
  • the first decimation filter 5a in the A / D converter 1B according to the second embodiment is a second-order or higher sinc M filter (M ⁇ 2) 5d.
  • M ⁇ 2 sinc M filter
  • the sinc M filter 5c and the first decimation filter 5a constituting the decimation filter 5 can be used.
  • the sinc M filters 5d that are configured can suppress aliasing noise at their output to such an extent that a sufficient SNR (signal-to-noise ratio) can be maintained even at the output of the compensation filter 6. Therefore, each A / D conversion output Dout in the A / D converter 1C according to the third embodiment and the A / D converter 1D according to the fourth embodiment becomes an output faithful to the analog input signal U. .
  • FIG. 5 (a) is an A / D converter 1E according to a fifth embodiment of the present invention
  • FIG. 5 (b) is an A / D converter 1F according to the sixth embodiment of the present invention
  • FIG. 5D is a circuit block diagram showing a schematic configuration of an A / D converter 1H according to an eighth embodiment of the present invention.
  • the same reference numerals as in FIGS. 1, 3 and 4 denote the same parts in FIG. 5, and a description thereof will be omitted.
  • Each of the A / D converters 1E, 1F, 1G and 1H according to the fifth, sixth, seventh and eighth embodiments includes an integrator 7 between the adder 2 and the quantizer 3; This differs from the A / D converters 1A, 1B, 1C and 1D according to the first, second, third and fourth embodiments.
  • the configuration other than this point is the same as that of each of the A / D converters 1A, 1B, 1C and 1D according to the first, second, third and fourth embodiments.
  • the quantization noise is noise shaped in such a way that its spectral distribution becomes high in the high frequency domain. Therefore, the quantization noise is efficiently removed by the band limiting functions of the decimation filter 5, the first and second decimation filters 5a and 5b, and the sinc M filters 5c and 5d, and the SNR is improved, and the A / D is improved.
  • the converted output Dout further becomes an output faithful to the analog input signal U.
  • the A / D converters 1A, 1B, 1C, 1D, 1E, 1F, 1G according to the first, second, third, fourth, fifth, sixth, seventh and eighth embodiments described above.
  • the compensation filter 6 may be configured by an integrator (1 / (1-z.sup.- 1 )). According to this configuration, compensation filter 6 can be formed with a simple circuit configuration, and the circuit scale of A / D converters 1A, 1B, 1C, 1D, 1E, 1F, 1G and 1H can be reduced. . For this reason, it is possible to provide compact and low power consumption A / D converters 1A, 1B, 1C, 1D, 1E, 1F, 1G and 1H.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

La présente invention a pour objet la réduction de la consommation d'énergie d'un convertisseur A/N comprenant un additionneur, un quantificateur, un filtre de prédiction et un filtre de décimation. Un convertisseur A/N (1A) est pourvu d'un additionneur (2), d'un quantificateur (3), d'un filtre de prédiction (4), d'un filtre de décimation (5) et d'un filtre de compensation (6). L'additionneur (2) calcule la différence entre un signal d'entrée analogique U et une valeur de prédiction P. Le quantificateur (3) quantifie ladite différence et convertit le signal d'entrée analogique U en une chaîne de données numériques d'une longueur de mot WL0. Le filtre de prédiction (4) génère la valeur de prédiction P d'une longueur de mot WL1 à partir de ladite chaîne de données numériques. Le filtre de décimation (5) atténue le bruit haute fréquence en provenance d'une sortie du quantificateur (3), abaisse une fréquence de données de fs à fo, et convertit la sortie du quantificateur (3) en données multi-bit à une faible vitesse d'une longueur de mot WL2. Le filtre de compensation (6) compense les caractéristiques de fréquence des données de sortie et délivre des données de la longueur de mot WL0 avec la fréquence de données fo.
PCT/JP2018/038902 2017-10-31 2018-10-18 Convertisseur analogique/numérique WO2019087809A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-210870 2017-10-31
JP2017210870 2017-10-31

Publications (1)

Publication Number Publication Date
WO2019087809A1 true WO2019087809A1 (fr) 2019-05-09

Family

ID=66331710

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/038902 WO2019087809A1 (fr) 2017-10-31 2018-10-18 Convertisseur analogique/numérique

Country Status (1)

Country Link
WO (1) WO2019087809A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10509544A (ja) * 1994-11-02 1998-09-14 アドバンスト・マイクロ・ディバイシス・インコーポレーテッド モノリシックｐｃオーディオ回路
JP2013042488A (ja) * 2011-08-15 2013-02-28 Freescale Semiconductor Inc 構成変更可能な連続時間シグマデルタアナログ−デジタル変換器
WO2016021382A1 (fr) * 2014-08-04 2016-02-11 アズビル株式会社 Filtre numérique
WO2017179508A1 (fr) * 2016-04-15 2017-10-19 株式会社村田製作所 Convertisseur a/n et dispositif capteur équipé dudit convertisseur

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10509544A (ja) * 1994-11-02 1998-09-14 アドバンスト・マイクロ・ディバイシス・インコーポレーテッド モノリシックｐｃオーディオ回路
JP2013042488A (ja) * 2011-08-15 2013-02-28 Freescale Semiconductor Inc 構成変更可能な連続時間シグマデルタアナログ−デジタル変換器
WO2016021382A1 (fr) * 2014-08-04 2016-02-11 アズビル株式会社 Filtre numérique
WO2017179508A1 (fr) * 2016-04-15 2017-10-19 株式会社村田製作所 Convertisseur a/n et dispositif capteur équipé dudit convertisseur

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
FELTON, CHRISTOPHER L. ET AL.: "A Comparison of Efficient First Stage Decimation Filters for Continuous Time Delta Sigma Modulators", 2017 51ST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS, AND COMPUTERS, 29 October 2017 (2017-10-29), pages 473 - 477, XP033346082, DOI: doi:10.1109/ACSSC.2017.8335384 *

Similar Documents

Publication Publication Date Title
JP4443591B2 (ja) 過負荷補償のフィードバックステアリングを用いたノイズシェーピング回路および方法ならびにそれを使用するシステム
US5682161A (en) High-order delta sigma modulator
US7557744B2 (en) PWM driver and class D amplifier using same
US9007247B2 (en) Multi-bit sigma-delta modulator with reduced number of bits in feedback path
US6384761B1 (en) Second and higher order dynamic element matching in multibit digital to analog and analog to digital data converters
US20090309774A1 (en) Delta-sigma modulator
US8223051B2 (en) Multi-bit sigma-delta modulator with reduced number of bits in feedback path
JP4331188B2 (ja) デジタル／アナログ変換器および信号のデジタル／アナログ変換方法
JP3830924B2 (ja) 縦続型デルタシグマ変調器
US7453382B2 (en) Method and apparatus for A/D conversion
JP2010171484A (ja) 半導体集積回路装置
US7436336B2 (en) Analog digital converter (ADC) having improved stability and signal to noise ratio (SNR)
JP4823244B2 (ja) 変換器
JP3785361B2 (ja) Δςモジュレータ、ａ／ｄコンバータおよびｄ／ａコンバータ
US6741197B1 (en) Digital-to-analog converter (DAC) output stage
JP4141865B2 (ja) モジュレータ
WO2019087809A1 (fr) Convertisseur analogique/numérique
US10659074B2 (en) Delta-sigma modulator, electronic device, and method for controlling delta-sigma modulator
JP4058175B2 (ja) 音声信号処理装置
KR101559456B1 (ko) 지연된 피드―포워드 경로를 갖는 저전력·저면적 3차 시그마―델타 변조기
KR20010101039A (ko) 디지털 신호의 양자화 및 양자화 잡음 필터회로
JP3799146B2 (ja) １ビット信号処理装置
US11799494B2 (en) Delta-sigma modulator, delta-sigma digital-analog converter, and method for operating a delta-sigma modulator and a delta-sigma digital-analog converter
JP3558911B2 (ja) Ｄ／ａ変換装置
US11121718B1 (en) Multi-stage sigma-delta analog-to-digital converter with dither

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18873702

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18873702

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP