WO2019085577A1 - Dispositif de transistor bipolaire à grille isolée et son procédé de fabrication, et équipement électronique de puissance - Google Patents

Dispositif de transistor bipolaire à grille isolée et son procédé de fabrication, et équipement électronique de puissance Download PDF

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Publication number
WO2019085577A1
WO2019085577A1 PCT/CN2018/099611 CN2018099611W WO2019085577A1 WO 2019085577 A1 WO2019085577 A1 WO 2019085577A1 CN 2018099611 W CN2018099611 W CN 2018099611W WO 2019085577 A1 WO2019085577 A1 WO 2019085577A1
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Prior art keywords
gate
trench
type
cells
planar
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PCT/CN2018/099611
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English (en)
Chinese (zh)
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史波
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格力电器（武汉）有限公司
珠海格力电器股份有限公司
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Publication of WO2019085577A1 publication Critical patent/WO2019085577A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate

Definitions

  • the present invention relates to the field of power electronics, and in particular to an insulated gate bipolar transistor device, a method of fabricating the same, and a power electronic device.
  • IGBTs Insulated Gate Bipolar Transistors
  • BJT Bipolar Junction Transistor
  • MOS Metal-Oxide-Semiconductor Field-Effect Transistor
  • An object of the embodiments of the present invention is to provide an IGBT device, a manufacturing method thereof, and a power electronic device to improve the overall performance of the IGBT device and improve the applicability of the IGBT device.
  • An embodiment of the present invention provides an IGBT device including a gate structure.
  • the gate structure includes a plurality of planar gate cells and a plurality of trench gate cells, wherein: the plurality of planar gate cells are located on the same layer, and the plurality of trenches
  • the trench gate unit is located at one side of the plurality of planar gate units and intersects a layer where the plurality of planar gate units are located, and each of the planar gate units is connected to at least two adjacent trench gate units.
  • the plurality of trench gate cells are orthogonal to a plane where the plurality of planar gate cells are located.
  • the plurality of trench gate units are arranged in an array, and the planar gate unit connects four adjacent trench gate units adjacent to each other in a row.
  • planar gate unit is a polysilicon planar gate unit
  • trench gate unit is a polysilicon trench gate unit
  • the overlapping width of the planar gate unit and the trench gate unit is 0.8-1.2 ⁇ m.
  • the IGBT device specifically includes: an N-type semiconductor substrate, a P-type well, an N-type emitter, and a P-type well disposed on one side of the N-type semiconductor substrate and in a direction away from the N-type semiconductor substrate a dielectric layer, the gate structure, the second dielectric layer, the first metal layer, and the passivation protective layer, and sequentially disposed on the other side of the N-type semiconductor substrate and in a direction away from the N-type semiconductor substrate N-type field stop layer, P-type collector region and second metal layer; wherein:
  • the overall structure of the N-type semiconductor substrate, the P-type well and the N-type emitter has a trench opening away from the N-type field stop layer, and the trench gate unit is located in the trench;
  • the P-type well has a P-type contact region on a side away from the N-type semiconductor substrate, and the entire structure of the second dielectric layer, the first dielectric layer and the N-type emitter has a first-pass to the P-type contact region a contact hole; the second dielectric layer has a second contact hole leading to the gate structure;
  • the first metal layer includes an emitter metal connected to the P-type contact region through the first contact hole, and a gate connection metal connected to the gate structure through the second contact hole.
  • the trench has a depth of 4 to 6 ⁇ m.
  • the first contact hole is located between two adjacent planar gate units adjacent to each other in the row direction and between the two planar gate units adjacent to each other in the column direction.
  • the gate connection metal includes a frame-shaped lead portion and a lead portion connected to the frame-shaped lead portion, wherein the frame-shaped lead portion is disposed around the gate structure and passes through the second contact hole and the gate Structural connection.
  • the IGBT device provided by the embodiment of the invention has a gate structure of a composite structure of a planar gate unit and a trench gate unit.
  • the gate resistance can be effectively reduced; the IGBT device with respect to the trench gate structure, the gate input capacitance Smaller, thus improving the switching frequency of the device; compared with the trench gate structure of the IGBT device, the saturation voltage drop is increased, thereby reducing the short-circuit current and improving the short-circuit characteristics; and the IGBT device relative to the planar gate structure is balanced. Parameters of saturation voltage drop and short circuit characteristics, and the area of the chip is also reduced.
  • the specific dimensions of the planar gate unit and the trench gate unit can be flexibly adjusted according to the parameter requirements of the device. Therefore, compared with the prior art, the performance of the IGBT device of the embodiment of the present invention is comprehensively improved, and the applicability is stronger.
  • the embodiment of the invention further provides a power electronic device, comprising the IGBT device described above according to any of the foregoing technical solutions. Since the IGBT device has the above-described advantageous effects, the electrical performance of the power electronic device is also better.
  • the embodiment of the invention further provides a method for fabricating an IGBT device, comprising the following steps:
  • the gate structure includes a plurality of planar gate cells and a plurality of trench gate cells, wherein: the plurality of planar gate cells are located on a same level, and the plurality of trench gate cells are located in the plurality of planar gate cells One side intersects with a layer on which the plurality of planar gate units are located, and each of the planar gate units is connected to at least two adjacent trench gate units.
  • the forming the gate structure specifically includes:
  • the foregoing manufacturing method further includes:
  • the first contact hole is located between two adjacent planar gate cells adjacent in the row direction and located between two adjacent planar gate cells adjacent in the column direction;
  • first metal layer Forming a first metal layer on a side of the second dielectric layer away from the gate structure, the first metal layer including an emitter metal connected to the P-type contact region through the first contact hole, and through the second contact a gate connection metal connected to the gate structure;
  • a passivation protective layer is formed on a side of the first metal layer away from the second dielectric layer.
  • the foregoing manufacturing method further includes:
  • an N-type field stop layer, a P-type collector region, and a second metal layer are sequentially formed on a side of the N-type semiconductor substrate away from the gate structure.
  • the IGBT device fabricated by the method of the above embodiment has comprehensively improved device performance and is more applicable.
  • FIG. 1 is a top plan view of a planar gate structure of a conventional IGBT device
  • FIG. 2 is a top plan view of a trench gate structure of a conventional IGBT device
  • FIG. 3 is a top view of a resistance connection of a conventional trench gate structure
  • FIG. 4 is a perspective view showing a gate structure of an IGBT device according to an embodiment of the present invention.
  • FIG. 5 is a top plan view of a gate structure of an IGBT device according to an embodiment of the present invention.
  • FIG. 6 is a schematic longitudinal cross-sectional view of an IGBT device according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural view of a cell of an IGBT device according to an embodiment of the present invention.
  • FIG. 8 is a top view showing a resistance connection of a gate structure of an IGBT device according to an embodiment of the present invention.
  • Figure 9 is a cross-sectional view taken along line A-A of Figure 5;
  • Figure 10 is a cross-sectional view taken along line B-B of Figure 5;
  • Figure 11 is a cross-sectional view taken along line C-C of Figure 5;
  • 13 is a schematic view showing the comparison of the input capacitance of the gate structure of the present embodiment and the existing planar gate structure and trench gate structure;
  • FIG. 14 is a schematic view showing a comparison of saturation voltage drop between a gate structure and a conventional planar gate structure and a trench gate structure according to the embodiment
  • FIG. 15 is a flow chart of a method for fabricating an IGBT device according to an embodiment of the present invention.
  • 16a to 16i are schematic diagrams showing the process of fabricating an IGBT device according to an embodiment of the present invention.
  • Gate structure 11, planar gate unit; 12, trench gate unit; 2. N-type semiconductor substrate; 3. P-type well; 4. N-type emitter; 5. First dielectric layer; Two dielectric layers; 7, a first metal layer; 8, a passivation protective layer; 9, an N-type field stop layer; 10, a P-type collector region; 13, a second metal layer; 14, a trench; Contact region; 16, first contact hole; 71, emitter metal; 72, gate connection metal; 721, frame lead portion; 722, lead portion; 51, first oxide film; , a second oxide film.
  • the gate structure of the IGBT device generally adopts a planar gate structure as shown in FIG. 1 or a trench gate structure as shown in FIG. 2, wherein the planar gate structure includes a plurality of planar gate units 011, and a trench gate
  • the structure includes a plurality of trench gate cells 012 that are located between adjacent planar gate cells 011 or trench gate cells 012.
  • the IGBT device with planar gate structure has the advantages of low input capacitance, good short-circuit characteristics, simple process technology, etc., but also has defects such as large conduction voltage drop, large cell size and low integration degree; IGBT with respect to planar gate structure
  • the IGBT device of the trench gate structure has the advantages of small on-voltage drop, small cell size and high integration, but also has defects such as large input capacitance, poor short-circuit characteristics and complicated process technology. Therefore, whether the planar gate structure or the trench gate structure is used, the parameter characteristics of the IGBT device cannot be well balanced.
  • an embodiment of the present invention provides an IGBT device, a manufacturing method thereof, and a power electronic device.
  • the present invention will be further described in detail below.
  • an IGBT device includes a gate structure 1.
  • the gate structure 1 includes a plurality of planar gate cells 11 and a plurality of trench gate cells 12, wherein:
  • the planar gate unit 11 is located at the same level, and the plurality of trench gate units 12 are located at one side of the plurality of planar gate units 11 and intersect with a layer where the plurality of planar gate units 11 are located, and each of the planar gate units 11 and at least Two adjacent trench gate cells 12 are connected.
  • the plurality of trench gate units 12 are orthogonal to the plane in which the plurality of planar gate units 11 are located.
  • the plurality of trench gate cells 12 are arranged in an array, and the planar gate cells 11 connect four adjacent trench gate cells 12 adjacent to each other.
  • the plane where the trench gate unit and the plurality of planar gate units are located may also be at an angle of less than 90 degrees; in addition, the planar gate unit and the trench gate unit may also be used.
  • Other arrangement connections for example, a planar gate unit connecting adjacent three trench gate units, etc., are not specifically limited herein.
  • the planar gate cell 11 is a polysilicon planar gate cell and the trench gate cell 12 is a polysilicon trench gate cell.
  • the IGBT device specifically includes an N-type semiconductor substrate 2 which is sequentially disposed on one side of the N-type semiconductor substrate 2 and in a direction away from the N-type semiconductor substrate 2.
  • N-type semiconductor substrate 2, P-type The overall structure of the well 3 and the N-type emitter 4 has a trench 14 opening away from the N-type field stop layer 9, the trench gate unit 12 is located in the trench 14; and the P-well 3 is away from the N-type semiconductor substrate 2
  • the side has a P-type contact region 15, the overall structure of the second dielectric layer 6, the first dielectric layer 5 and the N-type emitter 4 has a first contact hole 16 leading to the P-type contact region 15, and the second dielectric layer 6 has a pass a second contact hole (not shown) to the gate structure 1;
  • the first metal layer 7 includes an emitter metal 71 connected to
  • the gate connection metal 72 specifically includes a frame-shaped lead portion 721 and a lead portion 722 connected to the frame-shaped lead portion 721, wherein the frame-shaped lead portion The 721 is disposed around the gate structure 1 and connected to the gate structure 1 through the second contact hole.
  • the first contact hole 16 is located between the two planar gate cells 11 adjacent in the row direction and between the two planar gate cells 11 adjacent in the column direction.
  • FIG. 7 shows a cell structure in the structure shown in FIG. 5. As can be seen from FIG. 5 and FIG. 7, the planar gate unit 11, the trench gate unit 12, and the first contact hole 16 are arranged in a compact manner. Smaller size and higher integration.
  • FIG 12 shows an equivalent circuit diagram of the IGBT device.
  • the size of the capacitor Cies is proportional to the magnitude of the gate charge Qg, and the device operating frequency f is inversely proportional to the gate resistance Rg and the input capacitance Cies.
  • the trench gate unit 12 and the planar gate unit 11 are integrally connected in a crisscross network, which is equivalent to paralleling more resistors, thereby being effective.
  • the gate resistance Rg is lowered.
  • the gate connection metal 072 is electrically connected to the trench gate unit 012.
  • the simulation comparison results of the IGBT device of the embodiment of the present invention and the input capacitor Cies of the IGBT device of the conventional trench gate structure and the IGBT device of the planar gate structure are shown in FIG. 13, and it can be seen that the IGBT is compared with the trench gate structure.
  • the input capacitance Cies of the IGBT device of the embodiment of the present invention is effectively reduced.
  • the simulation comparison results of the IGBT device of the embodiment of the present invention and the saturation voltage drop Vce of the IGBT device of the conventional trench gate structure and the IGBT device of the planar gate structure are shown in FIG. 14, and it can be seen that the IGBT is compared with the planar gate structure.
  • the rate of change of the saturation voltage drop Vce of the IGBT device of the embodiment of the present invention is relatively small.
  • the IGBT device adopts the gate structure design of the embodiment of the invention, which can effectively reduce the gate resistance; the gate input capacitance is smaller than the IGBT device of the trench gate structure, thereby improving the switching of the device.
  • a cell structure of the IGBT device is shown in FIG.
  • the overlapping width c of the planar gate unit 11 and the trench gate unit 12 is 0.8 to 1.2 ⁇ m to achieve reliable connection of the planar gate unit 11 and the trench gate unit 12.
  • the depth of the trench is 4 to 6 ⁇ m, which can be flexibly adjusted according to the parameter requirements of different devices.
  • An embodiment of the present invention further provides a power electronic device, including the IGBT device of any of the foregoing technical solutions. Since the IGBT device has the above-described advantageous effects, the electrical performance of the power electronic device is also better.
  • the specific type of power electronic equipment is not limited, and may be, for example, an AC motor, a frequency converter, a switching power supply, a lighting device, or a traction drive device.
  • an embodiment of the present invention further provides a method for fabricating an IGBT device, including the following steps:
  • the gate structure includes a plurality of planar gate cells and a plurality of trench gate cells, wherein: the plurality of planar gate cells are on the same layer, and the plurality of trench gate cells are located on one side of the plurality of planar gate cells, and Each of the planar gate cells is connected to at least two adjacent trench gate cells.
  • a method for fabricating an IGBT device specifically includes the following steps:
  • Step 101 as shown in FIG. 16a, a first oxide film 51 and a mask oxide layer 100 are sequentially formed on one surface of the N-type semiconductor substrate 2.
  • the N-type semiconductor substrate can adopt an N-type single crystal silicon wafer.
  • a protective thin oxide layer is formed on the surface of the N-type single crystal silicon wafer by using a growth process as a first oxide film, and then a growth process is continuously formed.
  • the layer thickness oxide layer serves as a mask oxide layer.
  • Step 102 etching the first oxide film 51 and the mask oxide layer 100 to form a mask pattern including a cutout region corresponding to the trench gate unit.
  • This step can be accomplished by photolithography and etching processes.
  • Step 103 as shown in FIG. 16c, etching the N-type semiconductor substrate 2 through the hollow region of the mask pattern to form the trench 14.
  • the etching of the N-type semiconductor substrate can be performed by a plasma etching process, and the depth of the trench is in the range of 4 to 6 ⁇ m, and the specific depth can be flexibly adjusted according to the parameter requirements of different devices.
  • Step 104 as shown in FIG. 16d, a second oxide film 52 is formed on the surface of the trench 14, and the second oxide film 52 and the etched first oxide film 51 serve as a first dielectric layer of the IGBT device. Similar to the first oxide film, the second oxide film can be formed on the surface of the trench by a growth process to protect the surface of the trench.
  • Step 105 removing the etched mask oxide layer.
  • the second oxide film and the etched first oxide film serve as a first dielectric layer for isolating the N-type semiconductor substrate from the subsequently fabricated gate structure.
  • Step 106 forms a trench gate unit 12 located in the trench, and a planar gate unit 11 on the surface of the etched first oxide film 51.
  • a thick polysilicon layer is deposited on the side of the first dielectric layer away from the N-type semiconductor substrate by chemical vapor deposition, and the trench is filled, and then the trench gate unit is formed by photolithography and etching processes.
  • the pattern of the planar gate unit that is, the pattern forming the gate structure. After this step is completed, the gate structure is completed.
  • Step 107 as shown in FIG. 16f, a P-type well 3 and an N-type emitter 4, a P-type well 3, an N-type emitter 4 and a first medium are formed on a side of the N-type semiconductor substrate 2 close to the planar gate unit 11.
  • the layer structures of the layers 5 are sequentially arranged in the direction close to the planar gate unit 11. Specifically, first, a P-type impurity is doped on the side of the N-type semiconductor substrate close to the planar gate unit by ion implantation and thermal diffusion, so that a P-type well is formed, and then the P-type well is approached by ion implantation and thermal diffusion processes.
  • One side of the planar gate unit is doped with an N-type impurity to form an N-type emitter.
  • Step 108 as shown in FIG. 16g, forming a second dielectric layer 6 on a side of the gate structure away from the first dielectric layer 5, the second dielectric layer 6 having a first contact hole 16 leading to the P-type well 3 and a path
  • a second contact hole (not shown) of the gate structure, as shown in FIG. 5, is such that the first contact hole 16 is located between the two planar gate units 11 adjacent to each other in the row direction and is located along the column direction. Between two adjacent planar gate units 11 .
  • the second dielectric layer may be an oxide film layer, deposited by chemical vapor deposition, and then patterned by the photolithography and etching processes to form the first contact hole and the second contact hole.
  • Step 109 as shown in FIG. 16g, a P-type contact region 15 exposed to the first contact hole 16 is formed on a side of the P-type well 3 close to the N-type emitter 4. Specifically, a P-type impurity is doped in a region where the P-type well is exposed to the first contact hole by an ion implantation and a thermal diffusion process, thereby forming a P-type contact region.
  • Step 110 As shown in FIG. 16h, a first metal layer is formed on a side of the second dielectric layer 6 away from the gate structure, and the first metal layer includes an emitter metal 71 connected to the P-type contact region 15 through the first contact hole. And a gate connection metal connected to the gate structure through the second contact hole. Specifically, a metal layer is sputtered by physical vapor deposition, and then a pattern of the first metal layer is formed by photolithography and etching processes.
  • a passivation protective layer 8 is formed on a side of the first metal layer away from the second dielectric layer 6, and the passivation protective layer 8 exposes part of the emitter metal 71 to be electrically connected to the outside.
  • the passivation protective layer 8 also protects the device from environmental moisture and impurities.
  • Step 112 as shown in Fig. 16i, an N-type field stop layer 9, a P-type collector region 10, and a second metal layer 13 are sequentially formed on the side of the N-type semiconductor substrate 2 away from the gate structure.
  • the N-type field stop layer and the P-type collector region are formed by an ion implantation and diffusion process, and the second metal layer is formed by a physical vapor deposition process.
  • the IGBT device fabricated by the method of the above embodiment has comprehensively improved device performance and is more applicable.

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Abstract

La présente invention concerne un dispositif de transistor bipolaire à grille isolée et son procédé de fabrication, et un équipement électronique de puissance, afin d'améliorer la performance globale et le caractère applicable du dispositif de transistor bipolaire à grille isolée. Le dispositif de transistor bipolaire à grille isolée comprend une structure de grille, qui comprend une pluralité d'unités de grille dans le plan et une pluralité d'unités de grille en rainures ; la pluralité d'unités de grille dans le plan est positionnée sur la même couche ; la pluralité d'unités de grille en rainures est positionnée sur un côté de la pluralité des unités de grille dans le plan, et est en intersection avec la couche de la pluralité d'unités de grille dans le plan ; et chaque unité de grille dans le plan est connectée à au moins deux unités de grille en rainures adjacentes.
PCT/CN2018/099611 2017-10-31 2018-08-09 Dispositif de transistor bipolaire à grille isolée et son procédé de fabrication, et équipement électronique de puissance WO2019085577A1 (fr)

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CN107706237B (zh) * 2017-10-31 2024-03-29 珠海零边界集成电路有限公司 绝缘栅双极型晶体管器件及其制作方法、电力电子设备
CN109801911A (zh) * 2019-01-29 2019-05-24 上海擎茂微电子科技有限公司 一种混合元胞型集成igbt器件
CN112117327B (zh) * 2020-08-17 2022-06-28 江苏东海半导体科技有限公司 一种igbt器件及其制造工艺
CN114050184A (zh) * 2021-11-10 2022-02-15 安徽瑞迪微电子有限公司 低米勒电容功率器件及其制造方法

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WO2011118512A1 (fr) * 2010-03-24 2011-09-29 オンセミコンダクター・トレーディング・リミテッド Transistor bipolaire à porte isolée
CN102412298A (zh) * 2010-09-21 2012-04-11 株式会社东芝 半导体元件及该半导体元件的制造方法
CN107706237A (zh) * 2017-10-31 2018-02-16 珠海格力电器股份有限公司 绝缘栅双极型晶体管器件及其制作方法、电力电子设备

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